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comparison nuc-fw/L1/include/l1_confg.h @ 115:1e41550feec5

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nuc-fw: Init_Target() reconstructed
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 27 Oct 2013 04:43:04 +0000
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114:17b0511b243c 115:1e41550feec5
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_CONFG.H
4 *
5 * Filename l1_confg.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #ifndef __L1_CONFG_H__
11 #define __L1_CONFG_H__
12
13 // Traces...
14 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
15 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
16 // TRACE_TYPE == 1 -> L1/L3 interface trace
17 // TRACE_TYPE == 2 -> Trace mode: ~33~~1~011...
18 // TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace
19 // TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack
20 // TRACE_TYPE == 5 -> trace for full simulation
21 // TRACE_TYPE == 6 -> CPU load trace for hisr
22 // TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on
23 // UART at 38400 bps =>
24 // format : <hisr cpu value in microseconds> <frame number>
25
26 // Code PB reported workaround
27 //------------------------------
28
29
30 // Code Version possible choices
31 //------------------------------
32 #define SIMULATION 1
33 #define NOT_SIMULATION 2
34
35 // RCL functions Version possible choices
36 //------------------------------
37 #define POLL_FORCED 0
38 #define RLC_SCENARIO 1
39 #define MODEM_FLOW 2
40
41 // possible choices for UART trace output
42 //------------------------------
43 #define MODEM_UART 0
44 #define IRDA_UART 1
45 #if (CHIPSET == 12)
46 #define MODEM2_UART 2
47 #endif
48
49 //============
50 // CODE CHOICE
51 //============
52 #if 0
53 #if (OP_L1_STANDALONE==0)
54 #define CODE_VERSION NOT_SIMULATION
55 #else // OP_L1_STANDALONE
56 #ifdef WIN32
57 #define CODE_VERSION SIMULATION
58 #else // WIN32
59 #define CODE_VERSION NOT_SIMULATION
60 #endif // WIN32
61 #endif // OP_L1_STANDALONE
62 #endif // #if 0
63
64 /* FreeCalypso */
65 #define CODE_VERSION NOT_SIMULATION
66 #define AMR 1
67 #define L1_12NEIGH 1
68 #define L1_EOTD 0
69 #define L1_GTT 0
70 #define MELODY_E2 1
71 #define TESTMODE 1
72
73 #if CONFIG_GPRS
74 # define L1_GPRS 1
75 #else
76 # define L1_GPRS 0
77 #endif
78
79 //---------------------------------------------------------------------------------
80 // Test with full simulation.
81 //---------------------------------------------------------------------------------
82 #if (CODE_VERSION == SIMULATION)
83
84 // Test Scenari...
85 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
86 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
87
88 // Traces...
89 #undef TRACE_TYPE
90 #define TRACE_TYPE 5
91 #define LOGFILE_TRACE 1 // trace in an output logfile
92 #define FLOWCHART 0 // Message sequence/flow chart trace.
93 #define NUCLEUS_TRACE 0 // Nucleus error trace
94 #define EOTD_TRACE 1 // EOTD log trace
95 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
96
97 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
98
99 // Control algorithms...
100 #define AFC_ALGO 1 // AFC algorithm.
101 #define TOA_ALGO 1 // TOA algorithm.
102 #define AGC_ALGO 1 // AGC algorithm.
103 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
104 #undef VCXO_ALGO
105 #define VCXO_ALGO 0 // VCXO algo
106 #undef DCO_ALGO
107 #define DCO_ALGO 0 // DCO algo (TIDE)
108 #undef ORDER2_TX_TEMP_CAL
109 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
110
111
112 #define FACCH_TEST 0 // FACCH test enabled.
113
114 #define ADC_TIMER_ON 0 // Timer for ADC measurements
115 #define AFC_ON 1 // Enable of the Omega AFC module
116
117 #define AUDIO_TASK 1 // Enable the L1 audio features
118 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
119 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
120
121 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
122 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401
123 #define TTY_SYNC_MCU_2 1 //
124 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
125 #define NEW_WKA_PATCH 0
126 #define OPTIMISED 1
127
128 #define L1_RECOVERY 0 // L1 recovery
129
130 #undef L1_GPRS
131 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
132
133 #undef AMR
134 #define AMR 1 // AMR version 1.0 supported
135
136 #undef L1_12NEIGH
137 #define L1_12NEIGH 1 // new L1-RR interface for 12 neighbour cells
138
139 #undef L1_GTT
140 #define L1_GTT 1 // Enable Global Text Telephony feature for simulation
141
142 #undef OP_L1_STANDALONE
143 #define OP_L1_STANDALONE 1 // Selection of code for L1 stand alone
144
145 #undef OP_RIV_AUDIO
146 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
147
148 #undef OP_WCP
149 #define OP_WCP 0 // No WCP integration
150 //---------------------------------------------------------------------------------
151 // Test with H/W platform.
152 //---------------------------------------------------------------------------------
153 #elif (CODE_VERSION == NOT_SIMULATION)
154
155 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1)
156 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
157 // (corrected with Calypso ReV B and Calypso C035)
158 #if (CHIPSET == 7)
159 #define W_A_CALYPSO_BUG_01435 1
160 #else
161 #define W_A_CALYPSO_BUG_01435 0
162 #endif
163
164
165 // for AMR thresolds definition CQ22226
166 #define AMR_THRESHOLDS_WORKAROUND 1
167
168 #if (L1_GTT==1)
169 #define TTY_SYNC_MCU 1
170 #define TTY_SYNC_MCU_2 1
171 #define L1_GTT_FIFO_TEST_ATOMIC 0
172 #define NEW_WKA_PATCH 0
173 #define OPTIMISED 1
174 #else
175 #define TTY_SYNC_MCU_2 0
176 #define L1_GTT_FIFO_TEST_ATOMIC 0
177 #define TTY_SYNC_MCU 0
178 #define NEW_WKA_PATCH 0
179 #define OPTIMISED 0
180
181 #endif
182
183 // Traces...
184 #define NUCLEUS_TRACE 0 // Nucleus error trace
185 #define FLOWCHART 0 // Message sequence/flow chart trace.
186 #define LOGFILE_TRACE 0 // trace in an output logfile
187 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
188
189 // Test Scenari...
190 #define SCENARIO_FILE 0 // Test Scenario comes from input files.
191 #define SCENARIO_MEM 1 // // Test Scenario comes from RAM.
192
193 #if (OP_L1_STANDALONE == 1)
194 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
195 #else
196 #define L2_L3_SIMUL 0
197 #endif
198
199 // Control algorithms...
200 #define AFC_ALGO 1 // AFC algorithm.
201 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
202 #define TOA_ALGO 1 // TOA algorithm.
203 #define AGC_ALGO 1 // AGC algorithm.
204 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
205
206 #define FACCH_TEST 0 // FACCH test enabled.
207
208 #define ADC_TIMER_ON 0 // Timer for ADC measurements
209 #define AFC_ON 1 // Enable of the Omega AFC module
210
211 #define AUDIO_TASK 1 // Enable the L1 audio features
212 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
213 #if (OP_L1_STANDALONE == 1)
214 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
215 #else
216 #define AUDIO_L1_STANDALONE 0
217 #endif
218
219 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
220
221 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
222
223 #define L1_RECOVERY 1 // L1 recovery
224
225
226 #if (L1_GPRS == 1)
227 #define RLC_VERSION RLC_SCENARIO
228 #if (RLC_VERSION == RLC_SCENARIO)
229 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
230 // output stat on CRC error blocks
231 // The user must enter the cs type and
232 // the number of frames desired.
233 #else
234 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
235 #endif
236
237 #if (OP_L1_STANDALONE == 1)
238 #define DSP_BACKGROUND_TASKS 1 // Enable the TEST of DSP background.tasks
239 // activated by a layer 3 message (BG_TASK_START (<task number>))
240 // deactivated by a layer 3 message (BG_TASK_STOP (<task number>))
241 // Warning : Works only with DSP>=31
242 #else
243 #define DSP_BACKGROUND_TASKS 0
244 #endif
245
246 #else
247 #define DSP_BACKGROUND_TASKS 0
248 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
249 #endif
250 #endif
251
252 // Audio tasks selection
253 //-----------------------
254
255 #if (AUDIO_TASK == 1)
256 #define KEYBEEP 1 // Enable keybeep feature
257 #define TONE 1 // Enable tone feature
258 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
259 #if (OP_L1_STANDALONE == 1)
260 #define GSMLITE 1
261 #endif
262 #if ((OP_L1_STANDALONE == 1) || (!GSMLITE))
263 #define MELODY_E1 1 // Enable melody format E1 feature
264 #define VOICE_MEMO 1 // Enable voice memorization feature
265
266 #define FIR 1 // Enable FIR feature
267 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
268 #define AUDIO_MODE 1 // Enable Audio mode feature
269 #else
270 #define AUDIO_MODE 0 // Disable Audio mode feature
271 #endif
272 #else
273 #define MELODY_E1 0 // Disable melody format E1 feature
274 #define VOICE_MEMO 0 // Disable voice memorization feature
275 #if (MELODY_E2)
276 #define FIR 1 // Enable FIR feature
277 #else
278 #define FIR 0 // Disable FIR feature
279 #endif
280
281 #define AUDIO_MODE 0 // Disable Audio mode feature
282 #endif
283 // Define CPORT for ESample only
284 #if ((CHIPSET == 12) && ((DSP == 35) || (DSP == 36)))
285 #define L1_CPORT 1 // Enable cport feature
286 #else
287 #define L1_CPORT 0 // Disable cport feature
288 #endif
289
290 #else
291 #define KEYBEEP 0 // Enable keybeep feature
292 #define TONE 0 // Enable tone feature
293 #define MELODY_E1 0 // Enable melody format E1 feature
294 #define VOICE_MEMO 0 // Enable voice memorization feature
295
296 #define FIR 0 // Enable FIR feature
297 #define AUDIO_MODE 0 // Enable Audio mode feature
298 #define L1_CPORT 0 // Enable cport feature
299 #endif
300
301 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2
302 #if (OP_RIV_AUDIO == 1)
303 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
304 #endif
305
306
307 // Vocoder selections
308 //-------------------
309
310 #define FR 1 // Full Rate
311 #define FR_HR 2 // Full Rate + Half Rate
312 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
313 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
314
315 // Standard (frequency plan) selections
316 //-------------------------------------
317
318 #define GSM 1 // GSM900.
319 #define GSM_E 2 // GSM900 Extended.
320 #define PCS1900 3 // PCS1900.
321 #define DCS1800 4 // DCS1800.
322 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
323 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
324 #define GSM850 7 // GSM850 Band
325 #define DUAL_US 8 // PCS1900 + GSM850
326
327 /*------------------------------------*/
328 /* Power Management */
329 /*------------------------------------*/
330 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
331
332
333 /*---------------------------------------------------------------------------*/
334 /* DSP configurations */
335 /* ------------------ */
336 /* DSP | FR| HR|EFR|14.4| SPEED |12LA68|12LA68 |4L32|AEC| MCU/DSP */
337 /* (version) | | | | | |POLE80|POLE112| |/NS| interface */
338 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
339 /* 0 (821) | x | | | | 39Mhz | x | | | | 1 */
340 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
341 /* 1 (830) | x | | | | 39Mhz | (1) | | x | | 1 */
342 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
343 /* 2 (912) | x | x | | | 58.5Mhz | x | | | | 2 */
344 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
345 /* 3 (10xx) | x | | x | x | 65Mhz | x | | | x | 3 */
346 /* ----------+---+---+---+----+---------+------+-------+----|---+---------- */
347 /* 4 (11xx) | x | x | x | x | 65Mhz | x | x (3)| | x | 3 */
348 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
349 /* 5 (830) | x | | | | 39Mhz | x | | | | 1 */
350 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
351 /* 6 (11xx) | x | x | x | x | 65Mhz | x | x (3)| |(2)| 3 */
352 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
353 /* */
354 /*(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is*/
355 /* not corrected. */
356 /* */
357 /*(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP */
358 /* interface which support AEC, therefore AEC is defined as 1. */
359 /* */
360 /*(3) Pole112 include RIF DL correction. No patch is needed if this one only */
361 /* include RIF/DL problem. */
362 /* */
363 /*---------------------------------------------------------------------------*/
364 #if (DSP == 16 || DSP == 17)
365
366 /* #define CLKMOD1 0x414e // ...
367 #define CLKMOD2 0x414e // ...65 Mips
368 #define CLKSTART 0x29 // ...65 Mips */
369
370 #define CLKMOD1 0x4006 // ...
371 #define CLKMOD2 0x4116 // ...65 Mips pll free
372 #define CLKSTART 0x29 // ...65 Mips
373
374 /* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle
375 #define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips
376 #define CLKSTART 0x25 // ...39 Mips */
377
378 #define VOC FR_HR_EFR // FR + HR + EFR.
379 #define DATA14_4 1 // No 14.4 data allowed.
380 #define AEC 1 // AEC/NS supported.
381 #define MAP 3
382 #define DSP_START 0x2000
383 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
384
385 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
386
387 /* DSP debug trace configuration */
388 /*-------------------------------*/
389 #if (MELODY_E2)
390 // In case of the melody E2 the DSP trace must be disable because the
391 // melody instrument waves are overlayed with DSP trace buffer
392
393 // DSP debug trace API buufer config
394 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
395 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
396 #else
397 // DSP debug trace API buufer config
398 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
399 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
400 #endif
401
402 #elif (DSP == 30) // First GPRS.
403 #define CLKMOD1 0x4006 // ...
404 #define CLKMOD2 0x4116 // ...65 Mips pll free
405 #define CLKSTART 0x29 // ...65 Mips
406
407 #define VOC FR_HR_EFR // FR + HR + EFR.
408 #define DATA14_4 1 // No 14.4 data allowed.
409 #define AEC 1 // AEC/NS not supported.
410 #define MAP 3
411 #define DSP_START 0x1F81
412 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
413 #define ULYSSE 0
414
415 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
416 #elif (DSP == 31) // ROM Code GPRS G0.
417 #define CLKMOD1 0x4006 // ...
418 #define CLKMOD2 0x4116 // ...65 Mips pll free
419 #define CLKSTART 0x29 // ...65 Mips
420
421 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
422 #define DATA14_4 1 // 14.4 data allowed.
423 #define AEC 1 // AEC/NS not supported.
424 #define MAP 3
425
426 #define DSP_START 0x8763
427
428 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
429 #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
430
431 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
432 #define ULYSSE 0
433
434 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
435 #elif (DSP == 32) // ROM Code GPRS G1.
436 #define CLKMOD1 0x4006 // ...
437 #define CLKMOD2 0x4116 // ...65 Mips pll free
438 #define CLKSTART 0x29 // ...65 Mips
439
440 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
441 #define DATA14_4 1 // 14.4 data allowed.
442 #define AEC 1 // AEC/NS not supported.
443 #define MAP 3
444
445 #define DSP_START 0x8763
446
447 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
448
449 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
450 #define ULYSSE 0
451
452 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
453 #elif (DSP == 33) // ROM Code GPRS.
454 #define CLKMOD1 0x4006 // ...
455 #define CLKMOD2 0x4116 // ...65 Mips pll free
456 #define CLKSTART 0x29 // ...65 Mips
457 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
458 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
459 #define AEC 1 // AEC/NS not supported.
460 #if (OP_RIV_AUDIO == 0)
461 #define L1_NEW_AEC 1
462 #else
463 // Available but not yet tuned with Riviera AUDIO
464 #define L1_NEW_AEC 0
465 #endif
466 #if ((L1_NEW_AEC) && (!AEC))
467 // First undef the flag to avoid warnings at compilation time
468 #undef AEC
469 #define AEC 1
470 #endif
471
472 #define MAP 3
473
474 #define DSP_START 0x7000
475
476 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
477
478 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
479 #define ULYSSE 0
480
481 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
482
483 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
484
485 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
486
487 // management.
488
489 // DSP_IDLE3 is not supported in simulation
490
491 #else
492 #define W_A_DSP_IDLE3 0
493 #endif
494
495 // DSP software work-around config
496 // bit0 - Work-around to support CRTG.
497 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
498 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
499 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
500
501 #if (ANALOG == 1) // OMEGA / NAUSICA
502 #define C_DSP_SW_WORK_AROUND 0x0006
503
504 #elif (ANALOG == 2) // IOTA
505 #define C_DSP_SW_WORK_AROUND 0x000E
506
507 #elif (ANALOG == 3) // SYREN
508 #define C_DSP_SW_WORK_AROUND 0x000E
509
510 #endif
511
512 /* DSP debug trace configuration */
513 /*-------------------------------*/
514 #if (MELODY_E2)
515 // In case of the melody E2 the DSP trace must be disable because the
516 // melody instrument waves are overlayed with DSP trace buffer
517
518 // DSP debug trace API buufer config
519 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
520 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
521
522 // DSP debug trace type config
523 // |<-------------- Features -------------->|<---------- Levels ----------->|
524 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
525 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
526
527 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
528 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
529 // Currently not supported !
530 #endif
531 #else
532 // DSP debug trace API buufer config
533 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
534 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
535
536 // DSP debug trace type config
537 // |<-------------- Features -------------->|<---------- Levels ----------->|
538 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
539 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
540
541 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
542 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
543 #endif
544 #endif
545 /* d_error_status */
546 /*-------------------------------*/
547
548 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
549 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
550
551 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
552 #define DSP_DEBUG_GSM_MASK 0x0000
553 #define DSP_DEBUG_GPRS_MASK 0x0f3d
554 #endif
555
556 #if DCO_ALGO
557 // DCO type of scheduling
558 #define C_CN_DCO_PARAM 0xA248
559 #endif
560
561 #elif (DSP == 34) // ROM Code GPRS AMR.
562 #define CLKMOD1 0x4006 // ...
563 #define CLKMOD2 0x4116 // ...65 Mips pll free
564 #define CLKSTART 0x29 // ...65 Mips
565 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
566 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
567 #define AEC 1 // AEC/NS not supported.
568 #if (OP_RIV_AUDIO == 0)
569 #define L1_NEW_AEC 1
570 #else
571 // Available but not yet tuned with Riviera AUDIO
572 #define L1_NEW_AEC 0
573 #endif
574 #if ((L1_NEW_AEC) && (!AEC))
575 // First undef the flag to avoid warnings at compilation time
576 #undef AEC
577 #define AEC 1
578 #endif
579 #define MAP 3
580
581 #define DSP_START 0x7000
582
583 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
584
585 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
586 #define ULYSSE 0
587
588 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
589
590 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
591
592 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
593
594 // management.
595
596 // DSP_IDLE3 is not supported in simulation
597
598 #else
599 #define W_A_DSP_IDLE3 0
600 #endif
601
602 // DSP software work-around config
603 // bit0 - Work-around to support CRTG.
604 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
605 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
606 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
607 #if (ANALOG == 1) // OMEGA / NAUSICA
608 #define C_DSP_SW_WORK_AROUND 0x0006
609
610 #elif (ANALOG == 2) // IOTA
611 #define C_DSP_SW_WORK_AROUND 0x000E
612
613 #elif (ANALOG == 3) // SYREN
614 #define C_DSP_SW_WORK_AROUND 0x000E
615
616 #endif
617
618 /* DSP debug trace configuration */
619 /*-------------------------------*/
620 #if (MELODY_E2)
621 // In case of the melody E2 the DSP trace must be disable because the
622 // melody instrument waves are overlayed with DSP trace buffer
623
624 // DSP debug trace API buufer config
625 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
626 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
627
628 // DSP debug trace type config
629 // |<-------------- Features -------------->|<---------- Levels ----------->|
630 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
631 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
632
633 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
634 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
635 // Currently not supported !
636 #endif
637 #else
638 // DSP debug trace API buufer config
639 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
640 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
641
642 // DSP debug trace type config
643 // |<-------------- Features -------------->|<---------- Levels ----------->|
644 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
645 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
646
647 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
648 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
649 #endif
650
651 // AMR trace
652 #define C_AMR_TRACE_ID 55
653
654 #endif
655 /* d_error_status */
656 /*-------------------------------*/
657
658 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
659 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
660
661 // masks to apply on d_error_status bit field
662 #define DSP_DEBUG_GSM_MASK 0x0000
663 #define DSP_DEBUG_GPRS_MASK 0x0f3d
664 #endif
665
666 #elif (DSP == 35) // ROM Code GPRS AMR.
667 #define CLKMOD1 0x4006 // ...
668 #define CLKMOD2 0x4116 // ...65 Mips pll free
669 #define CLKSTART 0x29 // ...65 Mips
670 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
671 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
672 #define AEC 1 // AEC/NS not supported.
673 #if (OP_RIV_AUDIO == 0)
674 #define L1_NEW_AEC 1
675 #else
676 // Available but not yet tuned with Riviera AUDIO
677 #define L1_NEW_AEC 0
678 #endif
679 #if ((L1_NEW_AEC) && (!AEC))
680 // First undef the flag to avoid warnings at compilation time
681 #undef AEC
682 #define AEC 1
683 #endif
684 #define MAP 3
685
686 #define FF_L1_TCH_VOCODER_CONTROL 1
687 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
688
689 #define DSP_START 0x7000
690
691 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
692
693 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
694 #define ULYSSE 0
695
696 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
697
698 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
699
700 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
701
702 // management.
703
704 // DSP_IDLE3 is not supported in simulation
705
706 #else
707 #define W_A_DSP_IDLE3 0
708 #endif
709
710 // DSP software work-around config
711 // bit0 - Work-around to support CRTG.
712 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
713 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
714 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
715 #if (ANALOG == 1) // OMEGA / NAUSICA
716 #define C_DSP_SW_WORK_AROUND 0x0006
717
718 #elif (ANALOG == 2) // IOTA
719 #define C_DSP_SW_WORK_AROUND 0x000E
720
721 #elif (ANALOG == 3) // SYREN
722 #define C_DSP_SW_WORK_AROUND 0x000E
723
724 #endif
725
726 /* DSP debug trace configuration */
727 /*-------------------------------*/
728 #if (MELODY_E2)
729 // In case of the melody E2 the DSP trace must be disable because the
730 // melody instrument waves are overlayed with DSP trace buffer
731
732 // DSP debug trace API buufer config
733 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
734 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
735
736 // DSP debug trace type config
737 // |<-------------- Features -------------->|<---------- Levels ----------->|
738 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
739 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
740
741 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
742 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
743 // Currently not supported !
744 #endif
745 #else
746 // DSP debug trace API buufer config
747 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
748 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
749
750 // DSP debug trace type config
751 // |<-------------- Features -------------->|<---------- Levels ----------->|
752 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
753 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
754
755 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
756 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
757 #endif
758
759 // AMR trace
760 #define C_AMR_TRACE_ID 55
761
762 #endif
763 /* d_error_status */
764 /*-------------------------------*/
765
766 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
767 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
768
769 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
770 #define DSP_DEBUG_GSM_MASK 0x08BD
771 #define DSP_DEBUG_GPRS_MASK 0x0f3d
772 #endif
773 #elif (DSP == 36) // ROM Code GPRS AMR.
774 #define CLKMOD1 0x4006 // ...
775 #define CLKMOD2 0x4116 // ...65 Mips pll free
776 #define CLKSTART 0x29 // ...65 Mips
777 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
778 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
779 #define AEC 1 // AEC/NS not supported.
780 #if (OP_RIV_AUDIO == 0)
781 #define L1_NEW_AEC 1
782 #else
783 // Available but not yet tuned with Riviera AUDIO
784 #define L1_NEW_AEC 0
785 #endif
786 #if ((L1_NEW_AEC) && (!AEC))
787 // First undef the flag to avoid warnings at compilation time
788 #undef AEC
789 #define AEC 1
790 #endif
791 #define MAP 3
792 #undef L1_AMR_NSYNC
793 #define L1_AMR_NSYNC 1
794 #define FF_L1_TCH_VOCODER_CONTROL 1
795 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
796
797 #define DSP_START 0x7000
798
799 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
800
801 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
802 #define ULYSSE 0
803
804 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
805
806 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
807
808 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
809
810 // management.
811
812 // DSP_IDLE3 is not supported in simulation
813
814 #else
815 #define W_A_DSP_IDLE3 0
816 #endif
817
818 // DSP software work-around config
819 // bit0 - Work-around to support CRTG.
820 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
821 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
822 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
823 #if (ANALOG == 1) // OMEGA / NAUSICA
824 #define C_DSP_SW_WORK_AROUND 0x0006
825
826 #elif (ANALOG == 2) // IOTA
827 #define C_DSP_SW_WORK_AROUND 0x000E
828
829 #elif (ANALOG == 3) // SYREN
830 #define C_DSP_SW_WORK_AROUND 0x000E
831 #endif
832
833 // This workaround should be enabled only for H2-sample on full build config
834 #if (OP_L1_STANDALONE==1)
835 #define RAZ_VULSWITCH_REGAUDIO 0
836 #endif
837
838 /* DSP debug trace configuration */
839 /*-------------------------------*/
840 #if (MELODY_E2)
841 // In case of the melody E2 the DSP trace must be disable because the
842 // melody instrument waves are overlayed with DSP trace buffer
843
844 // DSP debug trace API buufer config
845 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
846 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
847
848 // DSP debug trace type config
849 // |<-------------- Features -------------->|<---------- Levels ----------->|
850 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
851 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
852
853 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
854 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
855 // Currently not supported !
856 #endif
857 #else
858 // DSP debug trace API buufer config
859 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
860 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
861
862 // DSP debug trace type config
863 // |<-------------- Features -------------->|<---------- Levels ----------->|
864 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
865 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
866
867 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
868 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
869 #endif
870
871 // AMR trace
872 #define C_AMR_TRACE_ID 55
873
874 #endif
875 /* d_error_status */
876 /*-------------------------------*/
877
878 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
879 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
880
881 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
882 #define DSP_DEBUG_GSM_MASK 0x08BD
883 #define DSP_DEBUG_GPRS_MASK 0x0f3d
884 #endif
885 #endif // DSP
886
887 /*------------------------------------*/
888 /* Default value */
889 /*------------------------------------*/
890 #ifndef W_A_DSP1
891 #define W_A_DSP1 0
892 #endif
893
894 #ifndef DATA14_4
895 #define DATA14_4 0
896 #endif
897
898 #ifndef W_A_ITFORCE
899 #define W_A_ITFORCE 0
900 #endif
901
902 #ifndef W_A_DSP_IDLE3
903 #define W_A_DSP_IDLE3 0
904 #endif
905
906 #ifndef L1_NEW_AEC
907 #define L1_NEW_AEC 0
908 #endif
909
910 #ifndef DSP_DEBUG_TRACE_ENABLE
911 #define DSP_DEBUG_TRACE_ENABLE 0
912 #endif
913
914 #ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
915 #define DEBUG_DEDIC_TCH_BLOCK_STAT 0
916 #endif
917
918 #ifndef D_ERROR_STATUS_TRACE_ENABLE
919 #define D_ERROR_STATUS_TRACE_ENABLE 0
920 #endif
921
922 #ifndef L1_GTT
923 #define L1_GTT 0
924 #define TTY_SYNC_MCU 0
925 #define TTY_SYNC_MCU_2 0
926 #define L1_GTT_FIFO_TEST_ATOMIC 0
927 #define NEW_WKA_PATCH 0
928 #define OPTIMISED 0
929 #endif
930
931 #ifndef L1_AMR_NSYNC
932 #define L1_AMR_NSYNC 0
933 #endif
934
935 #ifndef FF_L1_TCH_VOCODER_CONTROL
936 #define FF_L1_TCH_VOCODER_CONTROL 0
937 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
938 #endif
939
940 /*------------------------------------*/
941 /* Download */
942 /*------------------------------------*/
943
944
945 /* Possible values for the download status */
946
947 #define LEAD_READY 1
948 #define BLOCK_READY 2
949 #define PROGRAM_DONE 3
950 #define PAGE_SELECTION 4
951
952
953 /************************************/
954 /* Options of compilation... */
955 /************************************/
956
957 // Possible choice of hardware plateform.
958 #define GEMINI 1 // GEMINI chip (rom dsp code)
959 #define POLESTAR 2 // POLESTAR chip (no rom)
960
961 // Possible choice for DSP software setup.
962 #define NO_DWNLD 0
963 #define PATCH_DWNLD 1
964 #define DSP_DWNLD 2
965 #define PATCH_DSP_DWNLD 3
966
967 // MAC-S status reporting to Layer 1
968 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
969
970
971 // Possible choice for dll_dcch_downlink interface (with FN or without FN)
972 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
973
974 //---------------------------------------------------------------------------------
975
976 // Neighbor Cell RXLEV indication
977 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
978 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1
979 #else
980 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0
981 #endif
982
983 #endif /* __L1_CONFG_H__ */