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comparison nuc-fw/bsp/clkm.h @ 115:1e41550feec5

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nuc-fw: Init_Target() reconstructed
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 27 Oct 2013 04:43:04 +0000
parents 91460c8957f0
children
comparison
equal deleted inserted replaced
114:17b0511b243c 115:1e41550feec5
105 #define DPLL_BYPASS_DIV 0x000C // Mask of bypass mode configuration 105 #define DPLL_BYPASS_DIV 0x000C // Mask of bypass mode configuration
106 #define DPLL_PLL_ENABLE 0x0010 // Enable DPLL 106 #define DPLL_PLL_ENABLE 0x0010 // Enable DPLL
107 #define DPLL_PLL_DIV 0x0060 // Mask of division factor configuration 107 #define DPLL_PLL_DIV 0x0060 // Mask of division factor configuration
108 #define DPLL_PLL_MULT 0x0F80 // Mask of multiply factor configuration 108 #define DPLL_PLL_MULT 0x0F80 // Mask of multiply factor configuration
109 109
110 #define DPLL_BYPASS_DIV_1 0x00 // Configuration of bypass mode divided by 1 110 #define DPLL_BYPASS_DIV_1 0x0 // Configuration of bypass mode divided by 1
111 #define DPLL_BYPASS_DIV_2 0x01 // Configuration of bypass mode divided by 2 111 #define DPLL_BYPASS_DIV_2 0x1 // Configuration of bypass mode divided by 2
112 #define DPLL_BYPASS_DIV_4 0x10 // Configuration of bypass mode divided by 4 112 #define DPLL_BYPASS_DIV_4 0x2 // Configuration of bypass mode divided by 4
113 113
114 #define DPLL_BYPASS_DIV_OFFSET 2 // Offset of bypass bits configuration 114 #define DPLL_BYPASS_DIV_OFFSET 2 // Offset of bypass bits configuration
115 #define DPLL_PLL_DIV_OFFSET 5 // Offset of division bits configuration 115 #define DPLL_PLL_DIV_OFFSET 5 // Offset of division bits configuration
116 #define DPLL_PLL_MULT_OFFSET 7 // Offset of multiply bits configuration 116 #define DPLL_PLL_MULT_OFFSET 7 // Offset of multiply bits configuration
117 117
118 #define DPLL_LOCK_DIV_1 0x0000 // Divide by 1 when DPLL is locked 118 #define DPLL_LOCK_DIV_1 0x0000 // Divide by 1 when DPLL is locked
119 #define DPLL_LOCK_DIV_2 0x0001 // Divide by 2 when DPLL is locked 119 #define DPLL_LOCK_DIV_2 0x0001 // Divide by 2 when DPLL is locked
120 #define DPLL_LOCK_DIV_3 0x0002 // Divide by 3 when DPLL is locked 120 #define DPLL_LOCK_DIV_3 0x0002 // Divide by 3 when DPLL is locked
121 #define DPLL_LOCK_DIV_4 0x0003 // Divide by 4 when DPLL is locked 121 #define DPLL_LOCK_DIV_4 0x0003 // Divide by 4 when DPLL is locked
122 122
123 #else 123 #else
124 #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6) /* Lead PLL */ 124 #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6) /* Lead PLL */
125 #define CLKM_PLONOFF 0x0001 // PLL enable signal 125 #define CLKM_PLONOFF 0x0001 // PLL enable signal
126 #define CLKM_PLMUL 0x001e // Mask of multiply factor configuration 126 #define CLKM_PLMUL 0x001e // Mask of multiply factor configuration
127 #define CLKM_PLLNDIV 0x0020 // PLL or divide mode selection 127 #define CLKM_PLLNDIV 0x0020 // PLL or divide mode selection
258 #define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK = value) 258 #define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK = value)
259 259
260 /* 260 /*
261 * NOTE: the version of the CLKM_INITCNTL() macro in the Sotomodem source 261 * NOTE: the version of the CLKM_INITCNTL() macro in the Sotomodem source
262 * does |= instead of =. It remains to be investigated which is more correct. 262 * does |= instead of =. It remains to be investigated which is more correct.
263 *
264 * For now I'll define the ORing version under a different (and more
265 * descriptive) name: CLKM_CNTL_OR.
263 */ 266 */
264 267
268 #define CLKM_CNTL_OR(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= value)
265 269
266 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12)) 270 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
267 /*---------------------------------------------------------------/ 271 /*---------------------------------------------------------------/
268 /* CLKM_INITLEADPLL() */ 272 /* CLKM_INITLEADPLL() */
269 /*--------------------------------------------------------------*/ 273 /*--------------------------------------------------------------*/