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comparison nuc-fw/bsp/init_target.c @ 115:1e41550feec5

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nuc-fw: Init_Target() reconstructed
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 27 Oct 2013 04:43:04 +0000
parents
children 8b0793c67f9f
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114:17b0511b243c 115:1e41550feec5
1 /*
2 * Init_Target() is the first function called from Application_Initialize().
3 * But unfortunately, our TCS211 semi-src has this function in a binary lib.
4 * I was able to find a conditioned-out version in the LoCosto source that
5 * seems to be a fit - so I'm going to massage it a bit to match the sequence
6 * of operations seen in the disassembly of our reference binary.
7 */
8
9 #include "../include/config.h"
10 #include "../include/sys_types.h"
11
12 #include "mem.h"
13 #include "clkm.h"
14 #include "armio.h"
15 #include "timer.h"
16 #include "inth.h"
17 #include "rhea_arm.h"
18 #include "ulpd.h"
19
20 /* TPU_FREEZE is defined in l1_const.h */
21 #include "../L1/include/l1_confg.h"
22 #include "../L1/include/l1_const.h"
23
24 void Init_Target(void)
25 {
26 #if 1 //(PSP_STANDALONE == 0)
27 // RIF/SPI rising edge clock for ULYSSE
28 //--------------------------------------------------
29 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
30 #if ((CHIPSET >= 3))
31 #if (CHIPSET == 12)
32 F_CONF_RIF_RX_RISING_EDGE;
33 F_CONF_SPI_RX_RISING_EDGE;
34 #elif (CHIPSET == 15)
35 //do the DRP init here for Locosto
36 #if (L1_DRP == 1)
37 // drp_power_on(); This should be done after the script is downloaded.
38 #endif
39 #else
40 #if (BOARD==35)
41 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
42 #else
43 *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
44 #endif /* (BOARD == 35) */
45 #endif
46 #endif
47 #endif /* ANLG(ANALOG)) */
48
49 #if 0 //(OP_L1_STANDALONE == 1)
50 #if (BOARD == 40) || (BOARD == 41) || \
51 (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
52 // enable 8 Ohm amplifier for audio on D-sample
53 AI_ConfigBitAsOutput (1);
54 AI_SetBit(1);
55 #elif (BOARD == 70) || (BOARD == 71)
56 //Locosto I-sample or UPP costo board.BOARD
57 // Initialize the ARMIO bits as per the I-sample spec
58 // FIXME
59 #endif
60 #endif /* (OP_L1_STANDALONE == 1) */
61 #endif /* PSP_STANDALONE ==0 */
62
63 // Watchdog
64 //--------------------------------------------------
65 TM_DisableWatchdog(); /* Disable Watchdog */
66 #if (CHIPSET == 12) || (CHIPSET == 15)
67 TM_SEC_DisableWatchdog();
68 #endif
69
70 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
71
72 /*
73 * Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
74 */
75 // IRQ, Timer and bridge may SLEEP
76 // In first step, same configuration as SAMSON
77 //--------------------------------------------------
78 #if (CHIPSET == 12)
79 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS);
80 #elif (CHIPSET == 15)
81 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
82
83 #else
84 CLKM_CNTL_OR(CLKM_IRQ_DIS | CLKM_TIMER_DIS);
85
86 // Select VTCXO input frequency
87 //--------------------------------------------------
88 CLKM_UNUSED_VTCXO_26MHZ;
89
90 // Rita RF uses 26MHz VCXO
91 #if (RF_FAM == 12)
92 CLKM_USE_VTCXO_26MHZ;
93 #endif
94 // Renesas RF uses 26MHz on F-sample but 13MHz on TEB
95 #if (RF_FAM == 43) && (BOARD == 46)
96 CLKM_USE_VTCXO_26MHZ;
97 #endif
98 #endif
99
100 // Control HOM/SAM automatic switching
101 //--------------------------------------------------
102 *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
103
104 /*
105 * Disassembly of Init_Target() in init.obj in main.lib in the
106 * Leonardo reference version reveals that the code does the
107 * following at this point:
108 */
109 RHEA_INITRHEA(0,0,0xFF);
110 DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
111 DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
112 CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
113 /* at this point the original code sets up the memory wait states */
114 /* we'll do it differently */
115 RHEA_INITAPI(0,1);
116 RHEA_INITARM(0,0);
117 DPLL_SET_PLL_ENABLE;
118
119 /*
120 * Disable and Clear all pending interrupts
121 */
122 #if (CHIPSET == 12) || (CHIPSET == 15)
123 F_INTH_DISABLE_ALL_IT; // MASK all it
124 F_INTH2_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH2 IRQ
125 F_INTH_VALID_NEXT(C_INTH_IRQ); // reset current IT in INTH IRQ
126 F_INTH_VALID_NEXT(C_INTH_FIQ); // reset current IT in INTH FIQ
127 F_INTH_RESET_ALL_IT; // reset all IRQ/FIQ source
128 #else
129 INTH_DISABLEALLIT;
130 INTH_RESETALLIT;
131 INTH_CLEAR; /* reset IRQ/FIQ source */
132 #endif
133
134 // INTH
135 //--------------------------------------------------
136 #if (CHIPSET == 12) || (CHIPSET == 15)
137 #if (GSM_IDLE_RAM != 0)
138 f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram); // setup configuration IT handlers
139 #else
140 f_inth_setup((T_INTH_CONFIG *)a_inth_config); // setup configuration IT handlers
141 #endif
142 #else
143 IQ_SetupInterrupts();
144 #endif
145
146 // DMA
147 //--------------------------------------------------
148 // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
149 #if 1 //(OP_L1_STANDALONE == 0)
150 DMA_ALLOCDMA(1,0,1,1); // Channel 1 used by DSP with RIF RX
151 #endif
152
153 /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
154
155 #else
156
157 // RHEA Bridge
158 //--------------------------------------------------
159 // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
160 RHEA_INITRHEA(0,0,0x7F);
161
162 #if (CHIPSET == 6)
163 // WS_H = 1 , WS_L = 15
164 RHEA_INITAPI(1,15); // should be 0x01E1 for 65 Mhz
165 #else
166 // WS_H = 0 , WS_L = 7
167 RHEA_INITAPI(0,7); // should be 0x0101 for 65 Mhz
168 #endif
169
170 // Write_en_0 = 0 , Write_en_1 = 0
171 RHEA_INITARM(0,0);
172
173 // INTH
174 //--------------------------------------------------
175 INTH_DISABLEALLIT; // MASK all it
176 INTH_CLEAR; // reset IRQ/FIQ source
177 IQ_SetupInterrupts();
178
179 // DMA
180 //--------------------------------------------------
181 // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
182 DMA_ALLOCDMA(1,0,1,1); // should be 0x25 (channel 1 = lead)
183
184 #if (CHIPSET == 6)
185 // Memory WS configuration for ULYSS/G1 (26 Mhz) board
186 //-----------------------------------------------------
187 MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
188 #endif
189
190 // CLKM
191 //--------------------------------------------------
192 CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
193
194 #if (CHIPSET == 6)
195 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26);
196 #else
197 CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS);
198 #endif
199
200 #endif /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
201
202 // Freeze ULPD timer ....
203 //--------------------------------------------------
204 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0;
205 *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
206
207 // reset INC_SIXTEEN and INC_FRAC
208 //--------------------------------------------------
209 #if 0 //(OP_L1_STANDALONE == 1)
210 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
211 #else
212 ULDP_INCSIXTEEN_UPDATE(132); //32768.29038 =>132, 32500 => 133
213 // 26000 --> 166
214 ULDP_INCFRAC_UPDATE(15840); //32768.29038 =>15840, 32500 => 21845
215 // 26000 --> 43691
216 #endif /* OP_L1_STANDALONE */
217
218 // program ULPD WAKE-UP ....
219 //=================================================
220 #if (CHIPSET == 2)
221 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 2 frame
222 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 31 periods
223 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
224 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
225 #else
226 *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG) = SETUP_FRAME; // 3 frames
227 *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG) = SETUP_VTCXO; // 0 periods
228 *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
229 *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG) = SETUP_CLK13; // 31 periods
230 *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG) = SETUP_RF; // 31 periods
231 #endif
232
233 #if (CHIPSET == 15)
234 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SLEEPN) = SETUP_SLEEPZ; // 0
235 *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SYSCLKEN) = SETUP_SYSCLKEN; // 255 clocks of 32 KHz for 7.8 ms DCXO delay for Locosto
236 *((volatile SYS_UWORD16 *)0xFFFEF192) = 0x1; //CLRZ
237 *((volatile SYS_UWORD16 *)0xFFFEF190) = 0x2; //SLPZ
238 *((volatile SYS_UWORD16 *)0xFFFEF18E)= 0x2; //SYSCLKEN
239 *((volatile SYS_UWORD16 *)0xFFFEF186) = 0x2; //CLK13_EN
240 *((volatile SYS_UWORD16 *)0xFFFEF18A) = 0x2; //DRP_DBB_SYSCLK
241 #endif
242
243 // Set Gauging versus HF (PLL)
244 //=================================================
245 ULDP_GAUGING_SET_HF; // Enable gauging versus HF
246 ULDP_GAUGING_HF_PLL; // Gauging versus PLL
247
248 // current supply for quartz oscillation
249 //=================================================
250 #if 0 //(OP_L1_STANDALONE == 1)
251 #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value
252 *(volatile SYS_UWORD16 *)QUARTZ_REG = 0x27;
253 #endif
254 #else
255 #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41))
256 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x27;
257 #elif (BOARD == 7)
258 *((volatile SYS_UWORD16 *)QUARTZ_REG) = 0x24;
259 #endif
260 #endif /* OP_L1_STANDALONE */
261
262 // stop Gauging if any (debug purpose ...)
263 //--------------------------------------------------
264 if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN)
265 {
266 volatile int j;
267 ULDP_GAUGING_STOP; /* Stop the gauging */
268 /* wait for gauging it*/
269 // one 32khz period = 401 periods of 13Mhz
270 for (j=1; j<50; j++);
271 while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING);
272 }
273
274 #if 1 //(OP_L1_STANDALONE == 0)
275 AI_ClockEnable ();
276
277 #if (BOARD == 7)
278 // IOs configuration of the B-Sample in order to optimize the power consumption
279 AI_InitIOConfig();
280
281 // Set LPG instead of DSR_MODEM
282 *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40;
283 // Reset the PERM_ON bit of LCR_REG
284 *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80);
285 #elif ((BOARD == 8) || (BOARD == 9))
286 // IOs configuration of the C-Sample in order to optimize the power consumption
287 AI_InitIOConfig();
288
289 // set the debug latch to 0x00.
290 *((volatile SYS_UWORD8 *) 0x2800000) = 0x00;
291 #elif ((BOARD == 35) || (BOARD == 46))
292 AI_InitIOConfig();
293 // CSMI INTERFACE
294 // Initialize CSMI clients for GSM control
295 // and Fax/Data services
296 CSMI_Init();
297 GC_Initialize(); // GSM control initialization
298 CU_Initialize(); // Trace initialization
299 CF_Initialize(); // Fax/Data pre-initialization
300 #elif ((BOARD == 40) || (BOARD == 41))
301 // IOs configuration of the D-Sample in order to optimize the power consumption
302 AI_InitIOConfig();
303
304 #ifdef BTEMOBILE
305 // Reset BT chip by toggling the Island's nRESET_OUT signal
306 *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04;
307 *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4);
308 #endif
309
310 #if 0 // FreeCalypso
311 // set the debug latch to 0x0000.
312 *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
313 #endif
314 #elif ((BOARD == 70) || (BOARD == 71))
315 AI_InitIOConfig();
316 /* Mark The System configuration According to I-Sample */
317 /* Adding GPIO Mux Setting Here */
318 pin_configuration_all(); // Init Tuned for Power Management
319 /* A22 is Enabled in int.s hence not Here */
320 /* FIXME: PULL_UP Enable and PULL UP Values Need to revisited */
321
322 /* Add code to find out the manufacture id of NOR flash*/
323
324 // Copy ffsdrv_device_id_read() function code to RAM. The only known
325 // way to determine the size of the code is to look either in the
326 // linker-generated map file or in the assember output file.
327 ffsdrv_copy_code_to_ram((UWORD16 *) detect_code,
328 (UWORD16 *) &ffsdrv_device_id_read,
329 sizeof(detect_code));
330
331 // Combine bit 0 of the thumb mode function pointer with the address
332 // of the code in RAM. Then call the detect function in RAM.
333 myfp = (pf_t) (((int) &ffsdrv_device_id_read & 1) | (int) detect_code);
334 (*myfp)(0x06000000, &manufact, device_id);
335
336 enable_ps_ram_burst();
337
338 if( 0x7e == device_id[0] )
339 {
340 enable_flash_burst();
341 flash_device_id = 0x7E;
342 }
343 else
344 {
345 enable_flash_burst_mirror();
346 flash_device_id = 0;
347 }
348
349 /* FreeCalypso: a bunch of dead code cut out */
350
351 #endif // BOARD
352
353 // Enable HW Timers 1 & 2
354 TM_EnableTimer (1);
355 TM_EnableTimer (2);
356
357 #endif /* (OP_L1_STANDALONE == 0) */
358
359 }