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comparison gsm-fw/L1/include/l1_defty.h @ 530:25a7fe25864c

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gsm-fw/L1/include: switch to LoCosto versions of all header files
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 01 Aug 2014 16:38:35 +0000
parents ed6071292a5c
children de635895e0be
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529:f72c9db5e2f5 530:25a7fe25864c
1 /************* Revision Controle System Header ************* 1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software 2 * GSM Layer 1 software
3 * L1_DEFTY.H 3 * L1_DEFTY.H
4 * 4 *
5 * Filename l1_defty.h 5 * Filename l1_defty.h
6 * Copyright 2003 (C) Texas Instruments 6 * Copyright 2003 (C) Texas Instruments
7 * 7 *
8 ************* Revision Controle System Header *************/ 8 ************* Revision Controle System Header *************/
9
10 #include "sys.cfg"
11 #include "l1sw.cfg"
12
13 #if (L1_RF_KBD_FIX == 1)
14 #include "l1_macro.h"
15
16 #if(OP_L1_STANDALONE == 0)
17 #include "kpd/kpd_scan_functions.h"
18 #endif
19
20 #endif
21
22 #include "cust_os.h"
9 #if(L1_DYN_DSP_DWNLD == 1) 23 #if(L1_DYN_DSP_DWNLD == 1)
10 #include "../dyn_dwl_include/l1_dyn_dwl_defty.h" 24 #include "l1_dyn_dwl_defty.h"
11 #endif 25 #endif
26 #if (L1_AAC == 1) //ADDED for AAC -sajal
27 #include "l1aac_defty.h"
28 #endif
29
30 typedef struct
31 {
32 UWORD8 enable; // activation of FACCH test
33 UWORD8 period; // period of FACCH test
34 }
35 T_FACCH_TEST_PARAMS;
12 36
13 typedef struct 37 typedef struct
14 { 38 {
15 UWORD16 modulus; 39 UWORD16 modulus;
16 UWORD16 relative_position; 40 UWORD16 relative_position;
21 { 45 {
22 UWORD8 schedule_array_size; 46 UWORD8 schedule_array_size;
23 T_BCCHS_SCHEDULE schedule_array[10]; 47 T_BCCHS_SCHEDULE schedule_array[10];
24 } 48 }
25 T_BCCHS; 49 T_BCCHS;
50
51 typedef struct
52 {
53 UWORD8 srr; /* SACCH Repetition Request - UL */
54 UWORD8 sro; /* SACCH Repetition Order - DL */
55 UWORD8 buffer[22+1]; /* New uplink buffer to save the repetition block data in case of retransmission */
56 BOOL buffer_empty; /* It is equal to 1 if the UL repetion buffer should be empty otherwise 0 */
57 }
58 T_REPEAT_SACCH;
59
60 typedef struct
61 {
62 API buffer[12]; /* New buffer to save the DL data for comparison */
63 UWORD8 buffer_empty; /* To indicate the saved buffer */
64 }T_REPEAT_FACCH_PIPELINE;
65 typedef struct
66 {
67 T_REPEAT_FACCH_PIPELINE pipeline[2];
68 UWORD8 counter;
69 UWORD8 counter_candidate;
70 } T_REPEAT_FACCH;
26 71
27 typedef struct 72 typedef struct
28 { 73 {
29 BOOL status; 74 BOOL status;
30 UWORD16 radio_freq; 75 UWORD16 radio_freq;
38 UWORD8 gprs_priority; 83 UWORD8 gprs_priority;
39 UWORD8 sb26_offset; // Set to 1 when SB26 RX win is entirely in frame 25. 84 UWORD8 sb26_offset; // Set to 1 when SB26 RX win is entirely in frame 25.
40 #if (L1_12NEIGH ==1) 85 #if (L1_12NEIGH ==1)
41 UWORD32 fn_offset_mem; 86 UWORD32 fn_offset_mem;
42 UWORD32 time_alignmt_mem; 87 UWORD32 time_alignmt_mem;
88 #endif // (L1_12NEIGH ==1)
89 #if ((REL99 == 1) && ((FF_BHO == 1) || (FF_RTD == 1)))
90 UWORD8 nb_fb_attempt ;
91 UWORD8 fb26_position; // used for RTD feature
43 #endif 92 #endif
44 } 93 }
45 T_NCELL_SINGLE; 94 T_NCELL_SINGLE;
95
96 #if ((REL99 == 1) && (FF_BHO == 1))
97 typedef struct
98 {
99 UWORD8 fb_found_attempt;
100 UWORD16 radio_freq;
101 UWORD32 fn_offset;
102 UWORD32 time_alignmt;
103 UWORD32 fb_toa;
104 }
105 T_BHO_PARAM;
106 #endif // #if ((REL99 == 1) && (FF_BHO == 1))
46 107
47 typedef struct 108 typedef struct
48 { 109 {
49 UWORD8 active_neigh_id_norm; 110 UWORD8 active_neigh_id_norm;
50 UWORD8 active_neigh_tc_norm; 111 UWORD8 active_neigh_tc_norm;
127 T_AMR_CONFIGURATION; 188 T_AMR_CONFIGURATION;
128 #endif 189 #endif
129 190
130 typedef struct 191 typedef struct
131 { 192 {
193 #if(L1_A5_3 == 1 && OP_L1_STANDALONE != 1)
194 UWORD8 A[15+1];
195 #else
132 UWORD8 A[7+1]; 196 UWORD8 A[7+1];
197 #endif
133 } 198 }
134 T_ENCRYPTION_KEY; 199 T_ENCRYPTION_KEY;
135 200
136 typedef struct 201 typedef struct
137 { 202 {
263 } 328 }
264 T_HO_PARAMS; 329 T_HO_PARAMS;
265 330
266 typedef struct 331 typedef struct
267 { 332 {
268 T_CHANNEL_DESCRIPTION channel_desc;
269 T_MOBILE_ALLOCATION frequency_list;
270 T_STARTING_TIME starting_time;
271 }
272 T_MPHC_CHANGE_FREQUENCY;
273
274 typedef struct
275 {
276 UWORD8 subchannel; 333 UWORD8 subchannel;
277 UWORD8 channel_mode; 334 UWORD8 channel_mode;
278 #if (AMR == 1) 335 #if (AMR == 1)
279 T_AMR_CONFIGURATION amr_configuration; 336 T_AMR_CONFIGURATION amr_configuration;
280 #endif 337 #endif
281 } 338 }
282 T_MPHC_CHANNEL_MODE_MODIFY_REQ; 339 T_MPHC_CHANNEL_MODE_MODIFY_REQ;
283 340
284 typedef struct 341 typedef struct
285 { 342 {
286 UWORD8 cipher_mode;
287 UWORD8 a5_algorithm;
288 T_ENCRYPTION_KEY new_ciph_param;
289 }
290 T_MPHC_SET_CIPHERING_REQ;
291
292 typedef struct
293 {
294 UWORD8 sub_channel; 343 UWORD8 sub_channel;
295 UWORD8 frame_erasure; 344 UWORD8 frame_erasure;
296 } 345 }
297 T_OML1_CLOSE_TCH_LOOP_REQ; 346 T_OML1_CLOSE_TCH_LOOP_REQ;
298 347
350 { 399 {
351 const T_FCT *address; 400 const T_FCT *address;
352 UWORD8 size; 401 UWORD8 size;
353 } 402 }
354 T_TASK_MFTAB; 403 T_TASK_MFTAB;
404
405
406 #if (GSM_IDLE_RAM != 0)
407 typedef struct
408 {
409 BOOL l1s_full_exec;
410 BOOL trff_ctrl_enable_cause_int;
411 WORD32 hw_timer;
412 WORD32 os_load;
413 UWORD32 sleep_mode;
414
415 #if GSM_IDLE_RAM_DEBUG
416 UWORD32 killing_flash_access;
417 UWORD32 killing_ext_ram_access;
418 UWORD32 irq;
419 UWORD32 fiq;
420 UWORD32 nb_inth;
421
422 #if (CHIPSET == 10) && (OP_WCP == 1)
423 UWORD16 TC_true_control;
424 #endif // CHIPSET && OP_WCP
425 #endif // GSM_IDLE_RAM_DEBUG
426 UWORD32 task_bitmap_idle_ram[SIZE_TAB_L1S_MONITOR];
427 UWORD32 mem_task_bitmap_idle_ram[SIZE_TAB_L1S_MONITOR];
428 }
429 T_L1S_GSM_IDLE_INTRAM;
430 #endif // GSM_IDLE_RAM
431
355 432
356 /***********************************************************/ 433 /***********************************************************/
357 /* TPU controle register components definition. */ 434 /* TPU controle register components definition. */
358 /***********************************************************/ 435 /***********************************************************/
359 436
392 /* */ 469 /* */
393 /***********************************************************/ 470 /***********************************************************/
394 471
395 typedef struct 472 typedef struct
396 { 473 {
397 API d_task_d; // (0) Downlink task command. 474 API d_task_d; // 0x0800 (0) Downlink task command.
398 API d_burst_d; // (1) Downlink burst identifier. 475 API d_burst_d; // 0x0801 (1) Downlink burst identifier.
399 API d_task_u; // (2) Uplink task command. 476 API d_task_u; // 0x0802 (2) Uplink task command.
400 API d_burst_u; // (3) Uplink burst identifier. 477 API d_burst_u; // 0x0803 (3) Uplink burst identifier.
401 API d_task_md; // (4) Downlink Monitoring (FB/SB) command. 478 API d_task_md; // 0x0804 (4) Downlink Monitoring (FB/SB) command.
402 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) 479 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
403 API d_background; // (5) Background tasks 480 API d_background; // 0x0805 (5) Background tasks
404 #else 481 #else
405 API d_reserved; // (5) Reserved 482 API d_reserved; // 0x0805 (5) Reserved
406 #endif 483 #endif
407 API d_debug; // (6) Debug/Acknowledge/general purpose word. 484 API d_debug; // 0x0806 (6) Debug/Acknowledge/general purpose word.
408 API d_task_ra; // (7) RA task command. 485 API d_task_ra; // 0x0807 (7) RA task command.
409 API d_fn; // (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only. 486 API d_fn; // 0x0808 (8) FN, in Rep. period and FN%104, used for TRAFFIC/TCH only.
410 // bit [0..7] -> b_fn_report, FN in the normalized reporting period. 487 // bit [0..7] -> b_fn_report, FN in the normalized reporting period.
411 // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning. 488 // bit [8..15] -> b_fn_sid, FN % 104, used for SID positionning.
412 API d_ctrl_tch; // (9) Tch channel description. 489 API d_ctrl_tch; // 0x0809 (9) Tch channel description.
413 // bit [0..3] -> b_chan_mode, channel mode. 490 // bit [0..3] -> b_chan_mode, channel mode.
414 // bit [4..5] -> b_chan_type, channel type. 491 // bit [4..5] -> b_chan_type, channel type.
415 // bit [6] -> reset SACCH 492 // bit [6] -> reset SACCH
416 // bit [7] -> vocoder ON 493 // bit [7] -> vocoder O
417 // bit [8] -> b_sync_tch_ul, synchro. TCH/UL. 494 // bit [8] -> b_sync_tch_ul, synchro. TCH/UL.
418 // bit [9] -> b_sync_tch_dl, synchro. TCH/DL. 495 // bit [9] -> b_sync_tch_dl, synchro. TCH/DL.
419 // bit [10] -> b_stop_tch_ul, stop TCH/UL. 496 // bit [10] -> b_stop_tch_ul, stop TCH/UL.
420 // bit [11] -> b_stop_tch_dl, stop TCH/DL. 497 // bit [11] -> b_stop_tch_dl, stop TCH/DL.
421 // bit [12.13] -> b_tch_loop, tch loops A/B/C. 498 // bit [12.13] -> b_tch_loop, tch loops A/B/C.
422 API hole; // (10) unused hole. 499 API hole; // 0x080A (10) unused hole.
423 500
424 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3)) 501 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11))
425 API d_ctrl_abb; // (11) Bit field indicating the analog baseband register to send. 502 API d_ctrl_abb; // 0x080B (11) Bit field indicating the analog baseband register to send.
426 // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB 503 // bit [0] -> b_ramp: the ramp information(a_ramp[]) is located in NDB
427 // bit [1.2] -> unused 504 // bit [1.2] -> unused
428 // bit [3] -> b_apcdel: delays-register in NDB 505 // bit [3] -> b_apcdel: delays-register in NDB
429 // bit [4] -> b_afc: freq control register in DB 506 // bit [4] -> b_afc: freq control register in DB
430 // bit [5..15] -> unused 507 // bit [5..15] -> unused
431 #endif 508 #endif
432 API a_a5fn[2]; // (12..13) Encryption Frame number. 509 API a_a5fn[2]; // 0x080C (12..13) Encryption Frame number.
433 // word 0, bit [0..4] -> T2. 510 // word 0, bit [0..4] -> T2.
434 // word 0, bit [5..10] -> T3. 511 // word 0, bit [5..10] -> T3.
435 // word 1, bit [0..11] -> T1. 512 // word 1, bit [0..11] -> T1.
436 API d_power_ctl; // (14) Power level control. 513 API d_power_ctl; // 0x080E (14) Power level control.
437 API d_afc; // (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb"). 514 API d_afc; // 0x080F (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb").
438 API d_ctrl_system; // (16) Controle Register for RESET/RESUME. 515 API d_ctrl_system; // 0x0810 (16) Controle Register for RESET/RESUME.
439 // bit [0..2] -> b_tsq, training sequence. 516 // bit [0..2] -> b_tsq, training sequence.
440 // bit [3] -> b_bcch_freq_ind, BCCH frequency indication. 517 // bit [3] -> b_bcch_freq_ind, BCCH frequency indication.
441 // bit [15] -> b_task_abort, DSP task abort command. 518 // bit [15] -> b_task_abort, DSP task abort command.
519 // bit [4] -> B_SWH_APPLY_WHITENING, Apply whitening.
520 //#if (((DSP == 36)||(DSP == 37)||(DSP == 38) || (DSP == 39)))
521 // API d_swh_ApplyWhitening_db; // 0x0811 SWH Whitening Activation Flag
522 //#endif
442 } 523 }
443 T_DB_MCU_TO_DSP; 524 T_DB_MCU_TO_DSP;
444 525
445 typedef struct 526 #if (DSP == 38) || (DSP == 39)
446 { 527 // DB COMMON to GSM and GPRS
447 API d_task_d; // (0) Downlink task command. 528 typedef struct
448 API d_burst_d; // (1) Downlink burst identifier. 529 {
449 API d_task_u; // (2) Uplink task command. 530 API d_dco_algo_ctrl_nb; // DRP DCO enable/disable for normal burst
450 API d_burst_u; // (3) Uplink burst identifier. 531 API d_dco_algo_ctrl_sb; // DRP DCO enable/disable for synchro burst
451 API d_task_md; // (4) Downlink Monitoring (FB/SB) task command. 532 API d_dco_algo_ctrl_pw; // DRP DCO enable/disable for power burst
452 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) 533 API d_swh_ctrl_db;
453 API d_background; // (5) Background tasks 534 API d_fast_paging_ctrl;
535 }
536 T_DB_COMMON_MCU_TO_DSP;
537 #endif // DSP == 38 || DSP == 39
538
539 /* DSP CPU load measurement */
540 #if (DSP == 38) || (DSP == 39)
541 // DB COMMON to GSM and GPRS
542 typedef struct
543 {
544 API d_dsp_fgd_tsk_tim0;
545 API d_dsp_fgd_tsk_tim1;
546 API d_tdma_dsp_fn;
547 API d_dsp_page_read;
548 }
549 T_DB_MCU_TO_DSP_CPU_LOAD;
550 #endif // DSP == 38 || DSP == 39
551
552 typedef struct
553 {
554 API d_task_d; // 0x0828 (0) Downlink task command.
555 API d_burst_d; // 0x0829 (1) Downlink burst identifier.
556 API d_task_u; // 0x082A (2) Uplink task command.
557 API d_burst_u; // 0x082B (3) Uplink burst identifier.
558 API d_task_md; // 0x082C (4) Downlink Monitoring (FB/SB) task command.
559 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
560 API d_background; // 0x082D (5) Background tasks
454 #else 561 #else
455 API d_reserved; // (5) Reserved 562 API d_reserved; // 0x082D (5) Reserved
456 #endif 563 #endif
457 API d_debug; // (6) Debug/Acknowledge/general purpose word. 564 API d_debug; // 0x082E (6) Debug/Acknowledge/general purpose word.
458 API d_task_ra; // (7) RA task command. 565 API d_task_ra; // 0x082F (7) RA task command.
459 566
460 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) 567 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
461 API a_serv_demod[4]; // ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). 568 API a_serv_demod[4]; // 0x0830 ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
462 API a_pm[3]; // (12..14) Power measurement results, array of 3 words. 569 API a_pm[3]; // 0x0834 (12..14) Power measurement results, array of 3 words.
463 API a_sch[5]; // (15..19) Header + SB information, array of 5 words. 570 API a_sch[5]; // 0x0837 (15..19) Header + SB information, array of 5 words.
464 #else 571 #else
465 API a_pm[3]; // ( 8..10) Power measurement results, array of 3 words. 572 API a_pm[3]; // ( 8..10) Power measurement results, array of 3 words.
466 API a_serv_demod[4]; // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR). 573 API a_serv_demod[4]; // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
467 API a_sch[5]; // (15..19) Header + SB information, array of 5 words. 574 API a_sch[5]; // (15..19) Header + SB information, array of 5 words.
468 #endif 575 #endif
469 } 576 }
470 T_DB_DSP_TO_MCU; 577 T_DB_DSP_TO_MCU;
471 578
472 #if (DSP == 34) || (DSP == 35) || (DSP == 36) // NDB GSM 579 #if (DSP == 38) || (DSP == 39)
580 typedef struct
581 {
582 // MISC Tasks
583 API d_dsp_page; // 0x08D4
584
585 // DSP status returned (DSP --> MCU).
586 API d_error_status; // 0x08D5
587
588 // RIF control (MCU -> DSP). // following is removed for Locosto
589 API d_spcx_rif_hole; // 0x08D6
590
591
592 API d_tch_mode; // 0x08D7 TCH mode register.
593 // bit [0..1] -> b_dai_mode.
594 // bit [2] -> b_dtx.
595
596 API d_debug1; // 0x08D8 bit 0 at 1 enable dsp f_tx delay for Omega
597
598 API d_dsp_test; // 0x08D9
599
600 // Words dedicated to Software version (DSP code + Patch)
601 API d_version_number1; // 0x08DA
602 API d_version_number2; // 0x08DB
603
604 API d_debug_ptr; // 0x08DC
605 API d_debug_bk; // 0x08DD
606
607 API d_pll_config; // 0x08DE
608
609 // GSM/GPRS DSP Debug trace support
610 API p_debug_buffer; // 0x08DF
611 API d_debug_buffer_size; // 0x08E0
612 API d_debug_trace_type; // 0x08E1
613
614 #if (W_A_DSP_IDLE3 == 1)
615 // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
616 API d_dsp_state; // 0x08E2
617 // 5 words are reserved for any possible mapping modification
618 API d_hole1_ndb[2]; // 0x08E3
619 #else
620 // 6 words are reserved for any possible mapping modification
621 API d_hole1_ndb[3];
622 #endif
623
624 #if (AMR == 1)
625 API p_debug_amr; // 0x08E5??? DSP doc says reserved
626 #else
627 API d_hole_debug_amr;
628 #endif
629
630 API d_dsp_iq_scaling_factor; // 0x08E6
631 API d_mcsi_select; // 0x08E7
632
633 // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
634 API d_apcdel1_bis; // 0x08E8
635 API d_apcdel2_bis;
636 // New registers due to IOTA analog base band
637 API d_apcdel2;
638
639
640 API d_vbctrl2_hole; // 0x08EB
641 API d_bulgcal_hole; // 0x08EC
642 // Analog Based Band - removed in ROM 38
643 API d_afcctladd_hole; // 0x08ED
644 API d_vbuctrl_hole; // 0x08EE - removed in ROM38
645 API d_vbdctrl_hole; // 0x08EF - removed in ROM38
646
647 API d_apcdel1; // 0x08F0
648 // New Variables Added due to the APC Switch
649 // But for when DSP is in Idle3 all writes from MCU to APC are routed via DSP
650 API d_apclev; // APCLEV - 0x08F1 (In ROM36 - apcoff )
651 // NOTE: Used Only in Test mode
652 // Only when l1_config.tmode.rf_params.down_up == TMODE_UPLINK;
653 API d_apcctrl2; // APCCTRL2 - 0x08F2 (In ROM36 - bulioff)
654 API d_bulqoff_hole; // 0x08F3
655 API d_dai_onoff; // 0x08F4
656 API d_auxdac_hole; // 0x08F5
657
658 API d_vbctrl_hole; // 0x08F6 - removed in ROM38
659
660 API d_bbctrl_hole; // 0x08F7 - removed in ROM38
661
662 // Monitoring tasks control (MCU <- DSP)
663 // FB task
664 API d_fb_det; // 0x08F8 FB detection result. (1 for FOUND).
665 API d_fb_mode; // Mode for FB detection algorithm.
666 API a_sync_demod[4]; // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
667
668 // SB Task
669 API a_sch26[5]; // 0x08FE Header + SB information, array of 5 words.
670
671 API d_audio_gain_ul; // 0x0903
672 API d_audio_gain_dl; // 0x0904
673
674 // Controller of the melody E2 audio compressor - removed in ROM 38
675 API d_audio_compressor_ctrl_hole; // 0x0905 - removed in ROM37,38
676
677 // AUDIO module
678 API d_audio_init; // 0x0906
679 API d_audio_status; //
680
681 // Audio tasks
682 // TONES (MCU -> DSP)
683 API d_toneskb_init;
684 API d_toneskb_status;
685 API d_k_x1_t0;
686 API d_k_x1_t1;
687 API d_k_x1_t2;
688 API d_pe_rep;
689 API d_pe_off;
690 API d_se_off;
691 API d_bu_off; // 0x0910
692 API d_t0_on;
693 API d_t0_off;
694 API d_t1_on;
695 API d_t1_off;
696 API d_t2_on;
697 API d_t2_off;
698 API d_k_x1_kt0;
699 API d_k_x1_kt1;
700 API d_dur_kb;
701 API d_shiftdl;
702 API d_shiftul; // 0x091B
703
704 API d_aec_18_hole; // 0x091C
705
706 API d_es_level_api;
707 API d_mu_api;
708
709 // Melody Ringer module
710 API d_melo_osc_used; // 0x091F
711 API d_melo_osc_active; // 0x0920
712 API a_melo_note0[4];
713 API a_melo_note1[4];
714 API a_melo_note2[4];
715 API a_melo_note3[4];
716 API a_melo_note4[4];
717 API a_melo_note5[4];
718 API a_melo_note6[4];
719 API a_melo_note7[4];
720
721 // selection of the melody format
722 API d_melody_selection; // 0x0941
723
724 // Holes due to the format melody E1
725 API a_melo_holes[3];
726
727 // Speech Recognition module - Removed in ROM38
728 API d_sr_holes[19]; // 0x0945
729
730 // Audio buffer
731 API a_dd_1[22]; // 0x0958 Header + DATA traffic downlink information, sub. chan. 1.
732 API a_du_1[22]; // 0x096E Header + DATA traffic uplink information, sub. chan. 1.
733
734 // V42bis module
735 API d_v42b_nego0; // 0x0984
736 API d_v42b_nego1;
737 API d_v42b_control;
738 API d_v42b_ratio_ind;
739 API d_mcu_control;
740 API d_mcu_control_sema;
741
742 // Background tasks
743 API d_background_enable; // 0x098A
744 API d_background_abort;
745 API d_background_state;
746 API d_max_background;
747 API a_background_tasks[16]; // 0x098E
748 API a_back_task_io[16]; //0x099E
749
750 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
751 API d_gea_mode_ovly_hole; // 0x09AE
752 API a_gea_kc_ovly_hole[4]; // 0x09AF
753
754 API d_hole3_ndb[6]; //0x09B3
755 API d_dsp_aud_hint_flag; // 0x09B9;
756
757 // word used for the init of USF threshold
758 API d_thr_usf_detect; // 0x09BA
759
760 // Encryption module
761 API d_a5mode; // Encryption Mode.
762
763 API d_sched_mode_gprs_ovly; // 0x09Bc
764 #if (FF_L1_IT_DSP_USF == 1) || (FF_L1_IT_DSP_DTX == 1)
765 API d_hole1_fast_ndb[1]; // 0x09BD;
766 API d_dsp_hint_flag; // 0x09BE; //used for fast usf and fast dtx and other dyn dwn
767 // 6 words are reserved for any possible mapping modification
768 #if FF_L1_IT_DSP_DTX
769 API d_fast_dtx_enable;//used for enabling fast dtx- 0x09BF
770 API d_fast_dtx_enc_data;//fast usf written by DSP to indicate tx data is there or not- 0x09C0
771 #else // FF_L1_IT_DSP_DTX
772 API d_hole3_fast_ndb[2]; // 0x09BF
773 #endif // FF_L1_IT_DSP_USF
774 #if (FF_L1_FAST_DECODING == 1)
775 API d_fast_paging_data; // 0x9C1
776 #else
777 API d_hole_fast_paging_ndb;
778 #endif /* FF_L1_FAST_DECODING*/
779 #else
780 // 7 words are reserved for any possible mapping modification
781 API d_hole4_ndb[5]; // 0x09BD
782 #endif
783
784 // Ramp definition for Omega device
785 API a_ramp_hole[16]; //0x09C2
786
787 // CCCH/SACCH downlink information...(!!)
788 API a_cd[15]; //0x09D2 Header + CCCH/SACCH downlink information.
789
790 // FACCH downlink information........(!!)
791 API a_fd[15]; // 0x09E1 Header + FACCH downlink information.
792
793 // Traffic downlink data frames......(!!)
794 API a_dd_0[22]; // 0x09F0 Header + DATA traffic downlink information, sub. chan. 0.
795
796 // CCCH/SACCH uplink information.....(!!)
797 API a_cu[15]; // 0x0A06 Header + CCCH/SACCH uplink information.
798
799 // FACCH downlink information........(!!)
800 API a_fu[15]; // 0x0A15 Header + FACCH uplink information
801
802 // Traffic downlink data frames......(!!)
803 API a_du_0[22]; // 0x0A24 Header + DATA traffic uplink information, sub. chan. 0.
804
805 // Random access.....................(MCU -> DSP).
806 API d_rach; // 0x0A3A RACH information.
807
808 //...................................(MCU -> DSP).
809 API a_kc[4]; // 0x0A3B Encryption Key Code.
810
811 // Integrated Data Services module
812 API d_ra_conf;
813 API d_ra_act;
814 API d_ra_test;
815 API d_ra_statu;
816 API d_ra_statd;
817 API d_fax;
818 API a_data_buf_ul[21]; // 0x0A45
819 API a_data_buf_dl[37]; // 0x0A5A
820
821 API a_sr_holes0[422]; // 0x0A7F
822
823 #if (L1_AEC == 1)
824 #if (L1_NEW_AEC)
825 API d_cont_filter;
826 API d_granularity_att;
827 API d_coef_smooth;
828 API d_es_level_max;
829 API d_fact_vad;
830 API d_thrs_abs;
831 API d_fact_asd_fil;
832 API d_fact_asd_mut;
833 API d_far_end_pow_h;
834 API d_far_end_pow_l;
835 API d_far_end_noise_h;
836 API d_far_end_noise_l;
837 #else
838 API a_sr_hole1[12];
839 #endif
840 #else
841 API a_sr_hole2[12];
842 #endif
843
844 // Speech recognition model
845 API a_sr_holes1[145]; // 0x0C31
846
847 // Correction of PR G23M/L1_MCU-SPR-15494
848 API d_cport_init; // 0x0CC2
849 API d_cport_ctrl;
850 API a_cport_cfr[2];
851 API d_cport_tcl_tadt;
852 API d_cport_tdat;
853 API d_cport_tvs;
854 API d_cport_status;
855 API d_cport_reg_value;
856 API a_cport_holes[1011];
857
858 API a_model_holes[1041];
859
860 // EOTD buffer
861 #if (L1_EOTD==1)
862 API d_eotd_first;
863 API d_eotd_max;
864 API d_eotd_nrj_high;
865 API d_eotd_nrj_low;
866 API a_eotd_crosscor[18];
867 #else
868 API a_eotd_holes[22];
869 #endif
870 // AMR ver 1.0 buffers
871 API a_amr_config[4]; // 0x14E5
872 API a_ratscch_ul[6];
873 API a_ratscch_dl[6];
874 API d_amr_snr_est; // estimation of the SNR of the AMR speech block
875 #if (L1_VOICE_MEMO_AMR)
876 API d_amms_ul_voc;
877 #else
878 API a_voice_memo_amr_holes[1];
879 #endif
880 API d_thr_onset_afs; // thresh detection ONSET AFS
881 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
882 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS
883 API d_thr_update_afs; // thresh detection SID_UPDATE AFS
884 API d_thr_onset_ahs; // thresh detection ONSET AHS
885 API d_thr_sid_ahs; // thresh detection SID frames AHS
886 API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER
887 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA
888 API d_thr_soft_bits; // 0x14FF
889
890
891 API a_amrschd_debug[30]; // 0x1500
892 #if (W_A_AMR_THRESHOLDS)
893 API a_d_macc_thr_afs[8]; // 0x151E
894 API a_d_macc_thr_ahs[6]; // 0x1526
895 #else
896 API d_holes[14]; // 0x151E
897 #endif
898
899 // There is no melody E2 in DSP ROM38 as of now -> Only Holes
900 API d_melody_e2_holes[17]; // 0x152C
901
902
903 API d_vol_ul_level_hole; // 0x153D
904 API d_vol_dl_level_hole; // 0x153E
905 API d_vol_speed_hole; // 0x153F
906 API d_sidetone_level_hole; // 0x1540
907
908 // Audio control area
909 API d_es_ctrl; // 0x1541
910 API d_anr_ul_ctrl;
911 API d_aec_ul_ctrl;
912 API d_agc_ul_ctrl;
913 //API d_aqi_ctrl_hole1[4]; // Reserved for future UL modules earlier code now modified and added d_vad_noise_ene_ndb
914 API d_aqi_ctrl_hole1[1]; // Reserved for future UL modules
915
916 API d_vad_noise_ene_ndb[2]; //NAVC API address-0x1546-MSB, 0x1547-LSB-> 2-WORDs
917
918 API d_navc_ctrl_status; // NAVC control
919
920 API d_iir_dl_ctrl; // 0x1549
921 API d_lim_dl_ctrl;
922 API d_drc_dl_ctrl;
923 API d_agc_dl_ctrl;
924 API d_audio_apps_ctrl; // Reserved for future DL modules
925 API d_audio_apps_status;
926 API d_aqi_status;
927
928 #if (L1_IIR == 1)
929 API d_iir_input_scaling; // 0x1550
930 API d_iir_fir_scaling; //
931 API d_iir_input_gain_scaling; //
932 API d_iir_output_gain_scaling; //
933 API d_iir_output_gain; //
934 API d_iir_feedback; //
935 API d_iir_nb_iir_blocks; //
936 API d_iir_nb_fir_coefs; //
937 API a_iir_iir_coefs[80]; // 0x1558
938 API a_iir_fir_coefs[32]; // 0x15A8
939
940 #if (L1_ANR == 1)
941 API d_anr_min_gain;
942 API d_anr_vad_thr;
943 API d_anr_gamma_slow;
944 API d_anr_gamma_fast;
945 API d_anr_gamma_gain_slow;
946 API d_anr_gamma_gain_fast;
947 API d_anr_thr2;
948 API d_anr_thr4;
949 API d_anr_thr5;
950 API d_anr_mean_ratio_thr1;
951 API d_anr_mean_ratio_thr2;
952 API d_anr_mean_ratio_thr3;
953 API d_anr_mean_ratio_thr4;
954 API d_anr_div_factor_shift;
955 API d_anr_ns_level;
956 #else
957 API d_anr_hole[15];
958 #endif
959
960
961 #elif (L1_IIR == 2) //Srart address= 0x1550.
962 API d_iir4x_control;
963 API d_iir4x_frame_size;
964 API d_iir4x_fir_swap;
965 API d_iir4x_fir_enable;
966 API d_iir4x_fir_length;
967 API_SIGNED d_iir4x_fir_shift;
968 API_SIGNED a_iir4x_fir_taps[40];
969 API d_iir4x_sos_enable;
970 API d_iir4x_sos_number;
971 API_SIGNED d_iir4x_sos_fact_1;
972 API_SIGNED d_iir4x_sos_fact_form_1;
973 API_SIGNED a_iir4x_sos_den_1[2];
974 API_SIGNED a_iir4x_sos_num_1[3];
975 API_SIGNED d_iir4x_sos_num_form_1;
976 API_SIGNED d_iir4x_sos_fact_2;
977 API_SIGNED d_iir4x_sos_fact_form_2;
978 API_SIGNED a_iir4x_sos_den_2[2];
979 API_SIGNED a_iir4x_sos_num_2[3];
980 API_SIGNED d_iir4x_sos_num_form_2;
981 API_SIGNED d_iir4x_sos_fact_3;
982 API_SIGNED d_iir4x_sos_fact_form_3;
983 API_SIGNED a_iir4x_sos_den_3[2];
984 API_SIGNED a_iir4x_sos_num_3[3];
985 API_SIGNED d_iir4x_sos_num_form_3;
986 API_SIGNED d_iir4x_sos_fact_4;
987 API_SIGNED d_iir4x_sos_fact_form_4;
988 API_SIGNED a_iir4x_sos_den_4[2];
989 API_SIGNED a_iir4x_sos_num_4[3];
990 API_SIGNED d_iir4x_sos_num_form_4;
991 API_SIGNED d_iir4x_sos_fact_5;
992 API_SIGNED d_iir4x_sos_fact_form_5;
993 API_SIGNED a_iir4x_sos_den_5[2];
994 API_SIGNED a_iir4x_sos_num_5[3];
995 API_SIGNED d_iir4x_sos_num_form_5;
996 API_SIGNED d_iir4x_sos_fact_6;
997 API_SIGNED d_iir4x_sos_fact_form_6;
998 API_SIGNED a_iir4x_sos_den_6[2];
999 API_SIGNED a_iir4x_sos_num_6[3];
1000 API_SIGNED d_iir4x_sos_num_form_6;
1001 API_SIGNED d_iir4x_gain; //End address= 0x15B0
1002
1003
1004 #if (L1_AGC_UL == 1) //Start address= 0x15B1
1005 // AGC uplink
1006 API d_agc_ul_control;
1007 API d_agc_ul_frame_size;
1008 API_SIGNED d_agc_ul_targeted_level;
1009 API_SIGNED d_agc_ul_signal_up;
1010 API_SIGNED d_agc_ul_signal_down;
1011 API_SIGNED d_agc_ul_max_scale;
1012 API_SIGNED d_agc_ul_gain_smooth_alpha;
1013 API_SIGNED d_agc_ul_gain_smooth_alpha_fast;
1014 API_SIGNED d_agc_ul_gain_smooth_beta;
1015 API_SIGNED d_agc_ul_gain_smooth_beta_fast;
1016 API_SIGNED d_agc_ul_gain_intp_flag;
1017 #else
1018 API d_agc_ul_holes[11];
1019 #endif //End address= 0x15BB
1020
1021 #if (L1_AGC_DL == 1)
1022 // AGC downlink
1023 API d_agc_dl_control; //Start Address= 0x15BC
1024 API d_agc_dl_frame_size;
1025 API_SIGNED d_agc_dl_targeted_level;
1026 API_SIGNED d_agc_dl_signal_up;
1027 API_SIGNED d_agc_dl_signal_down;
1028 API_SIGNED d_agc_dl_max_scale;
1029 API_SIGNED d_agc_dl_gain_smooth_alpha;
1030 API_SIGNED d_agc_dl_gain_smooth_alpha_fast;
1031 API_SIGNED d_agc_dl_gain_smooth_beta;
1032 API_SIGNED d_agc_dl_gain_smooth_beta_fast;
1033 API_SIGNED d_agc_dl_gain_intp_flag;
1034 #else
1035 API d_agc_dl_holes[11];
1036 #endif //End address= 0x15C6
1037
1038
1039 #if(L1_AEC == 2)
1040 API d_aec_mode; //Start address= 0x15C7
1041 API d_mu;
1042 API d_cont_filter;
1043 API d_scale_input_ul;
1044 API d_scale_input_dl;
1045 API d_div_dmax;
1046 API d_div_swap_good;
1047 API d_div_swap_bad;
1048 API d_block_init;
1049 API d_fact_vad;
1050 API d_fact_asd_fil;
1051 API d_fact_asd_mut;
1052 API d_thrs_abs;
1053 API d_es_level_max;
1054 API d_granularity_att;
1055 API d_coef_smooth; //End address= 0x15D6
1056
1057 #else
1058
1059 #if (L1_ANR == 1)
1060 API d_iir_holes[1];
1061
1062 API d_anr_min_gain;
1063 API d_anr_vad_thr;
1064 API d_anr_gamma_slow;
1065 API d_anr_gamma_fast;
1066 API d_anr_gamma_gain_slow;
1067 API d_anr_gamma_gain_fast;
1068 API d_anr_thr2;
1069 API d_anr_thr4;
1070 API d_anr_thr5;
1071 API d_anr_mean_ratio_thr1;
1072 API d_anr_mean_ratio_thr2;
1073 API d_anr_mean_ratio_thr3;
1074 API d_anr_mean_ratio_thr4;
1075 API d_anr_div_factor_shift;
1076 API d_anr_ns_level;
1077 #else
1078 API d_iir_anr_hole[16];
1079 #endif
1080 #endif
1081
1082
1083 #else
1084 API d_iir_holes_1[97];
1085 #if (L1_AGC_UL == 1)
1086 // AGC uplink
1087 API d_agc_ul_control;
1088 API d_agc_ul_frame_size;
1089 API_SIGNED d_agc_ul_targeted_level;
1090 API_SIGNED d_agc_ul_signal_up;
1091 API_SIGNED d_agc_ul_signal_down;
1092 API_SIGNED d_agc_ul_max_scale;
1093 API_SIGNED d_agc_ul_gain_smooth_alpha;
1094 API_SIGNED d_agc_ul_gain_smooth_alpha_fast;
1095 API_SIGNED d_agc_ul_gain_smooth_beta;
1096 API_SIGNED d_agc_ul_gain_smooth_beta_fast;
1097 API_SIGNED d_agc_ul_gain_intp_flag;
1098 #else
1099 API d_agc_ul_holes[11];
1100 #endif
1101
1102 #if (L1_AGC_DL == 1)
1103 // AGC downlink
1104 API d_agc_dl_control;
1105 API d_agc_dl_frame_size;
1106 API_SIGNED d_agc_dl_targeted_level;
1107 API_SIGNED d_agc_dl_signal_up;
1108 API_SIGNED d_agc_dl_signal_down;
1109 API_SIGNED d_agc_dl_max_scale;
1110 API_SIGNED d_agc_dl_gain_smooth_alpha;
1111 API_SIGNED d_agc_dl_gain_smooth_alpha_fast;
1112 API_SIGNED d_agc_dl_gain_smooth_beta;
1113 API_SIGNED d_agc_dl_gain_smooth_beta_fast;
1114 API_SIGNED d_agc_dl_gain_intp_flag;
1115 #else
1116 API d_agc_dl_holes[11];
1117 #endif
1118
1119 #if(L1_AEC == 2)
1120 API d_aec_mode;
1121 API d_mu;
1122 API d_cont_filter;
1123 API d_scale_input_ul;
1124 API d_scale_input_dl;
1125 API d_div_dmax;
1126 API d_div_swap_good;
1127 API d_div_swap_bad;
1128 API d_block_init;
1129 API d_fact_vad;
1130 API d_fact_asd_fil;
1131 API d_fact_asd_mut;
1132 API d_thrs_abs;
1133 API d_es_level_max;
1134 API d_granularity_att;
1135 API d_coef_smooth;
1136
1137 #else
1138
1139 #if(L1_ANR == 1)
1140 API d_iir_holes[1];
1141
1142 API d_anr_min_gain;
1143 API d_anr_vad_thr;
1144 API d_anr_gamma_slow;
1145 API d_anr_gamma_fast;
1146 API d_anr_gamma_gain_slow;
1147 API d_anr_gamma_gain_fast;
1148 API d_anr_thr2;
1149 API d_anr_thr4;
1150 API d_anr_thr5;
1151 API d_anr_mean_ratio_thr1;
1152 API d_anr_mean_ratio_thr2;
1153 API d_anr_mean_ratio_thr3;
1154 API d_anr_mean_ratio_thr4;
1155 API d_anr_div_factor_shift;
1156 API d_anr_ns_level;
1157 #else
1158 API d_iir_anr_hole[16];
1159 #endif
1160
1161 #endif
1162
1163 #endif //L1_IIR
1164
1165 #if (L1_LIMITER == 1)
1166 API a_lim_mul_low[2]; // 0x15D7
1167 API a_lim_mul_high[2];
1168 API d_lim_gain_fall_q15; // 0x15DB
1169 API d_lim_gain_rise_q15; //
1170 API d_lim_block_size; // 0x15DD
1171 API d_lim_nb_fir_coefs; //
1172 API d_lim_slope_update_period;
1173 API a_lim_filter_coefs[16]; // 0x15E0
1174 #else
1175 API d_lim_hole[25];
1176 #endif
1177 #if (L1_ES == 1)
1178 API d_es_mode; // 0x15F0
1179 API d_es_gain_dl;
1180 API d_es_gain_ul_1;
1181 API d_es_gain_ul_2;
1182 API d_es_tcl_fe_ls_thr;
1183 API d_es_tcl_dt_ls_thr;
1184 API d_es_tcl_fe_ns_thr;
1185 API d_es_tcl_dt_ns_thr;
1186 API d_es_tcl_ne_thr;
1187 API d_es_ref_ls_pwr;
1188 API d_es_switching_time;
1189 API d_es_switching_time_dt;
1190 API d_es_hang_time;
1191 API a_es_gain_lin_dl_vect[4];
1192 API a_es_gain_lin_ul_vect[4];
1193 #else
1194 API d_es_hole[21];
1195 #endif
1196
1197 #if (L1_ANR == 2)
1198 API_SIGNED d_anr_ns_level; // start address= 0x1605
1199 API_SIGNED d_anr_control;
1200 API_SIGNED d_anr_tone_ene_th;
1201 API_SIGNED d_anr_tone_cnt_th;
1202 #else
1203 API d_anr_hole_2[4];
1204 #endif //End address= 0x1608
1205
1206 #if (L1_WCM == 1) // start address= 0x1609
1207 API_SIGNED d_wcm_mode;
1208 API_SIGNED d_wcm_frame_size;
1209 API_SIGNED d_wcm_num_sub_frames;
1210 API_SIGNED d_wcm_ratio;
1211 API_SIGNED d_wcm_threshold;
1212 API_SIGNED a_wcm_gain[16];
1213 #else
1214 API_SIGNED d_wcm_holes[21];
1215 #endif
1216
1217 API a_tty_holes1[24]; // 0x161E
1218
1219 #if (L1_GTT == 1)
1220 API d_tty_status; // 0x1636
1221 API d_ctm_detect_shift; // 0x1637
1222 API d_tty2x_baudot_mod_amplitude_scale;
1223 API d_tty2x_samples_per_baudot_stop_bit;
1224 API d_tty_reset_buffer_ul;
1225 API d_tty_loop_ctrl;
1226 API p_tty_loop_buffer;
1227 API d_ctm_mod_norm;
1228 API d_tty2x_offset_normalization;
1229 API d_tty2x_threshold_startbit;
1230 API d_tty2x_threshold_diff; // 0x1640
1231 API d_tty2x_duration_startdetect; // 0x1641
1232 API d_tty2x_startbit_thres; // 0x1642
1233 API d_tty2x_hole_init_mute_frame_count; // 0x1643
1234 API d_tty2x_dl_bypass_mute; // 0x1644
1235 #else
1236 API a_tty_holes2[15];
1237 #endif
1238
1239 API a_tty_fifo_holes[131]; // 0x1645
1240
1241 // New DRP Releated Variables Start Here
1242 API a_drp_holes_1[6]; // 0x16C8
1243 API d_drp_apcctrl2_hole; // 0x16CE - APC control register 2
1244 API d_drp_afc_add_api; // 0x16CF - Address where AFC value needs to be written
1245 API a_drp_holes_2[12]; // 0x16D0
1246 API a_drp_ramp[20]; // 0x16DC - Power ramp up/down in DRP registers format
1247 API a_drp_holes_3[271]; // 0x16F0
1248
1249
1250 API d_dsp_write_debug_pointer; // 0x17FF
1251
1252 #if (MELODY_E2)
1253 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; // 0x1800
1254 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
1255 API a_dsp_after_trace_holes[7440-(SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE + SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT)];
1256 #else
1257 API a_dsp_trace[C_DEBUG_BUFFER_SIZE]; // 0x1800;
1258 API a_dsp_after_trace_holes[7440-C_DEBUG_BUFFER_SIZE]; // 0x1800 + C_DEBUG_BUFFER_SIZE
1259 // In this region MP3 variables are placed + holes
1260 #endif
1261
1262 #if (L1_PCM_EXTRACTION)
1263 API a_pcm_api_download[160];
1264 API a_pcm_api_upload[160];
1265 API a_pcm_holes1[8];
1266 API d_pcm_api_upload;
1267 API d_pcm_api_download;
1268 API d_pcm_api_error;
1269 API a_pcm_holes2[1181];
1270 #else
1271 API a_pcm_holes[1512];
1272 #endif
1273
1274 #if REL99
1275 #if FF_EMR
1276 API a_mean_cv_bep_page_0[3];//0x3AF8
1277 API a_mean_cv_bep_padding_0;
1278 API a_mean_cv_bep_page_1[3];
1279 API a_mean_cv_bep_padding_1;
1280 API a_emr_holes2[378];
1281 #endif
1282 #else // L1_R99
1283 API a_emr_holes1[386];
1284 #endif // L1_R99
1285
1286 // SAIC related
1287 API a_swh_hole[16]; // 0x3C7A
1288 API d_swh_flag_ndb; // 0x3C8A - SWH (whitening) on / off flag
1289 API d_swh_Clipping_Threshold_ndb; // 0x3C8B - Threshold to which the DSP shall clip the SNR
1290
1291 // A5/3 related
1292 API a_a5_kc[8]; // 0x3C8C
1293
1294 // DCO related
1295 API d_dco_samples_per_symbol; // 0x3C94 No. of samples per symbol (IQ pair)
1296 API d_dco_fcw; // 0x3C95 Control word to tell the IF Frequency
1297 API a_dco_hole[15]; // 0x3C96 Hole related to DCO
1298
1299 // A5/3 related
1300 // API a_a5_holes[801]; // 0x3CA5
1301
1302 #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 ))
1303 API a_a5_holes[286]; // 0x3CA5
1304 API d_chase_comb_ctrl; // 0x3DC3 Control for the chase combine feature
1305 API a_a5_holes1[514]; // 0x3DC4
1306 #else
1307 // A5/3 related
1308 API a_a5_holes[801]; // 0x3CA5
1309 #endif /* (FF_REPEATED_SACCH == 1) */
1310
1311
1312
1313 }
1314 T_NDB_MCU_DSP;
1315
1316 #elif (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) // NDB GSM
473 typedef struct 1317 typedef struct
474 { 1318 {
475 // MISC Tasks 1319 // MISC Tasks
476 API d_dsp_page; 1320 API d_dsp_page;
477 1321
517 API p_debug_amr; 1361 API p_debug_amr;
518 #else 1362 #else
519 API d_hole_debug_amr; 1363 API d_hole_debug_amr;
520 #endif 1364 #endif
521 1365
522 #if (CHIPSET == 12) 1366 #if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2
523 #if (DSP == 35) || (DSP == 36) 1367 #if (DSP == 35) || (DSP == 36) || (DSP == 37)
524 API d_hole2_ndb[1]; 1368 API d_hole2_ndb[1];
525 API d_mcsi_select; 1369 API d_mcsi_select;
526 #else 1370 #else
527 API d_hole2_ndb[2]; 1371 API d_hole2_ndb[2];
528 #endif 1372 #endif
550 API d_bulioff; 1394 API d_bulioff;
551 API d_bulqoff; 1395 API d_bulqoff;
552 API d_dai_onoff; 1396 API d_dai_onoff;
553 API d_auxdac; 1397 API d_auxdac;
554 1398
555 #if (ANALOG == 1) 1399 #if (ANLG_FAM == 1)
556 API d_vbctrl; 1400 API d_vbctrl;
557 #elif ((ANALOG == 2) || (ANALOG == 3)) 1401 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
558 API d_vbctrl1; 1402 API d_vbctrl1;
559 #endif 1403 #endif
560 1404
561 API d_bbctrl; 1405 API d_bbctrl;
562 1406
563 // Monitoring tasks control (MCU <- DSP) 1407 // Monitoring tasks control (MCU <- DSP)
564 // FB task 1408 // FB task
565 API d_fb_det; // FB detection result. (1 for FOUND). 1409 API d_fb_det; // FB detection result. (1 for FOUND).
658 1502
659 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory) 1503 // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
660 API d_gea_mode_ovly; 1504 API d_gea_mode_ovly;
661 API a_gea_kc_ovly[4]; 1505 API a_gea_kc_ovly[4];
662 1506
663 #if (ANALOG == 3) 1507 #if (ANLG_FAM == 3)
664 // SYREN specific registers 1508 // SYREN specific registers
665 API d_vbpop; 1509 API d_vbpop;
666 API d_vau_delay_init; 1510 API d_vau_delay_init;
667 API d_vaud_cfg; 1511 API d_vaud_cfg;
668 API d_vauo_onoff; 1512 API d_vauo_onoff;
669 API d_vaus_vol; 1513 API d_vaus_vol;
670 API d_vaud_pll; 1514 API d_vaud_pll;
671 API d_hole3_ndb[1]; 1515 API d_togbr2;
672 #elif ((ANALOG == 1) || (ANALOG == 2)) 1516 #elif ((ANLG_FAM == 1) || (ANLG_FAM == 2))
673
674 API d_hole3_ndb[7]; 1517 API d_hole3_ndb[7];
675
676 #endif 1518 #endif
677 1519
678 // word used for the init of USF threshold 1520 // word used for the init of USF threshold
679 API d_thr_usf_detect; 1521 API d_thr_usf_detect;
680 1522
724 API a_data_buf_dl[37]; 1566 API a_data_buf_dl[37];
725 1567
726 // GTT API mapping for DSP code 34 (for test only) 1568 // GTT API mapping for DSP code 34 (for test only)
727 #if (L1_GTT == 1) 1569 #if (L1_GTT == 1)
728 API d_tty_status; 1570 API d_tty_status;
729 API d_tty_detect_thres;
730 API d_ctm_detect_shift; 1571 API d_ctm_detect_shift;
731 API d_tty_fa_thres; 1572 API d_tty2x_baudot_mod_amplitude_scale;
732 API d_tty_mod_norm; 1573 API d_tty2x_samples_per_baudot_stop_bit;
733 API d_tty_reset_buffer_ul; 1574 API d_tty_reset_buffer_ul;
734 API d_tty_loop_ctrl; 1575 API d_tty_loop_ctrl;
735 API p_tty_loop_buffer; 1576 API p_tty_loop_buffer;
1577 API d_ctm_mod_norm;
1578 API d_tty2x_offset_normalization;
1579 API d_tty2x_threshold_startbit;
1580 API d_tty2x_threshold_diff;
1581 API d_tty2x_duration_startdetect;
1582 API d_tty2x_startbit_thres;
736 #else 1583 #else
737 API a_tty_holes[8]; 1584 API a_tty_holes[13];
738 #endif 1585 #endif
739 1586
740 API a_sr_holes0[414]; 1587 API a_sr_holes0[409];
1588
741 1589
742 #if (L1_NEW_AEC) 1590 #if (L1_NEW_AEC)
743 // new AEC 1591 // new AEC
744 API d_cont_filter; 1592 API d_cont_filter;
745 API d_granularity_att; 1593 API d_granularity_att;
757 API a_new_aec_holes[12]; 1605 API a_new_aec_holes[12];
758 #endif // L1_NEW_AEC 1606 #endif // L1_NEW_AEC
759 1607
760 // Speech recognition model 1608 // Speech recognition model
761 API a_sr_holes1[145]; 1609 API a_sr_holes1[145];
1610
1611 // Correction of PR G23M/L1_MCU-SPR-15494
1612 #if ((CHIPSET == 12) || (CHIPSET == 4) || (CODE_VERSION == SIMULATION))
762 API d_cport_init; 1613 API d_cport_init;
763 API d_cport_ctrl; 1614 API d_cport_ctrl;
764 API a_cport_cfr[2]; 1615 API a_cport_cfr[2];
765 API d_cport_tcl_tadt; 1616 API d_cport_tcl_tadt;
766 API d_cport_tdat; 1617 API d_cport_tdat;
767 API d_cport_tvs; 1618 API d_cport_tvs;
768 API d_cport_status; 1619 API d_cport_status;
769 API d_cport_reg_value; 1620 API d_cport_reg_value;
770 1621
771 API a_cport_holes[1011]; 1622 API a_cport_holes[1011];
1623 #else // CHIPSET != 12
1624 API a_cport_holes[1020];
1625 #endif // CHIPSET == 12
772 1626
773 API a_model[1041]; 1627 API a_model[1041];
774 1628
775 // EOTD buffer 1629 // EOTD buffer
776 #if (L1_EOTD==1) 1630 #if (L1_EOTD==1)
790 #if (L1_VOICE_MEMO_AMR) 1644 #if (L1_VOICE_MEMO_AMR)
791 API d_amms_ul_voc; 1645 API d_amms_ul_voc;
792 #else 1646 #else
793 API a_voice_memo_amr_holes[1]; 1647 API a_voice_memo_amr_holes[1];
794 #endif 1648 #endif
795 API d_thr_onset_afs; // thresh detection ONSET AFS 1649 API d_thr_onset_afs; // thresh detection ONSET AFS
796 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS 1650 API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
797 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS 1651 API d_thr_ratscch_afs; // thresh detection RATSCCH AFS
798 API d_thr_update_afs; // thresh detection SID_UPDATE AFS 1652 API d_thr_update_afs; // thresh detection SID_UPDATE AFS
799 API d_thr_onset_ahs; // thresh detection ONSET AHS 1653 API d_thr_onset_ahs; // thresh detection ONSET AHS
800 API d_thr_sid_ahs; // thresh detection SID frames AHS 1654 API d_thr_sid_ahs; // thresh detection SID frames AHS
801 API d_thr_ratscch_marker;// thresh detection RATSCCH MARKER 1655 API d_thr_ratscch_marker; // thresh detection RATSCCH MARKER
802 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA 1656 API d_thr_sp_dgr; // thresh detection SPEECH DEGRADED/NO_DATA
803 API d_thr_soft_bits; 1657 API d_thr_soft_bits;
1658
1659 #if ((CODE_VERSION == SIMULATION) || (DSP != 37))
804 #if (MELODY_E2) 1660 #if (MELODY_E2)
805 API d_melody_e2_osc_stop; 1661 API d_melody_e2_osc_stop;
806 API d_melody_e2_osc_active; 1662 API d_melody_e2_osc_active;
807 API d_melody_e2_semaphore; 1663 API d_melody_e2_semaphore;
808 API a_melody_e2_osc[16][3]; 1664 API a_melody_e2_osc[16][3];
809 API d_melody_e2_globaltimefactor; 1665 API d_melody_e2_globaltimefactor;
810 API a_melody_e2_instrument_ptr[8]; 1666 API a_melody_e2_instrument_ptr[8];
811 API d_melody_e2_deltatime; 1667 API d_melody_e2_deltatime;
812 1668 #else
813 #if (AMR_THRESHOLDS_WORKAROUND) 1669 API d_melody_e2_holes[61];
814 API a_d_macc_thr_afs[8]; 1670 #endif
815 API a_d_macc_thr_ahs[6]; 1671 #else // (DSP == 37)
1672 API a_amrschd_debug[30]; // 0x1500
1673 #if (W_A_AMR_THRESHOLDS)
1674 API a_d_macc_thr_afs[8]; // 0x151E
1675 API a_d_macc_thr_ahs[6]; // 0x1526
1676 #else
1677 API a_d_macc_thr_holes[14]; // 0x151E
1678 #endif
1679 API d_melody_e2_holes[17]; //0x152C - This is not a melody E2 hole; But named like that;
1680 #endif
1681
1682 #if ((CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)) || (CODE_VERSION == SIMULATION)) // Calypso+ or Perseus2 or Samson
1683 API d_vol_ul_level;
1684 API d_vol_dl_level;
1685 API d_vol_speed;
1686 API d_sidetone_level;
1687
1688 // Audio control area
1689 API d_es_ctrl;
1690 API d_anr_ul_ctrl;
1691
1692 #if ((DSP == 36) || (DSP == 37))
1693
1694 API d_aqi_ctrl_hole1_1[3];
1695 #if (L1_SAIC != 0)
1696 API d_swh_flag_ndb;
1697 API d_swh_Clipping_Threshold_ndb;
1698 #else
1699 API d_swh_hole[2];
1700 #endif
1701 API d_aqi_ctrl_hole1_2[1];
816 #else 1702 #else
817 API a_melody_e2_holes0[14]; 1703 API d_aqi_ctrl_hole1[6]; // Reserved for future UL modules
818 #endif 1704 #endif
819 1705 API d_iir_dl_ctrl;
820 API a_melody_e2_holes1[693]; 1706 API d_lim_dl_ctrl;
1707 API d_aqi_ctrl_hole2[4]; // Reserved for future DL modules
1708 API d_aqi_status;
1709
1710 #if (L1_IIR == 1)
1711 API d_iir_input_scaling;
1712 API d_iir_fir_scaling;
1713 API d_iir_input_gain_scaling;
1714 API d_iir_output_gain_scaling;
1715 API d_iir_output_gain;
1716 API d_iir_feedback;
1717 API d_iir_nb_iir_blocks;
1718 API d_iir_nb_fir_coefs;
1719 API a_iir_iir_coefs[80];
1720 API a_iir_fir_coefs[32];
1721 #else
1722 API d_iir_hole[120];
1723 #endif
1724
1725 #if (L1_ANR == 1)
1726 API d_anr_min_gain;
1727 API d_anr_vad_thr;
1728 API d_anr_gamma_slow;
1729 API d_anr_gamma_fast;
1730 API d_anr_gamma_gain_slow;
1731 API d_anr_gamma_gain_fast;
1732 API d_anr_thr2;
1733 API d_anr_thr4;
1734 API d_anr_thr5;
1735 API d_anr_mean_ratio_thr1;
1736 API d_anr_mean_ratio_thr2;
1737 API d_anr_mean_ratio_thr3;
1738 API d_anr_mean_ratio_thr4;
1739 API d_anr_div_factor_shift;
1740 API d_anr_ns_level;
1741 #else
1742 API d_anr_hole[15];
1743 #endif
1744
1745 #if (L1_LIMITER == 1)
1746 API a_lim_mul_low[2];
1747 API a_lim_mul_high[2];
1748 API d_lim_gain_fall_q15;
1749 API d_lim_gain_rise_q15;
1750 API d_lim_block_size;
1751 API d_lim_nb_fir_coefs;
1752 API d_lim_slope_update_period;
1753 API a_lim_filter_coefs[16];
1754 #else
1755 API d_lim_hole[25];
1756 #endif
1757 #if (L1_ES == 1)
1758 API d_es_mode;
1759 API d_es_gain_dl;
1760 API d_es_gain_ul_1;
1761 API d_es_gain_ul_2;
1762 API d_es_tcl_fe_ls_thr;
1763 API d_es_tcl_dt_ls_thr;
1764 API d_es_tcl_fe_ns_thr;
1765 API d_es_tcl_dt_ns_thr;
1766 API d_es_tcl_ne_thr;
1767 API d_es_ref_ls_pwr;
1768 API d_es_switching_time;
1769 API d_es_switching_time_dt;
1770 API d_es_hang_time;
1771 API a_es_gain_lin_dl_vect[4];
1772 API a_es_gain_lin_ul_vect[4];
1773 #else
1774 API d_es_hole[21];
1775 #endif
1776
1777 #else // CALYPSO+ or PERSEUS2
1778 API a_calplus_holes[200];
1779 #endif
1780
1781 #if (W_A_AMR_THRESHOLDS)
1782 API d_holes[492];
1783 #if (CODE_VERSION == SIMULATION) || (DSP != 37)
1784 API a_d_macc_thr_afs[8]; // In ROM37 this is moved from 0x17F1 to 0x151E
1785 API a_d_macc_thr_ahs[6];
1786 #else
1787 API d_holes_rom37[14]; // In ROM37 this is moved from 0x17F1 to 0x151E
1788 #endif
1789 API d_one_hole[1];
1790 #else
1791 API d_holes[507];
1792 #endif
1793
1794 #if (MELODY_E2)
821 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE]; 1795 API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
822 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT]; 1796 API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
823 #else 1797 #endif
824 API d_holes[61];
825 #if (AMR_THRESHOLDS_WORKAROUND)
826 API a_d_macc_thr_afs[8];
827 API a_d_macc_thr_ahs[6];
828 #endif
829 #endif
830
831 } 1798 }
832 T_NDB_MCU_DSP; 1799 T_NDB_MCU_DSP;
833 #elif (DSP == 33) // NDB GSM 1800 #elif (DSP == 33) // NDB GSM
834 typedef struct 1801 typedef struct
835 { 1802 {
894 API d_bulioff; 1861 API d_bulioff;
895 API d_bulqoff; 1862 API d_bulqoff;
896 API d_dai_onoff; 1863 API d_dai_onoff;
897 API d_auxdac; 1864 API d_auxdac;
898 1865
899 #if (ANALOG == 1) 1866 #if (ANLG_FAM == 1)
900 API d_vbctrl; 1867 API d_vbctrl;
901 #elif ((ANALOG == 2) || (ANALOG == 3)) 1868 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
902 API d_vbctrl1; 1869 API d_vbctrl1;
903 #endif 1870 #endif
904 1871
905 API d_bbctrl; 1872 API d_bbctrl;
906 1873
1155 API d_tch_mode; // TCH mode register. 2122 API d_tch_mode; // TCH mode register.
1156 // bit [0..1] -> b_dai_mode. 2123 // bit [0..1] -> b_dai_mode.
1157 // bit [2] -> b_dtx. 2124 // bit [2] -> b_dtx.
1158 2125
1159 // OMEGA...........................(MCU -> DSP). 2126 // OMEGA...........................(MCU -> DSP).
1160 #if ((ANALOG == 1) || (ANALOG == 2)) 2127 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
1161 API a_ramp[16]; 2128 API a_ramp[16];
1162 #if (MELODY_E1) 2129 #if (MELODY_E1)
1163 API d_melo_osc_used; 2130 API d_melo_osc_used;
1164 API d_melo_osc_active; 2131 API d_melo_osc_active;
1165 API a_melo_note0[4]; 2132 API a_melo_note0[4];
1213 API d_bulioff; 2180 API d_bulioff;
1214 API d_bulqoff; 2181 API d_bulqoff;
1215 API d_dai_onoff; 2182 API d_dai_onoff;
1216 API d_auxdac; 2183 API d_auxdac;
1217 2184
1218 #if (ANALOG == 1) 2185 #if (ANLG_FAM == 1)
1219 API d_vbctrl; 2186 API d_vbctrl;
1220 #elif (ANALOG == 2) 2187 #elif (ANLG_FAM == 2)
1221 API d_vbctrl1; 2188 API d_vbctrl1;
1222 #endif 2189 #endif
1223 2190
1224 API d_bbctrl; 2191 API d_bbctrl;
1225 #else 2192 #else
1226 #error DSPCODE not supported with given ANALOG 2193 #error DSPCODE not supported with given ANALOG
1227 #endif //(ANALOG)1, 2 2194 #endif //(ANALOG)1, 2
1228 //...................................(MCU -> DSP). 2195 //...................................(MCU -> DSP).
1229 API a_sch26[5]; // Header + SB information, array of 5 words. 2196 API a_sch26[5]; // Header + SB information, array of 5 words.
1230 2197
1305 API d_audio_status; 2272 API d_audio_status;
1306 2273
1307 #if (L1_EOTD ==1) 2274 #if (L1_EOTD ==1)
1308 API a_eotd_hole[369]; 2275 API a_eotd_hole[369];
1309 2276
1310 API d_eotd_first; 2277 API d_eotd_first;
1311 API d_eotd_max; 2278 API d_eotd_max;
1312 API d_eotd_nrj_high; 2279 API d_eotd_nrj_high;
1313 API d_eotd_nrj_low; 2280 API d_eotd_nrj_low;
1314 API a_eotd_crosscor[18]; 2281 API a_eotd_crosscor[18];
1315 #endif 2282 #endif
1316 #endif 2283 #endif
1317 } 2284 }
1318 T_NDB_MCU_DSP; 2285 T_NDB_MCU_DSP;
1319 2286
1320 2287
1385 // bit [0..1] -> b_dai_mode. 2352 // bit [0..1] -> b_dai_mode.
1386 // bit [2] -> b_dtx. 2353 // bit [2] -> b_dtx.
1387 2354
1388 // OMEGA...........................(MCU -> DSP). 2355 // OMEGA...........................(MCU -> DSP).
1389 2356
1390 #if ((ANALOG == 1) || (ANALOG == 2)) 2357 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
1391 API a_ramp[16]; 2358 API a_ramp[16];
1392 #if (MELODY_E1) 2359 #if (MELODY_E1)
1393 API d_melo_osc_used; 2360 API d_melo_osc_used;
1394 API d_melo_osc_active; 2361 API d_melo_osc_active;
1395 API a_melo_note0[4]; 2362 API a_melo_note0[4];
1441 API d_apcoff; 2408 API d_apcoff;
1442 API d_bulioff; 2409 API d_bulioff;
1443 API d_bulqoff; 2410 API d_bulqoff;
1444 API d_dai_onoff; 2411 API d_dai_onoff;
1445 API d_auxdac; 2412 API d_auxdac;
1446 #if (ANALOG == 1) 2413 #if (ANLG_FAM == 1)
1447 API d_vbctrl; 2414 API d_vbctrl;
1448 #elif (ANALOG == 2) 2415 #elif (ANLG_FAM == 2)
1449 API d_vbctrl1; 2416 API d_vbctrl1;
1450 #endif 2417 #endif
1451 API d_bbctrl; 2418 API d_bbctrl;
1452 2419
1453 #else 2420 #else
1454 #error DSPCODE not supported with given ANALOG 2421 #error DSPCODE not supported with given ANALOG
1455 #endif //(ANALOG)1, 2 2422 #endif //(ANALOG)1, 2
1456 //...................................(MCU -> DSP). 2423 //...................................(MCU -> DSP).
1457 API a_sch26[5]; // Header + SB information, array of 5 words. 2424 API a_sch26[5]; // Header + SB information, array of 5 words.
1458 2425
1459 // TONES.............................(MCU -> DSP) 2426 // TONES.............................(MCU -> DSP)
1537 #endif 2504 #endif
1538 } 2505 }
1539 T_NDB_MCU_DSP; 2506 T_NDB_MCU_DSP;
1540 #endif 2507 #endif
1541 2508
1542 #if (DSP == 34) || (DSP == 35) || (DSP == 36) 2509 #if (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
1543 typedef struct 2510 typedef struct
1544 { 2511 {
1545 API_SIGNED d_transfer_rate; 2512 API_SIGNED d_transfer_rate; // 0x0C31
1546 2513
1547 // Common GSM/GPRS 2514 // Common GSM/GPRS
1548 // These words specified the latencies to applies on some peripherics 2515 // These words specified the latencies to applies on some peripherics
1549 API_SIGNED d_lat_mcu_bridge; 2516 API_SIGNED d_lat_mcu_bridge;
1550 API_SIGNED d_lat_mcu_hom2sam; 2517 API_SIGNED d_lat_mcu_hom2sam;
1556 2523
1557 API_SIGNED d_misc_config; 2524 API_SIGNED d_misc_config;
1558 2525
1559 API_SIGNED d_cn_sw_workaround; 2526 API_SIGNED d_cn_sw_workaround;
1560 2527
1561 API_SIGNED d_hole2_param[4]; 2528 API_SIGNED d_hole2_param[4]; // 0x0C39
1562 2529
1563 //...................................Frequency Burst. 2530 //...................................Frequency Burst.
1564 API_SIGNED d_fb_margin_beg; 2531 API_SIGNED d_fb_margin_beg; // 0x0C3D
1565 API_SIGNED d_fb_margin_end; 2532 API_SIGNED d_fb_margin_end;
1566 API_SIGNED d_nsubb_idle; 2533 API_SIGNED d_nsubb_idle;
1567 API_SIGNED d_nsubb_dedic; 2534 API_SIGNED d_nsubb_dedic;
1568 API_SIGNED d_fb_thr_det_iacq; 2535 API_SIGNED d_fb_thr_det_iacq;
1569 API_SIGNED d_fb_thr_det_track; 2536 API_SIGNED d_fb_thr_det_track;
1588 API_SIGNED d_v42b_switch_min; 2555 API_SIGNED d_v42b_switch_min;
1589 API_SIGNED d_v42b_switch_max; 2556 API_SIGNED d_v42b_switch_max;
1590 API_SIGNED d_v42b_reset_delay; 2557 API_SIGNED d_v42b_reset_delay;
1591 2558
1592 //...................................TCH Half Speech. 2559 //...................................TCH Half Speech.
1593 API_SIGNED d_ldT_hr; 2560 API_SIGNED d_ldT_hr; // 0x0C53
1594 API_SIGNED d_maccthresh_hr; 2561 API_SIGNED d_maccthresh_hr;
1595 API_SIGNED d_maccthresh1_hr; 2562 API_SIGNED d_maccthresh1_hr;
1596 API_SIGNED d_gu_hr; 2563 API_SIGNED d_gu_hr;
1597 API_SIGNED d_go_hr; 2564 API_SIGNED d_go_hr;
1598 API_SIGNED d_b_hr; 2565 API_SIGNED d_b_hr;
1608 API_SIGNED c_b_efr; 2575 API_SIGNED c_b_efr;
1609 API_SIGNED c_sm_efr; 2576 API_SIGNED c_sm_efr;
1610 API_SIGNED c_attmax_efr; 2577 API_SIGNED c_attmax_efr;
1611 2578
1612 //...................................CHED 2579 //...................................CHED
1613 API_SIGNED d_sd_min_thr_tchfs; 2580 API_SIGNED d_sd_min_thr_tchfs; // 0x0C63
1614 API_SIGNED d_ma_min_thr_tchfs; 2581 API_SIGNED d_ma_min_thr_tchfs;
1615 API_SIGNED d_md_max_thr_tchfs; 2582 API_SIGNED d_md_max_thr_tchfs;
1616 API_SIGNED d_md1_max_thr_tchfs; 2583 API_SIGNED d_md1_max_thr_tchfs;
1617 2584
1618 API_SIGNED d_sd_min_thr_tchhs; 2585 API_SIGNED d_sd_min_thr_tchhs;
1635 API_SIGNED d_y_max; 2602 API_SIGNED d_y_max;
1636 API_SIGNED d_wed_diff_threshold; 2603 API_SIGNED d_wed_diff_threshold;
1637 API_SIGNED d_mabfi_min_thr_tchhs; 2604 API_SIGNED d_mabfi_min_thr_tchhs;
1638 2605
1639 // FACCH module 2606 // FACCH module
1640 API_SIGNED d_facch_thr; 2607 API_SIGNED d_facch_thr; // 0x0C79
1641 2608
1642 // IDS module 2609 // IDS module
1643 API_SIGNED d_max_ovsp_ul; 2610 API_SIGNED d_max_ovsp_ul; //
1644 API_SIGNED d_sync_thres; 2611 API_SIGNED d_sync_thres;
1645 API_SIGNED d_idle_thres; 2612 API_SIGNED d_idle_thres;
1646 API_SIGNED d_m1_thres; 2613 API_SIGNED d_m1_thres;
1647 API_SIGNED d_max_ovsp_dl; 2614 API_SIGNED d_max_ovsp_dl;
1648 API_SIGNED d_gsm_bgd_mgt; 2615 API_SIGNED d_gsm_bgd_mgt;
1649 2616
1650 // FIR coefficients 2617 // FIR coefficients
1651 API a_fir_holes[4]; 2618 API a_fir_holes[4];
1652 API a_fir31_uplink[31]; 2619 API a_fir31_uplink[31]; // 0x0C84
1653 API a_fir31_downlink[31]; 2620 API a_fir31_downlink[31];
1654 } 2621 }
1655 T_PARAM_MCU_DSP; 2622 T_PARAM_MCU_DSP;
1656 #elif (DSP == 33) 2623 #elif (DSP == 33)
1657 typedef struct 2624 typedef struct
1913 UWORD8 t3; // FN modulo 51. 2880 UWORD8 t3; // FN modulo 51.
1914 UWORD8 tc; // Scell: TC 2881 UWORD8 tc; // Scell: TC
1915 UWORD8 fn_in_report; // FN modulo 102 or 104. 2882 UWORD8 fn_in_report; // FN modulo 102 or 104.
1916 UWORD16 fn_mod42432; // FN modulo 42432. 2883 UWORD16 fn_mod42432; // FN modulo 42432.
1917 UWORD8 fn_mod13; // FN modulo 13. 2884 UWORD8 fn_mod13; // FN modulo 13.
2885 UWORD8 fn_mod13_mod4; // FN modulo 13 modulo 4.
1918 #if L1_GPRS 2886 #if L1_GPRS
1919 UWORD8 fn_mod52; // FN modulo 52. 2887 UWORD8 fn_mod52; // FN modulo 52.
1920 UWORD8 fn_mod104; // FN modulo 104. 2888 UWORD8 fn_mod104; // FN modulo 104.
1921 UWORD8 fn_mod13_mod4; // FN modulo 13 modulo 4.
1922 UWORD32 block_id; // Block ID 2889 UWORD32 block_id; // Block ID
1923 #endif 2890 #endif
1924 } 2891 }
1925 T_TIME_INFO; 2892 T_TIME_INFO;
1926 2893
2016 UWORD32 qual_nbr_meas_sub; // Subset: nbr meas. of rxqual. 2983 UWORD32 qual_nbr_meas_sub; // Subset: nbr meas. of rxqual.
2017 UWORD8 dtx_used; // Set when DTX as been used in current reporting period. 2984 UWORD8 dtx_used; // Set when DTX as been used in current reporting period.
2018 } 2985 }
2019 T_SMEAS; 2986 T_SMEAS;
2020 2987
2988
2989 #if REL99
2990 #if FF_EMR
2991 typedef struct
2992 {
2993
2994 WORD16 rxlev_val_acc; // Accumulated value of RXLEV_VAL
2995 UWORD8 rxlev_val_nbr_meas; // Number of RXLEV_VAL value accumulated on block bases
2996 UWORD8 nbr_rcvd_blocks; // Number of correctly decoded blocks excluding SACCH FACCH etc Refer 05.08
2997 UWORD32 mean_bep_block_acc; // Accumulated value of MEAN_BEP
2998 UWORD16 cv_bep_block_acc; // Accumulated value of CV_BEP
2999 UWORD8 mean_bep_block_num; // Number of blocks over MEAN_BEP is accumulated.
3000 UWORD8 cv_bep_block_num; // Number of blocks over CV_BEP is accumulated.
3001 }
3002 T_SMEAS_EMR;
3003
3004 typedef struct
3005 {
3006 UWORD8 task; // task id (TCHTH, TCHTF, DDL, ADL, TCHA)
3007 UWORD8 burst_id; // burst ID only used for SDCCH.
3008 UWORD8 channel_mode; // channel mode in case of half / full rate
3009 UWORD8 subchannel; // subchannel number
3010 UWORD32 normalised_fn_mod13_mod4; // used to find block boundary in case of half rate
3011 BOOL facch_present; // necessary for processing to indicate reception of Facch
3012 BOOL facch_fire1; // necessary for processing to indicate good/bad reception of Facch
3013 UWORD8 a_ntd; // used for Data : FCS OK/FCS KO
3014 UWORD8 a_dd_0_blud; // check data/speech block presence on sub 0
3015 UWORD8 a_dd_0_bfi; // check data/speech block integrity on sub 0
3016 UWORD8 a_dd_1_blud; // check data/speech block presence on sub 1
3017 UWORD8 a_dd_1_bfi; // check data/speech block integrity on sub 1
3018 UWORD8 b_m1; // used for Data 14.4 M1 = 1 for second half block RLP
3019 UWORD8 b_f48blk_dl; // used for Data 4.8 : = 1 for second half block RLP
3020 UWORD8 b_ce; // used for Data : transparent / not transparent
3021 UWORD8 a_cd_fire1; // check SDCCH bloch integrity
3022 UWORD8 sid_present_sub0; // check sid present on sub 0
3023 UWORD8 sid_present_sub1; // check sid present on sub 1
3024 #if (AMR ==1)
3025 BOOL amr_facch_present; // necessary for AMR processing to indicate reception of Facch
3026 BOOL amr_facch_fire1; // necessary for AMR processing to indicate good/bad reception of Facch
3027 UWORD8 b_ratscch_blud; // check ratscch present
3028 UWORD8 ratscch_rxtype; // check type of AMR block
3029 UWORD8 amr_rx_type_sub0; // AMR type on sub 0
3030 UWORD8 amr_rx_type_sub1; // AMR type on sub 1
3031 #endif
3032 }
3033 T_EMR_PARAMS;
3034 #endif //FF_EMR
3035 #endif //REL99
3036
2021 /***************************************************************************************/ 3037 /***************************************************************************************/
2022 /* */ 3038 /* */
2023 /***************************************************************************************/ 3039 /***************************************************************************************/
2024 typedef struct 3040 typedef struct
2025 { 3041 {
2100 3116
2101 UWORD8 ms_ctrl; 3117 UWORD8 ms_ctrl;
2102 UWORD8 ms_ctrl_d; 3118 UWORD8 ms_ctrl_d;
2103 UWORD8 ms_ctrl_dd; 3119 UWORD8 ms_ctrl_dd;
2104 3120
2105 UWORD8 used_il [2]; 3121 UWORD8 used_il [C_BA_PM_MEAS];
2106 UWORD8 used_il_d [2]; 3122 UWORD8 used_il_d [C_BA_PM_MEAS];
2107 UWORD8 used_il_dd[2]; 3123 UWORD8 used_il_dd[C_BA_PM_MEAS];
2108 3124
2109 UWORD8 used_lna [2]; 3125 UWORD8 used_lna [C_BA_PM_MEAS];
2110 UWORD8 used_lna_d [2]; 3126 UWORD8 used_lna_d [C_BA_PM_MEAS];
2111 UWORD8 used_lna_dd[2]; 3127 UWORD8 used_lna_dd[C_BA_PM_MEAS];
2112 3128
2113 T_MEAS_INFO A[32+1]; // list of 32 neighbors + 1 serving. 3129 T_MEAS_INFO A[32+1]; // list of 32 neighbors + 1 serving.
2114 3130
2115 BOOL new_list_present; 3131 BOOL new_list_present;
2116 T_NEW_BA_LIST new_list; 3132 T_NEW_BA_LIST new_list;
2222 // For handover... 3238 // For handover...
2223 UWORD8 ho_acc; // Handover access (part of HO reference) 3239 UWORD8 ho_acc; // Handover access (part of HO reference)
2224 WORD32 ho_acc_to_send; // Set to 4 for SYNC HO and to -1 for ASYNC HO. 3240 WORD32 ho_acc_to_send; // Set to 4 for SYNC HO and to -1 for ASYNC HO.
2225 UWORD8 t3124; // Timer used in Async. Ho. 3241 UWORD8 t3124; // Timer used in Async. Ho.
2226 3242
3243 #if ((REL99 == 1) && (FF_BHO == 1))
3244 // For blind handover...
3245 BOOL report_time_diff;
3246 BOOL nci;
3247 UWORD8 real_time_difference;
3248 WORD32 HO_SignalCode;
3249 #endif
3250
2227 // For DPAGC algorithms purpose 3251 // For DPAGC algorithms purpose
2228 UWORD8 G_all[DPAGC_FIFO_LEN]; 3252 UWORD8 G_all[DPAGC_FIFO_LEN];
2229 UWORD8 G_DTX[DPAGC_FIFO_LEN]; 3253 UWORD8 G_DTX[DPAGC_FIFO_LEN];
2230 #if (AMR == 1) 3254 #if (AMR == 1)
2231 UWORD8 G_amr[DPAGC_AMR_FIFO_LEN]; 3255 UWORD8 G_amr[DPAGC_AMR_FIFO_LEN];
2276 BOOL pwrc; // Flag used to reject serving pwr meas. on beacon. 3300 BOOL pwrc; // Flag used to reject serving pwr meas. on beacon.
2277 3301
2278 BOOL handover_fail_mode; // Flag used to indicate that the L1 wait for an handover fail request 3302 BOOL handover_fail_mode; // Flag used to indicate that the L1 wait for an handover fail request
2279 #if (AMR == 1) 3303 #if (AMR == 1)
2280 BOOL sync_amr; // Flag used to tell to the DSP that a new AMR paramters is ready in the NDB. 3304 BOOL sync_amr; // Flag used to tell to the DSP that a new AMR paramters is ready in the NDB.
3305 #endif // (AMR == 1)
3306
3307 #if ((REL99 == 1) && (FF_BHO == 1))
3308 // For blind handover...
3309 BOOL handover_type;
3310 BOOL long_rem_handover_type;
3311 UWORD16 bcch_carrier_of_nbr_cell;
3312 UWORD32 fn_offset;
3313 UWORD32 time_alignment;
2281 #endif 3314 #endif
2282 } 3315 }
2283 T_DEDIC_PARAM; 3316 T_DEDIC_PARAM;
2284 3317
2285 /*************************************************************/ 3318 /*************************************************************/
2301 3334
2302 // flags and variables for wake-up .... 3335 // flags and variables for wake-up ....
2303 UWORD8 Os_ticks_required; // TRUE : Os ticks to recover 3336 UWORD8 Os_ticks_required; // TRUE : Os ticks to recover
2304 UWORD8 frame_adjust; // TRUE : adjust 1 frame 3337 UWORD8 frame_adjust; // TRUE : adjust 1 frame
2305 UWORD32 sleep_duration; // sleep duration computed at wakeup 3338 UWORD32 sleep_duration; // sleep duration computed at wakeup
3339 UWORD32 wakeup_time; // frame number of last wakeup
3340 UWORD16 wake_up_int_id; // Interrupt waking up the target
3341 UWORD8 wakeup_type; // Type of the interrupt
3342 UWORD8 why_big_sleep; // Type of the big sleep
2306 3343
2307 // flag for sleep .... 3344 // flag for sleep ....
2308 UWORD8 sleep_performed; // NONE,SMALL,BIG,DEEP,ALL 3345 UWORD8 sleep_performed; // NONE,SMALL,BIG,DEEP,ALL
2309 3346
2310 // status of clocks modules .... 3347 // status of clocks modules ....
2319 UWORD32 c_delta_hf_update; // UPDATE state 3356 UWORD32 c_delta_hf_update; // UPDATE state
2320 3357
2321 // trace gauging parameters 3358 // trace gauging parameters
2322 UWORD8 state; // state of the gauging 3359 UWORD8 state; // state of the gauging
2323 UWORD32 lf; // Number of the 32KHz 3360 UWORD32 lf; // Number of the 32KHz
2324 UWORD32 hf; // HF: nb_hf( Number of the 13MHz *6 ) 3361 UWORD32 hf; // HF: nb_hf( Number of the 13MHz *6 )
2325 UWORD32 root; // root & frac: the ratio of the HF & LF in each state. 3362 UWORD32 root; // root & frac: the ratio of the HF & LF in each state.
2326 UWORD32 frac; 3363 UWORD32 frac;
2327 3364
3365 // flag for AFC bypass mode
3366 UWORD8 afc_bypass_mode; // ENABLED/DISABLED
2328 } 3367 }
2329 T_POWER_MNGT; 3368 T_POWER_MNGT;
2330 3369
2331 /*************************************************************/ 3370 /*************************************************************/
2332 /* code version structure... */ 3371 /* code version structure... */
2352 UWORD32 frame_count; 3391 UWORD32 frame_count;
2353 } 3392 }
2354 T_L1S_RECOVER; 3393 T_L1S_RECOVER;
2355 #endif 3394 #endif
2356 3395
3396 #if (TOA_ALGO == 2)
3397 typedef struct
3398 {
3399 WORD16 toa_shift; // TOA, value used to update the TOA
3400 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results.
3401 BOOL toa_update_flag; // FLAG used to indicate when to the TOA module when to update TOA.
3402 // NOTE: Flag set to TRUE in l1s_synch() and reset to FALSE in l1ctl_toa()
3403 UWORD16 toa_frames_counter; // TOA Frames counter - Number of the TDMA frames (or bursts) which are used for TOA
3404 // updation OR number of times l1ctl_toa() function is invoked
3405 // Reset every TOA_PERIOD_LEN[l1_mode] frames
3406 UWORD16 toa_accumul_counter; // Number of TDMA frames (or bursts) which are actually used for TOA tracking
3407 // <= toa_frames_counter, as only if SNR>0.46875 TOA estimated by DSP is used to
3408 // update the tracking algorithm
3409 WORD16 toa_accumul_value; // TOA_tracking_value accumulated over 'toa_accumul_counter' frames
3410 // Based on this value the shift to be applied is decided
3411 UWORD32 toa_update_fn; // a counter which is in direct relation to l1s.actual_time.fn
3412 // and used for TOA tracking in ALL MODES every 433 MF's (approx. 2 seconds)
3413
3414 }T_TOA_ALGO;
3415 #endif
3416
3417
2357 /***************************************************************************************/ 3418 /***************************************************************************************/
2358 /* L1S global variable structure... */ 3419 /* L1S global variable structure... */
2359 /***************************************************************************************/ 3420 /***************************************************************************************/
2360 typedef struct 3421 typedef struct
2361 { 3422 {
2383 3444
2384 // Control parameters... 3445 // Control parameters...
2385 //----------------------------------------- 3446 //-----------------------------------------
2386 UWORD32 afc_frame_count; // AFC, Frame count between 2 calls to afc control function. 3447 UWORD32 afc_frame_count; // AFC, Frame count between 2 calls to afc control function.
2387 WORD16 afc; // AFC, Common Frequency controle. 3448 WORD16 afc; // AFC, Common Frequency controle.
3449 #if (TOA_ALGO == 2)
3450 T_TOA_ALGO toa_var;
3451 #else
2388 WORD16 toa_shift; // TOA, value used to update the TOA 3452 WORD16 toa_shift; // TOA, value used to update the TOA
2389 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results. 3453 UWORD8 toa_snr_mask; // TOA, mask counter to reject TOA/SNR results.
2390 3454
2391 UWORD16 toa_period_count; // TOA frame period used in PACKET TRANSFER MODE 3455 UWORD16 toa_period_count; // TOA frame period used in PACKET TRANSFER MODE
2392 BOOL toa_update; // TOA, is set at the end of the update period, toa update occurs on next valid frame 3456 BOOL toa_update; // TOA, is set at the end of the update period, toa update occurs on next valid frame
3457 #endif
2393 3458
2394 // Flag registers for RF task controle... 3459 // Flag registers for RF task controle...
2395 //----------------------------------------- 3460 //-----------------------------------------
2396 // Made these control registers short's as more than 8-bits required. 3461 // Made these control registers short's as more than 8-bits required.
2397 UWORD16 tpu_ctrl_reg; // (x,x,x,x,SYNC,RX,TX,MS) RX/TX/MS/SYNC bit ON whenever an 3462 UWORD16 tpu_ctrl_reg; // (x,x,x,x,SYNC,RX,TX,MS) RX/TX/MS/SYNC bit ON whenever an
2432 #if L2_L3_SIMUL 3497 #if L2_L3_SIMUL
2433 // GTT test 3498 // GTT test
2434 T_GTT_TEST_L1S gtt_test; 3499 T_GTT_TEST_L1S gtt_test;
2435 #endif 3500 #endif
2436 #endif 3501 #endif
2437 3502 #if (L1_DYN_DSP_DWNLD == 1)
2438 #if (L1_DYN_DSP_DWNLD == 1) 3503 UWORD8 dyn_dwnld_state; // state for L1S DYN DWNLD manager
2439 UWORD8 dyn_dwnld_state; // state for L1S DYN DWNLD manager 3504 #endif // L1_DYN_DSP_DWNLD
2440 #endif
2441 #if (AUDIO_TASK == 1) 3505 #if (AUDIO_TASK == 1)
2442 // Audio task. 3506 // Audio task.
2443 //----------------------------------------- 3507 //-----------------------------------------
2444 BOOL l1_audio_it_com; // Flag to enable the ITCOM. 3508 BOOL l1_audio_it_com; // Flag to enable the ITCOM.
2445 UWORD8 audio_state[NBR_AUDIO_MANAGER]; // state for L1S audio manager. 3509 UWORD8 audio_state[NBR_AUDIO_MANAGER]; // state for L1S audio manager.
2448 T_L1S_MELODY_TASK melody1; 3512 T_L1S_MELODY_TASK melody1;
2449 #endif 3513 #endif
2450 #if (VOICE_MEMO) 3514 #if (VOICE_MEMO)
2451 T_L1S_VM_TASK voicememo; 3515 T_L1S_VM_TASK voicememo;
2452 #endif 3516 #endif
3517 #if (L1_PCM_EXTRACTION)
3518 T_L1S_PCM_TASK pcm;
3519 #endif
2453 #if (L1_VOICE_MEMO_AMR) 3520 #if (L1_VOICE_MEMO_AMR)
2454 T_L1S_VM_AMR_TASK voicememo_amr; 3521 T_L1S_VM_AMR_TASK voicememo_amr;
2455 #endif 3522 #endif
2456 #if (SPEECH_RECO) 3523 #if (SPEECH_RECO)
2457 T_L1S_SR_TASK speechreco; 3524 T_L1S_SR_TASK speechreco;
2458 #endif 3525 #endif
2459 #if (AEC) 3526 #if (L1_AEC == 1)
2460 T_L1S_AEC_TASK aec; 3527 T_L1S_AEC_TASK aec;
2461 #endif 3528 #endif
2462 #if (MELODY_E2) 3529 #if (MELODY_E2)
2463 T_L1S_MELODY_E2_COMMON_VAR melody_e2; 3530 T_L1S_MELODY_E2_COMMON_VAR melody_e2;
2464 T_L1S_MELODY_E2_TASK melody0_e2; 3531 T_L1S_MELODY_E2_TASK melody0_e2;
2465 T_L1S_MELODY_E2_TASK melody1_e2; 3532 T_L1S_MELODY_E2_TASK melody1_e2;
2466 #endif 3533 #endif
3534 #if (L1_EXT_AUDIO_MGT == 1)
3535 T_L1S_EXT_AUDIO_MGT_VAR ext_audio_mgt;
3536 #endif
3537 #if (L1_WCM == 1)
3538 T_WCM_ACTION wcm_action;
3539 #endif
3540 #if (L1_AGC_UL == 1)
3541 T_AGC_ACTION agc_ul_action;
3542 #endif
3543 #if (L1_AGC_DL == 1)
3544 T_AGC_ACTION agc_dl_action;
3545 #endif
3546 #if (L1_ANR == 2)
3547 T_ANR_ACTION anr_ul_action;
3548 #endif
3549 #if (L1_IIR == 2)
3550 T_IIR_ACTION iir_dl_action;
3551 #endif
3552 #if (L1_DRC == 1)
3553 T_DRC_ACTION drc_dl_action;
3554 #endif
3555
2467 #endif 3556 #endif
2468 3557
2469 UWORD8 last_used_txpwr; 3558 UWORD8 last_used_txpwr;
2470 3559
2471 #if L1_GPRS 3560 #if L1_GPRS
2472 BOOL ctrl_synch_before; //control of synchro for CCCH reading en TN-2 3561 BOOL ctrl_synch_before; //control of synchro for CCCH reading en TN-2
3562 UWORD32 next_gauging_scheduled_for_PNP; // gauging for Packet Idle
2473 #endif 3563 #endif
2474 3564
2475 #if L1_RECOVERY 3565 #if L1_RECOVERY
2476 T_L1S_RECOVER recovery; 3566 T_L1S_RECOVER recovery;
2477 #endif 3567 #endif
2478 BOOL spurious_fb_detected; 3568 BOOL spurious_fb_detected;
2479 3569
2480 // Handling DTX mode 3570 // Handling DTX mode
2481 BOOL dtx_ul_on; 3571 BOOL dtx_ul_on; //earlier name was- dtx_on
2482 WORD8 facch_bursts; 3572 WORD8 facch_bursts;
2483
2484 // DTX mode in AMR 3573 // DTX mode in AMR
2485 BOOL dtx_amr_dl_on; // set to TRUE when the AMR is in DTX mode in downlink 3574 BOOL dtx_amr_dl_on; // set to TRUE when the AMR is in DTX mode in downlink
2486 3575
3576 //+++++++++++++++++
3577 // GSM IDLE IN RAM
3578 //+++++++++++++++++
3579
3580 #if (GSM_IDLE_RAM != 0)
3581 T_L1S_GSM_IDLE_INTRAM gsm_idle_ram_ctl;
3582
3583 #if (GSM_IDLE_RAM == 1)
3584 // Used to avoid allocation of ext mem data while in L1S_meas_manager (allocate signal long time before sending)
3585 T_RXLEV_MEAS A[8];
3586 #endif
3587 #endif
3588
3589 //+++++++++++++++++
3590 // Triton Audio ON/OFF Changes
3591 //+++++++++++++++++
3592 #if (L1_AUDIO_MCU_ONOFF == 1)
3593 T_L1S_AUDIO_ONOFF_MANAGER audio_on_off_ctl;
3594 #endif
3595
3596 #if (ANLG_FAM == 11)
3597 UWORD8 abb_write_done;
3598 #endif
3599 UWORD8 tcr_prog_done;
3600
3601 #if (L1_RF_KBD_FIX == 1)
3602 UWORD16 total_kbd_on_time;
3603 UWORD8 correction_ratio; //KPD_CORRECTION_RATIO correction_ratio;//omaps00090550
3604 #endif
3605 #if (L1_GPRS == 1)
3606 BOOL algo_change_synchro_active;
3607 #endif /* FF_L1_FAST_DECODING */
3608 #if (FF_REPEATED_SACCH == 1)
3609 // Repeated SACCH mode
3610 T_REPEAT_SACCH repeated_sacch;
3611 #endif /* FF_REPEATED_SACCH */
3612 #if (FF_REPEATED_DL_FACCH == 1)
3613 // Repeated FACCH mode
3614 T_REPEAT_FACCH repeated_facch;
3615 #endif /* FF_REPEATED_DL_FACCH == 1 */
3616 /* 0 indicates success, non zero value indicates failure */
3617 UWORD8 boot_result;
3618 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
3619 UWORD8 force_gauging_next_paging_due_to_CCHR;
3620
2487 } 3621 }
2488 T_L1S_GLOBAL; 3622 T_L1S_GLOBAL;
2489 3623
3624 #if (AUDIO_TASK == 1)
3625 #if (L1_VOCODER_IF_CHANGE == 1)
3626 typedef struct
3627 {
3628 BOOL enabled; // TRUE if enabled, FALSE if disabled
3629 BOOL automatic_disable; // TRUE if vocoders are automatically disabld via a MPHC_STOP_DEDICATED_REQ, FALSE otherwise.
3630 } T_L1A_VOCODER_CFG_GLOBAL;
3631 #endif // AUDIO_TASK == 1
3632 typedef struct
3633 {
3634 UWORD8 outen1;
3635 UWORD8 outen2;
3636 UWORD8 outen3;
3637 UWORD8 classD;
3638 UWORD8 command_requested; /* updated in L1a task context*/
3639 UWORD8 command_commited; /* updated in I2c ISR callback context*/
3640 } T_OUTEN_CFG_TASK;
3641
3642 #endif //L1_VOCODER_IF_CHANGE == 1
2490 /***************************************************************************************/ 3643 /***************************************************************************************/
2491 /* L1A global variable structure... */ 3644 /* L1A global variable structure... */
2492 /***************************************************************************************/ 3645 /***************************************************************************************/
2493 typedef struct 3646 typedef struct
2494 { 3647 {
2502 3655
2503 // Flag for forward/delete message management. 3656 // Flag for forward/delete message management.
2504 //--------------------------------------------- 3657 //---------------------------------------------
2505 UWORD8 l1_msg_forwarded; 3658 UWORD8 l1_msg_forwarded;
2506 3659
2507 #if (L1_DYN_DSP_DWNLD == 1) 3660 #if (L1_DYN_DSP_DWNLD == 1)
2508 // Dynamic donload global variables 3661 // Dynamic donload global variables
2509 T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld; 3662 T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld;
2510 #endif 3663 #endif
3664
3665 // New Vocoder IF global L1A variable: L1A checks if the vocoder has already been enabled/disabled
3666 // in order to robust to possible multiples enabling/disabling messages coming from PS
3667
3668 #if (L1_VOCODER_IF_CHANGE == 1)
3669 T_L1A_VOCODER_CFG_GLOBAL vocoder_state;
3670 #endif // L1_VOCODER_IF_CHANGE == 1
2511 3671
2512 // signal code indicating the reason of L1C_DEDIC_DONE 3672 // signal code indicating the reason of L1C_DEDIC_DONE
2513 UWORD32 confirm_SignalCode; 3673 UWORD32 confirm_SignalCode;
2514 3674
2515 // Trace the best frequencies reported in MPHC_RXLEV_IND 3675 #if (L1_MP3 == 1)
2516 #if (L1_MPHC_RXLEV_IND_REPORT_SORT==1) 3676 T_L1_MP3_L1A mp3_task;
2517 UWORD16 tab_index[MAX_MEAS_RXLEV_IND_TRACE]; 3677 //ADDED FOR AAC
2518 UWORD16 max_report; //max number of fq reported, can be < MAX_MEAS_RXLEV_IND_TRACE if list is smaller 3678 #endif
2519 #endif 3679
3680 #if (L1_AAC == 1)
3681 T_L1_AAC_L1A aac_task;
3682 #endif
3683 #if(L1_IIR == 2)
3684 xSignalHeaderRec *iir_req_msg_ptr;
3685 #endif
3686
3687 #if(L1_DRC == 1)
3688 xSignalHeaderRec *drc_req_msg_ptr;
3689 #endif
3690
3691 #if(L1_WCM == 1)
3692 xSignalHeaderRec *wcm_req_msg_ptr;
3693 #endif
3694
3695 #if(L1_CHECK_COMPATIBLE == 1)
3696 BOOL vcr_wait;
3697 BOOL stop_req;
3698 BOOL vcr_msg_param;
3699 BOOL vch_auto_disable;
3700 #endif
3701
2520 } 3702 }
2521 T_L1A_GLOBAL; 3703 T_L1A_GLOBAL;
2522 3704
2523 /***************************************************************************************/ 3705 /***************************************************************************************/
2524 /* L1A -> L1S communication structure... */ 3706 /* L1A -> L1S communication structure... */
2542 T_BCCHS nbcchs; 3724 T_BCCHS nbcchs;
2543 T_BCCHS ebcchs; 3725 T_BCCHS ebcchs;
2544 3726
2545 // Synchro information. 3727 // Synchro information.
2546 //--------------------------------------- 3728 //---------------------------------------
3729 #if L1_FF_WA_OMAPS00099442
3730 BOOL change_tpu_offset_flag;
3731 #endif
3732
2547 WORD8 tn_difference; // Timeslot difference for next synchro. 3733 WORD8 tn_difference; // Timeslot difference for next synchro.
2548 UWORD8 dl_tn; // Current timeslot for downlink stuffs. 3734 UWORD8 dl_tn; // Current timeslot for downlink stuffs.
2549 #if L1_GPRS 3735 #if L1_GPRS
2550 UWORD8 dsp_scheduler_mode; // DSP Scheduler mode (GPRS or GSM). 3736 UWORD8 dsp_scheduler_mode; // DSP Scheduler mode (GPRS or GSM).
2551 #endif 3737 #endif
2586 UWORD8 adc_traffic_period; 3772 UWORD8 adc_traffic_period;
2587 UWORD8 adc_cpt; 3773 UWORD8 adc_cpt;
2588 3774
2589 // TXPWR management. 3775 // TXPWR management.
2590 //------------------- 3776 //-------------------
3777 #if (L1_FF_MULTIBAND == 0)
2591 UWORD8 powerclass_band1; // Power class for the MS, given in ACCESS LINK mode (GSM Band). 3778 UWORD8 powerclass_band1; // Power class for the MS, given in ACCESS LINK mode (GSM Band).
2592 UWORD8 powerclass_band2; // Power class for the MS, given in ACCESS LINK mode (DCS Band). 3779 UWORD8 powerclass_band2; // Power class for the MS, given in ACCESS LINK mode (DCS Band).
3780 #else
3781 UWORD8 powerclass[RF_NB_SUPPORTED_BANDS];
3782 #endif
3783
2593 3784
2594 // Dedicated parameters. 3785 // Dedicated parameters.
2595 //---------------------- 3786 //----------------------
2596 T_DEDIC_PARAM dedic_set; // Dedicated channel parameters. 3787 T_DEDIC_PARAM dedic_set; // Dedicated channel parameters.
2597 3788
2605 // BA list / FULL list. 3796 // BA list / FULL list.
2606 //--------------------- 3797 //---------------------
2607 T_BA_LIST ba_list; 3798 T_BA_LIST ba_list;
2608 T_FULL_LIST full_list; 3799 T_FULL_LIST full_list;
2609 T_FULL_LIST_MEAS *full_list_ptr; 3800 T_FULL_LIST_MEAS *full_list_ptr;
3801
3802 #if ((REL99 == 1) && (FF_BHO == 1))
3803 // For blind handover...
3804 T_BHO_PARAM nsync_fbsb;
3805 #endif
2610 3806
2611 //+++++++++++++++++++ 3807 //+++++++++++++++++++
2612 // L1S scheduler... 3808 // L1S scheduler...
2613 //+++++++++++++++++++ 3809 //+++++++++++++++++++
2614 3810
2655 T_MELODY_TASK melody1_task; 3851 T_MELODY_TASK melody1_task;
2656 #endif 3852 #endif
2657 #if (VOICE_MEMO) 3853 #if (VOICE_MEMO)
2658 T_VM_TASK voicememo_task; 3854 T_VM_TASK voicememo_task;
2659 #endif 3855 #endif
3856 #if (L1_PCM_EXTRACTION)
3857 T_PCM_TASK pcm_task;
3858 #endif
2660 #if (L1_VOICE_MEMO_AMR) 3859 #if (L1_VOICE_MEMO_AMR)
2661 T_VM_AMR_TASK voicememo_amr_task; 3860 T_VM_AMR_TASK voicememo_amr_task;
2662 #endif 3861 #endif
2663 #if (SPEECH_RECO) 3862 #if (SPEECH_RECO)
2664 T_SR_TASK speechreco_task; 3863 T_SR_TASK speechreco_task;
2665 #endif 3864 #endif
2666 #if (AEC) 3865 #if (L1_AEC == 1)
3866 T_AEC_TASK aec_task;
3867 #endif
3868 #if (L1_AEC == 2)
2667 T_AEC_TASK aec_task; 3869 T_AEC_TASK aec_task;
2668 #endif 3870 #endif
2669 #if (FIR) 3871 #if (FIR)
2670 T_FIR_TASK fir_task; 3872 T_FIR_TASK fir_task;
2671 #endif 3873 #endif
2677 T_MELODY_E2_TASK melody1_e2_task; 3879 T_MELODY_E2_TASK melody1_e2_task;
2678 #endif 3880 #endif
2679 #if (L1_CPORT == 1) 3881 #if (L1_CPORT == 1)
2680 T_CPORT_TASK cport_task; 3882 T_CPORT_TASK cport_task;
2681 #endif 3883 #endif
2682 #endif 3884
3885 #if (L1_EXTERNAL_AUDIO_VOICE_ONOFF == 1 || L1_EXT_MCU_AUDIO_VOICE_ONOFF == 1)
3886 T_AUDIO_ONOFF_TASK audio_onoff_task;
3887 #endif
3888
3889 BOOL audio_forced_by_l1s; /* This value is used to indicate if the L1S is forcing the audio_on_off feature in the DSP CQ21718 */
3890
3891 #if (L1_STEREOPATH == 1)
3892 T_STEREOPATH_DRV_TASK stereopath_drv_task;
3893 #endif
3894
3895 #if (L1_MP3 == 1)
3896 T_MP3_TASK mp3_task;
3897 #endif
3898
3899 #if (L1_MIDI == 1)
3900 T_MIDI_TASK midi_task;
3901 #endif
3902 //ADDED FOR AAC
3903 #if (L1_AAC == 1)
3904 T_AAC_TASK aac_task;
3905 #endif
3906
3907 #if (L1_ANR == 1)
3908 T_ANR_TASK anr_task;
3909 #endif
3910
3911 #if (L1_ANR == 2)
3912 T_AQI_ANR_TASK anr_task;
3913 #endif
3914
3915 #if (L1_IIR == 1)
3916 T_IIR_TASK iir_task;
3917 #endif
3918
3919 #if (L1_AGC_UL == 1)
3920 T_AQI_AGC_UL_TASK agc_ul_task;
3921 #endif
3922
3923 #if (L1_AGC_DL == 1)
3924 T_AQI_AGC_DL_TASK agc_dl_task;
3925 #endif
3926
3927 #if (L1_IIR == 2)
3928 T_AQI_IIR_TASK iir_task;
3929 #endif
3930
3931 #if (L1_DRC == 1)
3932 T_AQI_DRC_TASK drc_task;
3933 #endif
3934
3935 #if (L1_LIMITER == 1)
3936 T_LIMITER_TASK limiter_task;
3937 #endif
3938
3939 #if (L1_ES == 1)
3940 T_ES_TASK es_task;
3941 #endif
3942
3943 #if (L1_WCM == 1)
3944 T_AQI_WCM_TASK wcm_task;
3945 #endif
3946
3947 //++++++++++++++++++++++++++++++++++++
3948 // Fake L1S sm for audio IT generation
3949 //++++++++++++++++++++++++++++++++++++
3950 T_AUDIOIT_TASK audioIt_task;
3951 #endif
3952
2683 3953
2684 //+++++++++++++ 3954 //+++++++++++++
2685 // GTT task 3955 // GTT task
2686 //+++++++++++++ 3956 //+++++++++++++
2687 3957
2688 #if (L1_GTT == 1) 3958 #if (L1_GTT == 1)
2689 T_GTT_TASK gtt_task; 3959 T_GTT_TASK gtt_task;
2690 #endif 3960 #endif
2691 3961
2692 // Dynamic DSP download task 3962 // Dynamic DSP download task
2693 #if (L1_DYN_DSP_DWNLD == 1) 3963 #if (L1_DYN_DSP_DWNLD == 1)
2694 T_DYN_DWNLD_TASK_COMMAND dyn_dwnld_task; 3964 T_DYN_DWNLD_TASK_COMMAND dyn_dwnld_task;
2695 #endif 3965 #endif
3966 T_OUTEN_CFG_TASK outen_cfg_task;
3967
3968 #if REL99
3969 #if FF_EMR
3970 T_SMEAS_EMR Smeas_dedic_emr;
3971 #endif
3972 #endif
3973
3974 #if (FF_L1_FAST_DECODING == 1)
3975 UWORD8 last_fast_decoding;
3976 #endif /* if (FF_L1_FAST_DECODING == 1) */
2696 3977
2697 } 3978 }
2698 T_L1A_L1S_COM; 3979 T_L1A_L1S_COM;
2699 3980
2700 /***************************************************************************************/ 3981 /***************************************************************************************/
2706 UWORD8 dsp_r_page; // Active page for ARM "reading" from DSP {0,1}. 3987 UWORD8 dsp_r_page; // Active page for ARM "reading" from DSP {0,1}.
2707 UWORD8 dsp_r_page_used; // Used in "l1_synch" to know if the read page must be chged. 3988 UWORD8 dsp_r_page_used; // Used in "l1_synch" to know if the read page must be chged.
2708 3989
2709 T_DB_DSP_TO_MCU *dsp_db_r_ptr; // MCU<->DSP comm. read page (Double Buffered comm. memory). 3990 T_DB_DSP_TO_MCU *dsp_db_r_ptr; // MCU<->DSP comm. read page (Double Buffered comm. memory).
2710 T_DB_MCU_TO_DSP *dsp_db_w_ptr; // MCU<->DSP comm. write page (Double Buffered comm. memory). 3991 T_DB_MCU_TO_DSP *dsp_db_w_ptr; // MCU<->DSP comm. write page (Double Buffered comm. memory).
3992 #if (DSP ==38) || (DSP == 39)
3993 T_DB_COMMON_MCU_TO_DSP *dsp_db_common_w_ptr; // MCU<->DSP comm. common write page (Double Buffered comm. memory).
3994 #endif
2711 T_NDB_MCU_DSP *dsp_ndb_ptr; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory). 3995 T_NDB_MCU_DSP *dsp_ndb_ptr; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
2712 3996
2713 T_PARAM_MCU_DSP *dsp_param_ptr; // MCU<->DSP comm. read/write (Param comm. memory). 3997 T_PARAM_MCU_DSP *dsp_param_ptr; // MCU<->DSP comm. read/write (Param comm. memory).
2714 3998
2715 #if (DSP_DEBUG_TRACE_ENABLE == 1) 3999 #if (DSP_DEBUG_TRACE_ENABLE == 1)
2716 T_DB2_DSP_TO_MCU *dsp_db2_current_r_ptr; 4000 T_DB2_DSP_TO_MCU *dsp_db2_current_r_ptr;
2717 T_DB2_DSP_TO_MCU *dsp_db2_other_r_ptr; 4001 T_DB2_DSP_TO_MCU *dsp_db2_other_r_ptr;
2718 #endif 4002 #endif
4003
4004 /* DSP CPU load measurement */
4005 T_DB_MCU_TO_DSP_CPU_LOAD *dsp_cpu_load_db_w_ptr;
2719 } 4006 }
2720 T_L1S_DSP_COM; 4007 T_L1S_DSP_COM;
2721 4008
2722 /***************************************************************************************/ 4009 /***************************************************************************************/
2723 /* L1A -> TPU communication structure... */ 4010 /* L1A -> TPU communication structure... */
2737 T_L1S_TPU_COM; 4024 T_L1S_TPU_COM;
2738 4025
2739 /***************************************************************************************/ 4026 /***************************************************************************************/
2740 /* L1 configuration structure */ 4027 /* L1 configuration structure */
2741 /***************************************************************************************/ 4028 /***************************************************************************************/
4029 #if (L1_FF_MULTIBAND == 0)
2742 4030
2743 typedef struct 4031 typedef struct
2744 { 4032 {
2745 UWORD8 id; //standard identifier 4033 UWORD8 id; //standard identifier
2746 4034
2772 UWORD16 lna_switch_thr_high_band1; 4060 UWORD16 lna_switch_thr_high_band1;
2773 UWORD16 lna_switch_thr_high_band2; 4061 UWORD16 lna_switch_thr_high_band2;
2774 } 4062 }
2775 T_L1_STD_CNFG; 4063 T_L1_STD_CNFG;
2776 4064
4065 #endif // #if (L1_FF_MULTIBAND == 0)
4066
4067 #if (L1_FF_MULTIBAND == 1)
4068
4069 #if 0
4070 typedef struct
4071 {
4072 UWORD16 nbmax_carrier;
4073 UWORD16 first_radio_freq;
4074 UWORD16 first_tpu_radio_freq;
4075 UWORD16 first_operative_radio_freq;
4076 UWORD8 physical_band_id;
4077 }
4078 T_MULTIBAND_CONVERSION_DATA;
4079
4080 typedef struct
4081 {
4082 UWORD16 lna_switch_thr_high;
4083 UWORD16 lna_switch_thr_low;
4084 UWORD16 lna_att;
4085 UWORD16 g_magic;
4086 UWORD8 swap_iq;
4087 UWORD16 cal_freq1;
4088 UWORD8 tx_turning_point;
4089 UWORD8 max_txpwr;
4090 UWORD8 gsm_band_identifier;
4091 }
4092 T_MULTIBAND_RF_DATA;
4093 #endif // if 0
4094 typedef struct
4095 {
4096 UWORD8 radio_band;
4097 UWORD8 power_class;
4098 UWORD8 _align0;
4099 UWORD8 _align1;
4100 }
4101 T_L1_MULTIBAND_POWER_CLASS;
4102
4103
4104 #endif /*if (L1_FF_MULTIBAND == 1)*/
4105
4106
2777 //RF dependent parameter definitions 4107 //RF dependent parameter definitions
2778 typedef struct 4108 typedef struct
2779 { 4109 {
2780 UWORD16 rx_synth_setup_time; 4110 UWORD16 rx_synth_setup_time;
2781 UWORD8 rx_synth_load_split; 4111 UWORD8 rx_synth_load_split;
2809 UWORD16 il_min; 4139 UWORD16 il_min;
2810 4140
2811 UWORD16 fixed_txpwr; 4141 UWORD16 fixed_txpwr;
2812 WORD16 eeprom_afc; 4142 WORD16 eeprom_afc;
2813 WORD8 setup_afc_and_rf; 4143 WORD8 setup_afc_and_rf;
4144 WORD8 rf_wakeup_tpu_scenario_duration; // Duration (in TDMA frames) of TPU scenario for RF wakeup
2814 4145
2815 UWORD32 psi_sta_inv; 4146 UWORD32 psi_sta_inv;
2816 UWORD32 psi_st; 4147 UWORD32 psi_st;
2817 UWORD32 psi_st_32; 4148 UWORD32 psi_st_32;
2818 UWORD32 psi_st_inv; 4149 UWORD32 psi_st_inv;
2832 4163
2833 #if DCO_ALGO 4164 #if DCO_ALGO
2834 BOOL dco_enabled; 4165 BOOL dco_enabled;
2835 #endif 4166 #endif
2836 4167
2837 #if (ANALOG == 1) 4168 #if (ANLG_FAM == 1)
2838 UWORD16 debug1; 4169 UWORD16 debug1;
2839 UWORD16 afcctladd; 4170 UWORD16 afcctladd;
2840 UWORD16 vbuctrl; 4171 UWORD16 vbuctrl;
2841 UWORD16 vbdctrl; 4172 UWORD16 vbdctrl;
2842 UWORD16 bbctrl; 4173 UWORD16 bbctrl;
2846 UWORD16 dai_onoff; 4177 UWORD16 dai_onoff;
2847 UWORD16 auxdac; 4178 UWORD16 auxdac;
2848 UWORD16 vbctrl; 4179 UWORD16 vbctrl;
2849 UWORD16 apcdel1; 4180 UWORD16 apcdel1;
2850 #endif 4181 #endif
2851 #if (ANALOG == 2) 4182 #if (ANLG_FAM == 2)
2852 UWORD16 debug1; 4183 UWORD16 debug1;
2853 UWORD16 afcctladd; 4184 UWORD16 afcctladd;
2854 UWORD16 vbuctrl; 4185 UWORD16 vbuctrl;
2855 UWORD16 vbdctrl; 4186 UWORD16 vbdctrl;
2856 UWORD16 bbctrl; 4187 UWORD16 bbctrl;
2863 UWORD16 vbctrl1; 4194 UWORD16 vbctrl1;
2864 UWORD16 vbctrl2; 4195 UWORD16 vbctrl2;
2865 UWORD16 apcdel1; 4196 UWORD16 apcdel1;
2866 UWORD16 apcdel2; 4197 UWORD16 apcdel2;
2867 #endif 4198 #endif
2868 #if (ANALOG == 3) 4199 #if (ANLG_FAM == 3)
2869 UWORD16 debug1; 4200 UWORD16 debug1;
2870 UWORD16 afcctladd; 4201 UWORD16 afcctladd;
2871 UWORD16 vbuctrl; 4202 UWORD16 vbuctrl;
2872 UWORD16 vbdctrl; 4203 UWORD16 vbdctrl;
2873 UWORD16 bbctrl; 4204 UWORD16 bbctrl;
2886 UWORD16 vaud_cfg; 4217 UWORD16 vaud_cfg;
2887 UWORD16 vauo_onoff; 4218 UWORD16 vauo_onoff;
2888 UWORD16 vaus_vol; 4219 UWORD16 vaus_vol;
2889 UWORD16 vaud_pll; 4220 UWORD16 vaud_pll;
2890 #endif 4221 #endif
2891 4222 #if (ANLG_FAM == 11)
4223 UWORD8 vulgain;
4224 UWORD8 vdlgain;
4225 UWORD8 sidetone;
4226 UWORD8 ctrl1;
4227 UWORD8 ctrl2;
4228 UWORD8 ctrl3;
4229 UWORD8 ctrl4;
4230 UWORD8 ctrl5;
4231 UWORD8 ctrl6;
4232 UWORD8 popauto;
4233 UWORD8 outen1;
4234 UWORD8 outen2;
4235 UWORD8 outen3;
4236 UWORD8 aulga;
4237 UWORD8 aurga;
4238 #endif
4239 #if (RF_FAM == 61)
4240 UWORD16 apcdel1;
4241 UWORD16 apcdel2;
4242 UWORD16 apcctrl2;
4243 #endif
2892 #if L1_GPRS 4244 #if L1_GPRS
2893 UWORD16 toa_pm_thres; // PM threshold for TOA algorithm feeding in packet transfer mode 4245 UWORD16 toa_pm_thres; // PM threshold for TOA algorithm feeding in packet transfer mode
2894 #endif 4246 #endif
2895 } 4247 }
2896 T_L1_PARAMS; 4248 T_L1_PARAMS;
2897 4249
2898 typedef struct 4250 typedef struct
2899 { 4251 {
2900 T_L1_STD_CNFG std; //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT 4252 #if (L1_FF_MULTIBAND == 0)
2901 UWORD8 pwr_mngt; //power management active 4253 T_L1_STD_CNFG std; //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT
2902 UWORD8 tx_pwr_code; 4254 #endif // L1_FF_MULTIBAND == 0
2903 UWORD16 dwnld; 4255
2904 T_L1_PARAMS params; 4256 UWORD8 pwr_mngt; //power management active
2905 double dpll; //dpll factor 4257 UWORD8 tx_pwr_code;
2906 4258 #if IDS
2907 #if TESTMODE 4259 UWORD8 ids_enable;
2908 //Define the TestMode flag and TestMode parameters 4260 #endif
2909 UWORD8 TestMode; 4261 UWORD16 dwnld;
2910 4262 T_L1_PARAMS params;
2911 UWORD8 agc_enable; 4263 double dpll; //dpll factor
2912 UWORD8 afc_enable; 4264
2913 UWORD8 adc_enable; 4265 #if TESTMODE
2914 4266 //Define the TestMode flag and TestMode parameters
2915 T_TM_PARAMS tmode; //TestMode parameters structure 4267 UWORD8 TestMode;
2916 #endif 4268
2917 4269 UWORD8 agc_enable;
4270 UWORD8 afc_enable;
4271 UWORD8 adc_enable;
4272 #if (FF_REPEATED_SACCH == 1)
4273 UWORD8 repeat_sacch_enable;
4274 #endif /* FF_REPEATED_SACCH == 1 */
4275 #if (FF_REPEATED_DL_FACCH == 1)
4276 UWORD8 repeat_facch_dl_enable;
4277 #endif /* (FF_REPEATED_DL_FACCH == 1)*/
4278
4279 T_TM_PARAMS tmode; //TestMode parameters structure
4280 #endif
4281
4282 T_FACCH_TEST_PARAMS facch_test;
2918 } 4283 }
2919 T_L1_CONFIG; 4284 T_L1_CONFIG;
4285 // SAPI identifier : 0 (Signalling), 3 (Short Messages Services)
4286 #if FF_REPEATED_SACCH
4287 typedef enum
4288 {
4289 SAPI_0 = 0,
4290 SAPI_3 = 3
4291 } T_L1_SAPI_ID;
4292 #endif /* FF_REPEATED_SACCH */
2920 4293
2921 /***************************************************************************************/ 4294 /***************************************************************************************/
2922 /* API HISR -> L1A communication structure... Defined in case dynamic download is defined */ 4295 /* API HISR -> L1A communication structure... */
2923 /***************************************************************************************/ 4296 /***************************************************************************************/
2924 /***************************************************************************************/ 4297 #if ( (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1) || (FF_L1_IT_DSP_USF == 1) ) // equivalent to an API_HISR flag
2925 /* Global API HISR -Defined in case dynamic download is defined 4298
2926 /***************************************************************************************/ 4299 #if FF_L1_IT_DSP_USF
2927 4300 typedef struct
2928 4301 {
2929 #if(L1_DYN_DSP_DWNLD==1) 4302 // Fast USF HISR pending
2930 typedef struct 4303 BOOL pending;
2931 { 4304 } T_L1A_USF_HISR_COM;
4305 #endif
4306
4307 #if FF_L1_IT_DSP_DTX
4308 typedef struct
4309 {
4310 // Fast DTX HISR pending
4311 BOOL pending;
4312 // TX activity programmed in TCH block
4313 BOOL tx_active;
4314 // Fast DTX service is available
4315 BOOL fast_dtx_ready;
4316 // Fast DTX service latency timer
4317 UWORD8 fast_dtx_ready_timer;
4318 // Fast DTX state variable
4319 UWORD8 dtx_status;
4320 } T_L1A_DTX_HISR_COM;
4321 #endif
4322
4323 #if (FF_L1_FAST_DECODING == 1)
4324 typedef struct
4325 {
4326 /* Fast Decoding HISR pending */
4327 BOOL pending;
4328 /* Current CRC */
4329 BOOL crc_error;
4330 /* Status (IT awaited?) */
4331 UWORD8 status;
4332 /* Control required during incoming fast API IT? */
4333 BOOL deferred_control_req;
4334 /* Task using fast decoding */
4335 UWORD8 task;
4336 /* Burst ID of the task */
4337 UWORD8 burst_id;
4338 /* Is the decoding of a contiguous block starting? */
4339 BOOL contiguous_decoding;
4340 } T_L1A_FAST_DECODING_HISR_COM;
4341 #endif /* FF_L1_FAST_DECODING */
4342
4343 typedef struct
4344 {
4345 #if (L1_MP3 == 1)
4346 T_L1A_MP3_HISR_COM mp3;
4347 #endif
4348 #if (L1_MIDI == 1)
4349 T_L1A_MIDI_HISR_COM midi;
4350 //ADDED FOR AAC
4351 #endif
4352 #if (L1_AAC == 1)
4353 T_L1A_AAC_HISR_COM aac;
4354 #endif
4355 #if (L1_DYN_DSP_DWNLD == 1)
2932 T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld; 4356 T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld;
4357 #endif // L1_DYN_DSP_DWNLD
4358 #if (FF_L1_IT_DSP_USF == 1)
4359 T_L1A_USF_HISR_COM usf;
4360 #endif
4361 #if (FF_L1_IT_DSP_DTX == 1)
4362 T_L1A_DTX_HISR_COM dtx;
4363 #endif
4364 #if (FF_L1_FAST_DECODING == 1)
4365 T_L1A_FAST_DECODING_HISR_COM fast_decoding;
4366 #endif /* FF_L1_FAST_DECODING */
2933 } T_L1A_API_HISR_COM; 4367 } T_L1A_API_HISR_COM;
2934 4368
2935 typedef struct 4369 #if (L1_MP3 == 1) || (L1_MIDI == 1) || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1)
2936 { 4370 typedef struct
4371 {
4372 #if (L1_MP3 == 1)
4373 T_L1_MP3_API_HISR mp3;
4374 #endif
4375 #if (L1_MIDI == 1)
4376 T_L1_MIDI_API_HISR midi;
4377 #endif
4378 //ADDED FOR AAC
4379 #if (L1_AAC == 1)
4380 T_L1_AAC_API_HISR aac;
4381 #endif
4382 #if (L1_DYN_DSP_DWNLD == 1)
2937 T_L1_DYN_DWNLD_API_HISR dyn_dwnld; 4383 T_L1_DYN_DWNLD_API_HISR dyn_dwnld;
4384 #endif // L1_DYN_DSP_DWNLD
2938 } T_L1_API_HISR; 4385 } T_L1_API_HISR;
2939 #endif 4386 #endif // #if (L1_MP3 == 1) || (L1_MIDI == 1) || || (L1_AAC == 1) || (L1_DYN_DSP_DWNLD == 1)
4387
4388 #endif //(L1_MP3 == 1) || (L1_MIDI == 1) || (L1_DYN_DSP_DWNLD == 1) || (FF_L1_IT_DSP_USF == 1)
4389
4390 typedef struct
4391 {
4392 /* 0 indicates success 1 indicates failure */
4393 UWORD16 boot_result;
4394 UWORD16 drp_maj_ver;
4395 UWORD16 drp_min_ver;
4396 // MCU versions
4397 UWORD16 mcu_tcs_program_release;
4398 UWORD16 mcu_tcs_official;
4399 UWORD16 mcu_tcs_internal;
4400 // DSP versions & checksum
4401 UWORD16 dsp_code_version;
4402 UWORD16 dsp_patch_version;
4403 }T_L1_BOOT_VERSION_CODE;
4404
4405