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comparison gsm-fw/L1/include/leo-based/l1_confg.h @ 530:25a7fe25864c

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gsm-fw/L1/include: switch to LoCosto versions of all header files
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 01 Aug 2014 16:38:35 +0000
parents gsm-fw/L1/include/l1_confg.h@80ee7eacdaeb
children
comparison
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529:f72c9db5e2f5 530:25a7fe25864c
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_CONFG.H
4 *
5 * Filename l1_confg.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #ifndef __L1_CONFG_H__
11 #define __L1_CONFG_H__
12
13 // Traces...
14 // TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
15 // TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
16 // TRACE_TYPE == 1 -> L1/L3 interface trace
17 // TRACE_TYPE == 2 -> Trace mode: ~33~~1~011...
18 // TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace
19 // TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack
20 // TRACE_TYPE == 5 -> trace for full simulation
21 // TRACE_TYPE == 6 -> CPU load trace for hisr
22 // TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on
23 // UART at 38400 bps =>
24 // format : <hisr cpu value in microseconds> <frame number>
25
26 // Code PB reported workaround
27 //------------------------------
28
29
30 // Code Version possible choices
31 //------------------------------
32 #define SIMULATION 1
33 #define NOT_SIMULATION 2
34
35 // RCL functions Version possible choices
36 //------------------------------
37 #define POLL_FORCED 0
38 #define RLC_SCENARIO 1
39 #define MODEM_FLOW 2
40
41 // possible choices for UART trace output
42 //------------------------------
43 #define MODEM_UART 0
44 #define IRDA_UART 1
45 #if (CHIPSET == 12)
46 #define MODEM2_UART 2
47 #endif
48
49 //============
50 // CODE CHOICE
51 //============
52 #if 0
53 #if (OP_L1_STANDALONE==0)
54 #define CODE_VERSION NOT_SIMULATION
55 #else // OP_L1_STANDALONE
56 #ifdef WIN32
57 #define CODE_VERSION SIMULATION
58 #else // WIN32
59 #define CODE_VERSION NOT_SIMULATION
60 #endif // WIN32
61 #endif // OP_L1_STANDALONE
62 #endif // #if 0
63
64 /* FreeCalypso */
65 #define CODE_VERSION NOT_SIMULATION
66 #define AMR 1
67 #define L1_12NEIGH 1
68 #define L1_DYN_DSP_DWNLD 0 /* for now */
69 #define L1_EOTD 0
70 #define L1_GTT 0
71 #define ORDER2_TX_TEMP_CAL 1
72 #define TRACE_TYPE 4
73 #define VCXO_ALGO 1
74
75 /* TESTMODE will be enabled with feature l1tm */
76
77 #if CONFIG_AUDIO
78 # define AUDIO_TASK 1 // Enable the L1 audio features
79 # define MELODY_E2 1
80 #endif
81
82 #if CONFIG_GPRS
83 # define L1_GPRS 1
84 #else
85 # define L1_GPRS 0
86 #endif
87
88 //---------------------------------------------------------------------------------
89 // Test with full simulation.
90 //---------------------------------------------------------------------------------
91 #if (CODE_VERSION == SIMULATION)
92
93 // Test Scenari...
94 #define SCENARIO_FILE 1 // Test Scenario comes from input files.
95 #define SCENARIO_MEM 0 // Test Scenario comes from RAM.
96
97 // Traces...
98 #undef TRACE_TYPE
99 #define TRACE_TYPE 5
100 #define LOGFILE_TRACE 1 // trace in an output logfile
101 #define FLOWCHART 0 // Message sequence/flow chart trace.
102 #define NUCLEUS_TRACE 0 // Nucleus error trace
103 #define EOTD_TRACE 1 // EOTD log trace
104 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
105
106 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
107
108 // Control algorithms...
109 #define AFC_ALGO 1 // AFC algorithm.
110 #define TOA_ALGO 1 // TOA algorithm.
111 #define AGC_ALGO 1 // AGC algorithm.
112 #define TA_ALGO 0 // TA (Timing Advance) algorithm.
113 #undef VCXO_ALGO
114 #define VCXO_ALGO 0 // VCXO algo
115 #undef DCO_ALGO
116 #define DCO_ALGO 0 // DCO algo (TIDE)
117 #undef ORDER2_TX_TEMP_CAL
118 #define ORDER2_TX_TEMP_CAL 0 // TX Temperature Compensation Algorithm selection
119
120
121 #define FACCH_TEST 0 // FACCH test enabled.
122
123 #define ADC_TIMER_ON 0 // Timer for ADC measurements
124 #define AFC_ON 1 // Enable of the Omega AFC module
125
126 #define AUDIO_TASK 1 // Enable the L1 audio features
127 #define AUDIO_SIMULATION 1 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
128 #define AUDIO_L1_STANDALONE 0 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
129
130 #define GTT_SIMULATION 1 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
131 #define TTY_SYNC_MCU 1 // TTY WORKAROUND BUG03401
132 #define TTY_SYNC_MCU_2 1 //
133 #define L1_GTT_FIFO_TEST_ATOMIC 0 //
134 #define NEW_WKA_PATCH 0
135 #define OPTIMISED 1
136
137 #define L1_RECOVERY 0 // L1 recovery
138
139 #undef L1_GPRS
140 #define L1_GPRS 1 // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
141
142 #undef AMR
143 #define AMR 1 // AMR version 1.0 supported
144
145 #undef L1_12NEIGH
146 #define L1_12NEIGH 1 // new L1-RR interface for 12 neighbour cells
147
148 #undef L1_GTT
149 #define L1_GTT 1 // Enable Global Text Telephony feature for simulation
150
151 #undef OP_L1_STANDALONE
152 #define OP_L1_STANDALONE 1 // Selection of code for L1 stand alone
153
154 #undef OP_RIV_AUDIO
155 #define OP_RIV_AUDIO 0 // Selection of code for Riviera audio
156
157 #undef OP_WCP
158 #define OP_WCP 0 // No WCP integration
159 //---------------------------------------------------------------------------------
160 // Test with H/W platform.
161 //---------------------------------------------------------------------------------
162 #elif (CODE_VERSION == NOT_SIMULATION)
163
164 #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1)
165 // Work around about Calypso RevA: the bus is floating (Cf PB01435)
166 // (corrected with Calypso ReV B and Calypso C035)
167 #if (CHIPSET == 7)
168 #define W_A_CALYPSO_BUG_01435 1
169 #else
170 #define W_A_CALYPSO_BUG_01435 0
171 #endif
172
173
174 // for AMR thresolds definition CQ22226
175 #define AMR_THRESHOLDS_WORKAROUND 1
176
177 #if (L1_GTT==1)
178 #define TTY_SYNC_MCU 1
179 #define TTY_SYNC_MCU_2 1
180 #define L1_GTT_FIFO_TEST_ATOMIC 0
181 #define NEW_WKA_PATCH 0
182 #define OPTIMISED 1
183 #else
184 #define TTY_SYNC_MCU_2 0
185 #define L1_GTT_FIFO_TEST_ATOMIC 0
186 #define TTY_SYNC_MCU 0
187 #define NEW_WKA_PATCH 0
188 #define OPTIMISED 0
189
190 #endif
191
192 // Traces...
193 #define NUCLEUS_TRACE 0 // Nucleus error trace
194 #define FLOWCHART 0 // Message sequence/flow chart trace.
195 #define LOGFILE_TRACE 0 // trace in an output logfile
196 #define TRACE_FULL_NAME 0 // display full fct names after a PM/COM error
197
198 // Test Scenari...
199 #define SCENARIO_FILE 0 // Test Scenario comes from input files.
200 #define SCENARIO_MEM 1 // // Test Scenario comes from RAM.
201
202 #if (OP_L1_STANDALONE == 1)
203 #define L2_L3_SIMUL 1 // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
204 #else
205 #define L2_L3_SIMUL 0
206 #endif
207
208 // Control algorithms...
209 #define AFC_ALGO 1 // AFC algorithm.
210 //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
211 #define TOA_ALGO 1 // TOA algorithm.
212 #define AGC_ALGO 1 // AGC algorithm.
213 #define TA_ALGO 1 // TA (Timing Advance) algorithm.
214
215 #define FACCH_TEST 0 // FACCH test enabled.
216
217 #define ADC_TIMER_ON 0 // Timer for ADC measurements
218 #define AFC_ON 1 // Enable of the Omega AFC module
219
220 #if 0
221 /* FreeCalypso: moved to config section above */
222 #define AUDIO_TASK 1 // Enable the L1 audio features
223 #endif
224 #define AUDIO_SIMULATION 0 // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
225 #if (OP_L1_STANDALONE == 1)
226 #define AUDIO_L1_STANDALONE 1 // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
227 #else
228 #define AUDIO_L1_STANDALONE 0
229 #endif
230
231 #define GTT_SIMULATION 0 // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
232
233 #define OP_BT 0 // Simulation of ISLAND (BLUETOOTH) sleep management
234
235 #define L1_RECOVERY 1 // L1 recovery
236
237
238 #if (L1_GPRS == 1)
239 #define RLC_VERSION RLC_SCENARIO
240 #if (RLC_VERSION == RLC_SCENARIO)
241 #define RLC_DL_BLOCK_STAT 0 // Works with RLC_VERSION = RLC_SCENARIO
242 // output stat on CRC error blocks
243 // The user must enter the cs type and
244 // the number of frames desired.
245 #else
246 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
247 #endif
248
249 #if (OP_L1_STANDALONE == 1)
250 #define DSP_BACKGROUND_TASKS 1 // Enable the TEST of DSP background.tasks
251 // activated by a layer 3 message (BG_TASK_START (<task number>))
252 // deactivated by a layer 3 message (BG_TASK_STOP (<task number>))
253 // Warning : Works only with DSP>=31
254 #else
255 #define DSP_BACKGROUND_TASKS 0
256 #endif
257
258 #else
259 #define DSP_BACKGROUND_TASKS 0
260 #define RLC_DL_BLOCK_STAT 0 // Default value; Never change it
261 #endif
262 #endif
263
264 // Audio tasks selection
265 //-----------------------
266
267 #if (AUDIO_TASK == 1)
268 #define KEYBEEP 1 // Enable keybeep feature
269 #define TONE 1 // Enable tone feature
270 // Temporary modification for protocol stack compatibility - GSMLITE will be removed
271 #if (OP_L1_STANDALONE == 1)
272 #define GSMLITE 1
273 #endif
274 #if ((OP_L1_STANDALONE == 1) || (!GSMLITE))
275 #define MELODY_E1 1 // Enable melody format E1 feature
276 #define VOICE_MEMO 1 // Enable voice memorization feature
277
278 #define FIR 1 // Enable FIR feature
279 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
280 #define AUDIO_MODE 1 // Enable Audio mode feature
281 #else
282 #define AUDIO_MODE 0 // Disable Audio mode feature
283 #endif
284 #else
285 #define MELODY_E1 0 // Disable melody format E1 feature
286 #define VOICE_MEMO 0 // Disable voice memorization feature
287 #if (MELODY_E2)
288 #define FIR 1 // Enable FIR feature
289 #else
290 #define FIR 0 // Disable FIR feature
291 #endif
292
293 #define AUDIO_MODE 0 // Disable Audio mode feature
294 #endif
295 // Define CPORT for ESample only
296 #if ((CHIPSET == 12) && ((DSP == 35) || (DSP == 36)))
297 #define L1_CPORT 1 // Enable cport feature
298 #else
299 #define L1_CPORT 0 // Disable cport feature
300 #endif
301
302 #else
303 #define KEYBEEP 0 // Enable keybeep feature
304 #define TONE 0 // Enable tone feature
305 #define MELODY_E1 0 // Enable melody format E1 feature
306 #define VOICE_MEMO 0 // Enable voice memorization feature
307
308 #define FIR 0 // Enable FIR feature
309 #define AUDIO_MODE 0 // Enable Audio mode feature
310 #define L1_CPORT 0 // Enable cport feature
311 #endif
312
313 #define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2
314 #if (OP_RIV_AUDIO == 1)
315 #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
316 #endif
317
318
319 // Vocoder selections
320 //-------------------
321
322 #define FR 1 // Full Rate
323 #define FR_HR 2 // Full Rate + Half Rate
324 #define FR_EFR 3 // Full Rate + Enhanced Full Rate
325 #define FR_HR_EFR 4 // Full Rate + Half Rate + Enhanced Full Rate
326
327 // Standard (frequency plan) selections
328 //-------------------------------------
329
330 #define GSM 1 // GSM900.
331 #define GSM_E 2 // GSM900 Extended.
332 #define PCS1900 3 // PCS1900.
333 #define DCS1800 4 // DCS1800.
334 #define DUAL 5 // Dual Band (GSM900 + DCS 1800 bands)
335 #define DUALEXT 6 // Dual Band (E-GSM900 + DCS 1800 bands)
336 #define GSM850 7 // GSM850 Band
337 #define DUAL_US 8 // PCS1900 + GSM850
338
339 /*------------------------------------*/
340 /* Power Management */
341 /*------------------------------------*/
342 #define PWR_MNGT 1 // POWER management active if l1_config.pwr_mngt=1
343
344
345 /*---------------------------------------------------------------------------*/
346 /* DSP configurations */
347 /* ------------------ */
348 /* DSP | FR| HR|EFR|14.4| SPEED |12LA68|12LA68 |4L32|AEC| MCU/DSP */
349 /* (version) | | | | | |POLE80|POLE112| |/NS| interface */
350 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
351 /* 0 (821) | x | | | | 39Mhz | x | | | | 1 */
352 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
353 /* 1 (830) | x | | | | 39Mhz | (1) | | x | | 1 */
354 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
355 /* 2 (912) | x | x | | | 58.5Mhz | x | | | | 2 */
356 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
357 /* 3 (10xx) | x | | x | x | 65Mhz | x | | | x | 3 */
358 /* ----------+---+---+---+----+---------+------+-------+----|---+---------- */
359 /* 4 (11xx) | x | x | x | x | 65Mhz | x | x (3)| | x | 3 */
360 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
361 /* 5 (830) | x | | | | 39Mhz | x | | | | 1 */
362 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
363 /* 6 (11xx) | x | x | x | x | 65Mhz | x | x (3)| |(2)| 3 */
364 /* ----------+---+---+---+----+---------+------+-------+----+---+---------- */
365 /* */
366 /*(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is*/
367 /* not corrected. */
368 /* */
369 /*(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP */
370 /* interface which support AEC, therefore AEC is defined as 1. */
371 /* */
372 /*(3) Pole112 include RIF DL correction. No patch is needed if this one only */
373 /* include RIF/DL problem. */
374 /* */
375 /*---------------------------------------------------------------------------*/
376 #if (DSP == 16 || DSP == 17)
377
378 /* #define CLKMOD1 0x414e // ...
379 #define CLKMOD2 0x414e // ...65 Mips
380 #define CLKSTART 0x29 // ...65 Mips */
381
382 #define CLKMOD1 0x4006 // ...
383 #define CLKMOD2 0x4116 // ...65 Mips pll free
384 #define CLKSTART 0x29 // ...65 Mips
385
386 /* #define CLKMOD1 0x2116 //This settings force the DSP to never enteridle
387 #define CLKMOD2 0x2116 //In this case the PLL will be always on. 39 Mips
388 #define CLKSTART 0x25 // ...39 Mips */
389
390 #define VOC FR_HR_EFR // FR + HR + EFR.
391 #define DATA14_4 1 // No 14.4 data allowed.
392 #define AEC 1 // AEC/NS supported.
393 #define MAP 3
394 #define DSP_START 0x2000
395 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
396
397 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
398
399 /* DSP debug trace configuration */
400 /*-------------------------------*/
401 #if (MELODY_E2)
402 // In case of the melody E2 the DSP trace must be disable because the
403 // melody instrument waves are overlayed with DSP trace buffer
404
405 // DSP debug trace API buufer config
406 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
407 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
408 #else
409 // DSP debug trace API buufer config
410 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
411 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
412 #endif
413
414 #elif (DSP == 30) // First GPRS.
415 #define CLKMOD1 0x4006 // ...
416 #define CLKMOD2 0x4116 // ...65 Mips pll free
417 #define CLKSTART 0x29 // ...65 Mips
418
419 #define VOC FR_HR_EFR // FR + HR + EFR.
420 #define DATA14_4 1 // No 14.4 data allowed.
421 #define AEC 1 // AEC/NS not supported.
422 #define MAP 3
423 #define DSP_START 0x1F81
424 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
425 #define ULYSSE 0
426
427 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
428 #elif (DSP == 31) // ROM Code GPRS G0.
429 #define CLKMOD1 0x4006 // ...
430 #define CLKMOD2 0x4116 // ...65 Mips pll free
431 #define CLKSTART 0x29 // ...65 Mips
432
433 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
434 #define DATA14_4 1 // 14.4 data allowed.
435 #define AEC 1 // AEC/NS not supported.
436 #define MAP 3
437
438 #define DSP_START 0x8763
439
440 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
441 #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
442
443 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
444 #define ULYSSE 0
445
446 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
447 #elif (DSP == 32) // ROM Code GPRS G1.
448 #define CLKMOD1 0x4006 // ...
449 #define CLKMOD2 0x4116 // ...65 Mips pll free
450 #define CLKSTART 0x29 // ...65 Mips
451
452 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
453 #define DATA14_4 1 // 14.4 data allowed.
454 #define AEC 1 // AEC/NS not supported.
455 #define MAP 3
456
457 #define DSP_START 0x8763
458
459 #define INSTALL_ADD 0x87c9 // Used to set gprs_install_address pointer
460
461 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
462 #define ULYSSE 0
463
464 #define W_A_DSP_SR_BGD 0 // Work around about the DSP speech reco background task.
465 #elif (DSP == 33) // ROM Code GPRS.
466 #define CLKMOD1 0x4006 // ...
467 #define CLKMOD2 0x4116 // ...65 Mips pll free
468 #define CLKSTART 0x29 // ...65 Mips
469 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
470 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
471 #define AEC 1 // AEC/NS not supported.
472 #if (OP_RIV_AUDIO == 0)
473 #define L1_NEW_AEC 1
474 #else
475 // Available but not yet tuned with Riviera AUDIO
476 #define L1_NEW_AEC 0
477 #endif
478 #if ((L1_NEW_AEC) && (!AEC))
479 // First undef the flag to avoid warnings at compilation time
480 #undef AEC
481 #define AEC 1
482 #endif
483
484 #define MAP 3
485
486 #define DSP_START 0x7000
487
488 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
489
490 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
491 #define ULYSSE 0
492
493 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
494
495 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
496
497 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
498
499 // management.
500
501 // DSP_IDLE3 is not supported in simulation
502
503 #else
504 #define W_A_DSP_IDLE3 0
505 #endif
506
507 // DSP software work-around config
508 // bit0 - Work-around to support CRTG.
509 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
510 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
511 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
512
513 #if (ANALOG == 1) // OMEGA / NAUSICA
514 #define C_DSP_SW_WORK_AROUND 0x0006
515
516 #elif (ANALOG == 2) // IOTA
517 #define C_DSP_SW_WORK_AROUND 0x000E
518
519 #elif (ANALOG == 3) // SYREN
520 #define C_DSP_SW_WORK_AROUND 0x000E
521
522 #endif
523
524 /* DSP debug trace configuration */
525 /*-------------------------------*/
526 #if (MELODY_E2)
527 // In case of the melody E2 the DSP trace must be disable because the
528 // melody instrument waves are overlayed with DSP trace buffer
529
530 // DSP debug trace API buufer config
531 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
532 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
533
534 // DSP debug trace type config
535 // |<-------------- Features -------------->|<---------- Levels ----------->|
536 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
537 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
538
539 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
540 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
541 // Currently not supported !
542 #endif
543 #else
544 // DSP debug trace API buufer config
545 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
546 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
547
548 // DSP debug trace type config
549 // |<-------------- Features -------------->|<---------- Levels ----------->|
550 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
551 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
552
553 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
554 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
555 #endif
556 #endif
557 /* d_error_status */
558 /*-------------------------------*/
559
560 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
561 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
562
563 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
564 #define DSP_DEBUG_GSM_MASK 0x0000
565 #define DSP_DEBUG_GPRS_MASK 0x0f3d
566 #endif
567
568 #if DCO_ALGO
569 // DCO type of scheduling
570 #define C_CN_DCO_PARAM 0xA248
571 #endif
572
573 #elif (DSP == 34) // ROM Code GPRS AMR.
574 #define CLKMOD1 0x4006 // ...
575 #define CLKMOD2 0x4116 // ...65 Mips pll free
576 #define CLKSTART 0x29 // ...65 Mips
577 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
578 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
579 #define AEC 1 // AEC/NS not supported.
580 #if (OP_RIV_AUDIO == 0)
581 #define L1_NEW_AEC 1
582 #else
583 // Available but not yet tuned with Riviera AUDIO
584 #define L1_NEW_AEC 0
585 #endif
586 #if ((L1_NEW_AEC) && (!AEC))
587 // First undef the flag to avoid warnings at compilation time
588 #undef AEC
589 #define AEC 1
590 #endif
591 #define MAP 3
592
593 #define DSP_START 0x7000
594
595 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
596
597 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
598 #define ULYSSE 0
599
600 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
601
602 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
603
604 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
605
606 // management.
607
608 // DSP_IDLE3 is not supported in simulation
609
610 #else
611 #define W_A_DSP_IDLE3 0
612 #endif
613
614 // DSP software work-around config
615 // bit0 - Work-around to support CRTG.
616 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
617 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
618 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
619 #if (ANALOG == 1) // OMEGA / NAUSICA
620 #define C_DSP_SW_WORK_AROUND 0x0006
621
622 #elif (ANALOG == 2) // IOTA
623 #define C_DSP_SW_WORK_AROUND 0x000E
624
625 #elif (ANALOG == 3) // SYREN
626 #define C_DSP_SW_WORK_AROUND 0x000E
627
628 #endif
629
630 /* DSP debug trace configuration */
631 /*-------------------------------*/
632 #if (MELODY_E2)
633 // In case of the melody E2 the DSP trace must be disable because the
634 // melody instrument waves are overlayed with DSP trace buffer
635
636 // DSP debug trace API buufer config
637 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
638 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
639
640 // DSP debug trace type config
641 // |<-------------- Features -------------->|<---------- Levels ----------->|
642 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
643 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
644
645 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
646 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
647 // Currently not supported !
648 #endif
649 #else
650 // DSP debug trace API buufer config
651 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
652 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
653
654 // DSP debug trace type config
655 // |<-------------- Features -------------->|<---------- Levels ----------->|
656 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
657 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
658
659 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
660 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
661 #endif
662
663 // AMR trace
664 #define C_AMR_TRACE_ID 55
665
666 #endif
667 /* d_error_status */
668 /*-------------------------------*/
669
670 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
671 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
672
673 // masks to apply on d_error_status bit field
674 #define DSP_DEBUG_GSM_MASK 0x0000
675 #define DSP_DEBUG_GPRS_MASK 0x0f3d
676 #endif
677
678 #elif (DSP == 35) // ROM Code GPRS AMR.
679 #define CLKMOD1 0x4006 // ...
680 #define CLKMOD2 0x4116 // ...65 Mips pll free
681 #define CLKSTART 0x29 // ...65 Mips
682 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
683 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
684 #define AEC 1 // AEC/NS not supported.
685 #if (OP_RIV_AUDIO == 0)
686 #define L1_NEW_AEC 1
687 #else
688 // Available but not yet tuned with Riviera AUDIO
689 #define L1_NEW_AEC 0
690 #endif
691 #if ((L1_NEW_AEC) && (!AEC))
692 // First undef the flag to avoid warnings at compilation time
693 #undef AEC
694 #define AEC 1
695 #endif
696 #define MAP 3
697
698 #define FF_L1_TCH_VOCODER_CONTROL 1
699 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
700
701 #define DSP_START 0x7000
702
703 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
704
705 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
706 #define ULYSSE 0
707
708 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
709
710 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
711
712 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
713
714 // management.
715
716 // DSP_IDLE3 is not supported in simulation
717
718 #else
719 #define W_A_DSP_IDLE3 0
720 #endif
721
722 // DSP software work-around config
723 // bit0 - Work-around to support CRTG.
724 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
725 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
726 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
727 #if (ANALOG == 1) // OMEGA / NAUSICA
728 #define C_DSP_SW_WORK_AROUND 0x0006
729
730 #elif (ANALOG == 2) // IOTA
731 #define C_DSP_SW_WORK_AROUND 0x000E
732
733 #elif (ANALOG == 3) // SYREN
734 #define C_DSP_SW_WORK_AROUND 0x000E
735
736 #endif
737
738 /* DSP debug trace configuration */
739 /*-------------------------------*/
740 #if (MELODY_E2)
741 // In case of the melody E2 the DSP trace must be disable because the
742 // melody instrument waves are overlayed with DSP trace buffer
743
744 // DSP debug trace API buufer config
745 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
746 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
747
748 // DSP debug trace type config
749 // |<-------------- Features -------------->|<---------- Levels ----------->|
750 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
751 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
752
753 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
754 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
755 // Currently not supported !
756 #endif
757 #else
758 // DSP debug trace API buufer config
759 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
760 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
761
762 // DSP debug trace type config
763 // |<-------------- Features -------------->|<---------- Levels ----------->|
764 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
765 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Timer + Buffer Header + Burst.
766
767 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
768 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
769 #endif
770
771 // AMR trace
772 #define C_AMR_TRACE_ID 55
773
774 #endif
775 /* d_error_status */
776 /*-------------------------------*/
777
778 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
779 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
780
781 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
782 #define DSP_DEBUG_GSM_MASK 0x08BD
783 #define DSP_DEBUG_GPRS_MASK 0x0f3d
784 #endif
785 #elif (DSP == 36) // ROM Code GPRS AMR.
786 #define CLKMOD1 0x4006 // ...
787 #define CLKMOD2 0x4116 // ...65 Mips pll free
788 #define CLKSTART 0x29 // ...65 Mips
789 #define C_PLL_CONFIG 0x154 // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
790 #define VOC FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
791 #define AEC 1 // AEC/NS not supported.
792 #if (OP_RIV_AUDIO == 0)
793 #define L1_NEW_AEC 1
794 #else
795 // Available but not yet tuned with Riviera AUDIO
796 #define L1_NEW_AEC 0
797 #endif
798 #if ((L1_NEW_AEC) && (!AEC))
799 // First undef the flag to avoid warnings at compilation time
800 #undef AEC
801 #define AEC 1
802 #endif
803 #define MAP 3
804 #undef L1_AMR_NSYNC
805 #define L1_AMR_NSYNC 1
806 #define FF_L1_TCH_VOCODER_CONTROL 1
807 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
808
809 #define DSP_START 0x7000
810
811 #define INSTALL_ADD 0x7002 // Used to set gprs_install_address pointer
812
813 #define W_A_DSP1 0 // Work Around correcting pb in DSP: SACCH
814 #define ULYSSE 0
815
816 #define W_A_DSP_SR_BGD 1 // Work around about the DSP speech reco background task.
817
818 #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
819
820 #define W_A_DSP_IDLE3 1 // Work around to report DSP state to the ARM for Deep Sleep
821
822 // management.
823
824 // DSP_IDLE3 is not supported in simulation
825
826 #else
827 #define W_A_DSP_IDLE3 0
828 #endif
829
830 // DSP software work-around config
831 // bit0 - Work-around to support CRTG.
832 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
833 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
834 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
835 #if (ANALOG == 1) // OMEGA / NAUSICA
836 #define C_DSP_SW_WORK_AROUND 0x0006
837
838 #elif (ANALOG == 2) // IOTA
839 #define C_DSP_SW_WORK_AROUND 0x000E
840
841 #elif (ANALOG == 3) // SYREN
842 #define C_DSP_SW_WORK_AROUND 0x000E
843 #endif
844
845 // This workaround should be enabled only for H2-sample on full build config
846 #if (OP_L1_STANDALONE==1)
847 #define RAZ_VULSWITCH_REGAUDIO 0
848 #endif
849
850 /* DSP debug trace configuration */
851 /*-------------------------------*/
852 #if (MELODY_E2)
853 // In case of the melody E2 the DSP trace must be disable because the
854 // melody instrument waves are overlayed with DSP trace buffer
855
856 // DSP debug trace API buufer config
857 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
858 #define C_DEBUG_BUFFER_SIZE 7 // Real size is incremented by 1 for DSP write pointer.
859
860 // DSP debug trace type config
861 // |<-------------- Features -------------->|<---------- Levels ----------->|
862 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
863 #define C_DEBUG_TRACE_TYPE 0x0000 // Level = BASIC; Features = Timer + Buffer Header + Burst.
864
865 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
866 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability
867 // Currently not supported !
868 #endif
869 #else
870 // DSP debug trace API buufer config
871 #define C_DEBUG_BUFFER_ADD 0x17ff // Address of DSP write pointer... data are just after.
872 #define C_DEBUG_BUFFER_SIZE 2047 // Real size is incremented by 1 for DSP write pointer.
873
874 // DSP debug trace type config
875 // |<-------------- Features -------------->|<---------- Levels ----------->|
876 // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
877 #define C_DEBUG_TRACE_TYPE 0x0012 // Level = BASIC; Features = Buffer Header.
878
879 #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
880 #define DSP_DEBUG_TRACE_ENABLE 1 // Enable DSP debug trace dumping capability (supported since patch 2090)
881 #endif
882
883 // AMR trace
884 #define C_AMR_TRACE_ID 55
885
886 #endif
887 /* d_error_status */
888 /*-------------------------------*/
889
890 #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
891 #define D_ERROR_STATUS_TRACE_ENABLE 1 // Enable d_error_status checking capability (supported since patch 2090)
892
893 // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
894 #define DSP_DEBUG_GSM_MASK 0x08BD
895 #define DSP_DEBUG_GPRS_MASK 0x0f3d
896 #endif
897 #endif // DSP
898
899 /*------------------------------------*/
900 /* Default value */
901 /*------------------------------------*/
902 #ifndef W_A_DSP1
903 #define W_A_DSP1 0
904 #endif
905
906 #ifndef DATA14_4
907 #define DATA14_4 0
908 #endif
909
910 #ifndef W_A_ITFORCE
911 #define W_A_ITFORCE 0
912 #endif
913
914 #ifndef W_A_DSP_IDLE3
915 #define W_A_DSP_IDLE3 0
916 #endif
917
918 #ifndef L1_NEW_AEC
919 #define L1_NEW_AEC 0
920 #endif
921
922 #ifndef DSP_DEBUG_TRACE_ENABLE
923 #define DSP_DEBUG_TRACE_ENABLE 0
924 #endif
925
926 #ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
927 #define DEBUG_DEDIC_TCH_BLOCK_STAT 0
928 #endif
929
930 #ifndef D_ERROR_STATUS_TRACE_ENABLE
931 #define D_ERROR_STATUS_TRACE_ENABLE 0
932 #endif
933
934 #ifndef L1_GTT
935 #define L1_GTT 0
936 #define TTY_SYNC_MCU 0
937 #define TTY_SYNC_MCU_2 0
938 #define L1_GTT_FIFO_TEST_ATOMIC 0
939 #define NEW_WKA_PATCH 0
940 #define OPTIMISED 0
941 #endif
942
943 #ifndef L1_AMR_NSYNC
944 #define L1_AMR_NSYNC 0
945 #endif
946
947 #ifndef FF_L1_TCH_VOCODER_CONTROL
948 #define FF_L1_TCH_VOCODER_CONTROL 0
949 #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0
950 #endif
951
952 /*------------------------------------*/
953 /* Download */
954 /*------------------------------------*/
955
956
957 /* Possible values for the download status */
958
959 #define LEAD_READY 1
960 #define BLOCK_READY 2
961 #define PROGRAM_DONE 3
962 #define PAGE_SELECTION 4
963
964
965 /************************************/
966 /* Options of compilation... */
967 /************************************/
968
969 // Possible choice of hardware plateform.
970 #define GEMINI 1 // GEMINI chip (rom dsp code)
971 #define POLESTAR 2 // POLESTAR chip (no rom)
972
973 // Possible choice for DSP software setup.
974 #define NO_DWNLD 0
975 #define PATCH_DWNLD 1
976 #define DSP_DWNLD 2
977 #define PATCH_DSP_DWNLD 3
978
979 // MAC-S status reporting to Layer 1
980 #define MACS_STATUS 0 // MAC-S STATUS activated if set to 1
981
982
983 // Possible choice for dll_dcch_downlink interface (with FN or without FN)
984 #define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
985
986 //---------------------------------------------------------------------------------
987
988 // Neighbor Cell RXLEV indication
989 #if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
990 #define L1_MPHC_RXLEV_IND_REPORT_SORT 1
991 #else
992 #define L1_MPHC_RXLEV_IND_REPORT_SORT 0
993 #endif
994
995 #endif /* __L1_CONFG_H__ */