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comparison gsm-fw/L1/cust0/l1_rf10.h @ 152:26472940e5b0

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l1_rf<N>.h headers preened
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 17 Nov 2013 04:59:55 +0000
parents d0de2d0a426d
children
comparison
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151:d0de2d0a426d 152:26472940e5b0
71 /******************************************************/ 71 /******************************************************/
72 /* TXPWR configuration... */ 72 /* TXPWR configuration... */
73 /* Fixed TXPWR value when GSM management is disabled. */ 73 /* Fixed TXPWR value when GSM management is disabled. */
74 /******************************************************/ 74 /******************************************************/
75 75
76 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 76 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
77 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252 77 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252
78 // #define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE) 78 // #define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE)
79 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15 79 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15
80 #endif 80 #endif
81 81
84 /************************************/ 84 /************************************/
85 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal 85 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
86 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block 86 #define UL_DELAY_1RF 5 // time spent in the first uplink RF block
87 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block 87 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
88 88
89 #if (ANLG_FAM == 1) 89 #if (ANALOG == 1)
90 #define UL_ABB_DELAY 6 // modulator input to output delay 90 #define UL_ABB_DELAY 6 // modulator input to output delay
91 #endif 91 #endif
92 92
93 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) 93 #if ((ANALOG == 2) || (ANALOG == 3))
94 #define UL_ABB_DELAY 3 // modulator input to output delay 94 #define UL_ABB_DELAY 3 // modulator input to output delay
95 #endif 95 #endif
96 96
97 /************************************/ 97 /************************************/
98 /* TX Propagation delay... */ 98 /* TX Propagation delay... */
99 /************************************/ 99 /************************************/
100 #if (ANLG_FAM == 1) 100 #if (ANALOG == 1)
101 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 101 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
102 #endif 102 #endif
103 103
104 #if (ANLG_FAM == 2) || (ANLG_FAM == 3) 104 #if (ANALOG == 2) || (ANALOG == 3)
105 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY + 2) // = 42 105 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY + 2) // = 42
106 #endif 106 #endif
107 107
108 /************************************/ 108 /************************************/
109 /* Initial value for APC DELAY */ 109 /* Initial value for APC DELAY */
110 /************************************/ 110 /************************************/
111 111
112 #if (ANLG_FAM == 1) 112 #if (ANALOG == 1)
113 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 113 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
114 #define APCDEL_DOWN 2 // minimum value: 2 114 #define APCDEL_DOWN 2 // minimum value: 2
115 #define APCDEL_UP (6+5) // minimum value: 6 115 #define APCDEL_UP (6+5) // minimum value: 6
116 #endif 116 #endif
117 117
118 #if (ANLG_FAM == 2) || (ANLG_FAM == 3) 118 #if (ANALOG == 2) || (ANALOG == 3)
119 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 119 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
120 #define APCDEL_DOWN (2+0) // minimum value: 2 120 #define APCDEL_DOWN (2+0) // minimum value: 2
121 #define APCDEL_UP (6+8) // minimum value: 6 121 #define APCDEL_UP (6+8) // minimum value: 6
122 #endif 122 #endif
123 123
134 134
135 /************************************/ 135 /************************************/
136 /* Baseband registers */ 136 /* Baseband registers */
137 /************************************/ 137 /************************************/
138 138
139 #if (ANLG_FAM == 1) 139 #if (ANALOG == 1)
140 140
141 // Omega registers values will be programmed at 1st DSP communication interrupt 141 // Omega registers values will be programmed at 1st DSP communication interrupt
142 142
143 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG 143 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
144 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset 144 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
154 // BULRUDEL will be initialized on rach only .... 154 // BULRUDEL will be initialized on rach only ....
155 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1) 155 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
156 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified' 156 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
157 #endif 157 #endif
158 158
159 #if (ANLG_FAM == 2) 159 #if (ANALOG == 2)
160 160
161 // IOTA registers values will be programmed at 1st DSP communication interrupt 161 // IOTA registers values will be programmed at 1st DSP communication interrupt
162 162
163 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG 163 #define C_DEBUG1 (0x0000 | TRUE ) // Enable f_tx delay of 400000 cyc DEBUG
164 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset 164 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
179 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE ) // External RX I/Q DC offset calibration, Output common mode=1.35V 179 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE ) // External RX I/Q DC offset calibration, Output common mode=1.35V
180 // Monoslot, Vpp=8/15*Vref 180 // Monoslot, Vpp=8/15*Vref
181 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB 181 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE ) // IAG=0 dB, QAG=0 dB
182 #endif 182 #endif
183 183
184 #if (ANLG_FAM == 3) 184 #if (ANALOG == 3)
185 185
186 // SYREN registers values will be programmed at 1st DSP communication interrupt 186 // SYREN registers values will be programmed at 1st DSP communication interrupt
187 187
188 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG 188 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
189 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset 189 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
303 }T_RF_AGC_BAND; 303 }T_RF_AGC_BAND;
304 304
305 /************************************/ 305 /************************************/
306 /* Ramp definitions */ 306 /* Ramp definitions */
307 /************************************/ 307 /************************************/
308 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 308 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
309 typedef struct 309 typedef struct
310 { 310 {
311 UWORD8 ramp_up [16]; // Ramp-up profile 311 UWORD8 ramp_up [16]; // Ramp-up profile
312 UWORD8 ramp_down [16]; // Ramp-down profile 312 UWORD8 ramp_down [16]; // Ramp-down profile
313 } 313 }
554 554
555 /************************************/ 555 /************************************/
556 /* ABB (Omega) Initialization */ 556 /* ABB (Omega) Initialization */
557 /************************************/ 557 /************************************/
558 558
559 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) 559 #if ((ANALOG == 1) || (ANALOG == 2))
560 #define ABB_TABLE_SIZE 16 560 #define ABB_TABLE_SIZE 16
561 #endif 561 #endif
562 562
563 #if (ANLG_FAM == 3) 563 #if (ANALOG == 3)
564 #define ABB_TABLE_SIZE 22 564 #define ABB_TABLE_SIZE 22
565 #endif 565 #endif
566 566
567 // Note that this translation is probably not needed at all. But until L1 is 567 // Note that this translation is probably not needed at all. But until L1 is
568 // (maybe) changed to simply initialize the ABB from a table of words, we 568 // (maybe) changed to simply initialize the ABB from a table of words, we
569 // use this to make things more easy-readable. 569 // use this to make things more easy-readable.
570 #if (ANLG_FAM == 1) 570 #if (ANALOG == 1)
571 enum ABB_REGISTERS { 571 enum ABB_REGISTERS {
572 ABB_AFCCTLADD = 0, 572 ABB_AFCCTLADD = 0,
573 ABB_VBUCTRL, 573 ABB_VBUCTRL,
574 ABB_VBDCTRL, 574 ABB_VBDCTRL,
575 ABB_BBCTRL, 575 ABB_BBCTRL,
581 ABB_VBCTRL, 581 ABB_VBCTRL,
582 ABB_APCDEL1 582 ABB_APCDEL1
583 }; 583 };
584 #endif 584 #endif
585 585
586 #if (ANLG_FAM == 2) 586 #if (ANALOG == 2)
587 enum ABB_REGISTERS { 587 enum ABB_REGISTERS {
588 ABB_AFCCTLADD = 0, 588 ABB_AFCCTLADD = 0,
589 ABB_VBUCTRL, 589 ABB_VBUCTRL,
590 ABB_VBDCTRL, 590 ABB_VBDCTRL,
591 ABB_BBCTRL, 591 ABB_BBCTRL,
600 ABB_APCDEL1, 600 ABB_APCDEL1,
601 ABB_APCDEL2 601 ABB_APCDEL2
602 }; 602 };
603 #endif 603 #endif
604 604
605 #if (ANLG_FAM == 3) 605 #if (ANALOG == 3)
606 enum ABB_REGISTERS { 606 enum ABB_REGISTERS {
607 ABB_AFCCTLADD = 0, 607 ABB_AFCCTLADD = 0,
608 ABB_VBUCTRL, 608 ABB_VBUCTRL,
609 ABB_VBDCTRL, 609 ABB_VBDCTRL,
610 ABB_BBCTRL, 610 ABB_BBCTRL,