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comparison gsm-fw/L1/cust0/l1_rf12.h @ 152:26472940e5b0

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l1_rf<N>.h headers preened
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 17 Nov 2013 04:59:55 +0000
parents d0de2d0a426d
children
comparison
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151:d0de2d0a426d 152:26472940e5b0
80 /******************************************************/ 80 /******************************************************/
81 /* TXPWR configuration... */ 81 /* TXPWR configuration... */
82 /* Fixed TXPWR value when GSM management is disabled. */ 82 /* Fixed TXPWR value when GSM management is disabled. */
83 /******************************************************/ 83 /******************************************************/
84 84
85 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 85 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
86 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252 86 // #define FIXED_TXPWR ((0xFC<<6) | AUXAPC | FALSE) // TXPWR=10, value=252
87 //#define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE) 87 //#define FIXED_TXPWR ((0x65<<6) | AUXAPC | FALSE)
88 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15 88 #define FIXED_TXPWR ((0x74<<6) | AUXAPC | FALSE) // TXPWR=15
89 #endif 89 #endif
90 90
93 /* ANALOG delay (in qbits) */ 93 /* ANALOG delay (in qbits) */
94 /************************************/ 94 /************************************/
95 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal 95 #define DL_DELAY_RF 1 // time spent in the Downlink global RF chain by the modulated signal
96 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block 96 #define UL_DELAY_1RF 7 // time spent in the first uplink RF block
97 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block 97 #define UL_DELAY_2RF 0 // time spent in the second uplink RF block
98 #if (ANLG_FAM == 1) 98 #if (ANALOG == 1)
99 #define UL_ABB_DELAY 3 // modulator input to output delay 99 #define UL_ABB_DELAY 3 // modulator input to output delay
100 #endif 100 #endif
101 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) 101 #if ((ANALOG == 2) || (ANALOG == 3))
102 #define UL_ABB_DELAY 3 // modulator input to output delay 102 #define UL_ABB_DELAY 3 // modulator input to output delay
103 #endif 103 #endif
104 104
105 /************************************/ 105 /************************************/
106 /* TX Propagation delay... */ 106 /* TX Propagation delay... */
107 /************************************/ 107 /************************************/
108 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 108 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
109 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40 109 #define PRG_TX (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY) // = 40
110 #endif 110 #endif
111 111
112 /************************************/ 112 /************************************/
113 /* Initial value for APC DELAY */ 113 /* Initial value for APC DELAY */
114 /************************************/ 114 /************************************/
115 #if (ANLG_FAM == 1) 115 #if (ANALOG == 1)
116 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 116 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
117 #define APCDEL_DOWN 2 // minimum value: 2 117 #define APCDEL_DOWN 2 // minimum value: 2
118 #define APCDEL_UP (6+5) // minimum value: 6 118 #define APCDEL_UP (6+5) // minimum value: 6
119 #endif 119 #endif
120 120
121 #if (ANLG_FAM == 2) || (ANLG_FAM == 3) 121 #if (ANALOG == 2) || (ANALOG == 3)
122 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2 122 //#define APCDEL_DOWN (32 - GUARD_BITS*4) // minimum value: 2
123 #define APCDEL_DOWN (2+0) // minimum value: 2 123 #define APCDEL_DOWN (2+0) // minimum value: 2
124 #define APCDEL_UP (6+3+1) // minimum value: 6 124 #define APCDEL_UP (6+3+1) // minimum value: 6
125 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8) 125 // REMOVE // Jerome Modif for ARF7: (6+3) instead of (6+8)
126 #endif 126 #endif
136 // Rita (RF=12) LDO wakeup requires 6 frames 136 // Rita (RF=12) LDO wakeup requires 6 frames
137 137
138 /************************************/ 138 /************************************/
139 /* Baseband registers */ 139 /* Baseband registers */
140 /************************************/ 140 /************************************/
141 #if (ANLG_FAM == 1) 141 #if (ANALOG == 1)
142 // Omega registers values will be programmed at 1st DSP communication interrupt 142 // Omega registers values will be programmed at 1st DSP communication interrupt
143 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG 143 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
144 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset 144 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
145 #define C_VBUCTRL ((0x106 << 6) | VBUCTRL | TRUE) // Uplink gain amp 0dB, Sidetone gain to mute 145 #define C_VBUCTRL ((0x106 << 6) | VBUCTRL | TRUE) // Uplink gain amp 0dB, Sidetone gain to mute
146 #define C_VBDCTRL ((0x026 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control 0 dB 146 #define C_VBDCTRL ((0x026 << 6) | VBDCTRL | TRUE) // Downlink gain amp 0dB, Volume control 0 dB
155 // BULRUDEL will be initialized on rach only .... 155 // BULRUDEL will be initialized on rach only ....
156 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1) 156 #define C_APCDEL1 (((APCDEL_DOWN-2) << 11) | ((APCDEL_UP-6) << 6) | APCDEL1)
157 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified' 157 #define C_BBCTRL ((0x181 << 6) | BBCTRL | TRUE) // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
158 #endif 158 #endif
159 159
160 #if (ANLG_FAM == 2) 160 #if (ANALOG == 2)
161 161
162 // IOTA registers values will be programmed at 1st DSP communication interrupt 162 // IOTA registers values will be programmed at 1st DSP communication interrupt
163 163
164 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG 164 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
165 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset 165 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
193 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V 193 #define C_BBCTRL ((0x2C1 << 6) | BBCTRL | TRUE) // Internal autocalibration, Output common mode=1.35V
194 // Monoslot, Vpp=8/15*Vref 194 // Monoslot, Vpp=8/15*Vref
195 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB 195 #define C_BULGCAL ((0x000 << 6) | BULGCAL | TRUE) // IAG=0 dB, QAG=0 dB
196 #endif 196 #endif
197 197
198 #if (ANLG_FAM == 3) 198 #if (ANALOG == 3)
199 199
200 // SYREN registers values will be programmed at 1st DSP communication interrupt 200 // SYREN registers values will be programmed at 1st DSP communication interrupt
201 201
202 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG 202 #define C_DEBUG1 0x0001 // Enable f_tx delay of 400000 cyc DEBUG
203 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset 203 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE) // Value at reset
330 }T_RF_AGC_BAND; 330 }T_RF_AGC_BAND;
331 331
332 /************************************/ 332 /************************************/
333 /* Ramp definitions */ 333 /* Ramp definitions */
334 /************************************/ 334 /************************************/
335 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 335 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
336 typedef struct 336 typedef struct
337 { 337 {
338 UWORD8 ramp_up [16]; // Ramp-up profile 338 UWORD8 ramp_up [16]; // Ramp-up profile
339 UWORD8 ramp_down [16]; // Ramp-down profile 339 UWORD8 ramp_down [16]; // Ramp-down profile
340 } 340 }
568 568
569 /************************************/ 569 /************************************/
570 /* ABB (Omega) Initialization */ 570 /* ABB (Omega) Initialization */
571 /************************************/ 571 /************************************/
572 572
573 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) 573 #if ((ANALOG == 1) || (ANALOG == 2))
574 #define ABB_TABLE_SIZE 16 574 #define ABB_TABLE_SIZE 16
575 #elif (ANLG_FAM == 3) 575 #elif (ANALOG == 3)
576 #define ABB_TABLE_SIZE 22 576 #define ABB_TABLE_SIZE 22
577 #endif 577 #endif
578 578
579 // Note that this translation is probably not needed at all. But until L1 is 579 // Note that this translation is probably not needed at all. But until L1 is
580 // (maybe) changed to simply initialize the ABB from a table of words, we 580 // (maybe) changed to simply initialize the ABB from a table of words, we
581 // use this to make things more easy-readable. 581 // use this to make things more easy-readable.
582 582
583 #if (ANLG_FAM == 1) 583 #if (ANALOG == 1)
584 enum ABB_REGISTERS { 584 enum ABB_REGISTERS {
585 ABB_AFCCTLADD = 0, 585 ABB_AFCCTLADD = 0,
586 ABB_VBUCTRL, 586 ABB_VBUCTRL,
587 ABB_VBDCTRL, 587 ABB_VBDCTRL,
588 ABB_BBCTRL, 588 ABB_BBCTRL,
592 ABB_DAI_ON_OFF, 592 ABB_DAI_ON_OFF,
593 ABB_AUXDAC, 593 ABB_AUXDAC,
594 ABB_VBCTRL, 594 ABB_VBCTRL,
595 ABB_APCDEL1 595 ABB_APCDEL1
596 }; 596 };
597 #elif (ANLG_FAM == 2) 597 #elif (ANALOG == 2)
598 enum ABB_REGISTERS { 598 enum ABB_REGISTERS {
599 ABB_AFCCTLADD = 0, 599 ABB_AFCCTLADD = 0,
600 ABB_VBUCTRL, 600 ABB_VBUCTRL,
601 ABB_VBDCTRL, 601 ABB_VBDCTRL,
602 ABB_BBCTRL, 602 ABB_BBCTRL,
609 ABB_VBCTRL1, 609 ABB_VBCTRL1,
610 ABB_VBCTRL2, 610 ABB_VBCTRL2,
611 ABB_APCDEL1, 611 ABB_APCDEL1,
612 ABB_APCDEL2 612 ABB_APCDEL2
613 }; 613 };
614 #elif (ANLG_FAM == 3) 614 #elif (ANALOG == 3)
615 enum ABB_REGISTERS { 615 enum ABB_REGISTERS {
616 ABB_AFCCTLADD = 0, 616 ABB_AFCCTLADD = 0,
617 ABB_VBUCTRL, 617 ABB_VBUCTRL,
618 ABB_VBDCTRL, 618 ABB_VBDCTRL,
619 ABB_BBCTRL, 619 ABB_BBCTRL,