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comparison gsm-fw/L1/cust0/l1_rf2.h @ 152:26472940e5b0

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l1_rf<N>.h headers preened
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 17 Nov 2013 04:59:55 +0000
parents d0de2d0a426d
children
comparison
equal deleted inserted replaced
151:d0de2d0a426d 152:26472940e5b0
31 31
32 /************************************/ 32 /************************************/
33 /* TXPWR configuration... */ 33 /* TXPWR configuration... */
34 /************************************/ 34 /************************************/
35 35
36 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 36 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
37 #define FIXED_TXPWR ((0x1FF << 6) | AUXAPC | FALSE) // TXPWR=15 37 #define FIXED_TXPWR ((0x1FF << 6) | AUXAPC | FALSE) // TXPWR=15
38 // #define FIXED_TXPWR ((0xFF << 6) | AUXAPC | FALSE) 38 // #define FIXED_TXPWR ((0xFF << 6) | AUXAPC | FALSE)
39 #endif 39 #endif
40 40
41 /************************************/ 41 /************************************/
42 /* TX Propagation delay... */ 42 /* TX Propagation delay... */
43 /************************************/ 43 /************************************/
44 44
45 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 45 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
46 // #define PRG_TX ( 52L ) 46 // #define PRG_TX ( 52L )
47 #define PRG_TX ( 8L) 47 #define PRG_TX ( 8L)
48 #endif 48 #endif
49 49
50 /************************************/ 50 /************************************/
61 61
62 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC and RF Band Gap(in Frames) 62 #define SETUP_AFC_AND_RF 2 // time to have a stable output of the AFC and RF Band Gap(in Frames)
63 // !! minimum Value : 1 Frame due to the fact there is no 63 // !! minimum Value : 1 Frame due to the fact there is no
64 // hisr() in the first wake-up frame !!!! 64 // hisr() in the first wake-up frame !!!!
65 65
66 #if (ANLG_FAM == 1) 66 #if (ANALOG == 1)
67 /************************************/ 67 /************************************/
68 /* Omega power on... */ 68 /* Omega power on... */
69 /************************************/ 69 /************************************/
70 // Omega registers values will be programmed at 1st DSP communication interrupt 70 // Omega registers values will be programmed at 1st DSP communication interrupt
71 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG 71 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
82 82
83 // BULRUDEL will be initialized on rach only .... 83 // BULRUDEL will be initialized on rach only ....
84 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | FALSE) 84 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | FALSE)
85 #endif 85 #endif
86 86
87 #if (ANLG_FAM == 2) 87 #if (ANALOG == 2)
88 /************************************/ 88 /************************************/
89 /* Iota power on... */ 89 /* Iota power on... */
90 /************************************/ 90 /************************************/
91 // Iota registers values will be programmed at 1st DSP communication interrupt 91 // Iota registers values will be programmed at 1st DSP communication interrupt
92 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG 92 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
106 // BULRUDEL will be initialized on rach only .... 106 // BULRUDEL will be initialized on rach only ....
107 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | TRUE ) 107 #define C_APCDEL1 ((0x000 << 6) | APCDEL1 | TRUE )
108 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE ) 108 #define C_APCDEL2 ((0x000 << 6) | APCDEL2 | TRUE )
109 #endif 109 #endif
110 110
111 #if (ANLG_FAM == 3) 111 #if (ANALOG == 3)
112 // SYREN registers values will be programmed at 1st DSP communication interrupt 112 // SYREN registers values will be programmed at 1st DSP communication interrupt
113 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG 113 #define C_DEBUG1 (0x0000 | FALSE) // Enable f_tx delay of 400000 cyc DEBUG
114 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset 114 #define C_AFCCTLADD ((0x000 << 6) | AFCCTLADD | TRUE ) // Value at reset
115 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB 115 #define C_VBUCTRL ((0x0C9 << 6) | VBUCTRL | TRUE ) // Side tone -17 dB, PGA_UL 3 dB
116 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB 116 #define C_VBDCTRL ((0x006 << 6) | VBDCTRL | TRUE ) // PGA_DL 0dB, Volume -12 dB
210 210
211 /************************************/ 211 /************************************/
212 /* Ramp definitions */ 212 /* Ramp definitions */
213 /************************************/ 213 /************************************/
214 214
215 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) 215 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
216 typedef struct 216 typedef struct
217 { 217 {
218 UWORD8 ramp_up [16]; // Ramp-up profile 218 UWORD8 ramp_up [16]; // Ramp-up profile
219 UWORD8 ramp_down [16]; // Ramp-down profile 219 UWORD8 ramp_down [16]; // Ramp-down profile
220 } 220 }
458 458
459 459
460 /************************************/ 460 /************************************/
461 /* ABB (Omega) Initialization */ 461 /* ABB (Omega) Initialization */
462 /************************************/ 462 /************************************/
463 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) 463 #if ((ANALOG == 1) || (ANALOG == 2))
464 #define ABB_TABLE_SIZE 16 464 #define ABB_TABLE_SIZE 16
465 #endif 465 #endif
466 466
467 #if (ANLG_FAM == 3) 467 #if (ANALOG == 3)
468 #define ABB_TABLE_SIZE 22 468 #define ABB_TABLE_SIZE 22
469 #endif 469 #endif
470 470
471 // Note that this translation is probably not needed at all. But until L1 is 471 // Note that this translation is probably not needed at all. But until L1 is
472 // (maybe) changed to simply initialize the ABB from a table of words, we 472 // (maybe) changed to simply initialize the ABB from a table of words, we
473 // use this to make things more easy-readable. 473 // use this to make things more easy-readable.
474 #if (ANLG_FAM == 1) 474 #if (ANALOG == 1)
475 enum ABB_REGISTERS { 475 enum ABB_REGISTERS {
476 ABB_AFCCTLADD = 0, 476 ABB_AFCCTLADD = 0,
477 ABB_VBUCTRL, 477 ABB_VBUCTRL,
478 ABB_VBDCTRL, 478 ABB_VBDCTRL,
479 ABB_BBCTRL, 479 ABB_BBCTRL,
483 ABB_DAI_ON_OFF, 483 ABB_DAI_ON_OFF,
484 ABB_AUXDAC, 484 ABB_AUXDAC,
485 ABB_VBCTRL, 485 ABB_VBCTRL,
486 ABB_APCDEL1 486 ABB_APCDEL1
487 }; 487 };
488 #elif (ANLG_FAM == 2) 488 #elif (ANALOG == 2)
489 enum ABB_REGISTERS { 489 enum ABB_REGISTERS {
490 ABB_AFCCTLADD = 0, 490 ABB_AFCCTLADD = 0,
491 ABB_VBUCTRL, 491 ABB_VBUCTRL,
492 ABB_VBDCTRL, 492 ABB_VBDCTRL,
493 ABB_BBCTRL, 493 ABB_BBCTRL,
500 ABB_VBCTRL1, 500 ABB_VBCTRL1,
501 ABB_VBCTRL2, 501 ABB_VBCTRL2,
502 ABB_APCDEL1, 502 ABB_APCDEL1,
503 ABB_APCDEL2 503 ABB_APCDEL2
504 }; 504 };
505 #elif (ANLG_FAM == 3) 505 #elif (ANALOG == 3)
506 enum ABB_REGISTERS { 506 enum ABB_REGISTERS {
507 ABB_AFCCTLADD = 0, 507 ABB_AFCCTLADD = 0,
508 ABB_VBUCTRL, 508 ABB_VBUCTRL,
509 ABB_VBDCTRL, 509 ABB_VBDCTRL,
510 ABB_BBCTRL, 510 ABB_BBCTRL,