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comparison nuc-fw/nucleus/tct.S @ 132:2c5160a9d652

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nuc-fw: switched from nucdemo to Riviera, got some serial output
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 02 Nov 2013 01:48:11 +0000
parents 947b1f473960
children
comparison
equal deleted inserted replaced
131:035672b72f9b 132:2c5160a9d652
2289 BEQ TCT_Not_Nested_Save @ No 2289 BEQ TCT_Not_Nested_Save @ No
2290 2290
2291 @ Nested interrupt. Save complete context on the current stack. 2291 @ Nested interrupt. Save complete context on the current stack.
2292 TCT_Nested_Save: 2292 TCT_Nested_Save:
2293 2293
2294 /* No longer needed in the FreeCalypso version, as we can use r0 instead. */
2295 #if 0
2294 @ 1. Save another register on the exception stack so we have enough to work with 2296 @ 1. Save another register on the exception stack so we have enough to work with
2295 STMDB r13!,{r5} 2297 STMDB r13!,{r5}
2298 #endif
2296 2299
2297 @ 2. Save the necessary exception registers into r1-r3 2300 @ 2. Save the necessary exception registers into r1-r3
2298 MOV r1,r13 @ Put the exception r13 into r1 2301 MOV r1,r13 @ Put the exception r13 into r1
2299 MOV r2,r14 @ Move the return address for the caller 2302 MOV r2,r14 @ Move the return address for the caller
2300 @ of this function into r2 2303 @ of this function into r2
2301 MRS r3,spsr @ Put the exception spsr into r3 2304 MRS r3,spsr @ Put the exception spsr into r3
2302 2305
2303 @ 3. Adjust the exception stack pointer for future exceptions 2306 @ 3. Adjust the exception stack pointer for future exceptions
2304 ADD r13,r13,#24 @ r13 will point to enable reg value when done 2307 ADD r13,r13,#20 @ r13 reset to pre-interrupt value
2305 2308
2306 @ 4. Switch CPU modes to save context on system stack 2309 @ 4. Switch CPU modes to save context on system stack
2307 MRS r5,CPSR @ Pickup the current CPSR 2310 MRS r0,CPSR @ Pickup the current CPSR
2308 BIC r5,r5,#MODE_MASK @ Clear the mode bits 2311 BIC r0,r0,#MODE_MASK @ Clear the mode bits
2309 2312
2310 ORR r5,r5,#SUP_MODE @ Change to supervisor mode (SVD) 2313 ORR r0,r0,#SUP_MODE @ Change to supervisor mode (SVD)
2311 2314
2312 MSR CPSR,r5 @ Switch modes (IRQ->SVC) 2315 MSR CPSR,r0 @ Switch modes (IRQ->SVC)
2313 2316
2314 @ 5. Store the SVC r13 into r5 so the r13 can be saved as is. 2317 @ 5. Store the SVC r13 into r5 so the r13 can be saved as is.
2315 MOV r5,r13 2318 @ FreeCalyspo: using r0 instead
2319 MOV r0,r13
2316 2320
2317 @ 6. Save the exception return address on the stack (r15). 2321 @ 6. Save the exception return address on the stack (r15).
2318 STMDB r5!,{r4} 2322 STMDB r0!,{r4}
2319 2323
2320 @ 7. Save r6-r14 on stack 2324 @ 7. Save r5-r14 on stack (used to be r6-r14)
2321 STMDB r5!,{r6-r14} 2325 STMDB r0!,{r5-r14}
2322 2326
2323 @ 8. Switch back to using r13 now that the original r13 has been saved. 2327 @ 8. Switch back to using r13 now that the original r13 has been saved.
2324 MOV r13,r5 2328 MOV r13,r0
2325 2329
2330 /* no longer relevant */
2331 #if 0
2326 @ 9. Get r5 and exception enable registers off of exception stack and 2332 @ 9. Get r5 and exception enable registers off of exception stack and
2327 @ save r5 (stored in r4) back to the system stack. 2333 @ save r5 (stored in r4) back to the system stack.
2328 LDMIA r1!,{r4-r5} 2334 LDMIA r1!,{r4-r5}
2329 STMDB r13!,{r4} 2335 STMDB r13!,{r4}
2330 MOV r4,r5 @ Put exception enable value into r4 2336 MOV r4,r5 @ Put exception enable value into r4
2337 #endif
2331 2338
2332 @ 10. Get the rest of the registers off the exception stack and 2339 @ 10. Get the rest of the registers off the exception stack and
2333 @ save them onto the system stack. 2340 @ save them onto the system stack.
2334 LDMIA r1!,{r5-r8,r11} @ Get r0-r4 off exception stack 2341 LDMIA r1!,{r5-r8,r11} @ Get r0-r4 off exception stack
2335 STMDB r13!,{r5-r8,r11} @ Put r0-r4 on system stack 2342 STMDB r13!,{r5-r8,r11} @ Put r0-r4 on system stack
2336 2343
2344 /* no longer relevant */
2345 #if 0
2337 @ 11. Store the exception enable value back on the exception stack. 2346 @ 11. Store the exception enable value back on the exception stack.
2338 STMDB r1,{r4} 2347 STMDB r1,{r4}
2348 #endif
2339 2349
2340 @ 12. Save the SPSR on the system stack (CPSR) 2350 @ 12. Save the SPSR on the system stack (CPSR)
2341 STMDB r13!,{r3} 2351 STMDB r13!,{r3}
2342 2352
2353 /* TI's approach to interrupt handling does not support re-enabling here */
2354 #if 0
2343 @ 13. Re-enable interrupts 2355 @ 13. Re-enable interrupts
2344 MRS r1,CPSR 2356 MRS r1,CPSR
2345 BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) 2357 BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT)
2346 MSR CPSR,r1 2358 MSR CPSR,r1
2359 #endif
2347 2360
2348 BX r2 @ Return to calling ISR 2361 BX r2 @ Return to calling ISR
2349 @ } 2362 @ }
2350 @ else 2363 @ else
2351 @ { 2364 @ {
2362 2375
2363 2376
2364 @ Yes, a thread was interrupted. Save complete context on the 2377 @ Yes, a thread was interrupted. Save complete context on the
2365 @ thread's stack. 2378 @ thread's stack.
2366 2379
2380 /* No longer needed in the FreeCalypso version, as we can use r0 instead. */
2381 #if 0
2367 @ 1. Save another register on the exception stack so we have enough to work with 2382 @ 1. Save another register on the exception stack so we have enough to work with
2368 STMDB r13!,{r5} 2383 STMDB r13!,{r5}
2384 #endif
2369 2385
2370 @ 2. Save the necessary exception registers into r1-r3 2386 @ 2. Save the necessary exception registers into r1-r3
2371 MOV r1,r13 @ Put the exception r13 into r1 2387 MOV r1,r13 @ Put the exception r13 into r1
2372 MOV r2,r14 @ Move the return address for the caller 2388 MOV r2,r14 @ Move the return address for the caller
2373 @ of this function into r2 2389 @ of this function into r2
2374 MRS r3,spsr @ Put the exception spsr into r3 2390 MRS r3,spsr @ Put the exception spsr into r3
2375 2391
2376 @ 3. Adjust the exception stack pointer for future exceptions 2392 @ 3. Adjust the exception stack pointer for future exceptions
2377 ADD r13,r13,#24 @ r13 will point to enable reg value when done 2393 ADD r13,r13,#20 @ r13 reset to pre-interrupt value
2378 2394
2379 @ 4. Switch CPU modes to save context on system stack 2395 @ 4. Switch CPU modes to save context on system stack
2380 MRS r5,CPSR @ Pickup the current CPSR 2396 MRS r0,CPSR @ Pickup the current CPSR
2381 BIC r5,r5,#MODE_MASK @ Clear the mode bits 2397 BIC r0,r0,#MODE_MASK @ Clear the mode bits
2382 2398
2383 ORR r5,r5,#SUP_MODE @ Change to supervisor mode (SVD) 2399 ORR r0,r0,#SUP_MODE @ Change to supervisor mode (SVD)
2384 2400
2385 MSR CPSR,r5 @ Switch modes (IRQ->SVC) 2401 MSR CPSR,r0 @ Switch modes (IRQ->SVC)
2386 2402
2387 @ 5. Store the SVC r13 into r5 so the r13 can be saved as is. 2403 @ 5. Store the SVC r13 into r5 so the r13 can be saved as is.
2388 MOV r5,r13 2404 @ FreeCalyspo: using r0 instead
2405 MOV r0,r13
2389 2406
2390 @ 6. Save the exception return address on the stack (r15). 2407 @ 6. Save the exception return address on the stack (r15).
2391 STMDB r5!,{r4} 2408 STMDB r0!,{r4}
2392 2409
2393 @ 7. Save r6-r14 on stack 2410 @ 7. Save r5-r14 on stack (used to be r6-r14)
2394 STMDB r5!,{r6-r14} 2411 STMDB r0!,{r5-r14}
2395 2412
2396 @ 8. Switch back to using r13 now that the original r13 has been saved. 2413 @ 8. Switch back to using r13 now that the original r13 has been saved.
2397 MOV r13,r5 2414 MOV r13,r0
2398 2415
2416 /* no longer relevant */
2417 #if 0
2399 @ 9. Get r5 and exception enable registers off of exception stack and 2418 @ 9. Get r5 and exception enable registers off of exception stack and
2400 @ save r5 (stored in r4) back to the system stack. 2419 @ save r5 (stored in r4) back to the system stack.
2401 LDMIA r1!,{r4-r5} 2420 LDMIA r1!,{r4-r5}
2402 STMDB r13!,{r4} 2421 STMDB r13!,{r4}
2403 MOV r4,r5 @ Put exception enable value into r4 2422 MOV r4,r5 @ Put exception enable value into r4
2423 #endif
2404 2424
2405 @ 10. Get the rest of the registers off the exception stack and 2425 @ 10. Get the rest of the registers off the exception stack and
2406 @ save them onto the system stack. 2426 @ save them onto the system stack.
2407 LDMIA r1!,{r5-r8,r11} @ Get r0-r4 off exception stack 2427 LDMIA r1!,{r5-r8,r11} @ Get r0-r4 off exception stack
2408 STMDB r13!,{r5-r8,r11} @ Put r0-r4 on system stack 2428 STMDB r13!,{r5-r8,r11} @ Put r0-r4 on system stack
2409 2429
2430 /* no longer relevant */
2431 #if 0
2410 @ 11. Store the exception enable value back on the exception stack. 2432 @ 11. Store the exception enable value back on the exception stack.
2411 STMDB r1,{r4} 2433 STMDB r1,{r4}
2434 #endif
2412 2435
2413 @ 12. Save the SPSR on the system stack (CPSR) 2436 @ 12. Save the SPSR on the system stack (CPSR)
2414 STMDB r13!,{r3} 2437 STMDB r13!,{r3}
2415 2438
2416 @ 13. Save stack type to the task stack (1=interrupt stack) 2439 @ 13. Save stack type to the task stack (1=interrupt stack)
2431 LDR r1,System_Stack @ Pickup address of stack pointer 2454 LDR r1,System_Stack @ Pickup address of stack pointer
2432 LDR r3,System_Limit @ Pickup address of stack limit ptr 2455 LDR r3,System_Limit @ Pickup address of stack limit ptr
2433 LDR r13,[r1, #0] @ Switch to system stack 2456 LDR r13,[r1, #0] @ Switch to system stack
2434 LDR r10,[r3, #0] @ Setup system stack limit 2457 LDR r10,[r3, #0] @ Setup system stack limit
2435 2458
2459 /* TI's approach to interrupt handling does not support re-enabling here */
2460 #if 0
2436 @ Re-enable interrupts 2461 @ Re-enable interrupts
2437 MRS r1,CPSR 2462 MRS r1,CPSR
2438 BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) 2463 BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT)
2439 MSR CPSR,r1 2464 MSR CPSR,r1
2465 #endif
2440 2466
2441 @ Return to caller ISR. 2467 @ Return to caller ISR.
2442 2468
2443 BX r2 @ Return to caller ISR 2469 BX r2 @ Return to caller ISR
2444 2470
2445 @ } 2471 @ }
2446 2472
2447 TCT_Idle_Context_Save: 2473 TCT_Idle_Context_Save:
2448 2474
2449 MOV r2,r14 @ Save r14 in r2 2475 MOV r2,r14 @ Save r14 in r2
2450 LDR r3,[r13] @ Get exception enable value from stack 2476 @ LDR r3,[r13] @ Get exception enable value from stack
2451 ADD r13,r13,#20 @ Adjust exception r13 for future interrupts 2477 ADD r13,r13,#20 @ Adjust exception r13 for future interrupts
2452 STR r3,[r13] @ Put exception enable value back on stack 2478 @ STR r3,[r13] @ Put exception enable value back on stack
2453 2479
2454 MRS r1,CPSR @ Pickup current CPSR 2480 MRS r1,CPSR @ Pickup current CPSR
2455 BIC r1,r1,#MODE_MASK @ Clear the current mode 2481 BIC r1,r1,#MODE_MASK @ Clear the current mode
2456 BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) @ Re-enable interrupts 2482 @ BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) @ Re-enable interrupts
2457 2483
2458 ORR r1,r1,#SUP_MODE @ Prepare to switch to supervisor 2484 ORR r1,r1,#SUP_MODE @ Prepare to switch to supervisor
2459 @ mode (SVC) 2485 @ mode (SVC)
2460 MSR CPSR,r1 @ Switch to supervisor mode (SVC) 2486 MSR CPSR,r1 @ Switch to supervisor mode (SVC)
2461 2487
2961 2987
2962 @ Transfer control to the main scheduling loop. 2988 @ Transfer control to the main scheduling loop.
2963 2989
2964 B TCT_Schedule @ Return to main scheduling loop 2990 B TCT_Schedule @ Return to main scheduling loop
2965 @} 2991 @}
2992
2993 /* FreeCalypso addition, used by riviera/rvf/rvf_task.c: */
2994 .globl INT_Check_IRQ_Mask
2995 INT_Check_IRQ_Mask:
2996 MRS r0,CPSR
2997 BX lr
2998