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comparison gsm-fw/L1/audio_cfile/l1audio_init.c @ 610:3121e35f422c

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gsm-fw/L1/audio_cfile/l1audio_init.c: initial preen, doesn't compile yet
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 29 Aug 2014 05:18:05 +0000
parents c5286d24539e
children bbe2b0d17d1e
comparison
equal deleted inserted replaced
609:b8a277d81746 610:3121e35f422c
9 9
10 /************************************/ 10 /************************************/
11 /* Include files... */ 11 /* Include files... */
12 /************************************/ 12 /************************************/
13 13
14 #include "config.h"
15 #include "l1_confg.h"
14 #include "l1_macro.h" 16 #include "l1_macro.h"
15 #include "l1_confg.h"
16 17
17 18
18 #include "l1_types.h" 19 #include "l1_types.h"
19 #include "sys_types.h" 20 #include "sys_types.h"
20 21
108 #if (L1_AAC == 1) 109 #if (L1_AAC == 1)
109 #include "l1aac_defty.h" 110 #include "l1aac_defty.h"
110 #endif 111 #endif
111 112
112 #include "l1_defty.h" 113 #include "l1_defty.h"
113 #include "cust_os.h" 114 #include "../../gpf/inc/cust_os.h"
114 #include "l1_msgty.h" 115 #include "l1_msgty.h"
115 #include "tpudrv.h" // TPU drivers. ("eva3.lib") 116 #include "tpudrv.h"
116 #include "l1_varex.h" 117 #include "l1_varex.h"
117 #include "l1_proto.h" 118 #include "l1_proto.h"
118 #include "l1_mftab.h" 119 #include "l1_mftab.h"
119 #include "l1_tabs.h" 120 #include "l1_tabs.h"
120 #include "mem.h" 121 #include "../../bsp/mem.h"
121 #include "armio.h" 122 #include "../../bsp/armio.h"
122 #include "timer.h" 123 #include "../../bsp/timer.h"
123 #include "timer1.h" 124 #include "../../bsp/timer1.h"
124 #include "dma.h" 125 #include "../../bsp/dma.h"
125 #include "inth.h" 126 #include "../../bsp/inth.h"
126 #include "ulpd.h" 127 #include "../../bsp/ulpd.h"
127 #include "rhea_arm.h" 128 #include "../../bsp/rhea_arm.h"
128 #include "clkm.h" // Clockm ("eva3.lib") 129 #include "../../bsp/clkm.h"
129 #include "l1_ctl.h" 130 #include "l1_ctl.h"
130 #include "l1_time.h" 131 #include "l1_time.h"
131 132
132 #if L2_L3_SIMUL 133 #if L2_L3_SIMUL
133 #include "l1_scen.h" 134 #include "l1_scen.h"
358 l1s_dsp_com.dsp_ndb_ptr->d_lim_dl_ctrl = 0; // Limiter control 359 l1s_dsp_com.dsp_ndb_ptr->d_lim_dl_ctrl = 0; // Limiter control
359 360
360 #endif 361 #endif
361 362
362 363
363
364 #if (DSP == 38) || (DSP == 39) 364 #if (DSP == 38) || (DSP == 39)
365 365
366 //----------------------------------- 366 //-----------------------------------
367 // AUDIO control words initialization 367 // AUDIO control words initialization
368 //----------------------------------- 368 //-----------------------------------
369 369
370 l1s_dsp_com.dsp_ndb_ptr->d_es_ctrl = 0; // ES control 370 l1s_dsp_com.dsp_ndb_ptr->d_es_ctrl = 0; // ES control
371 l1s_dsp_com.dsp_ndb_ptr->d_anr_ul_ctrl = 0; // ANR control 371 l1s_dsp_com.dsp_ndb_ptr->d_anr_ul_ctrl = 0; // ANR control
402 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_enable = (API) 0; 402 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_enable = (API) 0;
403 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_length = (API) 0; 403 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_length = (API) 0;
404 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_shift = (API) 0; 404 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_shift = (API) 0;
405 405
406 for (i=0; i < IIR_4X_FIR_MAX_LENGTH; i++) 406 for (i=0; i < IIR_4X_FIR_MAX_LENGTH; i++)
407 { 407 {
408 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_fir_taps[i] = (API) 0; 408 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_fir_taps[i] = (API) 0;
409 } 409 }
410 410
411 // Set parameters for IIR part 411 // Set parameters for IIR part
412 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_enable = (API) 0; 412 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_enable = (API) 0;
413 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_number = (API) 0; 413 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_number = (API) 0;
414 414
415 // Set parameters for IIR part - SOS 1 415 // Set parameters for IIR part - SOS 1
416 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_1 = (API) 0; 416 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_1 = (API) 0;
417 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_1 = (API) 0; 417 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_1 = (API) 0;
418 418
419 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++) 419 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
420 { 420 {
421 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_1[j] = (API) 0; 421 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_1[j] = (API) 0;
422 } 422 }
423 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++) 423 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
424 { 424 {
425 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_1[j] = (API) 0; 425 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_1[j] = (API) 0;
426 } 426 }
427 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_1 = (API) 0; 427 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_1 = (API) 0;
428 428
429 429
430 // Set parameters for IIR part - SOS 2 430 // Set parameters for IIR part - SOS 2
431 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_2 = (API) 0; 431 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_2 = (API) 0;
432 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_2 = (API) 0; 432 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_2 = (API) 0;
433 433
434 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++) 434 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
435 { 435 {
436 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_2[j] = (API) 0; 436 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_2[j] = (API) 0;
437 } 437 }
438 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++) 438 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
439 { 439 {
440 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_2[j] = (API) 0; 440 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_2[j] = (API) 0;
441 } 441 }
442 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_2 = (API) 0; 442 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_2 = (API) 0;
443 443
444 444
445 // Set parameters for IIR part - SOS 3 445 // Set parameters for IIR part - SOS 3
446 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_3 = (API) 0; 446 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_3 = (API) 0;
447 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_3 = (API) 0; 447 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_3 = (API) 0;
448 448
449 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++) 449 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
450 { 450 {
451 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_3[j] = (API) 0; 451 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_3[j] = (API) 0;
452 } 452 }
453 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++) 453 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
454 { 454 {
455 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_3[j] = (API) 0; 455 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_3[j] = (API) 0;
456 } 456 }
457 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_3 = (API) 0; 457 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_3 = (API) 0;
458 458
459 459
460 // Set parameters for IIR part - SOS 4 460 // Set parameters for IIR part - SOS 4
461 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_4 = (API) 0; 461 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_4 = (API) 0;
462 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_4 = (API) 0; 462 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_4 = (API) 0;
463 463
464 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++) 464 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
465 { 465 {
466 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_4[j] = (API) 0; 466 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_4[j] = (API) 0;
467 } 467 }
468 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++) 468 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
469 { 469 {
470 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_4[j] = (API) 0; 470 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_4[j] = (API) 0;
471 } 471 }
472 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_4 = (API) 0; 472 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_4 = (API) 0;
473 473
474 474
475 // Set parameters for IIR part - SOS 5 475 // Set parameters for IIR part - SOS 5
476 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_5 = (API) 0; 476 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_5 = (API) 0;
477 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_5 = (API) 0; 477 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_5 = (API) 0;
478 478
479 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++) 479 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
480 { 480 {
481 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_5[j] = (API) 0; 481 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_5[j] = (API) 0;
482 } 482 }
483 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++) 483 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
484 { 484 {
485 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_5[j] = (API) 0; 485 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_5[j] = (API) 0;
486 } 486 }
487 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_5 = (API) 0; 487 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_5 = (API) 0;
488 488
489 489
490 // Set parameters for IIR part - SOS 6 490 // Set parameters for IIR part - SOS 6
491 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_6 = (API) 0; 491 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_6 = (API) 0;
492 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_6 = (API) 0; 492 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_6 = (API) 0;
493 493
494 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++) 494 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
495 { 495 {
496 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_6[j] = (API) 0; 496 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_6[j] = (API) 0;
497 } 497 }
498 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++) 498 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
499 { 499 {
500 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_6[j] = (API) 0; 500 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_6[j] = (API) 0;
501 } 501 }
502 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_6 = (API) 0; 502 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_6 = (API) 0;
503
504 503
505 504
506 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_gain = (API) 0; 505 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_gain = (API) 0;
507 506
508 #endif 507 #endif
537 536
538 #if(L1_WCM == 1) 537 #if(L1_WCM == 1)
539 538
540 l1s_dsp_com.dsp_ndb_ptr->d_wcm_mode = (API) 0; 539 l1s_dsp_com.dsp_ndb_ptr->d_wcm_mode = (API) 0;
541 l1s_dsp_com.dsp_ndb_ptr->d_wcm_frame_size = (API) 0; 540 l1s_dsp_com.dsp_ndb_ptr->d_wcm_frame_size = (API) 0;
542 l1s_dsp_com.dsp_ndb_ptr->d_wcm_num_sub_frames = (API) 0; 541 l1s_dsp_com.dsp_ndb_ptr->d_wcm_num_sub_frames = (API) 0;
543 l1s_dsp_com.dsp_ndb_ptr->d_wcm_ratio = (API) 0; 542 l1s_dsp_com.dsp_ndb_ptr->d_wcm_ratio = (API) 0;
544 l1s_dsp_com.dsp_ndb_ptr->d_wcm_threshold = (API) 0; 543 l1s_dsp_com.dsp_ndb_ptr->d_wcm_threshold = (API) 0;
545 #endif 544 #endif
546 545
547 #endif // DSP 38 546 #endif // DSP 38
635 l1s.audio_on_off_ctl.l1_audio_dl_switched_on = FALSE; 634 l1s.audio_on_off_ctl.l1_audio_dl_switched_on = FALSE;
636 635
637 l1s.audio_on_off_ctl.l1_audio_ul_switched_off = TRUE; 636 l1s.audio_on_off_ctl.l1_audio_ul_switched_off = TRUE;
638 l1s.audio_on_off_ctl.l1_audio_dl_switched_off = TRUE; 637 l1s.audio_on_off_ctl.l1_audio_dl_switched_off = TRUE;
639 #endif // L1_AUDIO_MCU_ONOFF 638 #endif // L1_AUDIO_MCU_ONOFF
640 639
641 640
642 #if (L1_DRC == 1) 641 #if (L1_DRC == 1)
643 642
644 // init DRC NDB 643 // init DRC NDB
645 drc_ndb = (T_DRC_MCU_DSP *)API_address_dsp2mcu(C_DRC_API_BASE_ADDRESS); 644 drc_ndb = (T_DRC_MCU_DSP *)API_address_dsp2mcu(C_DRC_API_BASE_ADDRESS);