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nuc-fw: beginning to integrate TI's BSP code
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 31 Aug 2013 23:43:23 +0000
parents
children 5b7403f6ae93
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92:f459043fae0c 93:45911ad957fd
1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : clkm.c
12
13 Description : Set of functions useful to test the Saturn
14 CLKM peripheral
15
16 Project : drivers
17
18 Author : pmonteil@tif.ti.com Patrice Monteil.
19
20 Version number : 1.11
21
22 Date and time : 10/23/01 14:43:31
23
24 Previous delta : 10/23/01 14:43:31
25
26 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.c
27
28 Sccs Id (SID) : '@(#) clkm.c 1.11 10/23/01 14:43:31 '
29
30
31
32 *****************************************************************************/
33
34 //############################################################
35 //############################################################
36 //### Be careful: this file must be placed in Flash Memory ###
37 //### and compiled in 16 bits length intructions ###
38 //### (CF. the function wait_ARM_cycles() ###
39 //############################################################
40 //############################################################
41
42 #include "../include/config.h"
43 #include "../include/sys_types.h"
44
45 #include "mem.h"
46 #include "clkm.h"
47
48 static SYS_UWORD32 ratio_wait_loop = 0;
49
50 #if (CHIPSET == 12)
51 const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE] = {1, 1.5, 2, 3};
52 #endif
53
54 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
55 /*---------------------------------------------------------------/
56 /* CLKM_InitARMClock() */
57 /*--------------------------------------------------------------*/
58 /* Parameters : clk_src : 0x00 means DPLL selected */
59 /* 0x01 means VTCX0 selected */
60 /* 0x03 means CLKIN selected */
61 /* clk_xp5 : Enable 1.5 or 2.5 division factor */
62 /* (0 or 1) */
63 /* clk_div : Division factor applied to clock */
64 /* source */
65 /* WARNING : reverse order in comparison to ULYSSE */
66 /* */
67 /* Return : none */
68 /* Functionality :Initialize the ARM Clock frequency */
69 /*--------------------------------------------------------------*/
70
71 inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5)
72 {
73 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK;
74
75 cntl &= ~(CLKM_CLKIN0 | CLKM_CLKIN_SEL | CLKM_ARM_MCLK_XP5 | CLKM_MCLK_DIV);
76
77 cntl |= ((clk_src << 1) | (clk_xp5 << 3) | (clk_div << 4));
78
79 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl;
80 }
81 #else
82 /*---------------------------------------------------------------/
83 /* CLKM_InitARMClock() */
84 /*--------------------------------------------------------------*/
85 /* Parameters : clk_src : 0x00 means CLKIN selected */
86 /* 0x01 means 32 K selected */
87 /* 0x02 means External clock selected */
88 /* */
89 /* Return : none */
90 /* Functionality :Initialize the ARM Clock frequency */
91 /*--------------------------------------------------------------*/
92
93 inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div)
94 {
95 SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK;
96
97 cntl &= ~(CLKM_LOW_FRQ | CLKM_CLKIN_SEL | CLKM_MCLK_DIV);
98
99 cntl |= ((clk_src << 1) | (clk_div << 4));
100
101 * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl;
102 }
103
104 #endif
105
106
107 /*-------------------------------------------------------*/
108 /* convert_nanosec_to_cycles() */
109 /*-------------------------------------------------------*/
110 /* parameter: time in 10E-9 seconds */
111 /* return: Number of cycles for the wait_ARM_cycles() */
112 /* function */
113 /* */
114 /* Description: */
115 /* ------------ */
116 /* convert x nanoseconds in y cycles used by the ASM loop*/
117 /* function . Before calling this function, call the */
118 /* initialize_wait_loop() function */
119 /* Called when the HardWare needs time to wait */
120 /*-------------------------------------------------------*/
121 inline SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time)
122 {
123 return( time / ratio_wait_loop);
124 }
125
126
127 /*-------------------------------------------------------*/
128 /* initialize_wait_loop() */
129 /*-------------------------------------------------------*/
130 /* */
131 /* Description: */
132 /* ------------ */
133 /* Init the ratio used to convert time->Cycles according */
134 /* to hardware parameters */
135 /* measurement time for this function (ARM 39Mhz, 3 waits*/
136 /* states) = 75 micoseconds */
137 /*-------------------------------------------------------*/
138
139 void initialize_wait_loop(void)
140 {
141 #define NBR_CYCLES_IN_LOOP 5 // this value is got from an oscilloscope measurement
142
143 double src_ratio;
144 double final_ratio;
145
146 SYS_UWORD16 flash_access_size;
147 SYS_UWORD16 flash_wait_state;
148 SYS_UWORD32 nbr;
149 SYS_UWORD32 arm_clock;
150
151 //////////////////////////////////
152 // compute the ARM clock used //
153 //////////////////////////////////
154 {
155 SYS_UWORD16 arm_mclk_xp5;
156 SYS_UWORD16 arm_ratio;
157 SYS_UWORD16 clk_src;
158 SYS_UWORD16 clkm_cntl_arm_clk_reg = * (volatile SYS_UWORD16 *) CLKM_CNTL_ARM_CLK;
159
160 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
161 clk_src = (clkm_cntl_arm_clk_reg & MASK_CLKIN) >> 1;
162 switch (clk_src)
163 {
164 case 0x00: //DPLL selected
165 // select the DPLL factor
166 if (((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK) != 0)
167 {
168 SYS_UWORD16 dpll_div;
169 SYS_UWORD16 dpll_mul;
170
171 dpll_div=DPLL_READ_DPLL_DIV;
172 dpll_mul=DPLL_READ_DPLL_MUL;
173 src_ratio = (double)(dpll_mul)/(double)(dpll_div+1);
174 }
175 else // DPLL in bypass mode
176 {
177 SYS_UWORD16 dpll_div = DPLL_BYPASS_DIV;
178 src_ratio= (double)(1)/(double)(dpll_div+1);
179 }
180 break;
181 case 0x01: //VTCX0 selected
182 src_ratio = 1;
183 break;
184 case 0x03: //CLKIN selected (external clock)
185 src_ratio = 1;
186 break;
187 }
188 // define the division factor applied to clock source (CLKIN or VTCXO or DPLL)
189 arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4;
190
191 // check if the 1.5 or 2.5 division factor is enabled
192 arm_mclk_xp5 = clkm_cntl_arm_clk_reg & CLKM_ARM_MCLK_XP5;
193
194 if (arm_mclk_xp5 == 0) // division factor enable for ARM clock ?
195 {
196 if (arm_ratio == 0)
197 arm_ratio =1;
198 }
199 else
200 arm_ratio = ((arm_ratio>>1) & 0x0001) == 0 ? 1.5 : 2.5;
201
202
203 #else // CHIPSET
204 src_ratio = 1;
205
206 // define the division factor applied to clock source (CLKIN or VTCXO or DPLL)
207 arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4;
208
209 // check if the 1.5 or 2.5 division factor is enabled
210 arm_mclk_xp5 = clkm_cntl_arm_clk_reg & MASK_ARM_MCLK_1P5;
211
212 if (arm_mclk_xp5 == 1) // division factor enable for ARM clock ?
213 arm_ratio = 1.5;
214 else
215 {
216 if (arm_ratio == 0)
217 arm_ratio = 4;
218 else
219 if (arm_ratio == 1 )
220 arm_ratio = 2;
221 else
222 arm_ratio = 1;
223 }
224
225 #endif // CHIPSET
226
227 final_ratio = (src_ratio / (double) arm_ratio);
228
229 }
230 //////////////////////////////////////////
231 // compute the Flash wait states used //
232 //////////////////////////////////////////
233
234 #if (CHIPSET == 12)
235 flash_access_size = *((volatile SYS_UWORD16 *) MEM_REG_nCS5);
236 #else
237 flash_access_size = *((volatile SYS_UWORD16 *) MEM_REG_nCS0);
238 #endif
239 flash_access_size = (flash_access_size >> 5) & 0x0003; // 0=>8bits, 1=>16 bits, 2 =>32 bits
240
241 // the loop file is compiled in 16 bits it means
242 // flash 8 bits => 2 loads for 1 16 bits assembler instruction
243 // flash 16 bits => 1 loads for 1 16 bits assembler instruction
244 // flash 32 bits => 1 loads for 1 16 bits assembler instruction (ARM bus 16 bits !!)
245
246 // !!!!!!!!! be careful: if this file is compile in 32 bits, change these 2 lines here after !!!
247 if (flash_access_size == 0) flash_access_size = 2;
248 else flash_access_size = 1;
249
250 #if (CHIPSET == 12)
251 /*
252 * WARNING - New ARM Memory Interface features are not supported here below (Page Mode, extended WS, Dummy Cycle,...).
253 */
254 flash_wait_state = *((volatile SYS_UWORD16 *) MEM_REG_nCS5);
255 #else
256 flash_wait_state = *((volatile SYS_UWORD16 *) MEM_REG_nCS0);
257 #endif
258 flash_wait_state &= 0x001F;
259
260 //////////////////////////////////////
261 // compute the length of the loop //
262 //////////////////////////////////////
263
264 // Number of flash cycles for the assembler loop
265 nbr = NBR_CYCLES_IN_LOOP;
266
267 // Number of ARM cycles for the assembler loop
268 nbr = nbr * (flash_wait_state + 1) * (flash_access_size);
269
270 // time for the assembler loop (unit nanoseconds: 10E-9)
271 arm_clock = final_ratio * 13; // ARM clock in Mhz
272 ratio_wait_loop = (SYS_UWORD32)((nbr*1000) / arm_clock);
273 }
274
275
276 /*-------------------------------------------------------*/
277 /* wait_ARM_cycles() */
278 /*-------------------------------------------------------*/
279 /* */
280 /* Description: */
281 /* ------------ */
282 /* Called when the HardWare needs time to wait. */
283 /* this function wait x cycles and is used with the */
284 /* convert_nanosec_to_cycles() & initialize_wait_loop() */
285 /* */
286 /* Exemple: wait 10 micro seconds: */
287 /* initialize_wait_loop(); */
288 /* wait_ARM_cycles(convert_nanosec_to_cycles(10000)) */
289 /* */
290 /* minimum time value with cpt_loop = 0 (estimated) */
291 /* and C-SAMPLE / flash 6,5Mhz ~ 1,5 micro seconds */
292 /* */
293 /* */
294 /* Be careful : in order to respect the rule about the */
295 /* conversion "time => number of cylcles in this loop" */
296 /* (Cf the functions: convert_nanosec_to_cycles() and */
297 /* initialize_wait_loop() ) respect the following rules: */
298 /* This function must be placed in Flash Memory and */
299 /* compiled in 16 bits instructions length */
300 /*-------------------------------------------------------*/
301 void wait_ARM_cycles(SYS_UWORD32 cpt_loop)
302 {
303 // C code:
304 // while (cpt_loop -- != 0);
305
306 asm(" CMP A1, #0");
307 asm(" BEQ END_FUNCTION");
308
309 asm("LOOP_LINE: ");
310 asm(" SUB A1, A1, #1");
311 asm(" CMP A1, #0");
312 asm(" BNE LOOP_LINE");
313
314 asm("END_FUNCTION: ");
315 }
316
317