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nuc-fw: beginning to integrate TI's BSP code
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 31 Aug 2013 23:43:23 +0000
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children 91460c8957f0
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92:f459043fae0c 93:45911ad957fd
1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : clkm.h
12
13 Description : Header file for the CLKM module
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.10
20
21 Date and time : 10/23/01 14:34:54
22
23 Previous delta : 10/19/01 15:25:25
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.h
26
27 Sccs Id (SID) : '@(#) clkm.h 1.10 10/23/01 14:34:54 '
28
29
30 *****************************************************************************/
31
32 #include "../include/config.h"
33 #include "../include/sys_types.h"
34
35 #define CLKM_ARM_CLK MEM_CLKM_ADDR /* CLKM ARM CLock Control reg.*/
36 #define CLKM_MCLK_EN 0x0001
37
38
39 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
40 #define MASK_CLKIN 0x0006
41 #endif
42
43 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
44 #define CLKM_CLKIN0 0x0002 // Mask to select between DPLL and VTCXO or CLKIN
45 #else
46 #define CLKM_LOW_FRQ 0x0002 // Mask to select low frequency input CLK_32K
47 #endif
48 #define CLKM_CLKIN_SEL 0x0004 // Mask to select between VTCXO and CLKIN
49
50 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
51 #define CLKM_ARM_MCLK_XP5 0x0008 // Mask to enable the 1.5 or 2.5 division factor
52 #define CLKM_MCLK_DIV 0x0070 // Mask to configure the division factor
53 #else
54 #define MASK_ARM_MCLK_1P5 0x0008 // Mask to enable the 1.5 division factor
55 #define CLKM_MCLK_DIV 0x0030 // Mask to configure the division factor
56 #endif
57
58 #define CLKM_DEEP_PWR 0x0f00 // Mask to configure deep power
59 #define CLKM_DEEP_SLEEP 0x1000 // Mask to configure deep sleep
60
61 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
62 #define CLKM_SEL_DPLL 0x0000 // Selection of DPLL for ARM clock generation
63 #define CLKM_SEL_VTCXO 0x0001 // Selection of VTCXO for ARM clock generation
64 #define CLKM_SEL_CLKIN 0x0003 // Selection of CLKIN for ARM clock generation
65
66 #define CLKM_ENABLE_XP5 0x0001 // Enable 1.5 or 2.5 division factor
67 #define CLKM_DISABLE_XP5 0x0000 // Disable 1.5 or 2.5 division factor
68
69 #define CLKM_ARM_MCLK_DIV_OFFSET 4 // Offset of ARM_MCLK_DIV bits in CNTL_ARM_CLK register
70
71 #define CLKM_ARM_CLK_RESET 0x1081 // Reset value of CNTL_ARM_CLK register
72 #endif
73
74 #define CLKM_CNTL_ARM_CLK (MEM_CLKM_ADDR + 0x00)
75 #define CLKM_CNTL_CLK (MEM_CLKM_ADDR + 2) /* CLKM Clock Control reg. */
76
77 #define CLKM_IRQ_DIS 0x0001 // IRQ clock is disabled and enabled according to the sleep command
78 #define CLKM_BRIDGE_DIS 0x0002 // BRIDGE clock is disabled and enabled according to the sleep command
79 #define CLKM_TIMER_DIS 0x0004 // TIMER clock is disabled and enabled according to the sleep command
80 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
81 #define CLKM_DPLL_DIS 0x0008 // DPLL is set in IDLE when both DSP and ARM are respectively in IDLE3 and sleep mode
82 #else
83 #define CLKM_PLL_SEL 0x0008 // CLKIN input is connected to the PLL
84 #endif
85 #define CLKM_CLKOUT_EN 0x0010 // Enable CLKOUT(2:0) output clocks
86 #if (CHIPSET == 4)
87 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
88 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
89 #elif (CHIPSET == 6)
90 #define CLKM_VTCXO_26 0x0040 // VTCXO is divided by 2
91 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
92 #define CLKM_EN_IDLE3_FLG 0x0020 // DSP idle flag control the API wait state
93 #define CLKM_VCLKOUT_2 0x0040 // VTCXO is divided by 2
94 #define CLKM_VTCXO_2 0x0080 // Input clock to DPLL is divided by 2
95 #endif
96
97 #define CLKM_CNTL_RST (MEM_CLKM_ADDR + 4) /* CLKM Reset Control reg. */
98 #define CLKM_LEAD_RST 0x0002
99 #define CLKM_EXT_RST 0x0004
100
101 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
102 #define DPLL_LOCK 0x0001 // Mask of DPLL lock status
103 #define DPLL_BYPASS_DIV 0x000C // Mask of bypass mode configuration
104 #define DPLL_PLL_ENABLE 0x0010 // Enable DPLL
105 #define DPLL_PLL_DIV 0x0060 // Mask of division factor configuration
106 #define DPLL_PLL_MULT 0x0F80 // Mask of multiply factor configuration
107
108 #define DPLL_BYPASS_DIV_1 0x00 // Configuration of bypass mode divided by 1
109 #define DPLL_BYPASS_DIV_2 0x01 // Configuration of bypass mode divided by 2
110 #define DPLL_BYPASS_DIV_4 0x10 // Configuration of bypass mode divided by 4
111
112 #define DPLL_BYPASS_DIV_OFFSET 2 // Offset of bypass bits configuration
113 #define DPLL_PLL_DIV_OFFSET 5 // Offset of division bits configuration
114 #define DPLL_PLL_MULT_OFFSET 7 // Offset of multiply bits configuration
115
116 #define DPLL_LOCK_DIV_1 0x0000 // Divide by 1 when DPLL is locked
117 #define DPLL_LOCK_DIV_2 0x0001 // Divide by 2 when DPLL is locked
118 #define DPLL_LOCK_DIV_3 0x0002 // Divide by 3 when DPLL is locked
119 #define DPLL_LOCK_DIV_4 0x0003 // Divide by 4 when DPLL is locked
120
121 #else
122 #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6) /* Lead PLL */
123 #define CLKM_PLONOFF 0x0001 // PLL enable signal
124 #define CLKM_PLMUL 0x001e // Mask of multiply factor configuration
125 #define CLKM_PLLNDIV 0x0020 // PLL or divide mode selection
126 #define CLKM_PLDIV 0x0040 // Mask of multiply factor configuration
127 #define CLKM_LEAD_PLL_CNTL_MSK 0x00ef // Mask of PLL control register
128 #endif
129
130 #if (CHIPSET == 12)
131 #define CLKM_CNTL_CLK_DSP (MEM_CLKM_ADDR + 0x8A) /* CLKM CNTL_CLK_REG register */
132
133 #define CLKM_NB_DSP_DIV_VALUE 4
134
135 #define CLKM_DSP_DIV_1 0x00
136 #define CLKM_DSP_DIV_1_5 0x01
137 #define CLKM_DSP_DIV_2 0x02
138 #define CLKM_DSP_DIV_3 0x03
139
140 #define CLKM_DSP_DIV_MASK 0x0003
141
142 extern const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE];
143
144 /*---------------------------------------------------------------/
145 /* CLKM_DSP_DIV_FACTOR() */
146 /*--------------------------------------------------------------*/
147 /* Parameters : none */
148 /* Return : none */
149 /* Functionality : Set the DSP division factor */
150 /*--------------------------------------------------------------*/
151
152 #define CLKM_DSP_DIV_FACTOR(d_dsp_div) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP = d_dsp_div)
153
154
155 /*---------------------------------------------------------------/
156 /* CLKM_READ_DSP_DIV() */
157 /*--------------------------------------------------------------*/
158 /* Parameters : none */
159 /* Return : none */
160 /* Functionality : Read DSP division factor */
161 /*--------------------------------------------------------------*/
162
163 #define CLKM_READ_DSP_DIV ((* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP) & CLKM_DSP_DIV_MASK)
164
165 #define CLKM_GET_DSP_DIV_VALUE dsp_div_value[CLKM_READ_DSP_DIV]
166
167 #endif
168
169
170 /*---------------------------------------------------------------/
171 /* CLKM_SETLEADRESET() */
172 /*--------------------------------------------------------------*/
173 /* Parameters : none */
174 /* Return : none */
175 /* Functionality : Set the LEAD reset signal */
176 /*--------------------------------------------------------------*/
177
178 #define CLKM_SETLEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_LEAD_RST)
179
180 /*---------------------------------------------------------------/
181 /* CLKM_RELEASELEADRESET() */
182 /*--------------------------------------------------------------*/
183 /* Parameters : none */
184 /* Return : none */
185 /* Functionality : Release the LEAD reset signal */
186 /*--------------------------------------------------------------*/
187
188 #define CLKM_RELEASELEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_LEAD_RST)
189
190 /*---------------------------------------------------------------/
191 /* CLKM_SETEXTRESET() */
192 /*--------------------------------------------------------------*/
193 /* Parameters : none */
194 /* Return : none */
195 /* Functionality : Set the external reset signal */
196 /*--------------------------------------------------------------*/
197
198 #define CLKM_SETEXTRESET ( * (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_EXT_RST)
199
200 /*---------------------------------------------------------------/
201 /* CLKM_CLEAREXTRESET() */
202 /*--------------------------------------------------------------*/
203 /* Parameters : none */
204 /* Return : none */
205 /* Functionality : Clear the external reset signal */
206 /*--------------------------------------------------------------*/
207
208 #define CLKM_CLEAREXTRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_EXT_RST)
209
210
211 /*---------------------------------------------------------------/
212 /* CLKM_POWERDOWNARM() */
213 /*--------------------------------------------------------------*/
214 /* Parameters : none */
215 /* Return : none */
216 /* Functionality : Power down the ARM mcu */
217 /*--------------------------------------------------------------*/
218 #define CLKM_POWERDOWNARM (* (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_MCLK_EN)
219
220 /*---------------------------------------------------------------/
221 /* CLKM_SET1P5() */
222 /*--------------------------------------------------------------*/
223 /* Parameters : none */
224 /* Return : none */
225 /* Functionality : Set ARM_MCLK_1P5 bit */
226 /*--------------------------------------------------------------*/
227
228 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
229 #define CLKM_SETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= CLKM_ARM_MCLK_XP5)
230 #else
231 #define CLKM_SET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= 0x0008)
232 #endif
233
234 /*---------------------------------------------------------------/
235 /* CLKM_RESET1P5() */
236 /*--------------------------------------------------------------*/
237 /* Parameters : none */
238 /* Return : none */
239 /* Functionality : Reset ARM_MCLK_1P5 bit */
240 /*--------------------------------------------------------------*/
241
242 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
243 #define CLKM_RESETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_ARM_MCLK_XP5)
244 #else
245 #define CLKM_RESET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= 0xfff7)
246 #endif
247
248 /*---------------------------------------------------------------/
249 /* CLKM_INITCNTL() */
250 /*--------------------------------------------------------------*/
251 /* Parameters : value to write in the CNTL register */
252 /* Return : none */
253 /* Functionality :Initialize the CLKM Control Clock register */
254 /*--------------------------------------------------------------*/
255
256 #define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK = value)
257
258
259 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
260 /*---------------------------------------------------------------/
261 /* CLKM_INITLEADPLL() */
262 /*--------------------------------------------------------------*/
263 /* Parameters : value to write in the CNTL_PLL LEAD register */
264 /* Return : none */
265 /* Functionality :Initialize LEAD PLL control register */
266 /*--------------------------------------------------------------*/
267
268 #define CLKM_INITLEADPLL(value) (* (volatile SYS_UWORD16 *) CLKM_LEAD_PLL_CNTL = value)
269 #endif
270
271 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
272 /*---------------------------------------------------------------/
273 /* CLKM_DPLL_SWITH_OFF_MODE_CONFIG() */
274 /*--------------------------------------------------------------*/
275 /* Parameters : None */
276 /* Return : none */
277 /* Functionality : Configure DPLL switch off mode */
278 /*--------------------------------------------------------------*/
279
280 #define CLKM_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= \
281 (CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
282
283 /*---------------------------------------------------------------/
284 /* CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG() */
285 /*--------------------------------------------------------------*/
286 /* Parameters : None */
287 /* Return : none */
288 /* Functionality : Reset configuration of DPLL switch off mode */
289 /*--------------------------------------------------------------*/
290
291 #define CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &=\
292 ~(CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
293
294 /*---------------------------------------------------------------/
295 /* CLKM_FORCE_API_HOM_IN_IDLE3() */
296 /*--------------------------------------------------------------*/
297 /* Parameters : None */
298 /* Return : none */
299 /* Functionality : SAM/HOM wait-state register force to HOM when*/
300 /* DSP is in IDLE3 mode */
301 /*--------------------------------------------------------------*/
302
303 #define CLKM_FORCE_API_HOM_IN_IDLE3 (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_EN_IDLE3_FLG))
304
305 #if (CHIPSET == 4)
306 /*---------------------------------------------------------------/
307 /* CLKM_USE_VTCXO_26MHZ() */
308 /*--------------------------------------------------------------*/
309 /* Parameters : None */
310 /* Return : none */
311 /* Functionality : Divide by 2 the clock used by the peripheral */
312 /* when using external VTCXO at 26 MHz instead */
313 /* of 13MHz */
314 /*--------------------------------------------------------------*/
315
316 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_26))
317
318 /*---------------------------------------------------------------/
319 /* CLKM_UNUSED_VTCXO_26MHZ() */
320 /*--------------------------------------------------------------*/
321 /* Parameters : None */
322 /* Return : none */
323 /* Functionality : Use VTCXO=13MHz */
324 /*--------------------------------------------------------------*/
325
326 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VTCXO_26))
327 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
328 /*---------------------------------------------------------------/
329 /* CLKM_UNUSED_VTCXO_26MHZ() */
330 /*--------------------------------------------------------------*/
331 /* Parameters : None */
332 /* Return : none */
333 /* Functionality : Use VTCXO=13MHz */
334 /*--------------------------------------------------------------*/
335
336 #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_2))
337
338 #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VCLKOUT_2 | CLKM_VTCXO_2))
339 #endif
340
341
342 #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR |= DPLL_PLL_ENABLE)
343 #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR &= ~DPLL_PLL_ENABLE)
344
345 #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
346 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~DPLL_BYPASS_DIV; \
347 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
348 }
349
350 #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
351 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
352 *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
353 (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
354 }
355
356 #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
357 #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
358 #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK)
359
360
361 #endif
362
363 /* ----- Prototypes ----- */
364
365 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
366 inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5);
367 #else
368 inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div);
369 #endif
370
371 void wait_ARM_cycles(SYS_UWORD32 cpt_loop);
372 void initialize_wait_loop(void);
373 inline SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time);