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comparison nuc-fw/bsp/dma.h @ 93:45911ad957fd

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nuc-fw: beginning to integrate TI's BSP code
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 31 Aug 2013 23:43:23 +0000
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92:f459043fae0c 93:45911ad957fd
1 /******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : dma.h
12
13 Description : DMA
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.6
20
21 Date and time : 01/30/01 10:22:23
22
23 Previous delta : 12/08/00 11:22:15
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.dma.h
26
27 Sccs Id (SID) : '@(#) dma.h 1.6 01/30/01 10:22:23 '
28
29
30 *****************************************************************************/
31
32 #include "../include/config.h"
33
34 /**** DMA configuration register ****/
35
36 #if (CHIPSET == 12)
37
38 #define DMA_GCR (MEM_DMA_ADDR + 0x0400)
39 #define DMA_CAR (MEM_DMA_ADDR + 0x0404)
40 #define DMA_SCR (MEM_DMA_ADDR + 0x0406)
41 #define DMA_AR (MEM_DMA_ADDR + 0x040A)
42
43 #define DMA_CONFIG { \
44 * (volatile unsigned short *) DMA_GCR = 0x0000; /* Force Autogating off */ \
45 * (volatile unsigned short *) DMA_CAR |= 0x0001; /* Channel 0 allocated to DSP */ \
46 * (volatile unsigned short *) DMA_SCR &= ~0x0001; /* Channel 0 is not secure */ \
47 * (volatile unsigned short *) DMA_AR = 0x001C; /* Reset value */ \
48 }
49
50 #else
51
52 // CONTROLLER_CONFIG register
53 //---------------------------
54 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
55 #define DMA_CONFIG_ADDR MEM_DMA_ADDR
56 #else
57 #define DMA_CONFIG_ADDR (MEM_DMA_ADDR + 0x20)
58 #endif
59 #define DMA_CONFIG_BURST 0x1c /* length of burst */
60
61 // ALLOC_CONFIG register
62 //---------------------------
63 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
64 #define DMA_ALLOC_CONFIG_ADDR (MEM_DMA_ADDR + 0x02)
65 #endif
66 #define DMA_CONFIG_ALLOC1 0x01 /* allocation for channel 1 */
67 #define DMA_CONFIG_ALLOC2 0x02 /* allocation for channel 2 */
68
69 // DMA Channel 1 configuration
70 //---------------------------
71
72 // DMA1_RAD register
73 //---------------------------
74 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
75 #define DMA1_RAD_ADDR (MEM_DMA_ADDR + 0x10)
76 #else
77 #define DMA1_RAD_ADDR MEM_DMA_ADDR
78 #endif
79 #define DMA_RHEA_ADDR 0x07ff /* rhea start address */
80 #define DMA_RHEA_CS 0xf800 /* rhea chip select */
81
82 // DMA1_RDPTH register
83 //---------------------------
84 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
85 #define DMA1_RDPTH_ADDR (MEM_DMA_ADDR + 0x12)
86 #else
87 #define DMA1_RDPTH_ADDR (MEM_DMA_ADDR + 0x02)
88 #endif
89 #define DMA_RHEA_LENGTH 0x07ff /* rhea buffer length */
90
91 // DMA1_AAD register
92 //---------------------------
93 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
94 #define DMA1_AAD_ADDR (MEM_DMA_ADDR + 0x14)
95 #else
96 #define DMA1_AAD_ADDR (MEM_DMA_ADDR + 0x04)
97 #endif
98 #define DMA_API_ADDR 0x0fff /* API start address */
99
100 // DMA1_ALGTH register
101 //---------------------------
102 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
103 #define DMA1_ALGTH_ADDR (MEM_DMA_ADDR + 0x16)
104 #else
105 #define DMA1_ALGTH_ADDR (MEM_DMA_ADDR + 0x06)
106 #endif
107 #define DMA_API_LENGTH 0x0fff /* API page length */
108
109 // DMA1_CTRL register
110 //---------------------------
111 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
112 #define DMA1_CTRL_ADDR (MEM_DMA_ADDR + 0x18)
113 #else
114 #define DMA1_CTRL_ADDR (MEM_DMA_ADDR + 0x08)
115 #endif
116 #define DMA_CTRL_ENABLE 0x0001 /* DMA enable */
117 #define DMA_CTRL_IDLE 0x0002 /* idle */
118 #define DMA_CTRL_ONE_SHOT 0x0004
119 #define DMA_CTRL_FIFO_MODE 0x0008
120 #define DMA_CTRL_CUR_PAGE 0x0010 /* current page # */
121 #define DMA_CTRL_MAS 0x0020
122 #define DMA_CTRL_START 0x0040 /* DMA start */
123 #define DMA_CTRL_IRQ_MODE 0x0080
124 #define DMA_CTRL_IRQ_STATE 0x0100
125 #define DMA_CTRL_RHEA_ABORT 0x0200
126 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
127 #define DMA_CTRL_PRIORITY 0x1800 /* Number of additional reading on the bus */
128 #endif
129
130 // DMA1_CUR_OFFSET_API register
131 //---------------------------
132 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
133 #define DMA1_OFFSET_ADDR (MEM_DMA_ADDR + 0x1A)
134 #else
135 #define DMA1_OFFSET_ADDR (MEM_DMA_ADDR + 0x0A)
136 #endif
137
138
139 // DMA Channel 2 configuration
140 //---------------------------
141
142 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
143 #define DMA2_RAD_ADDR (MEM_DMA_ADDR + 0x20)
144 #define DMA2_RDPTH_ADDR (MEM_DMA_ADDR + 0x22)
145 #define DMA2_AAD_ADDR (MEM_DMA_ADDR + 0x24)
146 #define DMA2_ALGTH_ADDR (MEM_DMA_ADDR + 0x26)
147 #define DMA2_CTRL_ADDR (MEM_DMA_ADDR + 0x28)
148 #define DMA2_OFFSET_ADDR (MEM_DMA_ADDR + 0x2A)
149 #else
150 #define DMA2_RAD_ADDR (MEM_DMA_ADDR + 0x10)
151 #define DMA2_RDPTH_ADDR (MEM_DMA_ADDR + 0x12)
152 #define DMA2_AAD_ADDR (MEM_DMA_ADDR + 0x14)
153 #define DMA2_ALGTH_ADDR (MEM_DMA_ADDR + 0x16)
154 #define DMA2_CTRL_ADDR (MEM_DMA_ADDR + 0x18)
155 #define DMA2_OFFSET_ADDR (MEM_DMA_ADDR + 0x1A)
156 #endif
157
158 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
159 // DMA Channel 3 configuration
160 //---------------------------
161
162 #define DMA3_RAD_ADDR (MEM_DMA_ADDR + 0x30)
163 #define DMA3_RDPTH_ADDR (MEM_DMA_ADDR + 0x32)
164 #define DMA3_AAD_ADDR (MEM_DMA_ADDR + 0x34)
165 #define DMA3_ALGTH_ADDR (MEM_DMA_ADDR + 0x36)
166 #define DMA3_CTRL_ADDR (MEM_DMA_ADDR + 0x38)
167 #define DMA3_OFFSET_ADDR (MEM_DMA_ADDR + 0x3A)
168
169 // DMA Channel 4 configuration
170 //---------------------------
171
172 #define DMA4_RAD_ADDR (MEM_DMA_ADDR + 0x40)
173 #define DMA4_RDPTH_ADDR (MEM_DMA_ADDR + 0x42)
174 #define DMA4_AAD_ADDR (MEM_DMA_ADDR + 0x44)
175 #define DMA4_ALGTH_ADDR (MEM_DMA_ADDR + 0x46)
176 #define DMA4_CTRL_ADDR (MEM_DMA_ADDR + 0x48)
177 #define DMA4_OFFSET_ADDR (MEM_DMA_ADDR + 0x4A)
178 #endif
179
180 /*---------------------------------------------------------------/
181 /* DMA_ALLOCDMA() */
182 /*--------------------------------------------------------------*/
183 /* Parameters : none */
184 /* Return : none */
185 /* Functionality : alloc DMA channel */
186 /*--------------------------------------------------------------*/
187
188 #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
189 // WARNING :
190 // Only the first two channels can be configured and the last two channels are forced to be controlled by the ARM
191 #define DMA_ALLOCDMA(channel0, channel1, dma_burst,priority) { \
192 * (volatile unsigned short *) DMA_CONFIG_ADDR = (dma_burst << 2) | (priority << 5); \
193 * (volatile unsigned short *) DMA_ALLOC_CONFIG_ADDR = channel0 | (channel1 << 1) | 0x000C; \
194 }
195 #else
196 #define DMA_ALLOCDMA(channel0, channel1,dma_burst,priority) (* (volatile unsigned short *) DMA_CONFIG_ADDR = channel0 | channel1 << 1 | dma_burst << 2 | priority << 5)
197 #endif
198
199 #endif /* CHIPSET != 12 */
200