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nuc-fw: beginning to integrate TI's BSP code
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 31 Aug 2013 23:43:23 +0000
parents
children 91460c8957f0
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92:f459043fae0c 93:45911ad957fd
1 /*******************************************************************************
2 TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION
3
4 Property of Texas Instruments -- For Unrestricted Internal Use Only
5 Unauthorized reproduction and/or distribution is strictly prohibited. This
6 product is protected under copyright law and trade secret law as an
7 unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All
8 rights reserved.
9
10
11 Filename : inth.h
12
13 Description : Header file for the INTH module
14
15 Project : drivers
16
17 Author : pmonteil@tif.ti.com Patrice Monteil.
18
19 Version number : 1.10
20
21 Date and time : 01/30/01 10:22:23
22
23 Previous delta : 01/22/01 10:32:33
24
25 SCCS file : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.inth.h
26
27 Sccs Id (SID) : '@(#) inth.h 1.10 01/30/01 10:22:23 '
28
29
30 *****************************************************************************/
31
32 #include "../include/config.h"
33 #include "../include/sys_types.h"
34
35 /* Adress of the registers */
36
37 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9)|| (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
38 #define INTH_IT_REG1 MEM_INTH_ADDR /* INTH IT register 1 */
39 #define INTH_IT_REG2 (MEM_INTH_ADDR + 0x02) /* INTH IT register 2 */
40 #define INTH_MASK_REG1 (MEM_INTH_ADDR + 0x08) /* INTH mask register 1 */
41 #define INTH_MASK_REG2 (MEM_INTH_ADDR + 0x0a) /* INTH mask register 2 */
42 #define INTH_B_IRQ_REG (MEM_INTH_ADDR + 0x10) /* INTH source binary IRQ reg. */
43 #define INTH_B_FIQ_REG (MEM_INTH_ADDR + 0x12) /* INTH source binary FIQ reg. */
44 #define INTH_CTRL_REG (MEM_INTH_ADDR + 0x14) /* INTH control register */
45 #define INTH_EXT_REG (MEM_INTH_ADDR + 0x20) /* INTH 1st external int. reg. */
46 #else
47 #define INTH_IT_REG MEM_INTH_ADDR /* INTH IT register */
48 #define INTH_MASK_REG (MEM_INTH_ADDR + 0x02) /* INTH mask register */
49 #define INTH_S_IRQ_REG (MEM_INTH_ADDR + 0x04) /* INTH source IRQ register */
50 #define INTH_S_FIQ_REG (MEM_INTH_ADDR + 0x06) /* INTH source FIQ register */
51 #define INTH_B_IRQ_REG (MEM_INTH_ADDR + 0x08) /* INTH source binary IRQ reg. */
52 #define INTH_B_FIQ_REG (MEM_INTH_ADDR + 0x0a) /* INTH source binary FIQ reg. */
53 #define INTH_CTRL_REG (MEM_INTH_ADDR + 0x0c) /* INTH control register */
54 #define INTH_EXT_REG (MEM_INTH_ADDR + 0x0e) /* INTH 1st external int. reg. */
55 #endif
56
57 /* Interrupts number */
58
59 #define INTH_TIMER 0 /* number of the TIMER int. */
60 #define INTH_AIRQ_FIRST 1 /* first external int. number */
61 #define INTH_AIRQ_LAST 13 /* last external int. number */
62 #define INTH_DMA 14 /* number of the DMA int. */
63 #define INTH_LEAD 15 /* number of the LEAD int. */
64
65 /* Bit definition of INTH interrupt level registers */
66
67 #define INTH_FIQ_NIRQ 0x0001
68 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
69 #define INTH_PRIORITY 0x007c
70 #define INTH_EDGE_NLVL 0x0002
71 #else
72 #define INTH_PRIORITY 0x001e
73 #define INTH_EDGE_NLVL 0x0020
74 #endif
75
76
77 /* Bit definition of INTH source binary registers */
78
79 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
80 #define INTH_SRC_NUM 0x001f
81 #else
82 #define INTH_SRC_NUM 0x000f
83 #endif
84
85
86 /* Bit definition of INTH Control Register */
87
88 #define INTH_NEW_IRQ_AGR 0x0001
89 #define INTH_NEW_FIQ_AGR 0x0002
90
91 /* Other useful constants */
92
93 #define INTH_IRQ 0
94 #define INTH_FIQ 1
95 #define INTH_LEVEL 0
96 #define INTH_EDGE 1
97
98 /*
99 * Macros
100 */
101
102 #define INT_MASK(interrupt) (1 << (interrupt - 1))
103 #define PENDING_INT(pendingITs, interrupt) (pendingITs & INT_MASK(interrupt))
104
105 /*--------------------------------------------------------------*/
106 /* INTH_ENABLEONEIT() */
107 /*--------------------------------------------------------------*/
108 /* Parameters : num of the IT to enable */
109 /* Return : none */
110 /* Functionality : Unmask one it */
111 /*--------------------------------------------------------------*/
112 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
113 #define INTH_ENABLEONEIT(it)( \
114 (it < 16) ? (* (volatile unsigned short *) INTH_MASK_REG1 &= ~(1 << it)) : \
115 (* (volatile unsigned short *) INTH_MASK_REG2 &= ~(1 << (it-16))) \
116 )
117 #else
118 #define INTH_ENABLEONEIT(it)(* (volatile unsigned short *) INTH_MASK_REG &= ~(1 << it))
119 #endif
120
121 /*--------------------------------------------------------------*/
122 /* INTH_DISABLEONEIT() */
123 /*--------------------------------------------------------------*/
124 /* Parameters : num of the IT to disable */
125 /* Return : none */
126 /* Functionality : mask one it */
127 /*--------------------------------------------------------------*/
128 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
129 #define INTH_DISABLEONEIT(it)( \
130 (it < 16) ? (* (volatile unsigned short *) INTH_MASK_REG1 |= (1 << it)) : \
131 (* (volatile unsigned short *) INTH_MASK_REG2 |= (1 << (it-16))) \
132 )
133 #else
134 #define INTH_DISABLEONEIT(it)(* (volatile unsigned short *) INTH_MASK_REG |= (1 << it))
135 #endif
136
137 /*--------------------------------------------------------------*/
138 /* INTH_ENABLEALLIT() */
139 /*--------------------------------------------------------------*/
140 /* Parameters : none */
141 /* Return : none */
142 /* Functionality : Enable all it */
143 /*--------------------------------------------------------------*/
144
145 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
146 #define INTH_ENABLEALLIT { \
147 * (volatile unsigned short *) INTH_MASK_REG1 = 0x0000; \
148 * (volatile unsigned short *) INTH_MASK_REG2 = 0x0000; \
149 }
150 #else
151 #define INTH_ENABLEALLIT ( * (volatile unsigned short *) INTH_MASK_REG = 0x0000)
152 #endif
153
154 /*--------------------------------------------------------------*/
155 /* INTH_DISABLEALLIT() */
156 /*--------------------------------------------------------------*/
157 /* Parameters : none */
158 /* Return : none */
159 /* Functionality :mask all it */
160 /*--------------------------------------------------------------*/
161
162 #if (CHIPSET == 4)
163 #define INTH_DISABLEALLIT { \
164 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
165 * (volatile unsigned short *) INTH_MASK_REG2 = 0x000f; \
166 }
167 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
168 #define INTH_DISABLEALLIT { \
169 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
170 * (volatile unsigned short *) INTH_MASK_REG2 = 0x01ff; \
171 }
172 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
173 #define INTH_DISABLEALLIT { \
174 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
175 * (volatile unsigned short *) INTH_MASK_REG2 = 0xffff; \
176 }
177 #elif (CHIPSET == 12)
178 #define INTH_DISABLEALLIT { \
179 * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
180 * (volatile unsigned short *) INTH_MASK_REG2 = 0xffff; \
181 }
182 #else
183 #define INTH_DISABLEALLIT (* (volatile unsigned short *) INTH_MASK_REG = 0xffff)
184 #endif
185
186 /*--------------------------------------------------------------*/
187 /* INTH_CLEAR() */
188 /*--------------------------------------------------------------*/
189 /* Parameters : value to write */
190 /* Return : none */
191 /* Functionality :valid next it */
192 /*--------------------------------------------------------------*/
193
194 #define INTH_CLEAR (* (volatile SYS_UWORD16 *) INTH_CTRL_REG = 0x0003)
195
196
197 /*--------------------------------------------------------------*/
198 /* INTH_VALIDNEXT() */
199 /*--------------------------------------------------------------*/
200 /* Parameters : num of the processed it */
201 /* Return : none */
202 /* Functionality :valid next it */
203 /*--------------------------------------------------------------*/
204
205 #define INTH_VALIDNEXT (intARM)( * (volatile SYS_UWORD16 *) INTH_CTRL_REG |= (1 << intARM))
206
207 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
208 /*--------------------------------------------------------------*/
209 /* INTH_RESETALLIT() */
210 /*--------------------------------------------------------------*/
211 /* Parameters : None */
212 /* Return : none */
213 /* Functionality :Reset the inth it register */
214 /*--------------------------------------------------------------*/
215
216 #define INTH_RESETALLIT { \
217 * (volatile unsigned short *) INTH_IT_REG1 &= 0x0000; \
218 * (volatile unsigned short *) INTH_IT_REG2 &= 0x0000; \
219 }
220 #endif
221
222 /* Prototypes */
223
224 #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
225 unsigned long INTH_GetPending (void);
226 unsigned long INTH_ResetIT (void);
227 #else
228 unsigned short INTH_GetPending (void);
229 unsigned short INTH_ResetIT (void);
230 #endif
231
232 unsigned short INTH_Ack (int);
233 void INTH_InitLevel (int, int, int, int);