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comparison gsm-fw/bsp/abb+spi/abb.c @ 154:47754cdb6248

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abb.c compiles!
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 17 Nov 2013 05:53:10 +0000
parents 26472940e5b0
children 99e44a92274c
comparison
equal deleted inserted replaced
153:65efffcb28dc 154:47754cdb6248
32 32
33 #include "abb.h" 33 #include "abb.h"
34 #include "../clkm.h" // for wait_ARM_cycles function 34 #include "../clkm.h" // for wait_ARM_cycles function
35 #include "abb_inline.h" 35 #include "abb_inline.h"
36 #include "../ulpd.h" // for FRAME_STOP definition 36 #include "../ulpd.h" // for FRAME_STOP definition
37
38 #include "../../include/sys_types.h"
39 #include "../../riviera/rv/general.h"
37 #include "../../nucleus/nucleus.h" // for NUCLEUS functions and types 40 #include "../../nucleus/nucleus.h" // for NUCLEUS functions and types
38 #include "../../L1/include/l1_types.h" 41 #include "../../L1/include/l1_types.h"
39 42
40 #include "../../include/sys_types.h" 43 #if 0 // FreeCalypso
41 #include "../../riviera/rv/general.h"
42 #if 0
43 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function 44 #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function
44 #endif 45 #endif
45 46
46 #if (VCXO_ALGO == 1) 47 #if (VCXO_ALGO == 1)
47 #include "../../L1/include/l1_ctl.h" 48 #include "../../L1/include/l1_ctl.h"
50 #if (RF_FAM == 35) 51 #if (RF_FAM == 35)
51 #include "../../L1/cust0/l1_rf35.h" 52 #include "../../L1/cust0/l1_rf35.h"
52 #endif 53 #endif
53 54
54 #if (RF_FAM == 12) 55 #if (RF_FAM == 12)
55 #include "tpudrv12.h" 56 #include "../../L1/tpudrv/tpudrv12.h"
56 #include "../../L1/cust0/l1_rf12.h" 57 #include "../../L1/cust0/l1_rf12.h"
57 #endif 58 #endif
58 59
59 #if (RF_FAM == 10) 60 #if (RF_FAM == 10)
60 #include "../../L1/cust0/l1_rf10.h" 61 #include "../../L1/cust0/l1_rf10.h"
94 /* This function waits for the first IBIC access. */ 95 /* This function waits for the first IBIC access. */
95 /* */ 96 /* */
96 /*-----------------------------------------------------------------------*/ 97 /*-----------------------------------------------------------------------*/
97 void ABB_Wait_IBIC_Access(void) 98 void ABB_Wait_IBIC_Access(void)
98 { 99 {
99 #if (ANLG_FAM ==1) 100 #if (ANALOG ==1)
100 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access 101 // Wait 6 OSCAS cycles (100 KHz) for first IBIC access
101 // (i.e wait 60us + 10% security marge = 66us) 102 // (i.e wait 60us + 10% security marge = 66us)
102 wait_ARM_cycles(convert_nanosec_to_cycles(66000)); 103 wait_ARM_cycles(convert_nanosec_to_cycles(66000));
103 #elif ((ANLG_FAM ==2) || (ANLG_FAM == 3)) 104 #elif ((ANALOG ==2) || (ANALOG == 3))
104 // Wait 6 x 32 KHz clock cycles for first IBIC access 105 // Wait 6 x 32 KHz clock cycles for first IBIC access
105 // (i.e wait 187us + 10% security marge = 210us) 106 // (i.e wait 187us + 10% security marge = 210us)
106 wait_ARM_cycles(convert_nanosec_to_cycles(210000)); 107 wait_ARM_cycles(convert_nanosec_to_cycles(210000));
107 #endif 108 #endif
108 } 109 }
308 } 309 }
309 #endif // ABB_SEMAPHORE_PROTECTION 310 #endif // ABB_SEMAPHORE_PROTECTION
310 311
311 ABB_SetPage(PAGE0); 312 ABB_SetPage(PAGE0);
312 313
313 #if (ANLG_FAM == 1) || (ANLG_FAM == 2) 314 #if (ANALOG == 1) || (ANALOG == 2)
314 ABB_SetPage(PAGE0); 315 ABB_SetPage(PAGE0);
315 reg_val = ABB_ReadRegister(VRPCSTS); 316 reg_val = ABB_ReadRegister(VRPCSTS);
316 #elif (ANLG_FAM == 3) 317 #elif (ANALOG == 3)
317 ABB_SetPage(PAGE1); 318 ABB_SetPage(PAGE1);
318 reg_val = ABB_ReadRegister(VRPCCFG); 319 reg_val = ABB_ReadRegister(VRPCCFG);
319 #endif 320 #endif
320 321
321 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) 322 #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3))
341 /* */ 342 /* */
342 /*------------------------------------------------------------------------*/ 343 /*------------------------------------------------------------------------*/
343 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag) 344 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag)
344 { 345 {
345 volatile SYS_UWORD16 status; 346 volatile SYS_UWORD16 status;
346 #if ((ANLG_FAM ==2) || (ANLG_FAM == 3)) 347 #if ((ANALOG ==2) || (ANALOG == 3))
347 SYS_UWORD32 reg; 348 SYS_UWORD32 reg;
348 #endif 349 #endif
349 350
350 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13 351 // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13
351 if (bRecoveryFlag) 352 if (bRecoveryFlag)
377 ABB_SetPage(PAGE0); 378 ABB_SetPage(PAGE0);
378 379
379 // This transmission disables MADC,AFC,VDL,VUL modules. 380 // This transmission disables MADC,AFC,VDL,VUL modules.
380 ABB_WriteRegister(TOGBR1, 0x0155); 381 ABB_WriteRegister(TOGBR1, 0x0155);
381 382
382 #if (ANLG_FAM == 1) 383 #if (ANALOG == 1)
383 // This transmission disables Band gap fast mode Enable BB charge. 384 // This transmission disables Band gap fast mode Enable BB charge.
384 ABB_WriteRegister(VRPCCTL2, 0x1fc); 385 ABB_WriteRegister(VRPCCTL2, 0x1fc);
385 386
386 /* *********** DC/DC enabling selection ************************************************************** */ 387 /* *********** DC/DC enabling selection ************************************************************** */
387 // This transmission changes the register page in OMEGA for usp to pg1. 388 // This transmission changes the register page in OMEGA for usp to pg1.
407 } 408 }
408 409
409 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */ 410 /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */
410 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */ 411 /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */
411 /* ***************************************************************************************************/ 412 /* ***************************************************************************************************/
412 #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica) 413 #if (BOARD==6)&& (ANALOG==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica)
413 // This transmission enables Omega test register. 414 // This transmission enables Omega test register.
414 ABB_WriteRegister(TAPCTRL, 0x01); 415 ABB_WriteRegister(TAPCTRL, 0x01);
415 416
416 // This transmission select Omega test instruction. 417 // This transmission select Omega test instruction.
417 ABB_WriteRegister(TAPREG, TSPTEST1); 418 ABB_WriteRegister(TAPREG, TSPTEST1);
435 if(modules & MADC) // check if the ADC is enabled 436 if(modules & MADC) // check if the ADC is enabled
436 { 437 {
437 // This transmission connects the resistive divider to MB and BB. 438 // This transmission connects the resistive divider to MB and BB.
438 ABB_WriteRegister(BCICTL1, 0x0005); 439 ABB_WriteRegister(BCICTL1, 0x0005);
439 } 440 }
440 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) 441 #elif ((ANALOG == 2) || (ANALOG == 3))
441 // Restore the ABB checks and debouncing if start on TESTRESETZ 442 // Restore the ABB checks and debouncing if start on TESTRESETZ
442 443
443 // This transmission changes the register page in the ABB for usp to pg1. 444 // This transmission changes the register page in the ABB for usp to pg1.
444 ABB_SetPage(PAGE1); 445 ABB_SetPage(PAGE1);
445 446
453 ABB_WriteRegister(TAPREG, 0x01b); 454 ABB_WriteRegister(TAPREG, 0x01b);
454 455
455 // This transmission changes the register page in the ABB for usp to pg2. 456 // This transmission changes the register page in the ABB for usp to pg2.
456 ABB_SetPage(PAGE2); 457 ABB_SetPage(PAGE2);
457 458
458 #if (ANLG_FAM == 2) 459 #if (ANALOG == 2)
459 // Restore push button environment 460 // Restore push button environment
460 ABB_WriteRegister(0x3C, 0x07); 461 ABB_WriteRegister(0x3C, 0x07);
461 462
462 #elif (ANLG_FAM == 3) 463 #elif (ANALOG == 3)
463 464
464 // Restore push button environment 465 // Restore push button environment
465 ABB_WriteRegister(0x3C, 0xBF); 466 ABB_WriteRegister(0x3C, 0xBF);
466 467
467 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/ 468 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/
501 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows 502 // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows
502 // This transmission enables BB charge and BB bridge connection for BB measurements. 503 // This transmission enables BB charge and BB bridge connection for BB measurements.
503 ABB_WriteRegister(BCICONF, 0x060); 504 ABB_WriteRegister(BCICONF, 0x060);
504 505
505 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/ 506 /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/
506 #if (ANLG_FAM == 3) 507 #if (ANALOG == 3)
507 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO 508 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO
508 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register 509 ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register
509 #endif 510 #endif
510 #endif 511 #endif
511 512
532 ABB_WriteRegister(BCICTL1, 0x0001); 533 ABB_WriteRegister(BCICTL1, 0x0001);
533 } 534 }
534 535
535 /********* Sleep definition part ******************/ 536 /********* Sleep definition part ******************/
536 // This transmission changes the register page in the ABB for usp to pg1. 537 // This transmission changes the register page in the ABB for usp to pg1.
537 #if (ANLG_FAM == 2) 538 #if (ANALOG == 2)
538 ABB_SetPage(PAGE1); 539 ABB_SetPage(PAGE1);
539 540
540 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. 541 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
541 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0; 542 reg = ABB_ReadRegister(VRPCCFG) & 0x1e0;
542 543
543 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg)); 544 ABB_WriteRegister(VRPCCFG, (SLPDLY | reg));
544 545
545 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value. 546 // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value.
546 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0; 547 reg = ABB_ReadRegister(VRPCMSK) & 0x1e0;
547 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg)); 548 ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg));
548 #elif (ANLG_FAM == 3) 549 #elif (ANALOG == 3)
549 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY); 550 Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY);
550 #endif 551 #endif
551 // This transmission changes the register page in the ABB for usp to pg0. 552 // This transmission changes the register page in the ABB for usp to pg0.
552 ABB_SetPage(PAGE0); 553 ABB_SetPage(PAGE0);
553 #endif 554 #endif
620 *Buff++ = ABB_ReadRegister(VBKPREG); 621 *Buff++ = ABB_ReadRegister(VBKPREG);
621 *Buff++ = ABB_ReadRegister(ADIN1REG); 622 *Buff++ = ABB_ReadRegister(ADIN1REG);
622 *Buff++ = ABB_ReadRegister(ADIN2REG); 623 *Buff++ = ABB_ReadRegister(ADIN2REG);
623 *Buff++ = ABB_ReadRegister(ADIN3REG); 624 *Buff++ = ABB_ReadRegister(ADIN3REG);
624 625
625 #if (ANLG_FAM ==1) 626 #if (ANALOG ==1)
626 *Buff++ = ABB_ReadRegister(ADIN4XREG); 627 *Buff++ = ABB_ReadRegister(ADIN4XREG);
627 *Buff++ = ABB_ReadRegister(ADIN5YREG); 628 *Buff++ = ABB_ReadRegister(ADIN5YREG);
628 #elif (ANLG_FAM ==2) 629 #elif (ANALOG ==2)
629 *Buff++ = ABB_ReadRegister(ADIN4REG); 630 *Buff++ = ABB_ReadRegister(ADIN4REG);
630 #elif (ANLG_FAM == 3) 631 #elif (ANALOG == 3)
631 *Buff++ = ABB_ReadRegister(ADIN4REG); 632 *Buff++ = ABB_ReadRegister(ADIN4REG);
632 *Buff++ = ABB_ReadRegister(ADIN5REG); 633 *Buff++ = ABB_ReadRegister(ADIN5REG);
633 #endif // ANLG_FAM 634 #endif // ANALOG
634 635
635 #if (ABB_SEMAPHORE_PROTECTION == 3) 636 #if (ABB_SEMAPHORE_PROTECTION == 3)
636 // release the semaphore only if it has correctly been created. 637 // release the semaphore only if it has correctly been created.
637 if(&abb_sem != 0) 638 if(&abb_sem != 0)
638 { 639 {
678 679
679 // This transmission changes the register page in the ABB for usp to pg0. 680 // This transmission changes the register page in the ABB for usp to pg0.
680 ABB_SetPage(PAGE0); 681 ABB_SetPage(PAGE0);
681 682
682 /* select ADC channels to be converted */ 683 /* select ADC channels to be converted */
683 #if (ANLG_FAM == 1) 684 #if (ANALOG == 1)
684 ABB_WriteRegister(MADCCTRL1, Channels); 685 ABB_WriteRegister(MADCCTRL1, Channels);
685 #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) 686 #elif ((ANALOG == 2) || (ANALOG == 3))
686 ABB_WriteRegister(MADCCTRL, Channels); 687 ABB_WriteRegister(MADCCTRL, Channels);
687 #endif 688 #endif
688 689
689 reg_val = ABB_ReadRegister(ITMASK); 690 reg_val = ABB_ReadRegister(ITMASK);
690 691
730 volatile SYS_UWORD16 nb_it; 731 volatile SYS_UWORD16 nb_it;
731 SYS_UWORD16 reg_val; 732 SYS_UWORD16 reg_val;
732 733
733 // table for AFC allowed values during Sleep mode. First 5th elements 734 // table for AFC allowed values during Sleep mode. First 5th elements
734 // are related to positive AFC values, last 5th to negative ones. 735 // are related to positive AFC values, last 5th to negative ones.
735 SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f}; 736 static const SYS_UWORD32 Afcout_T[10] =
737 {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f};
736 738
737 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. 739 // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags.
738 SPI_Ready_for_RDWR 740 SPI_Ready_for_RDWR
739 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; 741 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
740 742
745 else 747 else
746 afcout_index = (afc + 512)>>10; 748 afcout_index = (afc + 512)>>10;
747 749
748 if (sleep_performed == FRAME_STOP) // Big sleep 750 if (sleep_performed == FRAME_STOP) // Big sleep
749 { 751 {
750 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) 752 #if ((ANALOG == 2) || (ANALOG == 3))
751 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP //////////////////////////// 753 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP ////////////////////////////
752 #endif 754 #endif
753 755
754 } 756 }
755 else // Deep sleep 757 else // Deep sleep
756 { 758 {
757 #if(ANLG_FAM == 1) 759 #if(ANALOG == 1)
758 // SELECTION OF AFC TEST MODE FOR OMEGA 760 // SELECTION OF AFC TEST MODE FOR OMEGA
759 //--------------------------------------------------- 761 //---------------------------------------------------
760 // This test configuration allows access on the AFCOUT register 762 // This test configuration allows access on the AFCOUT register
761 ABB_SetPage(PAGE1); 763 ABB_SetPage(PAGE1);
762 764
769 // Set AFCOUT to 0. 771 // Set AFCOUT to 0.
770 ABB_WriteRegister(AFCOUT, 0x00 >> 6); 772 ABB_WriteRegister(AFCOUT, 0x00 >> 6);
771 773
772 ABB_SetPage(PAGE0); 774 ABB_SetPage(PAGE0);
773 775
774 #elif (ANLG_FAM == 2) 776 #elif (ANALOG == 2)
775 // This configuration allows access on the AFCOUT register 777 // This configuration allows access on the AFCOUT register
776 ABB_SetPage(PAGE1); 778 ABB_SetPage(PAGE1);
777 779
778 // Read AFCCTLADD value and enable USP access to AFCOUT register 780 // Read AFCCTLADD value and enable USP access to AFCOUT register
779 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04); 781 reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04);
797 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe; 799 reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe;
798 800
799 ABB_WriteRegister(BCICTL1, reg_val); 801 ABB_WriteRegister(BCICTL1, reg_val);
800 #endif 802 #endif
801 803
802 #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected 804 #if (ANALOG == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected
803 // in Syren during sleep mode. BB charge stays enabled 805 // in Syren during sleep mode. BB charge stays enabled
804 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission 806 ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission
805 // change the register page in IOTA for usp to pg1 807 // change the register page in IOTA for usp to pg1
806 808
807 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode 809 ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode
812 // switch off MADC, AFC, AUXDAC, VOICE. 814 // switch off MADC, AFC, AUXDAC, VOICE.
813 ABB_WriteRegister(TOGBR1, 0x155); 815 ABB_WriteRegister(TOGBR1, 0x155);
814 816
815 // Switch off Analog supply LDO 817 // Switch off Analog supply LDO
816 //----------------------------- 818 //-----------------------------
817 #if (ANLG_FAM == 1) 819 #if (ANALOG == 1)
818 ABB_SetPage(PAGE1); 820 ABB_SetPage(PAGE1);
819 821
820 // Read VRPCCTL3 register value and switch off VR3. 822 // Read VRPCCTL3 register value and switch off VR3.
821 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df; 823 reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df;
822 824
823 ABB_WriteRegister(VRPCCTRL3, reg_val); 825 ABB_WriteRegister(VRPCCTRL3, reg_val);
824 826
825 #elif (ANLG_FAM == 2) 827 #elif (ANALOG == 2)
826 // Read VRPCSTS register value and extract status of meaningfull inputs. 828 // Read VRPCSTS register value and extract status of meaningfull inputs.
827 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070; 829 reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070;
828 830
829 if (reg_val == 0x30) 831 if (reg_val == 0x30)
830 { 832 {
833 } 835 }
834 836
835 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read". 837 // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read".
836 ABB_WriteRegister(0x0000 | 0x0001, 0x0000); 838 ABB_WriteRegister(0x0000 | 0x0001, 0x0000);
837 839
838 #elif (ANLG_FAM == 3) 840 #elif (ANALOG == 3)
839 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed 841 // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed
840 // start the SLPDLY counter in order to switch the ABB in sleep mode 842 // start the SLPDLY counter in order to switch the ABB in sleep mode
841 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission 843 ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission
842 // set Syren sleep bit 844 // set Syren sleep bit
843 /* 845 /*
887 SPI_Ready_for_RDWR 889 SPI_Ready_for_RDWR
888 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; 890 status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS;
889 891
890 if (sleep_performed == FRAME_STOP) // Big sleep 892 if (sleep_performed == FRAME_STOP) // Big sleep
891 { 893 {
892 #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) 894 #if ((ANALOG == 2) || (ANALOG == 3))
893 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP //////////////////////////// 895 //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP ////////////////////////////
894 #endif 896 #endif
895 } 897 }
896 else // Deep sleep 898 else // Deep sleep
897 { 899 {
907 909
908 // Restitutes 13MHZ Clock to ABB 910 // Restitutes 13MHZ Clock to ABB
909 ABB_free_13M(); 911 ABB_free_13M();
910 912
911 // Switch ON Analog supply LDO 913 // Switch ON Analog supply LDO
912 #if (ANLG_FAM == 1) 914 #if (ANALOG == 1)
913 ABB_SetPage(PAGE1); 915 ABB_SetPage(PAGE1);
914 916
915 // Read VRPCCTL3 register value and switch on VR3. 917 // Read VRPCCTL3 register value and switch on VR3.
916 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020; 918 reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020;
917 919
926 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7)); 928 ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7));
927 929
928 // This transmission sets the AUXAFC1. 930 // This transmission sets the AUXAFC1.
929 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff)); 931 ABB_WriteRegister(AUXAFC1, (afc & 0x3ff));
930 932
931 #if (ANLG_FAM == 1) 933 #if (ANALOG == 1)
932 // Remove AFC test mode 934 // Remove AFC test mode
933 ABB_SetPage(PAGE1); 935 ABB_SetPage(PAGE1);
934 936
935 // This transmission select Omega test instruction. 937 // This transmission select Omega test instruction.
936 ABB_WriteRegister(TAPREG, TSPTEST1); 938 ABB_WriteRegister(TAPREG, TSPTEST1);
939 // This transmission disables Omega test register. 941 // This transmission disables Omega test register.
940 ABB_WriteRegister(TAPCTRL, 0x00 >> 6); 942 ABB_WriteRegister(TAPCTRL, 0x00 >> 6);
941 943
942 ABB_SetPage(PAGE0); 944 ABB_SetPage(PAGE0);
943 945
944 #elif (ANLG_FAM == 2) 946 #elif (ANALOG == 2)
945 ABB_SetPage(PAGE1); 947 ABB_SetPage(PAGE1);
946 948
947 // Read AFCCTLADD register value and disable USP access to AFCOUT register. 949 // Read AFCCTLADD register value and disable USP access to AFCOUT register.
948 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04; 950 reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04;
949 951
969 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001; 971 reg_val = ABB_ReadRegister(BCICTL1) | 0x0001;
970 972
971 ABB_WriteRegister(BCICTL1, reg_val); 973 ABB_WriteRegister(BCICTL1, reg_val);
972 #endif 974 #endif
973 975
974 #if (ANLG_FAM == 3) 976 #if (ANALOG == 3)
975 977
976 ABB_SetPage(PAGE1); 978 ABB_SetPage(PAGE1);
977 979
978 /* *************************************************************************************************** */ 980 /* *************************************************************************************************** */
979 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. 981 // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value.
1028 } 1030 }
1029 #endif // ABB_SEMAPHORE_PROTECTION 1031 #endif // ABB_SEMAPHORE_PROTECTION
1030 1032
1031 ABB_SetPage(PAGE1); 1033 ABB_SetPage(PAGE1);
1032 1034
1033 #if (ANLG_FAM == 1) 1035 #if (ANALOG == 1)
1034 // This transmission initializes the VRPCCTL1 register. 1036 // This transmission initializes the VRPCCTL1 register.
1035 ABB_WriteRegister(VRPCCTRL1, value); 1037 ABB_WriteRegister(VRPCCTRL1, value);
1036 1038
1037 #elif (ANLG_FAM == 2) 1039 #elif (ANALOG == 2)
1038 // This transmission initializes the VRPCSIM register. 1040 // This transmission initializes the VRPCSIM register.
1039 ABB_WriteRegister(VRPCSIM, value); 1041 ABB_WriteRegister(VRPCSIM, value);
1040 1042
1041 #elif (ANLG_FAM == 3) 1043 #elif (ANALOG == 3)
1042 // This transmission initializes the VRPCSIMR register. 1044 // This transmission initializes the VRPCSIMR register.
1043 ABB_WriteRegister(VRPCSIMR, value); 1045 ABB_WriteRegister(VRPCSIMR, value);
1044 1046
1045 #endif 1047 #endif
1046 1048
1095 #endif 1097 #endif
1096 } 1098 }
1097 1099
1098 //////////////////////// IDEV-INLO integration of sleep mode for Syren /////////////////////////////////////// 1100 //////////////////////// IDEV-INLO integration of sleep mode for Syren ///////////////////////////////////////
1099 1101
1100 #if (ANLG_FAM == 3) 1102 #if (ANALOG == 3)
1101 1103
1102 // Syren Sleep configuration function -------------------------- 1104 // Syren Sleep configuration function --------------------------
1103 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay) 1105 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay)
1104 { 1106 {
1105 volatile SYS_UWORD16 status,sl_ldo_stat; 1107 volatile SYS_UWORD16 status,sl_ldo_stat;
1132 NU_Sleep (30); 1134 NU_Sleep (30);
1133 1135
1134 // Wait also until <ON/OFF> key is released. 1136 // Wait also until <ON/OFF> key is released.
1135 // This is needed to avoid, if the power key is pressed for a long time, to switch 1137 // This is needed to avoid, if the power key is pressed for a long time, to switch
1136 // ON-switch OFF the mobile, until the power key is released. 1138 // ON-switch OFF the mobile, until the power key is released.
1137 #if((ANLG_FAM == 1) || (ANLG_FAM == 2)) 1139 #if((ANALOG == 1) || (ANALOG == 2))
1138 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) { 1140 while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) {
1139 #elif(ANLG_FAM == 3) 1141 #elif(ANALOG == 3)
1140 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) { 1142 while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) {
1141 #endif 1143 #endif
1142 1144
1143 NU_Sleep (1); } 1145 NU_Sleep (1); }
1144 1146
1147 #if 0 // FreeCalypso
1145 BZ_KeyBeep_OFF(); 1148 BZ_KeyBeep_OFF();
1146 1149 #endif
1147 #if(ANLG_FAM == 1) 1150
1151 #if(ANALOG == 1)
1148 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE); 1152 ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE);
1149 #elif((ANLG_FAM == 2) || (ANLG_FAM == 3)) 1153 #elif((ANALOG == 2) || (ANALOG == 3))
1150 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001); 1154 ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001);
1151 #endif 1155 #endif
1152 } 1156 }
1153 #endif 1157 #endif
1154
1155
1156