comparison gsm-fw/bsp/abb+spi/abb.h @ 148:63750f70796d

gsm-fw/bsp/abb+spi: initial import from the Leonardo TCS211 version
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sat, 16 Nov 2013 19:03:37 +0000
parents
children 971e84124a6f
comparison
equal deleted inserted replaced
147:4ac657b95f52 148:63750f70796d
1 /**********************************************************************************/
2 /* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */
3 /* */
4 /* Property of Texas Instruments -- For Unrestricted Internal Use Only */
5 /* Unauthorized reproduction and/or distribution is strictly prohibited. This */
6 /* product is protected under copyright law and trade secret law as an */
7 /* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */
8 /* rights reserved. */
9 /* */
10 /* */
11 /* Filename : abb.h */
12 /* */
13 /* Description : Analog BaseBand registers and bits definition. */
14 /* Functions to drive the ABB device. */
15 /* The Serial Port Interface is used to connect the TI */
16 /* Analog BaseBand (ABB). */
17 /* It is assumed that the ABB is connected as the SPI */
18 /* device 0. */
19 /* */
20 /* Author : Pascal PUEL */
21 /* */
22 /* Version number : 1.3 */
23 /* */
24 /* Date and time : 08/22/03 */
25 /* */
26 /* Previous delta : Creation */
27 /* */
28 /**********************************************************************************/
29
30 #ifndef __ABB_H__
31 #define __ABB_H__
32
33 #include "l1sw.cfg"
34
35 #if (OP_L1_STANDALONE == 0)
36 #include "main/sys_types.h"
37 #else
38 #include "sys_types.h"
39 #endif
40
41
42 #ifndef _WINDOWS
43
44
45 #include "chipset.cfg"
46
47
48
49
50 /*------------------------------------*/
51 /* SYREN PG Definition */
52 /*------------------------------------*/
53
54 #if (ANLG_FAM == 3) // SYREN
55 #define S_PG_10 1
56 #define S_PG_20 2
57 #endif // (ANLG_FAM == 3)
58
59
60
61 // DEFINITIONS FOR OMEGA/NAUSICA
62 #if (ANLG_FAM == 1)
63 // ABB PAGE
64 #define PAGE0 0x0001
65 #define PAGE1 0x0002
66
67 // ABB REGISTERS
68 //=== PAGE 0 =======
69 #define PAGEREG (1 << 1)
70 #define APCDEL1 (2 << 1)
71 #define BULDATA1_2 (3 << 1)
72 #define TOGBR1 (4 << 1)
73 #define TOGBR2 (5 << 1)
74 #define VBDCTRL (6 << 1)
75 #define AUXAFC1 (7 << 1)
76 #define AUXAFC2 (8 << 1)
77 #define AUXAPC (9 << 1)
78 #define APCRAM (10 << 1)
79 #define APCOFF (11 << 1)
80 #define AUXDAC (12 << 1)
81 #define MADCCTRL1 (13 << 1)
82 #define MADCCTRL2 (14 << 1)
83 #define VBATREG (15 << 1)
84 #define VCHGREG (16 << 1)
85 #define ICHGREG (17 << 1)
86 #define VBKPREG (18 << 1)
87 #define ADIN1REG (19 << 1)
88 #define ADIN2REG (20 << 1)
89 #define ADIN3REG (21 << 1)
90 #define ADIN4XREG (22 << 1)
91 #define ADIN5YREG (23 << 1)
92 #define MADCSTAT (24 << 1)
93 #define CHGREG (25 << 1)
94 #define ITMASK (26 << 1)
95 #define ITSTATREG (27 << 1)
96 #define BCICTL1 (28 << 1)
97 #define BCICTL2 (29 << 1)
98 #define VRPCCTL2 (30 << 1)
99 #define VRPCSTS (31 << 1)
100
101 //=== PAGE 1 =======
102 #define PAGEREG (1 << 1)
103 #define BULIOFF (2 << 1)
104 #define BULQOFF (3 << 1)
105 #define BULQDAC (4 << 1)
106 #define BULIDAC (5 << 1)
107 #define BBCTRL (6 << 1)
108 #define VBUCTRL (7 << 1)
109 #define VBCTRL (8 << 1)
110 #define PWDNRG (9 << 1)
111 #define TSC_TIMER (10 << 1)
112 #define VRPCCTRL3 (11 << 1)
113 #define APCOUT (12 << 1)
114 #define VRPCBGT (18 << 1)
115 #define TAPCTRL (19 << 1)
116 #define TAPREG (20 << 1)
117 #define AFCCTLADD (21 << 1)
118 #define AFCOUT (22 << 1)
119 #define VRPCCTRL1 (23 << 1)
120 #define VRPCCTRL4 (24 << 1)
121 #define APCDEL2 (26 << 1)
122 #define ITSTATREG (27 << 1)
123
124 // Registers bit definitions
125 // ABB device bits definition of register VBCTRL
126 #define VDLAUX 0x001
127 #define VDLEAR 0x002
128 #define VBUZ 0x004
129 #define VULSWITCH 0x008
130 #define MICBIAS 0x010
131 #define VALOOP 0x020
132 #define VCLKMODE 0x040
133 #define VSYNC 0x080
134 #define VBDFAUXG 0x100
135 #define VFBYP 0x200
136
137 // ABB device bits definition of register VBUCTRL
138 #define DXEN 0x200
139
140 // ABB device bits definition of register VRPCSTS
141 #define ONBSTS 0x01 // ON Button push flag
142 #define ONRSTS 0x02 // Remote ON flag
143 #define ITWSTS 0x04 // Wake-up IT flag
144 #define CHGSTS 0x08 // Charger plug flag
145 #define ONREFLT 0x10 // ON Button current state
146 #define ORMRFLT 0x20 // Remote ON current state
147 #define CHGPRES 0x40 // Charger plug current state
148
149 // ABB device bits definition of register ITSTATREG
150 #define REMOT_IT_STS 0x02
151 #define PUSHOFF_IT_STS 0x04
152 #define CHARGER_IT_STS 0x08
153 #define ADCEND_IT_STS 0x20
154
155 // On Nausica, if the PWR key is pressed, the bit is set, and cleared when released
156 #define PWR_OFF_KEY_PRESSED (ONREFLT)
157
158 // ABB ADC Interrupts
159 #define EOC_INTENA 0x03DF
160 #define EOC_INTMASK 0x0020
161
162 // ABB ADC CHANNELS
163 #define VBATCV 0x0001
164 #define VCHGCV 0x0002
165 #define ICHGCV 0x0004
166 #define VBKPCV 0x0008
167 #define ADIN1CV 0x0010
168 #define ADIN2CV 0x0020
169 #define ADIN3CV 0x0040
170 #define vADIN4XCV 0x0080
171 #define ADIN5XCV 0x0100
172 #define ALL 0x01FF
173 #define NONE 0x0000
174
175 // ABB MODULES
176 #define MADC 0x8000
177 #define AFC 0x2000
178 #define ADAC 0x0800
179 #define DCDC 0x0080
180 #define ALLOFF 0x0000
181
182 // Definitions of OMEGA test modes for baseband windows
183 #define TSPTEST1 0x001d
184 #define TSPTEST2 0x001e
185 #define AFCTEST 0x0010
186 #define AFCNORM 0x0000
187
188
189 // DEFINITIONS FOR IOTA
190 #elif (ANLG_FAM == 2)
191 // ABB PAGE
192 #define PAGE0 0x0001
193 #define PAGE1 0x0002
194 #define PAGE2 0x0010
195
196 // ABB REGISTERS
197 //=== PAGE 0 =======
198 #define PAGEREG (1 << 1)
199 #define APCDEL1 (2 << 1)
200 #define BULDATA1_2 (3 << 1)
201 #define TOGBR1 (4 << 1)
202 #define TOGBR2 (5 << 1)
203 #define VBDCTRL (6 << 1)
204 #define AUXAFC1 (7 << 1)
205 #define AUXAFC2 (8 << 1)
206 #define AUXAPC (9 << 1)
207 #define APCRAM (10 << 1)
208 #define APCOFF (11 << 1)
209 #define AUXDAC (12 << 1)
210 #define MADCCTRL (13 << 1)
211 #define VBATREG (15 << 1)
212 #define VCHGREG (16 << 1)
213 #define ICHGREG (17 << 1)
214 #define VBKPREG (18 << 1)
215 #define ADIN1REG (19 << 1)
216 #define ADIN2REG (20 << 1)
217 #define ADIN3REG (21 << 1)
218 #define ADIN4REG (22 << 1)
219 #define MADCSTAT (24 << 1)
220 #define CHGREG (25 << 1)
221 #define ITMASK (26 << 1)
222 #define ITSTATREG (27 << 1)
223 #define BCICTL1 (28 << 1)
224 #define BCICTL2 (29 << 1)
225 #define VRPCDEV (30 << 1)
226 #define VRPCSTS (31 << 1)
227
228 //=== PAGE 1 =======
229 #define PAGEREG (1 << 1)
230 #define BULIOFF (2 << 1)
231 #define BULQOFF (3 << 1)
232 #define BULQDAC (4 << 1)
233 #define BULIDAC (5 << 1)
234 #define BBCTRL (6 << 1)
235 #define VBUCTRL (7 << 1)
236 #define VBCTRL1 (8 << 1)
237 #define PWDNRG (9 << 1)
238 #define VBPOP (10 << 1)
239 #define VBCTRL2 (11 << 1)
240 #define APCOUT (12 << 1)
241 #define BCICONF (13 << 1)
242 #define BULGCAL (14 << 1)
243 #define TAPCTRL (19 << 1)
244 #define TAPREG (20 << 1)
245 #define AFCCTLADD (21 << 1)
246 #define AFCOUT (22 << 1)
247 #define VRPCSIM (23 << 1)
248 #define AUXLED (24 << 1)
249 #define APCDEL2 (26 << 1)
250 #define ITSTATREG (27 << 1)
251 #define VRPCMSKABB (29 << 1)
252 #define VRPCCFG (30 << 1)
253 #define VRPCMSK (31 << 1)
254
255 // Registers bit definitions
256 // ABB device bits definition of register VBCTRL1
257 #define VDLAUX 0x001
258 #define VDLEAR 0x002
259 #define VBUZ 0x004
260 #define VULSWITCH 0x008
261 #define MICBIAS 0x010
262 #define VALOOP 0x020
263 #define VCLKMODE 0x040
264 #define VSYNC 0x080
265 #define VBDFAUXG 0x100
266 #define VFBYP 0x200
267
268 // ABB device bits definition of register VBCTRL2
269 #define MICBIASEL 0x001
270 #define VDLHSO 0x002
271 #define MICNAUX 0x004
272
273 // ABB device bits definition of register VBUCTRL
274 #define DXEN 0x200
275
276 // ABB device bits definition of register VBPOP
277 #define HSODIS 0x001
278 #define HSOCHG 0x002
279 #define HSOAUTO 0x004
280 #define EARDIS 0x008
281 #define EARCHG 0x010
282 #define EARAUTO 0x020
283 #define AUXDIS 0x040
284 #define AUXCHG 0x080
285 #define AUXAUTO 0x100
286
287 // ABB device bits definition of register VRPCSTS
288 #define ONBSTS 0x01 // ON Button push flag
289 #define ONRSTS 0x02 // Remote ON flag
290 #define ITWSTS 0x04 // Wake-up IT flag
291 #define CHGSTS 0x08 // Charger plug flag
292 #define ONREFLT 0x10 // ON Button current state
293 #define ORMRFLT 0x20 // Remote ON current state
294 #define CHGPRES 0x40 // Charger plug current state
295
296 // ABB device bits definition of register ITSTATREG
297 #define REMOT_IT_STS 0x02
298 #define PUSHOFF_IT_STS 0x04
299 #define CHARGER_IT_STS 0x08
300 #define ADCEND_IT_STS 0x20
301
302 // On Iota, the bit is set when the key is released and set when the key is pressed
303 #define PWR_OFF_KEY_PRESSED (0)
304
305 // ABB ADC Interrupts
306 #define EOC_INTENA 0x03DF
307 #define EOC_INTMASK 0x0020
308
309 // ABB ADC CHANNELS
310 #define VBATCV 0x0001
311 #define VCHGCV 0x0002
312 #define ICHGCV 0x0004
313 #define VBKPCV 0x0008
314 #define ADIN1CV 0x0010
315 #define ADIN2CV 0x0020
316 #define ADIN3CV 0x0040
317 #define ADIN4CV 0x0080
318 #define ALL 0x00FF
319 #define NONE 0x0000
320
321 // ABB MODULES
322 #define MADC 0x8000
323 #define AFC 0x2000
324 #define ADAC 0x0800
325 #define DCDC 0x0080
326 #define ALLOFF 0x0000
327
328 // Definitions of IOTA test modes
329 #define TSPTEST1 0x001d
330 #define TSPTEST2 0x001e
331 #define AFCTEST 0x0010
332 #define AFCNORM 0x0000
333
334 // Definition for IOTA test modes
335 #define TSPEN 0x001a
336 #define MADCTEST 0x0012
337 #define TSPADC 0x0015
338 #define TSPUP 0x0017
339 #define TSPDN 0x0018
340
341 // Definition for IOTA Power Management
342
343 //The duration of the SLPDLY counter must be greater than the process execution time:
344 //DBB deep sleep routine included the IT check = DBB sleep routine and IT check
345 //+ the seven 32Khz clock cycle interval needed to ABB in order to make effective the sleep abort write access in VRPCDEV ++ // register -> 7*T32Khz = = ABB IBIC propagation delay
346 //+ 150us of short asynchronous wake-up time (approximately 4*T32Khz) = ULPD short sleep where Syren/IOTA aborts sleep and
347 // write DEVSLEEP = 0
348
349
350
351
352 #define SLPDLY 0x001F // delay to set IOTA in sleep mode (unit: 20*T32Khz)
353 #define MASK_SLEEP_MODE 0x0000 // set the regulators in low consumption in sleep mode
354
355
356 // DEFINITIONS FOR SYREN
357 #elif (ANLG_FAM == 3)
358
359 // ABB PAGE
360 #define PAGE0 0x0001
361 #define PAGE1 0x0002
362 #define PAGE2 0x0010
363
364 // ABB REGISTERS
365 //=== PAGE 0 =======
366 #define PAGEREG (1 << 1)
367 #define APCDEL1 (2 << 1)
368 #define BULDATA1_2 (3 << 1)
369 #define TOGBR1 (4 << 1)
370 #define TOGBR2 (5 << 1)
371 #define VBDCTRL (6 << 1)
372 #define AUXAFC1 (7 << 1)
373 #define AUXAFC2 (8 << 1)
374 #define AUXAPC (9 << 1)
375 #define APCRAM (10 << 1)
376 #define APCOFF (11 << 1)
377 #define AUXDAC (12 << 1)
378 #define MADCCTRL (13 << 1)
379 #define CHGIREG (14 << 1)
380 #define VBATREG (15 << 1)
381 #define VCHGREG (16 << 1)
382 #define ICHGREG (17 << 1)
383 #define VBKPREG (18 << 1)
384 #define ADIN1REG (19 << 1)
385 #define ADIN2REG (20 << 1)
386 #define ADIN3REG (21 << 1)
387 #define ADIN4REG (22 << 1)
388 #define ADIN5REG (23 << 1)
389 #define MADCSTAT (24 << 1)
390 #define CHGVREG (25 << 1)
391 #define ITMASK (26 << 1)
392 #define ITSTATREG (27 << 1)
393 #define BCICTL1 (28 << 1)
394 #define BCICTL2 (29 << 1)
395 #define VRPCDEV (30 << 1)
396 #define VRPCSTS (31 << 1)
397
398 //=== PAGE 1 =======
399 #define PAGEREG (1 << 1)
400 #define BULIOFF (2 << 1)
401 #define BULQOFF (3 << 1)
402 #define BULQDAC (4 << 1)
403 #define BULIDAC (5 << 1)
404 #define BBCTRL (6 << 1)
405 #define VBUCTRL (7 << 1)
406 #define VBCTRL1 (8 << 1)
407 #define PWDNRG (9 << 1)
408 #define VBPOP (10 << 1)
409 #define VBCTRL2 (11 << 1)
410 #define APCOUT (12 << 1)
411 #define BCICONF (13 << 1)
412 #define BULGCAL (14 << 1)
413 #define VAUDCTRL (15 << 1)
414 #define VAUSCTRL (16 << 1)
415 #define VAUOCTRL (17 << 1)
416 #define VAUDPLL (18 << 1)
417 #define TAPCTRL (19 << 1)
418 #define TAPREG (20 << 1)
419 #define AFCCTLADD (21 << 1)
420 #define AFCOUT (22 << 1)
421 #define VRPCSIMR (23 << 1)
422 #define BCIWDOG (24 << 1)
423 #define NONE8 (25 << 1)
424 #define APCDEL2 (26 << 1)
425 #define ITSTATREG (27 << 1)
426
427 #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO
428 #define BBCFG (28 << 1)
429 #else
430 #define NONE9 (28 << 1)
431 #endif
432
433 #define VRPCMSKOFF (29 << 1)
434 #define VRPCCFG (30 << 1)
435 #define VRPCMSKSLP (31 << 1)
436
437 //=== PAGE 2 =======
438
439 #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE
440 #define BBCFG (5 << 1)
441 #endif
442
443 #define VRPCABBTST (25 << 1)
444 #define VRPCAUX (30 << 1)
445 #define VRPCLDO (31 << 1)
446
447 /* INSERT HERE OTHER DEVICES REGISTERS */
448
449
450 // Registers bit definitions
451 /*** SYREN internal control bits ***/
452
453 /** For reg. VBCTRL1 **/
454 #define VULSWITCH 0x008
455 #define MICBIAS 0x010
456 #define VALOOP 0x020
457 #define VCLKMODE 0x040
458 #define VSYNC 0x080
459 #define VBDFAUXG 0x100
460 #define VFBYP 0x200
461
462 /** For reg. VBCTRL2 **/
463 #define HSMICSEL 0x001
464 #define MICBIASEL 0x004
465 #define SPKG 0x008
466 #define HSOVMID 0x010
467 #define HSDIF 0x020
468
469 /** For reg. VBUCTRL **/
470 #define DXEN 0x200
471
472 /** For reg. VBPOP **/
473 #define HSODIS 0x001
474 #define HSOCHG 0x002
475 #define HSOAUTO 0x004
476 #define EARDIS 0x008
477 #define EARCHG 0x010
478 #define EARAUTO 0x020
479 #define AUXFDIS 0x040
480 #define AUXAUTO 0x080
481 #define AUXFBYP 0x200
482
483 // ABB device bits definition of register VRPCCFG
484 #define PWOND 0x20 // ON Button current state
485 #define CHGPRES 0x40
486
487 // ABB device bits definition of register ITSTATREG
488 #define REMOT_IT_STS 0x02
489 #define PUSHOFF_IT_STS 0x04
490 #define CHARGER_IT_STS 0x08
491 #define ADCEND_IT_STS 0x20
492
493 // ABB device bits definition of register VRPCSTS
494 #define ITWSTS 0x10 // Wake-up IT flag
495 #define PWONBSTS 0x20 // ON Button push flag
496 #define CHGSTS 0x40 // Charger plug flag
497 #define RPSTS 0x100 // Remote ON flag
498
499 // ABB ADC Interrupts
500 #define EOC_INTENA 0x03DF
501 #define EOC_INTMASK 0x0020
502
503 // ABB ADC CHANNELS (reg. MADCCTRL)
504 #define VBATCV 0x0001
505 #define VCHGCV 0x0002
506 #define ICHGCV 0x0004
507 #define VBKPCV 0x0008
508 #define ADIN1CV 0x0010
509 #define ADIN2CV 0x0020
510 #define ADIN3CV 0x0040
511 #define ADIN4CV 0x0080
512 #define ADIN5CV 0x0100
513 #define ALL 0x01FF
514 #define NONE 0x0000
515
516 // ABB MODULES
517 #define MADC 0x8000
518 #define AFC 0x2000
519 #define ADAC 0x0800
520 #define DCDC 0x0080
521 #define ALLOFF 0x0000
522
523 // Definitions of SYREN test modes
524 #define TSPTEST1 0x001d
525 #define TSPTEST2 0x001e
526 #define AFCTEST 0x0010
527 #define AFCNORM 0x0000
528
529 #define TSPEN 0x001a
530 #define MADCTEST 0x0012
531 #define TSPADC 0x0015
532 #define TSPUP 0x0017
533 #define TSPDN 0x0018
534
535 // Definition for SYREN Power Management
536
537 //The duration of the SLPDLY counter must be greater than the process execution time:
538 //DBB deep sleep routine included the IT check = DBB sleep routine and IT check
539 //+ the seven 32Khz clock cycle interval needed to ABB in order to make effective the sleep abort write access in VRPCDEV ++ // register -> 7*T32Khz = = ABB IBIC propagation delay
540 //+ 150us of short asynchronous wake-up time (approximately 4*T32Khz) = ULPD short sleep where Syren/IOTA aborts sleep and
541 // write DEVSLEEP = 0
542
543 #define SLPDLY 0x001F // delay to set SYREN in sleep mode (unit: 20*T32Khz)
544 #define MASK_SLEEP_MODE 0x0000 // set the regulators in low consumption in sleep mode
545
546 #define LOCORE_SLEEP 0x01
547 #define NORMAL_SLEEP 0x00
548
549 #define MAIN_BG 0x01,
550 #define SLEEP_BG 0x00
551
552 #endif // ANLG_FAM == 1,2,3
553
554
555 // Define the level of semaphore protection for all accesses to the ABB
556 // 0 for no protection
557 // 1 for protection low
558 // 2 for protection medium
559 // 3 for protection high
560 #if (OP_L1_STANDALONE == 1)
561 #define ABB_SEMAPHORE_PROTECTION (0)
562 #else
563 #define ABB_SEMAPHORE_PROTECTION (1)
564 #endif
565
566
567
568 // PROTOTYPES
569 #if (ABB_SEMAPHORE_PROTECTION)
570 void ABB_Sem_Create(void);
571 #endif
572 void ABB_Wait_IBIC_Access(void);
573 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value);
574 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id);
575 void ABB_free_13M(void);
576 void ABB_stop_13M(void);
577 SYS_UWORD16 ABB_Read_Status(void);
578 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal);
579 void ABB_Read_ADC(SYS_UWORD16 *Buff);
580 void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag);
581 SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc);
582 void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc);
583 void ABB_wa_VRPC(SYS_UWORD16 value);
584 void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data);
585 #if (OP_L1_STANDALONE == 0)
586 void ABB_Power_Off(void);
587 #endif
588 #if (ANLG_FAM ==3)
589 void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay);
590 #endif
591
592 #else // _WINDOWS
593 // DEFINITIONS FOR IOTA
594 // ABB PAGE
595 #define PAGE0 0x0001
596 #define PAGE1 0x0002
597 #define PAGE2 0x0010
598
599 // ABB REGISTERS
600 //=== PAGE 0 =======
601 #define PAGEREG (1 << 1)
602 #define APCDEL1 (2 << 1)
603 #define BULDATA1_2 (3 << 1)
604 #define TOGBR1 (4 << 1)
605 #define TOGBR2 (5 << 1)
606 #define VBDCTRL (6 << 1)
607 #define AUXAFC1 (7 << 1)
608 #define AUXAFC2 (8 << 1)
609 #define AUXAPC (9 << 1)
610 #define APCRAM (10 << 1)
611 #define APCOFF (11 << 1)
612 #define AUXDAC (12 << 1)
613 #define MADCCTRL (13 << 1)
614 #define VBATREG (15 << 1)
615 #define VCHGREG (16 << 1)
616 #define ICHGREG (17 << 1)
617 #define VBKPREG (18 << 1)
618 #define ADIN1REG (19 << 1)
619 #define ADIN2REG (20 << 1)
620 #define ADIN3REG (21 << 1)
621 #define ADIN4REG (22 << 1)
622 #define MADCSTAT (24 << 1)
623 #define CHGREG (25 << 1)
624 #define ITMASK (26 << 1)
625 #define ITSTATREG (27 << 1)
626 #define BCICTL1 (28 << 1)
627 #define BCICTL2 (29 << 1)
628 #define VRPCDEV (30 << 1)
629 #define VRPCSTS (31 << 1)
630
631 //=== PAGE 1 =======
632 #define PAGEREG (1 << 1)
633 #define BULIOFF (2 << 1)
634 #define BULQOFF (3 << 1)
635 #define BULQDAC (4 << 1)
636 #define BULIDAC (5 << 1)
637 #define BBCTRL (6 << 1)
638 #define VBUCTRL (7 << 1)
639 #define VBCTRL1 (8 << 1)
640 #define PWDNRG (9 << 1)
641 #define VBPOP (10 << 1)
642 #define VBCTRL2 (11 << 1)
643 #define APCOUT (12 << 1)
644 #define BCICONF (13 << 1)
645 #define BULGCAL (14 << 1)
646 #define TAPCTRL (19 << 1)
647 #define TAPREG (20 << 1)
648 #define AFCCTLADD (21 << 1)
649 #define AFCOUT (22 << 1)
650 #define VRPCSIM (23 << 1)
651 #define AUXLED (24 << 1)
652 #define APCDEL2 (26 << 1)
653 #define ITSTATREG (27 << 1)
654 #define VRPCMSKABB (29 << 1)
655 #define VRPCCFG (30 << 1)
656 #define VRPCMSK (31 << 1)
657
658 // ABB device bits definition of register VBUCTRL
659 #define DXEN 0x200
660
661 // ABB device bits definition of register VRPCSTS
662 #define ONBSTS 0x01 // ON Button push flag
663 #define ONRSTS 0x02 // Remote ON flag
664 #define ITWSTS 0x04 // Wake-up IT flag
665 #define CHGSTS 0x08 // Charger plug flag
666 #define ONREFLT 0x10 // ON Button current state
667 #define ORMRFLT 0x20 // Remote ON current state
668 #define CHGPRES 0x40 // Charger plug current state
669
670 // ABB device bits definition of register ITSTATREG
671 #define REMOT_IT_STS 0x02
672 #define PUSHOFF_IT_STS 0x04
673 #define CHARGER_IT_STS 0x08
674 #define ADCEND_IT_STS 0x20
675
676
677 // PROTOTYPES
678 void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD32 value);
679 SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id);
680 SYS_UWORD16 ABB_Read_Status(void);
681 void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal);
682 void ABB_Read_ADC(SYS_UWORD16 *Buff);
683
684 #endif // _WINDOWS
685
686 #endif // __ABB_H__