comparison gsm-fw/L1/tpudrv/tpudrv12.h @ 153:65efffcb28dc

tpudrv*.h headers imported
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 17 Nov 2013 05:10:06 +0000
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children 47754cdb6248
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152:26472940e5b0 153:65efffcb28dc
1 /****************** Revision Controle System Header ***********************
2 * GSM Layer 1 software
3 * Copyright (c) Texas Instruments 1998
4 *
5 * Filename tpudrv12.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ****************** Revision Controle System Header ***********************/
9
10 //--- Configuration values
11 #define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode
12 #define RF_VERSION 1 // 1 or V1, 5 for V5, etc
13 #define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init"
14 // TeST - Enable Main VCO buffer for test
15 #define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer
16
17 #include "rf.cfg"
18
19 //--- RITA PG declaration
20
21 #define R_PG_10 0
22 #define R_PG_13 1
23 #define R_PG_20 2 // For RFPG 2.2, use 2.0
24 #define R_PG_23 3
25
26 //--- PA declaration
27 #define PA_MGF9009 0
28 #define PA_RF3146 1
29 #define PA_RF3133 2
30 #define PA_PF08123B 3
31 #define PA_AWT6108 4
32
33 #if (RF_PA == PA_MGF9009 || RF_PA == PA_PF08123B)
34 #define PA_CTRL_INT 0
35 #else
36 #define PA_CTRL_INT 1
37 #endif
38
39 //- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0
40 // AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number)
41 // This is also used in l1_rf12.h to select the SWAP_IQ
42 #if (RF_PG >= R_PG_20)
43 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
44 #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around")
45 #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds
46 #elif (RF_PG == R_PG_13)
47 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
48 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
49 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
50 #else
51 // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX
52 #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around")
53 #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds
54 #endif
55
56 //- Bit definitions for TST register programings, etc
57 #define BIT_0 0x000001
58 #define BIT_1 0x000002
59 #define BIT_2 0x000004
60 #define BIT_3 0x000008
61 #define BIT_4 0x000010
62 #define BIT_5 0x000020
63 #define BIT_6 0x000040
64 #define BIT_7 0x000080
65 #define BIT_8 0x000100
66 #define BIT_9 0x000200
67 #define BIT_10 0x000400
68 #define BIT_11 0x000800
69 #define BIT_12 0x001000
70 #define BIT_13 0x002000
71 #define BIT_14 0x004000
72 #define BIT_15 0x008000
73 #define BIT_16 0x010000
74 #define BIT_17 0x020000
75 #define BIT_18 0x040000
76 #define BIT_19 0x080000
77 #define BIT_20 0x100000
78 #define BIT_21 0x200000
79 #define BIT_22 0x400000
80 #define BIT_23 0x800000
81
82 //--- TRF6151 definitions ------------------------------------------
83
84 //- BASE REGISTER definitions
85 #define REG_RX 0x000000 // MODE0
86 #define REG_PLL 0x000001 // MODE1
87 #define REG_PWR 0x000002 // MODE2
88 #define REG_CFG 0x000003 // MODE3
89
90 //- TeST REGISTER definitions => Used for WA only
91 // TeST - PLL2 WA => Define PLL2 TEST register
92 #define TST_PLL2 0x00001E // MODE 14
93
94 // TeST - Enable Main VCO buffer for test => Define TST_VCO3 register
95 #define TST_VCO3 0x00000F // MODE 15 (0*16+15*1)
96 #define TST_VCO4 0x000024 // MODE 36 (2*16+4*1)
97
98 // Alpha RF7 WA TeST registers
99 #define TST_LDO 0x000027 // MODE 39 (2*16+7*1)
100 #define TST_PLL1 0x00001D // MODE 29 (1*16+13*1)
101 #define TST_TX2 0x000037 // MODE 55 (3*16+7*1)
102
103 // More Alpha RF7 WA TeST registers
104 #define TST_TX3 0x00003C // MODE 61 (3*16+12*1)
105 #define TST_TX4 0x00003D // MODE 61 (3*16+13*1)
106
107 // PG 2.1 WA TeST registers
108 #define TST_PLL3 0x00001F // MODE 31 (1*16+15*1)
109 // #define TST_PLL4 0x00002C // MODE 44 (2*16+12*1)
110 #define TST_MISC 0x00003E // MODE 62 (3*16+14*1) => Used for setting the VCXO current
111 #define TST_LO 0x00001C // MODE 28 (1*16+12*1)
112
113 // Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1
114 // UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that,
115 // when accessed, triggers the copy of the serial registers.
116 // This is necessary to switch into "manual operation mode"
117 #define UPDATE_SERIAL_INTERFACE_COPY 0x000007
118 #define TX_LOOP_MANUAL BIT_3
119
120
121 //- REG_RX - MODE0
122 #define BLOCK_DETECT_0 BIT_3
123 #define BLOCK_DETECT_1 BIT_4
124 #define RST_BLOCK_DETECT_0 BIT_5
125 #define RST_BLOCK_DETECT_1 BIT_6
126 #define READ_EN BIT_7
127 #define RX_CAL_MODE BIT_8
128 #define RF_GAIN (BIT_10 | BIT_9)
129
130
131 //- REG_PLL - MODE1
132 //PLL_REGB
133 //PLL_REGA
134
135 //- REG_PWR - MODE2
136 #define BANDGAP_MODE_OFF 0x0
137 #define BANDGAP_MODE_ON_ENA BIT_4
138 #define BANDGAP_MODE_ON_DIS (BIT_4 | BIT_3)
139 #define REGUL_MODE_ON BIT_5
140 // BIT[8..6] band
141 #define BAND_SELECT_GSM BIT_6
142 #define BAND_SELECT_DCS BIT_7
143 #define BAND_SELECT_850_LO BIT_8
144 #define BAND_SELECT_850_HI (BIT_8 | BIT_6)
145 #define BAND_SELECT_PCS (BIT_8 | BIT_7)
146
147 #define SYNTHE_MODE_OFF 0x0
148 #define SYNTHE_MODE_RX BIT_9
149 #define SYNTHE_MODE_TX BIT_10
150 #define RX_MODE_OFF 0x0
151 #define RX_MODE_A BIT_11
152 #define RX_MODE_B1 BIT_12
153 #define RX_MODE_B2 (BIT_12 | BIT_11)
154 #define TX_MODE_OFF 0x0
155 #define TX_MODE_ON BIT_13
156 #define PACTRL_APC_OFF 0x0
157 #define PACTRL_APC_ON BIT_14
158 #define PACTRL_APC_DIS 0x0
159 #define PACTRL_APC_ENA BIT_15
160
161
162 //- REG_CFG - MODE3
163 // Common PA controller settings:
164 #define PACTRL_TYPE_PWR 0x0
165 #define PACTRL_TYPE_CUR BIT_3
166 #define PACTRL_IDIOD_30_UA 0x0
167 #define PACTRL_IDIOD_300_UA BIT_4
168
169 // PA controller Clara-like (Power Sensing) settings:
170 #define PACTRL_VHOME_610_MV (BIT_7 | BIT_5)
171 #define PACTRL_VHOME_839_MV (BIT_7 | BIT_5)
172 #define PACTRL_VHOME_1000_MV (BIT_6 | BIT_9)
173 #define PACTRL_VHOME_1600_MV (BIT_8 | BIT_5)
174 #define PACTRL_RES_OPEN 0x0
175 #define PACTRL_RES_150_K BIT_10
176 #define PACTRL_RES_300_K BIT_11
177 #define PACTRL_RES_NU (BIT_10 | BIT_11)
178 #define PACTRL_CAP_0_PF 0x0
179 #define PACTRL_CAP_12_5_PF BIT_12
180 #define PACTRL_CAP_25_PF (BIT_13 | BIT_12)
181 #define PACTRL_CAP_50_PF BIT_13
182
183 // PACTRL_CFG contains the configuration of the PACTRL that will
184 // be put into the REG_CFG register at initialization time
185 // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR)
186 // in this #define!!!
187 #if (RF_PA == 0) // MGF9009 (LCPA)
188 #define PACTRL_CFG \
189 PACTRL_IDIOD_300_UA | \
190 PACTRL_CAP_25_PF | \
191 PACTRL_VHOME_1000_MV | \
192 PACTRL_RES_300_K
193 #elif (RF_PA == 1) // 3146
194 #define PACTRL_CFG 0
195
196 #elif (RF_PA == 2) // 3133
197 #define PACTRL_CFG 0
198
199 #elif (RF_PA == 3) // PF08123B
200 #define PACTRL_CFG \
201 PACTRL_TYPE_PWR | \
202 PACTRL_CAP_50_PF | \
203 PACTRL_RES_300_K | \
204 PACTRL_VHOME_610_MV
205 #elif (RF_PA == 4) // AWT6108
206 #define PACTRL_CFG 0
207 #else
208 #error Unknown PA specifiec!
209 #endif
210
211 // Temperature sensor
212 #define TEMP_SENSOR_OFF 0x0
213 #define TEMP_SENSOR_ON BIT_14
214 // Internal Logic Init Disable
215 #define ILOGIC_INIT_DIS BIT_15
216 // ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register
217 // It was introduced in PG 1.2
218 // For previous PGs this BIT was unused, so it can be safelly programmed
219 // for all PGs
220
221
222 // RF signals connected to TSPACT [0..7]
223 //#define RESET_RF BIT_0 // act0
224 #define RF_SER_ON BIT_0 // act0
225 #define RF_SER_OFF 0
226
227
228 #if (FEM_TEST==1)
229 //for test
230 #define TEST_TX_ON BIT_2 // act2
231 #define TEST_RX_ON BIT_3 // act3
232
233 //3-band config (D-sample)
234 #define FEM_1 BIT_1 // act1
235 #define FEM_2 0 //BIT_2 // act2
236 #define FEM_3 0 //BIT_3 // act3
237 #elif (BOARD == 42 || BOARD == 43 || BOARD == 35 || (BOARD == 41 && (RF_PA == 0 || RF_PA == 1 || RF_PA == 2 || RF_PA == 4))) // ESample, P2, Leonardo
238 #define TEST_TX_ON 0
239 #define TEST_RX_ON 0
240 // 4-band config (E-sample, P2, Leonardo)
241 #define FEM_7 BIT_2 // act2
242 #define FEM_8 BIT_1 // act1
243 #define FEM_9 BIT_4 // act4
244
245 #if (RF_PA == 0) // LCPA for ES, P2 and Leo
246 #define PA_HI_BAND BIT_3 // act3
247 #define PA_LO_BAND 0
248 #define PA_OFF 0
249 #elif (RF_PA == 1) // RF3146 for ES and Leonardo
250 #define PA_HI_BAND BIT_3 // act3
251 #define PA_LO_BAND 0
252 #define PA_OFF 0
253 #elif (RF_PA == 2) // RF3133 for P2 and Leonardo
254 #define PA_HI_BAND BIT_3 // act3
255 #define PA_LO_BAND 0
256 #define PA_OFF 0
257 #elif (RF_PA == 4) // AWT6108 for Leonardo
258 #define PA_HI_BAND BIT_3 // act3
259 #define PA_LO_BAND 0
260 #define PA_OFF 0
261 #else
262 #error "RF_PA not correctly defined"
263 #endif
264
265 #else // DSample + EVARITA
266 #if (RF_PA != 3) // Hitachi for EVARITA
267 #error
268 #endif
269
270 //#define TEST_RX_ON 0
271 //#define TEST_TX_ON BIT_3 // act3
272 #define TEST_TX_ON 0
273 #define TEST_RX_ON BIT_3 // act3
274
275 //3-band config (D-sample)
276 #define FEM_1 BIT_1 // act1
277 #define FEM_2 BIT_2 // act2
278 #define FEM_3 BIT_3 // act3
279 #endif
280
281 #if (BOARD == 42 || BOARD == 43 || BOARD == 35 || (BOARD == 41 && (RF_PA == 0 || RF_PA == 1 || RF_PA == 2 || RF_PA == 4))) // ESample, P2, Leonardo
282
283 #define FEM_PINS (FEM_7 | FEM_8 | FEM_9)
284
285 #define FEM_OFF ( FEM_PINS ^ 0 )
286
287 #define FEM_SLEEP ( 0 )
288
289 // This configuration is always inverted.
290
291 // 4-band config
292 // RX_UP/DOWN and TX_UP/DOWN
293 #define RU_900 ( PA_OFF | FEM_PINS ^ 0 )
294 #define RD_900 ( PA_OFF | FEM_PINS ^ 0 )
295 #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_9 )
296 #define TD_900 ( PA_OFF | FEM_PINS ^ 0 )
297
298 #define RU_850 ( PA_LO_BAND | FEM_PINS ^ 0 )
299 #define RD_850 ( PA_OFF | FEM_PINS ^ 0 )
300 #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_9 )
301 #define TD_850 ( PA_OFF | FEM_PINS ^ 0 )
302
303 #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 )
304 #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 )
305 #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_7 )
306 #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 )
307
308 #define RU_1900 ( PA_LO_BAND | FEM_PINS ^ FEM_8 )
309 #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 )
310 #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_7 )
311 #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 )
312
313 #else // end BOARD = 43
314 // start RF HW interfacing with EVARITA
315
316 #define FEM_OFF (FEM_1 | FEM_2)
317 #define FEM_SLEEP (0) // To avoid leakage during Deep-Seep
318
319 // 3-band config
320 // RX_UP/DOWN and TX_UP/DOWN
321 #define RU_900 ( FEM_1 | FEM_2 )
322 #define RD_900 ( FEM_1 | FEM_2 )
323 #define TU_900 ( FEM_1 )
324 #define TD_900 ( FEM_1 | FEM_2 )
325
326 #define RU_850 ( FEM_1 | FEM_2 )
327 #define RD_850 ( FEM_1 | FEM_2 )
328 #define TU_850 ( FEM_1 )
329 #define TD_850 ( FEM_1 | FEM_2 )
330
331 #define RU_1800 ( FEM_1 | FEM_2 )
332 #define RD_1800 ( FEM_1 | FEM_2 )
333 #define TU_1800 ( FEM_2 )
334 #define TD_1800 ( FEM_1 | FEM_2 )
335
336 #define RU_1900 ( FEM_1 | FEM_2 )
337 #define RD_1900 ( FEM_1 | FEM_2 )
338 #define TU_1900 ( FEM_2)
339 #define TD_1900 ( FEM_1 | FEM_2 )
340
341 #endif // BOARD != 43
342
343 #define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0
344 #define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2
345
346
347 //--- TIMINGS ----------------------------------------------------------
348
349 /*------------------------------------------*/
350 /* Download delay values */
351 /*------------------------------------------*/
352 // 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12)
353
354 #define T TPU_CLOCK_RANGE
355
356
357 // - TPU instruction into TSP timings ---
358 // 1 tpu instruction = 1 qbit
359 #define DLT_1 1 // 1 tpu instruction = 1 qbit
360 #define DLT_2 2 // 2 tpu instruction = 2 qbit
361 #define DLT_3 3 // 3 tpu instruction = 3 qbit
362 #define DLT_4 4 // 4 tpu instruction = 4 qbit
363 #define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12
364
365 // - Serialization timings ---
366 // The following values where calculated with Katrin Matthes...
367 //#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed,
368 // // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit
369 //#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed,
370 // // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit
371 // ... while the following values are based on the HYP004.doc document
372 #define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed,
373 // i.e. 12 / 6 qbit = 2 qbit
374 #define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed,
375 // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit
376
377 // - TPU command execution + serialization length ---
378 #define DLT_1B 4 // 3*move + serialization of 7 bits
379 #define DLT_2B 7 // 4*move + serialization of 2 bytes
380 //#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits
381 //#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes
382
383
384 // - INIT (delta or DLT) timings ---
385 #define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON
386 #define DLT_I2 8 // Time required to set RF_SER_OFF
387 #define DLT_I3 5 // Time required to set RF_SER_ON
388 #define DLT_I4 110 // Regulator Turn-ON time
389
390
391 // - tdt & rdt ---
392 // MAX GSM (not GPRS) rdt and tdt values are...
393 //#define rdt 380 // MAX GSM rx delta timing
394 //#define tdt 400 // MAX GSM tx delta timing
395 // but current rdt and tdt values are...
396 #define rdt 0 // rx delta timing
397 #define tdt 0 // tx delta timing
398
399 // - RX timings ---
400 // - RX down:
401 // The times below are offsets to when BDLENA goes down
402 #define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute
403 #define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode)
404
405 // - RX up:
406 // The times below are offsets to when BDLENA goes high
407 // Burst data comes here
408 #define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later)
409 #define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH
410 #define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init
411 #define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path
412 #define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX
413 #define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically)
414 //l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst
415 #define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth
416 #define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel
417
418 // - TX timings ---
419 // - TX down:
420 // The times below are offsets to when BULENA goes down
421
422 #if (PA_CTRL_INT == 1)
423 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
424 #define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF.
425 #define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN.
426 #endif
427
428 #if (PA_CTRL_INT == 0)
429 #define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low
430 #define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2
431 #define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1
432 #endif
433
434 #define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst
435 #define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read
436
437 // - TX up:
438 // The times below are offsets to when BULENA goes high
439 //burst data comes here
440 #define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN
441 #define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH
442
443 #if (PA_CTRL_INT == 0)
444 #define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL
445 #endif
446
447 #define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst
448 #define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration
449 #define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration
450 #define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX
451 #define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path
452 // TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above
453 #define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS
454 #define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode"
455 #define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation"
456 #define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode"
457 #define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON
458 #define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel
459