FreeCalypso > hg > freecalypso-sw
comparison gsm-fw/L1/tpudrv/tpudrv8.h @ 153:65efffcb28dc
tpudrv*.h headers imported
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
---|---|
date | Sun, 17 Nov 2013 05:10:06 +0000 |
parents | |
children |
comparison
equal
deleted
inserted
replaced
152:26472940e5b0 | 153:65efffcb28dc |
---|---|
1 /****************** Revision Controle System Header *********************** | |
2 * GSM Layer 1 software | |
3 * Copyright (c) Texas Instruments 1998 | |
4 * | |
5 * Filename tpudrv8.h | |
6 * Copyright 2003 (C) Texas Instruments | |
7 * | |
8 ****************** Revision Controle System Header ***********************/ | |
9 | |
10 //SI4133 definitions | |
11 #define WordAdd0000 0x000000 //Main Configuration | |
12 #define AutoPDB 0x000080 //Auto Power Down - Uses PWDNB pin | |
13 #define AuxSel 0x030000 //Auxiliary output pin use = LOCK Detect | |
14 #define WordAdd0011 0x000003 //RF1 N Divider | |
15 #define WordAdd0100 0x000004 //RF2 N Divider | |
16 #define WordAdd0101 0x000005 //IF N Divider | |
17 #define RFPWR 0x000020 //RF LO high power | |
18 #define XPDM 0x000100 //Reference amplifier ON when PWDNB pin = 0 | |
19 | |
20 //TRF6053 definitions | |
21 #define Mode0 0x000000 | |
22 #define Mode1 0x000001 | |
23 #define Mode2 0x000003 | |
24 #define Mode3 0x000005 | |
25 #define Mode4 0x000007 | |
26 #define LNAMixPwrOn 0x000080 //Mode0 | |
27 #define VCODiv2PwrOn 0x000040 //Mode0 | |
28 #define RXBBIFStgPwrOn 0x000020 //Mode0 | |
29 #define OFFStrCalOn 0x000010 //Mode0 | |
30 #define VCORDivPwrOn 0x000008 //Mode0 | |
31 #define MixLOBuffPwrOn 0x000004 //Mode0 | |
32 #define TXStagesPwrOn 0x000002 //Mode0 | |
33 #define FreqDetDis 0x000400 //Mode4 | |
34 #define IFVCOExternal 0x000200 //Mode4 | |
35 #define IFPLLBuffDis 0x000100 //Mode4 | |
36 #define LBandLNAExt 0x000080 //Mode4 | |
37 #define HBandLNAExt 0x000040 //Mode4 | |
38 #define Div2ToRXStgs 0x000020 //Mode4 | |
39 #define DivRToTXStgs 0x000010 //Mode4 | |
40 #define ChgPPLBNeg 0x000010 //Mode2 | |
41 #define ChgPPHBNeg 0x000010 //Mode3 | |
42 #define PreCCLBDis 0x000008 //Mode2 | |
43 #define PreCCHBDis 0x000008 //Mode3 | |
44 #define LNAGainLow 0x000010 //Mode2 | |
45 #define BandHigh 0x000008 //Mode1 | |
46 #define LowBIF610 0x000020 //Mode2 | |
47 #define HighBIF412 0x000020 //Mode3 | |
48 #define HighBIF25 0x000040 //Mode3 | |
49 #define HighBIF410 0x000060 //Mode3 | |
50 | |
51 /*------------------------------------------*/ | |
52 /* Download delay values */ | |
53 /*------------------------------------------*/ | |
54 #define TRF6053_DOWNLOAD_TIME 15 | |
55 #define SYNTH_DOWNLOAD_TIME 20 | |
56 | |
57 //-------------------------------------------- | |
58 // internal tpu timing | |
59 //-------------------------------------------- | |
60 | |
61 #define DLT_1 1 // 1 tpu instruction = 1 qbit | |
62 #define DLT_2 2 | |
63 #define DLT_3 3 | |
64 #define DLT_4 4 | |
65 | |
66 #define DLT_1B 4 // 3*move + 1*byte (download) | |
67 #define DLT_2B 6 // 4*move + 2*byte | |
68 #define DLT_3B 8 // 5*move + 3*byte | |
69 | |
70 #define SL_SU_DELAY1 4 // No. bits to send + load data to shift + send write cmd + 1 | |
71 #define SL_SU_DELAY2 3 // load data to shift + send write cmd + 1 | |
72 #define SL_SU_DELAY3 5 // SL_SU_DELAY1 + serialization | |
73 | |
74 /*------------------------------------------*/ | |
75 /* Download delay values */ | |
76 /*------------------------------------------*/ | |
77 // 0.9230769 usec ~ 1 qbit i.e. 200 usec is ~ 217 qbit | |
78 | |
79 #define T TPU_CLOCK_RANGE // TODO: should be a define from L1. | |
80 | |
81 // time below are offset to when BDLENA goes low | |
82 #define TRF_R11 ( 0 - DLT_1B) // disable BDLON & BDLENA | |
83 #define TRF_R10 ( - 5 - DLT_1B) // disable TRF6053 | |
84 | |
85 // burst data comes here | |
86 // time below are offset to when BDLENA goes high | |
87 #define TRF_R9 (PROVISION_TIME - 0 - DLT_1B) // enable BDLENA, disable BDLCAL | |
88 #define TRF_R8 (PROVISION_TIME - 11 - DLT_1B) // power on RX front end, DC cal. off | |
89 #define TRF_R7 (PROVISION_TIME - 65 - DLT_1B) // enable BDLCAL | |
90 #define TRF_R6 (PROVISION_TIME - 72 - DLT_1B) // enable BDLON | |
91 #define TRF_R5 (PROVISION_TIME - 76 - DLT_1B) // power on receiver, start DC cal. | |
92 #define TRF_R4 (PROVISION_TIME - 80 - DLT_2B) // set RX gain & band. | |
93 // ADC read, uses min 11 qbit due to 5 wait | |
94 #define TRF_R3 (PROVISION_TIME - 196 - DLT_1B) // power up TRF2253 | |
95 #define TRF_R1 (PROVISION_TIME - 205 - DLT_3B) // set RF PLL N counter = r1 and IF PLL N counter in TRF2253 = r2 | |
96 | |
97 // time below are offset to when BULENA goes low | |
98 #define TRF_T13 ( 32 - DLT_1B) // disable PA_ON, BULON, TRF6053 | |
99 #define TRF_T12 ( 18 - DLT_1 ) // disable TSPACT01 | |
100 #define TRF_T11 ( 0 - DLT_1B) // disable BULENA | |
101 #define TRF_T10_1 (- 40 - DLT_1B) // ADC read | |
102 // burst data comes here | |
103 // time below are offset to when BULENA goes high | |
104 #define TRF_T10 (+ 15 - DLT_3) // enable PA_ON + 2*rfswitch | |
105 #define TRF_T9 (- 0 - DLT_1B) // enable BULENA | |
106 #define TRF_T8 (- 109 - DLT_2B) // power on transceiver | |
107 #define TRF_T7 (- 115 - DLT_1B) // disable BULCAL | |
108 #define TRF_T6 (- 230 - DLT_1B) // power up TRF2253 | |
109 #define TRF_T5 (- 233 - DLT_2B) // set TX band in TRF6053 | |
110 #define TRF_T3 (- 249 - DLT_3B) // set RF PLL N counter = t3 and IF PLL N counter in TRF2253 = t4 | |
111 #define TRF_T2 (- 260 - DLT_1B) // enable BULCAL | |
112 #define TRF_T1 (- 278 - DLT_1B) // enable BULON | |
113 | |
114 #if (BOARD == 7) || (BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45) | |
115 #define PA_ON 0x20 // act5 | |
116 #define TSPACT01 0x02 // act1 | |
117 | |
118 // RF signals connected to TSPACTX | |
119 #define RX900 0x04 // act10 | |
120 #define RX1800 0x08 // act11 | |
121 | |
122 #define TC1_DEVICE_ABB TC1_DEVICE0 | |
123 #define TC1_DEVICE_RF TC1_DEVICE1 | |
124 #define TC1_DEVICE_PLL TC1_DEVICE2 | |
125 #endif | |
126 | |
127 #if (BOARD == 6) | |
128 #define PA_ON 0x10 // act4 | |
129 | |
130 // RF signals connected to TSPACTX | |
131 #define RX900 0x08 // act11 => needs to be connected to act12 | |
132 #define RX1800 0x04 // act10 | |
133 | |
134 #define TC1_DEVICE_ABB TC1_DEVICE0 | |
135 #define TC1_DEVICE_PLL TC1_DEVICE1 | |
136 #define TC1_DEVICE_RF TC1_DEVICE2 | |
137 #endif | |
138 | |
139 #ifdef TPUDRV8_C | |
140 // Function prototypes | |
141 SYS_UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq); | |
142 | |
143 #endif |