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comparison gsm-fw/L1/tpudrv/tpudrv.c @ 576:660e83f13cab

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gsm-fw/L1/tpudrv: tpudrv.c and tpudrv61.[ch] imported from LoCosto source
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Mon, 11 Aug 2014 04:45:42 +0000
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children d70ebaea3003
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575:1d7a12925b8e 576:660e83f13cab
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 *
4 * Filename tpudrv.c
5 * Copyright 2003 (C) Texas Instruments
6 *
7 ************* Revision Controle System Header *************/
8 /*
9 * TPUDRV.C
10 *
11 * TPU driver for Pole Star
12 *
13 *
14 * Copyright (c) Texas Instruments 1996
15 *
16 */
17
18 #include "l1_macro.h"
19 #include "iq.h"
20 #include "l1_confg.h"
21 #include "l1_const.h"
22 #include "l1_types.h"
23
24 #if (AUDIO_TASK == 1)
25 #include "l1audio_const.h"
26 #include "l1audio_cust.h"
27 #include "l1audio_defty.h"
28 #endif
29
30 #if (L1_GTT == 1)
31 #include "l1gtt_const.h"
32 #include "l1gtt_defty.h"
33 #endif
34
35 #if (L1_MIDI == 1)
36 #include "l1midi_defty.h"
37 #endif
38
39 #include "sys_types.h"
40
41 #if TESTMODE
42 #include "l1tm_defty.h"
43 #endif
44
45 #if (L1_MP3 == 1)
46 #include "l1mp3_defty.h"
47 #endif
48
49 #if (L1_MIDI == 1)
50 #include "l1midi_defty.h"
51 #endif
52
53 #if (L1_AAC == 1)
54 #include "l1aac_defty.h"
55 #endif
56 #include "l1_defty.h"
57 #include "tpudrv.h"
58 #include "sys_types.h"
59 #include "clkm.h"
60 #include "l1_time.h"
61 #include "l1_varex.h"
62 #include "l1_trace.h"
63
64 #if (L1_MADC_ON == 1)
65 #if (RF_FAM == 61)
66 #include "drp_api.h"
67 #include "l1_rf61.h"
68 #include "drp_drive.h"
69 #include "tpudrv61.h"
70 extern T_DRP_REGS_STR *drp_regs;
71 #endif
72 #endif //L1_MADC_ON
73
74 /* RFTime environment */
75 #if defined (HOST_TEST)
76 #include "hostmacros.h"
77 #endif
78
79
80 /*
81 * VEGA and OMEGA receive windows - Defined in Customer-specific file
82 */
83
84 extern UWORD32 debug_tpu;
85
86 #if ( OP_WCP == 1 ) && ( OP_L1_STANDALONE != 1 )
87 // WCS Patch : ADC during RX or TX
88 extern inline void GC_SetAdcInfo(unsigned char bTxBasedAdc);
89 #endif
90
91 /*
92 * Global Variables
93 */
94 // GSM1.5 : TPU MEMORY is 16-bit instead of 32 in Gemini/Polxx
95 //------------------------------------------------------------
96 SYS_UWORD16 *TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
97
98
99 /*--------------------------------------------------------------*/
100 /* TPU_Reset : Reset the TPU */
101 /*--------------------------------------------------------------*/
102 /* Parameters : on/off(1/0) */
103 /* Return : none */
104 /* Functionality : ) Reset the TPU */
105 /*--------------------------------------------------------------*/
106 void TPU_Reset(SYS_UWORD16 on)
107 {
108 if (on)
109 {
110 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_RESET;
111 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
112 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
113 }
114 else
115 {
116 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_RESET;
117 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
118 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_RESET));
119 }
120 }
121
122 /*--------------------------------------------------------------*/
123 /* TSP_Reset : Reset the TSP */
124 /*--------------------------------------------------------------*/
125 /* Parameters : on/off(1/0) */
126 /* Return : none */
127 /* Functionality : ) Reset the TSP */
128 /*--------------------------------------------------------------*/
129 void TSP_Reset(SYS_UWORD16 on)
130 {
131 if (on)
132 {
133 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TSP_CTRL_RESET;
134 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
135 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
136 }
137 else
138 {
139 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TSP_CTRL_RESET;
140 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
141 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TSP_CTRL_RESET));
142 }
143 }
144
145 /*--------------------------------------------------------------*/
146 /* TPU_SPIReset : Reset the SPI of the TPU */
147 /*--------------------------------------------------------------*/
148 /* Parameters : on/off(1/0) */
149 /* Return : none */
150 /* Functionality : ) the SPI of the TPU */
151 /*--------------------------------------------------------------*/
152
153 void TPU_SPIReset(SYS_UWORD16 on)
154 {
155 if (on)
156 {
157 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_SPI_RST;
158 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
159 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
160 }
161 else
162 {
163 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_SPI_RST;
164 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
165 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_SPI_RST));
166 }
167 }
168
169 /*--------------------------------------------------------------*/
170 /* TPU_ClkEnable : */
171 /*--------------------------------------------------------------*/
172 /* Parameters : on/off(1/0) */
173 /* Return : none */
174 /* Functionality : Enable the TPU clock */
175 /*--------------------------------------------------------------*/
176
177 void TPU_ClkEnable(SYS_UWORD16 on)
178 {
179 if (on)
180 {
181 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_CLK_EN;
182 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
183 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
184 }
185 else
186 {
187 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_CLK_EN;
188 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
189 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_CLK_EN));
190 }
191 }
192
193 /*--------------------------------------------------------------*/
194 /* TPU_Frame_ItOn : */
195 /*--------------------------------------------------------------*/
196 /* Parameters : bit of it to enable */
197 /* Return : none */
198 /* Functionality : Enable frame it */
199 /*--------------------------------------------------------------*/
200
201 /*-----------------------------------------------------------*/
202 /* Warning read modify write access to TPU_INT_CTRL register */
203 /* may generate problems using Hyperion. */
204 /*-----------------------------------------------------------*/
205
206 void TPU_FrameItOn(SYS_UWORD16 it)
207 {
208 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) &= ~it;
209 }
210
211 void TPU_FrameItEnable(void)
212 {
213 #if W_A_ITFORCE
214 (*(volatile SYS_UWORD16 *)TPU_INT_CTRL) |= TPU_INT_ITD_F;
215 #else
216 // enable IT_DSP generation on next frame
217 // reset by DSP when IT occurs
218 (*(volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_D_ENBL;
219 // WA for read/modify/write access problem with REG_TPU_CTRL present on Ulysse/Samson/Calypso
220 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL));
221 #endif
222 }
223
224 /*--------------------------------------------------------------*/
225 /* TPU_check_IT_DSP : */
226 /*--------------------------------------------------------------*/
227 /* Parameters : none */
228 /* Return : none */
229 /* Functionality : check if an IT DSP still pending */
230 /*--------------------------------------------------------------*/
231 BOOL TPU_check_IT_DSP(void)
232 { // return TRUE if an IT DSP still pending.
233 return( (((*(volatile SYS_UWORD16 *) TPU_CTRL) & TPU_CTRL_D_ENBL) == TPU_CTRL_D_ENBL));
234 }
235
236 /*--------------------------------------------------------------*/
237 /* TPU_DisableAllIt : */
238 /*--------------------------------------------------------------*/
239 /* Parameters : none */
240 /* Return : none */
241 /* Functionality : Disabl all it */
242 /*--------------------------------------------------------------*/
243 void TPU_DisableAllIt()
244 {
245 * ((volatile SYS_UWORD16 *) TPU_INT_CTRL) |= TPU_INT_ITF_M | TPU_INT_ITP_M | TPU_INT_ITD_M;
246
247 }
248
249
250
251
252
253 /*
254 * TP_Program
255 *
256 * Write a null-terminated scenario into TPU memory at a given start address
257 * (Do not write terminating 0)
258 *
259 */
260 void *TP_Program(const SYS_UWORD16 *src)
261 {
262 /* Write TPU instructions until SLEEP */
263 while (*src)
264 {
265 *TP_Ptr++ = *src++;
266 }
267 #if (TOOL_CHOICE == 3) // 2.54 Migration
268 return((void *)NULL);
269 #endif // TOOL_CHOICE == 3
270 // return((void *)NULL);//ompas00090550
271
272 }
273
274
275
276 void TP_Reset(SYS_UWORD16 on)
277 {
278 if (on) {
279 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= (TPU_CTRL_RESET | TSP_CTRL_RESET);
280 while (!((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
281 }
282 else {
283 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~(TPU_CTRL_RESET | TSP_CTRL_RESET);
284 while (((*(volatile SYS_UWORD16 *) TPU_CTRL) & (TPU_CTRL_RESET | TSP_CTRL_RESET)));
285 }
286 }
287
288 void TP_Enable(SYS_UWORD16 on)
289 {
290 if(on)
291 {
292 * ((volatile SYS_UWORD16 *) TPU_CTRL) |= TPU_CTRL_T_ENBL;
293
294 // Some time shall be wait before leaving the function to ensure that bit has been taken
295 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
296 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
297 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
298 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
299 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
300 }
301 else
302 {
303 * ((volatile SYS_UWORD16 *) TPU_CTRL) &= ~TPU_CTRL_T_ENBL;
304 // Some time shall be wait before leaving the function to ensure that bit has been taken
305 // in account by the TPU. A while loop such as in function TP_reset can't be used as the
306 // ARM can be interrupted within this loop and in that case the pulse will be missed (CQ20781).
307 // The bit is updated in the worst case 24 cycles of 13MHz later it as been written by the MCU.
308 // 24 ticks of 13MHz = 1.84us. Lets take 3us to keep some margin.
309 wait_ARM_cycles(convert_nanosec_to_cycles(3000)); // wait 3us
310 }
311 }
312
313
314 /*-----------------------------------------------------------------------*/
315 /* Function name: TPU_wait_idle */
316 /*-----------------------------------------------------------------------*/
317 /* */
318 /* Parameters: None */
319 /* */
320 /* Return: None */
321 /* */
322 /*-----------------------------------------------------------------------*/
323 /* Description: Wait until TPU scenario execution is complete */
324 /* */
325 /*-----------------------------------------------------------------------*/
326 void TPU_wait_idle(void)
327 {
328 while( ((*(volatile SYS_UWORD16 *) (TPU_CTRL)) & TPU_CTRL_TPU_IDLE) == TPU_CTRL_TPU_IDLE)
329 {
330 wait_ARM_cycles(convert_nanosec_to_cycles(3000));
331 }
332 }
333
334
335 /*
336 * l1dmacro_idle
337 *
338 * Write SLEEP instruction, start TPU and reset pointer
339 */
340 void l1dmacro_idle (void)
341 {
342 *TP_Ptr++ = TPU_SLEEP;
343
344 /* start TPU */
345 TP_Ptr = (SYS_UWORD16 *) TPU_RAM;
346 TP_Enable(1);
347 }
348
349 /*
350 * l1dmacro_offset
351 *
352 * Set OFFSET register
353 *
354 */
355 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time)
356 {
357 // WARNING: 'relative time' and 'offset_value' must always be comprised
358 // between 0 and TPU_CLOCK_RANGE !!!
359
360 if (relative_time != IMM) // IMM indicates to set directly without AT
361 {
362 *TP_Ptr++ = TPU_FAT(relative_time);
363 }
364 *TP_Ptr++ = TPU_OFFSET(offset_value);
365 }
366
367 /*
368 * l1dmacro_synchro
369 *
370 * Set synchro register
371 */
372 void l1dmacro_synchro (UWORD32 when, UWORD32 value)
373 {
374 // WARNING: 'when' must always be comprised between 0 and TPU_CLOCK_RANGE !!!
375 #if (TRACE_TYPE!=0) && (TRACE_TYPE!=5)
376 trace_fct(CST_L1DMACRO_SYNCHRO, 1);//omaps00090550
377 #endif
378
379 if (value != IMM) // IMM indicates to set directly without AT
380 {
381 *TP_Ptr++ = TPU_FAT(when);
382 }
383
384 *TP_Ptr++ = TPU_SYNC(value);
385 l1s.tpu_offset_hw = value; // memorize the offset set into the TPU.
386 }
387
388
389 /*
390 * l1dmacro_adc_read
391 *
392 */
393 void l1dmacro_adc_read_rx(void)
394 {
395
396 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
397 // TSP needs to be configured in order to send serially to Omega
398
399 // *TP_Ptr++ = TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE); // Clock configuration
400 *TP_Ptr++ = TPU_WAIT (5);
401 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
402 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,STARTADC); // Load data to send
403 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
404 *TP_Ptr++ = TPU_WAIT (5);
405 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1,0x00);
406 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
407
408 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
409 #if (GSM_IDLE_RAM == 0)
410 l1_trace_ADC(0);
411 #else
412 l1_trace_ADC_intram(0);
413 #endif
414 #endif
415 #endif
416
417 #if (L1_MADC_ON == 1)
418 #if (ANLG_FAM == 11)
419
420 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
421 #if (GSM_IDLE_RAM == 0)
422 l1_trace_ADC(0);
423 #else
424 l1_trace_ADC_intram(0);
425 #endif
426 #endif
427 #endif
428
429 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
430 // WCS patch: ADC during RX
431 GC_SetAdcInfo(0);
432 #endif
433 #endif
434 }
435
436
437 #if (CODE_VERSION != SIMULATION)
438 #if (L1_MADC_ON ==1)
439 /*
440 * l1dmacro_adc_read_rx_cs_mode0
441 *
442 * Purpose:
443 * ======
444 * MADC is not enabled during CS_MODE0 periodically. MADC is enabled in CS_MODE0
445 * when Layer 1 receives MPHC_RXLEV_REQ from L23. However in CS_MODE0, MPHC_RXLEV_REQ
446 * is not received periodically. In case network is not found, the period between 2 MPHC_RXLEV_REQ
447 * increases and can be as high as 360 seconds (Maximum Value)
448 * This can result in battery related issues like phone powering off without MMI indication.
449 */
450
451
452 void l1dmacro_adc_read_rx_cs_mode0(void)
453 {
454 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,START_ADC);
455 *TP_Ptr++ = TPU_WAIT (2);
456 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,0);
457
458 #if (L1_MADC_ON == 1)
459 #if (ANLG_FAM == 11)
460
461 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
462 #if (GSM_IDLE_RAM == 0)
463 l1_trace_ADC(0);
464 #else
465 l1_trace_ADC_intram(0);
466 #endif
467 #endif
468 #endif
469
470 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
471 // WCS patch: ADC during RX
472 GC_SetAdcInfo(0);
473 #endif
474 #endif
475 }
476
477
478 #endif //If MADC is enabled
479 #endif //If Not Simulation
480
481 /*
482 * l1dmacro_adc_read_tx
483 *
484 */
485
486
487 #if (ANLG_FAM != 11)
488 void l1dmacro_adc_read_tx(UWORD32 when)
489 #else
490 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
491 #endif
492 {
493
494 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
495
496 *TP_Ptr++ = TPU_FAT (when);
497 *TP_Ptr++ = TPU_MOVE (TSP_CTRL1,6); // Device and Nb of bits configuration
498 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, STARTADC|BULON|BULENA); // Load data to send
499 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Start serialization command and adc conversion
500 *TP_Ptr++ = TPU_WAIT (5);
501 *TP_Ptr++ = TPU_MOVE (TSP_TX_REG_1, BULON|BULENA);
502 *TP_Ptr++ = TPU_MOVE (TSP_CTRL2, TC2_WR); // Reset startadc pulse
503
504 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
505 l1_trace_ADC(1);
506 #endif
507 #endif
508
509 #if (L1_MADC_ON == 1)
510 #if (ANLG_FAM == 11)
511 *TP_Ptr++ = TPU_FAT (when);
512 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
513 *TP_Ptr++ = TPU_WAIT (2);
514 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
515
516 #if 1 // TEMP MEASUREMENT - uncomment and test after MADC
517 #if (RF_FAM == 61)
518 *TP_Ptr++ = TPU_MOVE(OCP_DATA_MSB, ((START_SCRIPT(DRP_TEMP_CONV))>>8) & 0xFF); \
519 *TP_Ptr++ = TPU_MOVE(OCP_DATA_LSB, (START_SCRIPT(DRP_TEMP_CONV)) & 0xFF); \
520 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_MSB, (((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)>>8) & 0xFF)); \
521 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_LSB, ((UWORD16)( ((UWORD32)(&drp_regs->SCRIPT_STARTL))&0xFFFF)) & 0xFF); \
522 *TP_Ptr++ = TPU_MOVE(OCP_ADDRESS_START, 0x01); \
523 //TEMP_MEAS: Call TEMP Conv Script in DRP
524 //MOVE_REG_TSP_TO_RF(START_SCRIPT(DRP_TEMP_CONV),(UWORD16)(&drp_regs->SCRIPT_STARTL));
525 #endif
526
527 #endif
528
529 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
530 l1_trace_ADC(1);
531 #endif
532
533 #endif
534 #endif //L1_MADC_ON
535
536 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
537 // WCS patch: ADC during TX
538 GC_SetAdcInfo(1);
539 #endif
540
541
542 }
543
544
545 /*
546 #if (RF_FAM == 61)
547
548 void l1dmacro_adc_read_tx(UWORD32 when, UWORD8 tx_up_state)
549 {
550 int i;
551
552 *TP_Ptr++ = TPU_FAT (when);
553 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state | START_ADC);
554 *TP_Ptr++ = TPU_WAIT (2);
555 *TP_Ptr++ = TPU_MOVE(REG_SPI_ACT_U,tx_up_state);
556
557 #if (TRACE_TYPE==1)||(TRACE_TYPE ==4)
558 l1_trace_ADC(1);
559 #endif
560
561
562 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
563 // WCS patch: ADC during TX
564 GC_SetAdcInfo(1);
565 #endif
566 }
567
568 #endif
569 */
570
571 /*
572 * l1dmacro_set_frame_it
573 *
574 */
575 void l1dmacro_set_frame_it(void)
576 {
577 TPU_FrameItEnable();
578 }