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comparison nuc-fw/nucleus/sd_defs.h @ 79:947b1f473960

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beginning of nuc-fw
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 11 Aug 2013 07:17:25 +0000
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78:2c266d4339ff 79:947b1f473960
1 /*************************************************************************
2 *
3 * Copyright Mentor Graphics Corporation 2002
4 * All Rights Reserved.
5 *
6 * THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION WHICH IS
7 * THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS AND IS
8 * SUBJECT TO LICENSE TERMS.
9 *
10 *************************************************************************/
11
12 /*************************************************************************
13 *
14 * FILE NAME VERSION
15 *
16 * sd_defs.h Nucleus PLUS\ARM925\Code Composer 1.14.1
17 *
18 * COMPONENT
19 *
20 * SD - Serial Driver
21 *
22 * DESCRIPTION
23 *
24 * This file contains constant definitions and function macros
25 * for the Serial Driver module.
26 *
27 * DATA STRUCTURES
28 *
29 * SD_PORT : Structure to keep all needed info. about a port.
30 *
31 * DEPENDENCIES
32 *
33 * none
34 *
35 *
36 *************************************************************************/
37 #ifndef SD_DEFS_H
38 #define SD_DEFS_H
39
40 /**************** User configurable section *************************/
41
42 /*
43 * The OMAP1510 version of this code found in XVilka's original
44 * code drop supported two UARTs numbered 1 and 2.
45 * In this proof-of-concept Calypso version this numbering
46 * has been retained, even though all other Calypso software
47 * I know of uses 0 and 1.
48 * The FreeNucleus UART numbers have been mapped as follows:
49 * 1 = MODEM, 2 = IrDA
50 */
51
52 /* The base addresses for the seperate UART registers. */
53 #define SD_UART_MODEM_BASE 0xFFFF5800
54 #define SD_UART_IRDA_BASE 0xFFFF5000
55
56 /* Macros for specifying which UART to use. */
57 #define SD_UART1 1
58 #define SD_UART2 2
59
60 #define SD_UART_MODEM 1
61 #define SD_UART_IRDA 2
62
63 #define SD_MAX_UARTS 2
64
65 /* These use specific type names, putting the register name
66 in the macro, because these macros are used by port specific
67 sections of code and will most likely have different names
68 on other UARTS. */
69 /*************************************/
70 /* Receive Holding Register - RHR (R)*/
71 /*************************************/
72 #define RHR_OFFSET 0x00
73
74 /**************************************/
75 /* Transmit Holding Register - THR (W)*/
76 /**************************************/
77 #define THR_OFFSET 0x00
78
79 /****************************************/
80 /* Interrupt Enable Register - IER (R/W)*/
81 /****************************************/
82 #define IER_OFFSET 0x01
83 #define IER_RX_HOLDING_REG 0x01 /* bit 0 - Recieve Holding Register Interrupt
84 - Enabled When Set */
85 #define IER_TX_HOLDING_REG 0x02 /* bit 1 - Transmit Holding Register Interrupt
86 - Enabled When Set */
87 #define IER_RX_LINE_STATUS 0x04 /* bit 2 - recieve Line Status Interrupt
88 - Enabled When Set */
89 #define IER_MODEM_STATUS 0x08 /* bit 3 - Modem Status Interrupt
90 - Enabled When Set */
91
92
93 /************************************/
94 /* FIFO Control Register - FCR (W) */
95 /************************************/
96 #define FCR_OFFSET 0x02
97 #define FCR_FIFO_ENABLED 0x01 /* bit 0 - Enabled When Set */
98 #define FCR_RCVR_TRIG_LEVEL 0x00 /* bit 6:bit 7 - 8 Bytes Trigger Level */
99 #define FCR_FIFO_RESET 0x06 /* bit 1-2 - TX/RX FIFO Reset When Set */
100
101 /************************************************/
102 /* Interrupt Identification Register - IIR (IIR)*/
103 /************************************************/
104 #define IIR_OFFSET 0x02
105 #define IIR_TYPE_MASK 0x0000003E /* bit 5:bit 1 */
106 #define IIR_PENDING 0x00000001 /* ISR pending bit - 0=pending, 1=not pending */
107 #define IIR_RX_TIMEOUT 0x0000000C /* 1 1 0 - RX time out Priority 2 */
108 #define IIR_RX_RDY 0x00000004 /* 0 1 0 - Received Data Ready Priority 2 */
109 #define IIR_TX_RDY 0x00000002 /* 0 0 1 - Transmitter Holding Reg Empty Priority 3 */
110 #define IIR_RX_LINE_STAT 0x00000006 /* 0 1 1 - Receive Line Status Priority 1 */
111
112 /**************************************/
113 /* Latch Control Register - LCR (R/W)*/
114 /**************************************/
115 #define LCR_OFFSET 0x03
116 #define LCR_5_BIT_WORD 0x00 /* 0 0 - 5 Bit Word */
117 #define LCR_6_BIT_WORD 0x01 /* 0 1 - 6 Bit Word */
118 #define LCR_7_BIT_WORD 0x02 /* 1 0 - 7 Bit Word */
119 #define LCR_8_BIT_WORD 0x03 /* 1 1 - 8 Bit Word */
120
121 #define LCR_STOP_BIT_1 0x00 /* 1 stop bit */
122 #define LCR_STOP_BIT_2 0x04 /* 2 stop bit */
123
124 #define LCR_PARITY_ENABLE 0x08 /* bit 3 - Enable Parity Bit Generation and Check
125 - Enabled When Set */
126 #define LCR_PARITY_DISABLE 0x00 /* bit 3 - Enable Parity Bit Generation and Check
127 - Enabled When Set */
128 #define LCR_PARITY_EVEN 0x10 /* bit 4 - Odd/Even Parity Generation and Check
129 - Even When Set */
130 #define LCR_PARITY_ODD 0x00 /* bit 4 - Odd/Even Parity Generation and Check
131 - Odd When Set */
132 #define LCR_BREAK_SET 0x40 /* bit 6 - Force Break Control ( Tx o/p low)
133 - Forced When Set */
134 #define LCR_NO_BREAK 0x00 /* bit 6 - Normal operating conditions */
135 #define LCR_DIV_EN 0x80 /* Enable access to DLL and DLH */
136
137 /*************************************/
138 /* Modem Control Register - MCR (R/W)*/
139 /*************************************/
140 #define MCR_OFFSET 0x04
141
142 #define MCR_DTR_LOW 0x01 /* bit 0 - Set DCD Signal Low/High - DCD Low when Set */
143 #define MCR_RTS_LOW 0x02 /* bit 1 - Set RTS Signal Low/High - RTS Low when Set */
144 #define MCR_NORMAL_MODE 0x00 /* bit 4 - normal operating mode */
145 #define MCR_LOOP_BACK 0x10 /* bit 4 - enable loopback mode */
146 #define MCR_TCR_TLR 0x40 /* bit 6 - enable access to TCR and TLR */
147 #define MCR_CLKSEL 0x80 /* bit 7 - enable clk/4 */
148 #define MCR_Not_Used 0x0C /* bit 2,bit 3 - not used */
149
150
151 /* The Following Registers are Status Registers which Report conditions within the */
152 /* UART/PPP during operation. The defined values are masks to ensure that the register*/
153 /* flags are correctly accessed */
154
155 /*********************************/
156 /* Line Status Register - LSR (R)*/
157 /*********************************/
158 #define LSR_OFFSET 0x05
159 #define LSR_RX_DATA_READY 0x01 /* bit 0 - Data Received and Saved in Holding Reg
160 - Set when Valid */
161 #define LSR_OVERRUN_ERROR 0x02 /* bit 1 - Overrun Error Occured
162 - Set When Valid */
163 #define LSR_PARITY_ERROR 0x04 /* bit 2 - Parity Error Occured
164 - Set When Valid */
165 #define LSR_FRAMING_ERROR 0x08 /* bit 3 - Framing Error Occured
166 - Set When Valid */
167 #define LSR_BREAK_ERROR 0x10 /* bit 4 - Break Error Occured
168 - Set When Valid */
169 #define LSR_TX_HOLD_EMPTY 0x20 /* bit 5 - Tx Holding Register is empty and ready
170 - Set When Valid */
171 #define LSR_TX_HOLD_FULL 0x00 /* bit 5 - Tx Holding Register is Full */
172
173 #define LSR_TX_EMPTY 0x40 /* bit 6 - 1= Tx Holding and shift registers are empty */
174 #define LSR_TX_FULL 0x00 /* bit 6 - 0= Tx Holding and shift registers are full */
175
176 #define LSR_FIFO_ERROR 0x80 /* bit 7 - At Least one of b4 - b2 has occurred
177 - Set When Valid */
178
179 /**********************************/
180 /* Modem Status Register - MSR (R)*/
181 /**********************************/
182 #define MSR_OFFSET 0x06
183
184 /******************************************/
185 /* Supplementary Status Register - SSR (R)*/
186 /******************************************/
187 #define SSR_OFFSET 0x11 /* Supplementary Status Reg Offset */
188 #define SSR_TX_FIFO_FULL 0x01 /* bit 0 - Tx FIFO full - Set when full */
189
190 /***************************************/
191 /* Mode Definition Register - MDR (R/W)*/
192 /***************************************/
193 #define MDR_OFFSET 0x08
194 #define MDR_UART_MODE 0x00 /* bit 2:bit 0 - 0 0 0 - Uart Mode */
195 #define MDR_AUTO_MODE 0x02 /* bit 2:bit 0 - 0 1 0 - AutoBaud Mode */
196 #define MDR_RESET_MODE 0x07 /* bit 2:bit 0 - 1 1 1 - Reset Mode */
197
198 /***********************************************/
199 /* Divisor for baud-rate generation - DLH (R/W)*/
200 /***********************************************/
201 #define DLH_OFFSET 0x01
202
203 /***********************************************/
204 /* Divisor for baud-rate generation - DLL (R/W)*/
205 /***********************************************/
206 #define DLL_OFFSET 0x00
207
208
209 /* These use generic type names, leaving off the register name
210 in the macro, because they are used by generic sections of
211 code which will not require changes for other UARTS. Only the
212 bits these correspond to should change. */
213
214 /* UART Line Control Register Bits */
215 #define SD_PARITY_NONE LCR_PARITY_DISABLE
216 #define SD_PARITY_EVEN LCR_PARITY_EVEN
217 #define SD_PARITY_ODD LCR_PARITY_ODD
218
219 #define SD_DATA_BITS_5 LCR_5_BIT_WORD
220 #define SD_DATA_BITS_6 LCR_6_BIT_WORD
221 #define SD_DATA_BITS_7 LCR_7_BIT_WORD
222 #define SD_DATA_BITS_8 LCR_8_BIT_WORD
223
224 #define SD_STOP_BITS_1 LCR_STOP_BIT_1
225 #define SD_STOP_BITS_2 LCR_STOP_BIT_2
226
227 #define SD_MODE_NORMAL MCR_NORMAL_MODE
228 #define SD_MODE_AUTO_ECHO MCR_NOT_USED
229 #define SD_MODE_LOCAL_LOOP MCR_LOOP_BACK
230 #define SD_MODE_REMOTE_LOOP MCR_NOT_USED
231
232 /* Define default Serial Driver settings for this board */
233 #define DEFAULT_UART_PORT SD_UART_IRDA
234 #define DEFAULT_PPP_BAUD 57600
235 #define DEFAULT_UART_BAUD 115200
236 #define DEFAULT_UART_DATA DATA_BITS_8
237 #define DEFAULT_UART_STOP STOP_BITS_1
238 #define DEFAULT_UART_PARITY PARITY_NONE
239 #define DEFAULT_UART_MODE MODE_NORMAL
240 #define DEFAULT_UART_BUFFER 100
241
242 /* Define data structures for management of a serial port. */
243
244 typedef struct SD_INIT_STRUCT
245 {
246 UINT32 data_mode;
247 UINT32 base_address;
248
249 /* The following elements should generic accross other
250 platforms. */
251 NU_SEMAPHORE *sd_semaphore;
252 UINT32 com_port;
253 UINT32 data_bits;
254 UINT32 stop_bits;
255 UINT32 parity;
256 UINT32 baud_rate;
257 UINT32 vector;
258 UINT32 driver_options;
259 UINT32 sd_buffer_size;
260
261 UINT32 parity_errors;
262 UINT32 frame_errors;
263 UINT32 overrun_errors;
264 UINT32 busy_errors;
265 UINT32 general_errors;
266
267 CHAR *rx_buffer;
268 INT rx_buffer_read;
269 INT rx_buffer_write;
270 volatile INT rx_buffer_status;
271
272 /* All of the following elements are required by PPP, do not modify. */
273 UINT32 communication_mode;
274 CHAR *tx_buffer;
275 INT tx_buffer_read;
276 INT tx_buffer_write;
277 volatile INT tx_buffer_status;
278
279 } SD_PORT;
280
281 /* Defines to be used by application */
282 #define MODE_NORMAL SD_MODE_NORMAL
283 #define MODE_AUTO_ECHO SD_MODE_AUTO_ECHO
284 #define MODE_LOCAL_LOOP SD_MODE_LOCAL_LOOP
285 #define MODE_REMOTE_LOOP SD_MODE_REMOTE_LOOP
286
287 #define STOP_BITS_1 SD_STOP_BITS_1
288 #define STOP_BITS_2 SD_STOP_BITS_2
289
290 #define UART1 SD_UART1
291 #define UART2 SD_UART2
292
293 /* Defines to determine communication mode */
294 #define SERIAL_MODE 0
295 #define SERIAL_MOUSE 3
296 /* MDM_NETWORK and MDM_TERMINAL do not need to be defined here
297 since they are defined in PPP. */
298
299 /***********************************************************************
300 Note: everything below should be genric.
301 */
302
303 #define NU_SERIAL_PORT SD_PORT
304 #define PARITY_NONE SD_PARITY_NONE
305 #define PARITY_EVEN SD_PARITY_EVEN
306 #define PARITY_ODD SD_PARITY_ODD
307
308 #define DATA_BITS_6 SD_DATA_BITS_6
309 #define DATA_BITS_7 SD_DATA_BITS_7
310 #define DATA_BITS_8 SD_DATA_BITS_8
311
312 #define NU_SD_Put_Char SDC_Put_Char
313 #define NU_SD_Get_Char SDC_Get_Char
314 #define NU_SD_Put_String SDC_Put_String
315 #define NU_SD_Init_Port SDC_Init_Port
316 #define NU_SD_Data_Ready SDC_Data_Ready
317
318 #define NU_UART_SUCCESS 0
319 #define NU_INVALID_PARITY -1
320 #define NU_INVALID_DATA_BITS -2
321 #define NU_INVALID_STOP_BITS -3
322 #define NU_INVALID_BAUD -4
323 #define NU_INVALID_COM_PORT -5
324 #define NU_INVALID_DATA_MODE -6
325 #define NU_UART_LIST_FULL -7
326 #define NU_INVALID_MOUSE_MODE -8
327
328 #define NU_BUFFER_FULL 1
329 #define NU_BUFFER_DATA 2
330 #define NU_BUFFER_EMPTY 3
331
332 /* Deifine IO macros. */
333
334 /* 8 bit access */
335 #define SD_OUTBYTE(reg, data) ( (*( (volatile UINT8 *) (reg) ) ) = (UINT8) (data) )
336
337 #define SD_INBYTE(reg) ( *( (volatile UINT8 *) (reg) ) )
338
339 /* 16 bit access */
340 #define SD_OUTWORD(reg, data) ( (*( (volatile UINT16 *) (reg) ) ) = (data) )
341
342 #define SD_INWORD(reg) ( *( (volatile UINT16 *) (reg) ) )
343
344 /* 32 bit access */
345 #define SD_OUTDWORD(reg, data) ( (*( (volatile UINT32 *) (reg) ) ) = (data) )
346
347 #define SD_INDWORD(reg) ( *( (volatile UINT32 *) (reg) ) )
348
349 /*Macro used for converting URT to SD_PORT. This is for PPP serial driver
350 backwards compatability. */
351 #define URT_LAYER SD_PORT
352
353 #define URT_TX_BUFFER_SIZE uart->sd_buffer_size
354 #define URT_Get_Char SDC_Get_Char
355 #define URT_Put_Char SDC_Put_Char
356 #define URT_Reset SDC_Reset
357 #define URT_Change_Communication_Mode SDC_Change_Communication_Mode
358 #define URT_Carrier SDC_Carrier
359
360
361 #endif /* ifndef SD_DEFS_H */