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comparison gsm-fw/L1/cfile/l1_drive.c @ 544:96a96ec34139

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gsm-fw/L1/cfile: initial import from LoCosto source
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 03 Aug 2014 06:06:45 +0000
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children 67ab5f240b7d
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543:2dccd2b4e5a2 544:96a96ec34139
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_DRIVE.C
4 *
5 * Filename l1_drive.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_DRIVE_C
11
12
13 #include "l1_confg.h"
14
15
16 #if (RF_FAM == 61)
17 #include "apc.h"
18 #endif
19
20 #if ((W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)&&(W_A_DSP_PR20037 == 1))
21 #include "nucleus.h"
22 #endif
23 #include "l1_macro.h"
24 #if (CODE_VERSION == SIMULATION)
25 #include <string.h>
26 #include "l1_types.h"
27 #include "sys_types.h"
28 #include "l1_const.h"
29 #include "l1_time.h"
30 #if TESTMODE
31 #include "l1tm_defty.h"
32 #endif
33 #if (AUDIO_TASK == 1)
34 #include "l1audio_const.h"
35 #include "l1audio_cust.h"
36 #include "l1audio_defty.h"
37 #endif
38 #if (L1_GTT == 1)
39 #include "l1gtt_const.h"
40 #include "l1gtt_defty.h"
41 #endif
42 #if (L1_MP3 == 1)
43 #include "l1mp3_defty.h"
44 #endif
45 #if (L1_MIDI == 1)
46 #include "l1midi_defty.h"
47 #endif
48 //ADDED FOR AAC
49 #if (L1_AAC == 1)
50 #include "l1aac_defty.h"
51 #endif
52 #include "l1_defty.h"
53 #include "l1_varex.h"
54 #include "cust_os.h"
55 #include "l1_msgty.h"
56 #if TESTMODE
57 #include "l1tm_varex.h"
58 #endif
59 #if L2_L3_SIMUL
60 #include "hw_debug.h"
61 #endif
62
63 #if L1_GPRS
64 #include "l1p_cons.h"
65 #include "l1p_msgt.h"
66 #include "l1p_deft.h"
67 #include "l1p_vare.h"
68 #include "l1p_sign.h"
69 #endif
70
71 #include <stdio.h>
72 #include "sim_cfg.h"
73 #include "sim_cons.h"
74 #include "sim_def.h"
75 #include "sim_var.h"
76
77 #include "l1_ctl.h"
78
79 #else
80
81 #include <string.h>
82 #include "l1_types.h"
83 #include "sys_types.h"
84 #include "l1_const.h"
85 #include "l1_time.h"
86 #if TESTMODE
87 #include "l1tm_defty.h"
88 #endif
89 #if (AUDIO_TASK == 1)
90 #include "l1audio_const.h"
91 #include "l1audio_cust.h"
92 #include "l1audio_defty.h"
93 #endif
94 #if (L1_GTT == 1)
95 #include "l1gtt_const.h"
96 #include "l1gtt_defty.h"
97 #endif
98 #if (L1_MP3 == 1)
99 #include "l1mp3_defty.h"
100 #endif
101 #if (L1_MIDI == 1)
102 #include "l1midi_defty.h"
103 #endif
104 //ADDED FOR AAC
105 #if (L1_AAC == 1)
106 #include "l1aac_defty.h"
107 #endif
108 #include "l1_defty.h"
109 #include "l1_varex.h"
110 #include "cust_os.h"
111 #include "l1_msgty.h"
112 #if TESTMODE
113 #include "l1tm_varex.h"
114 #endif
115 #if L2_L3_SIMUL
116 #include "hw_debug.h"
117 #endif
118 #include "tpudrv.h"
119
120 #if L1_GPRS
121 #include "l1p_cons.h"
122 #include "l1p_msgt.h"
123 #include "l1p_deft.h"
124 #include "l1p_vare.h"
125 #include "l1p_sign.h"
126 #endif
127
128 #include "l1_ctl.h"
129
130 #endif
131
132 #if (RF_FAM == 61)
133 #include "tpudrv61.h"
134 #endif
135
136
137
138 /*-------------------------------------------------------*/
139 /* Prototypes of external functions used in this file. */
140 /*-------------------------------------------------------*/
141 void l1dmacro_reset_hw (UWORD32 servingCellOffset);
142 void l1dmacro_idle (void);
143 void l1dmacro_rx_synth (UWORD16 arfcn);
144 void l1dmacro_tx_synth (UWORD16 arfcn);
145 void l1dmacro_agc (UWORD16 arfcn,WORD8 gain, UWORD8 lna
146 #if (RF_FAM == 61)
147 , UWORD8 if_ctl
148 #endif
149 );
150 void l1dmacro_afc (UWORD16 afc_value, UWORD8 win_id);
151 #if (CODE_VERSION == SIMULATION)
152 void l1dmacro_rx_ms (UWORD16 arfcn, BOOL rxnb_select);
153 #else
154 #if (L1_MADC_ON == 1)
155 #if (RF_FAM == 61)
156 void l1dmacro_rx_ms (SYS_UWORD16 arfcn,UWORD8 adc_active);
157 #endif
158 #else
159 void l1dmacro_rx_ms (SYS_UWORD16 arfcn);
160 #endif
161 #endif
162
163 #if (L1_MADC_ON == 1)
164 #if (RF_FAM == 61)
165 void l1dmacro_rx_fb (UWORD16 arfcn , UWORD8 adc_active);
166 void l1dmacro_rx_fb26 (UWORD16 arfcn, UWORD8 adc_active);
167 #endif
168 #else
169 void l1dmacro_rx_fb (UWORD16 arfcn);
170 void l1dmacro_rx_fb26 (UWORD16 arfcn);
171 #endif
172 void l1dmacro_offset (UWORD32 offset_value, WORD32 relative_time);
173 void l1dmacro_synchro (UWORD32 when, UWORD32 value);
174 #if (L1_MADC_ON == 1)
175 #if (RF_FAM == 61)
176 void l1dmacro_rx_sb (UWORD16 arfcn, UWORD8 adc_active);
177 void l1dmacro_rx_nb (UWORD16 arfcn, UWORD8 adc_active, UWORD8 csf_filter_choice
178 #if (NEW_SNR_THRESHOLD == 1)
179 ,UWORD8 saic_flag
180 #endif /* NEW_SNR_THRESHOLD*/
181 );
182 #endif
183 #if ((REL99 == 1) && (FF_BHO == 1))
184 #if (L1_MADC_ON == 1)
185 void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq,UWORD8 adc_active);
186 #else
187 void l1dmacro_rx_fbsb (SYS_UWORD16 radio_freq);
188 #endif
189 #endif//#if ((REL99 == 1) && (FF_BHO == 1))
190 #else
191 void l1dmacro_rx_sb (UWORD16 arfcn);
192 void l1dmacro_rx_nb (UWORD16 arfcn, UWORD8 csf_filter_choice);
193 #endif
194 void l1dmacro_tx_nb (UWORD16 arfcn, UWORD8 txpwr, UWORD8 adc_active);
195 void l1dmacro_tx_ra (UWORD16 arfcn, UWORD8 txpwr, UWORD8 adc_active);
196 void l1dmacro_adc_read_rx (void);
197
198 void Cust_get_ramp_tab(API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq);
199 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
200 UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq
201 #if(REL99 && FF_PRF)
202 ,UWORD8 number_uplink_timeslot
203 #endif
204 );
205 #endif
206
207 #if L1_GPRS
208 void l1ps_reset_db_mcu_to_dsp(T_DB_MCU_TO_DSP_GPRS *page_ptr);
209 #endif
210
211 /*-------------------------------------------------------*/
212 /* l1ddsp_load_info() */
213 /*-------------------------------------------------------*/
214 /* Parameters : */
215 /* Return : */
216 /* Functionality : */
217 /*-------------------------------------------------------*/
218 void l1ddsp_load_info(UWORD32 task, API *info_ptr, UWORD8 *data)
219 {
220 if(task == RACH_DSP_TASK)
221 // RACH info. format is only 2 words...
222 {
223 info_ptr[0] = ((API)(data[0])) | ((API)(data[1])<<8);
224 }
225 else
226 // Fill mcu-dsp comm. buffer.
227 {
228 UWORD8 i,j;
229
230 // Fill data block Header...
231 info_ptr[0] = (1 << B_BLUD); // 1st word: Set B_BLU bit.
232 info_ptr[1] = 0; // 2nd word: cleared.
233 info_ptr[2] = 0; // 3rd word: cleared.
234
235 if((info_ptr == l1s_dsp_com.dsp_ndb_ptr->a_du_0) ||
236 (info_ptr == l1s_dsp_com.dsp_ndb_ptr->a_du_1))
237 // DATA traffic buffers: size of buffer is 260 bit -> 17 words but DATA traffic uses
238 // only a max of 240 bit (30 bytes) -> 15 words.
239 {
240 for (i=0, j=(3+0); j<(3+15); j++)
241 {
242 info_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8);
243 i += 2;
244 }
245 #if (TRACE_TYPE==3)
246 if (l1_stats.type == PLAY_UL)
247 {
248 for (i=0, j=(3+0); j<(3+17); j++)
249 {
250 info_ptr[j] = ((API)(data[i])) |
251 ((API)(data[i]) << 8);
252 i ++;
253 }
254 }
255 #endif
256 }
257 else
258 // Data block for control purpose is 184 bit length: 23 bytes: 12 words (16 bit/word).
259 {
260 // Copy first 22 bytes in the first 11 words after header.
261 for (i=0, j=(3+0); j<(3+11); j++)
262 {
263 info_ptr[j] = ((API)(data[i])) | ((API)(data[i+1]) << 8);
264 i += 2;
265 }
266
267 // Copy last UWORD8 (23rd) in the 12th word after header.
268 info_ptr[14] = data[22];
269 }
270 }
271 }
272
273 /*-------------------------------------------------------*/
274 /* l1ddsp_load_monit_task() */
275 /*-------------------------------------------------------*/
276 /* Parameters : */
277 /* Return : */
278 /* Functionality : */
279 /*-------------------------------------------------------*/
280 void l1ddsp_load_monit_task(API monit_task, API fb_mode)
281 {
282 l1s_dsp_com.dsp_db_w_ptr->d_task_md = monit_task; // Write number of measurements
283
284 if(l1a_l1s_com.mode == CS_MODE)
285 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = fb_mode; // Write FB detection algo. mode.
286 else
287 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = 1;
288 }
289
290
291 /* --------------------------------------------------- */
292
293 /* Locosto Changes....*/
294
295 // Parameters: UWORD16 afcval
296 // Return :Void
297 //Functionality: TPU to accept the afcvalue from the MCU and copy it
298 //to the mem_xtal before triggering of AFC Script in DRP
299
300 #if(RF_FAM == 61)
301 void l1dtpu_load_afc(UWORD16 afc)
302 {
303 l1dmacro_afc(afc, 0);
304 }
305
306 /* --------------------------------------------------- */
307
308 /* Locosto Changes....*/
309
310 /* Parameters: API dco_algo_ctl_sb */
311 /* Functionality: Loads the API d_dco_ctl_algo_sb in the API
312 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
313
314 /* --------------------------------------------------- */
315
316 void l1ddsp_load_dco_ctl_algo_sb (UWORD16 dco_ctl_algo)
317 {
318 #if (DSP == 38) || (DSP == 39)
319 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_sb = (API) dco_ctl_algo;
320 #endif
321 }
322
323 /* --------------------------------------------------- */
324
325 /* Locosto Changes....*/
326
327 /* Parameters: API dco_algo_ctl_nb */
328 /* Functionality: Loads the API d_dco_ctl_algo_nb in the API
329 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
330
331 /* --------------------------------------------------- */
332
333 void l1ddsp_load_dco_ctl_algo_nb (UWORD16 dco_ctl_algo)
334 {
335 #if (DSP == 38) || (DSP == 39)
336 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_nb = (API) dco_ctl_algo;
337 #endif
338
339 }
340 /* --------------------------------------------------- */
341
342 /* Locosto Changes....*/
343
344 /* Parameters: API dco_algo_ctl_pw */
345 /* Functionality: Loads the API d_dco_ctl_algo_pw in the API
346 This should be called after updating the value in the API via cust_Get_dco_algo_ctl(...) */
347
348 /* --------------------------------------------------- */
349
350 void l1ddsp_load_dco_ctl_algo_pw (UWORD16 dco_ctl_algo)
351 {
352 #if (DSP == 38) || (DSP == 39)
353 l1s_dsp_com.dsp_db_common_w_ptr->d_dco_algo_ctrl_pw = (API) dco_ctl_algo;
354 #endif
355 }
356
357 #endif
358
359 /*-------------------------------------------------------*/
360 /* l1ddsp_load_afc() */
361 /*-------------------------------------------------------*/
362 /* Parameters : */
363 /* Return : */
364 /* Functionality : */
365 /*-------------------------------------------------------*/
366 void l1ddsp_load_afc(API afc)
367 {
368 #if (L1_EOTD==1)
369 // NEW !!! For EOTD measurements in IDLE mode only, cut AFC updates....
370 #if (L1_GPRS)
371 if ( (l1a_l1s_com.nsync.eotd_meas_session == FALSE) ||
372 (l1a_l1s_com.mode == DEDIC_MODE)||
373 (l1a_l1s_com.l1s_en_task[PDTCH] == TASK_ENABLED))
374 #else
375 if ( (l1a_l1s_com.nsync.eotd_meas_session == FALSE) ||
376 (l1a_l1s_com.mode == DEDIC_MODE))
377 #endif
378
379 {
380 #endif
381 //######################## For DSP Rom #################################
382 l1s_dsp_com.dsp_db_w_ptr->d_afc = afc; // Write new afc command.
383 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
384 // NOTE: In Locosto AFC loading is w.r.t DRP not in ABB
385 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= (1 << B_AFC); // Validate new afc value.
386 #endif
387 #if (L1_EOTD==1)
388 }
389 #endif
390
391 }
392
393 /*-------------------------------------------------------*/
394 /* l1ddsp_load_txpwr() */
395 /*-------------------------------------------------------*/
396 /* Parameters : */
397 /* Return : */
398 /* Functionality : */
399 /*Notes:
400
401 While Programming APC Ramp always Program the APCDEL also
402 Cal+:
403 APCDEL1: LSB Dwn(9:5):Up(4:0)
404 APCDEL2: MSB Dwn(9:5):Up(4:0)
405
406 Locosto:
407 APCDEL1: LSB Dwn(9:5):Up(4:0)
408 APCDEL2: MSB Dwn(9:5):Up(4:0)
409 -----
410 Cal+
411 APCRAM : Dwn(51:11)Up(10:6)Forced(0)
412 Locosto:
413 APCRAM: Dwn(9:5)Up(4:0)
414
415 For AFC, APCDEL1, APCDEL2, APCRAMP the Control word d_ctl_abb is checked
416 i f they are reqd to be updated.
417
418 For AUXAPC (Cal+), the last bit = 1 would mean the DSP would pick it at Tx
419 For APCLEV (Loc), it is picked at every Tx, for dummy burst DSP would make it 0
420 */
421
422 /*-------------------------------------------------------*/
423 void l1ddsp_load_txpwr(UWORD8 txpwr, UWORD16 radio_freq)
424 {
425 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
426 UWORD16 pwr_data;
427 #endif
428
429 //config
430 if (l1_config.tx_pwr_code ==0)
431 {
432 // Fixed TXPWR.
433 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = l1_config.params.fixed_txpwr; // GSM management disabled: Fixed TXPWR used.
434
435
436 #if(RF_FAM == 61)
437 //Locosto has new API for Ramp
438 #if (DSP == 38) || (DSP == 39)
439 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
440 #endif
441 #else
442 #if (CODE_VERSION != SIMULATION)
443 /*** Reference to real ramp array (GSM: 15 power levels, 5-19, DCS: 16 power levels, 0-15) ***/
444 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
445 #endif
446 #endif
447
448 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
449 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
450 #endif
451
452 #if(RF_FAM == 61)
453 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
454 #endif
455
456 }
457 else
458 {
459 static UWORD8 last_used_freq_band = 0;
460 UWORD8 freq_band;
461
462 #if (L1_FF_MULTIBAND == 0)
463 // Check whether band has changed
464 // This will be used to reload ramps
465 if ((l1_config.std.id == DUAL) ||
466 (l1_config.std.id == DUALEXT) ||
467 (l1_config.std.id == DUAL_US))
468 {
469 if (radio_freq < l1_config.std.first_radio_freq_band2)
470 freq_band = BAND1;
471 else
472 freq_band = BAND2;
473 }
474 else
475 freq_band = BAND1;
476 #else
477
478 freq_band = l1_multiband_radio_freq_convert_into_effective_band_id(radio_freq);
479
480 #endif
481
482 // Note: txpwr = NO_TXPWR is reserved for forcing the transmitter off
483 // ----- (to suppress SACCH during handover, for example)
484
485 /*** Check to see if the TXPWR is to be suppressed (txpwr = NO_TXPWR) ***/
486
487 if(txpwr == NO_TXPWR)
488 {
489 /*** No transmit ***/
490 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
491 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = 0x12; // AUXAPC initialization addr 9 pg 0 Omega
492 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
493 #endif
494
495 #if(RF_FAM == 61 ) //Locosto without Syren Format
496 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = (API) 0; // APCLEV
497 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
498 #endif
499
500 l1s.last_used_txpwr = NO_TXPWR;
501 return;
502 }
503 else
504 {
505 /*** Get power data according to clipped TXPWR ***/
506 pwr_data = Cust_get_pwr_data(txpwr, radio_freq
507 #if(REL99 && FF_PRF)
508 ,1
509 #endif
510 );
511
512 /*** Load power control level adding the APC address register ***/
513 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
514 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = ((pwr_data << 6) | 0x12);
515 // AUXAPC initialization addr 9 pg 0 Omega
516 #endif
517
518 #if(RF_FAM == 61)
519 l1s_dsp_com.dsp_db_w_ptr->d_power_ctl = (API)(pwr_data);
520 #endif
521 }
522
523 #if TESTMODE
524 #if(RF_FAM == 61)
525 // Currently for RF_FAM=61 Enabling APC-Ramp, APCDEL1 and APCDEL2 writing always i.e. in every TDMA frame
526 // TODO: Check whether this is okay
527 if ((l1_config.TestMode) && (l1_config.tmode.rf_params.down_up & TMODE_UPLINK))
528 #else
529 if ((l1_config.TestMode) && (l1_config.tmode.rf_params.down_up & TMODE_UPLINK) &&
530 ((l1s.last_used_txpwr != txpwr) || (l1_config.tmode.rf_params.reload_ramps_flag)))
531 #endif
532 {
533 #if(RF_FAM == 61)
534 #if (DSP == 38) || (DSP == 39)
535 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
536 #endif
537 #else
538 #if (CODE_VERSION != SIMULATION)
539 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
540 #endif
541 #endif
542
543 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
544 // Setting bit 3 of this register causes DSP to write to APCDEL1 register in Omega. However,
545 // we are controlling this register from MCU through the SPI. Therefore, set it to 0.
546 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (0 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
547 #endif
548
549 #if (RF_FAM == 61)
550 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
551 #endif
552
553 l1s.last_used_txpwr = txpwr;
554 l1_config.tmode.rf_params.reload_ramps_flag = 0;
555 }
556 else
557 #endif
558
559 if ((l1s.last_used_txpwr != txpwr) || (last_used_freq_band != freq_band))
560 {
561 /*** Power level or band has changed, so update the ramp, and trigger the data send to ABB ***/
562
563 l1s.last_used_txpwr = txpwr;
564 last_used_freq_band = freq_band;
565
566 /*** Reference to real ramp array (GSM: 15 power levels, 5-19, DCS: 16 power levels, 0-15) ***/
567 #if(RF_FAM == 61)
568 #if (DSP == 38) || (DSP == 39)
569 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp, txpwr, txpwr, radio_freq);
570 #endif
571 #else
572 #if (CODE_VERSION != SIMULATION)
573 Cust_get_ramp_tab(l1s_dsp_com.dsp_ndb_ptr->a_ramp, txpwr, txpwr, radio_freq);
574 #endif
575 #endif
576
577 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) ||(RF_FAM == 61))
578 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_abb |= ( (1 << B_RAMP) | (1 << B_BULRAMPDEL) | (1 << B_BULRAMPDEL2));
579 #endif
580 }
581 }
582 }
583
584 #if (FF_L1_FAST_DECODING == 1)
585 /*-------------------------------------------------------*/
586 /* l1ddsp_load_fp_task() */
587 /*-------------------------------------------------------*/
588 /* Parameters : */
589 /* Return : */
590 /* Functionality : */
591 /*-------------------------------------------------------*/
592 void l1ddsp_load_fast_dec_task(API task, UWORD8 burst_id)
593 {
594 if (l1s_check_fast_decoding_authorized(task))
595 {
596 //l1s_dsp_com.dsp_db_w_ptr->d_fast_paging_ctrl = 0x0001
597 l1s_dsp_com.dsp_db_common_w_ptr->d_fast_paging_ctrl = 0x00001;
598 if(burst_id == BURST_1)
599 {
600 l1s_dsp_com.dsp_db_common_w_ptr->d_fast_paging_ctrl |= 0x8000;
601 }
602 }
603 }
604 #endif /* FF_L1_FAST_DECODING */
605
606 /*-------------------------------------------------------*/
607 /* l1ddsp_load_rx_task() */
608 /*-------------------------------------------------------*/
609 /* Parameters : */
610 /* Return : */
611 /* Functionality : */
612 /*-------------------------------------------------------*/
613 void l1ddsp_load_rx_task(API rx_task, UWORD8 burst_id, UWORD8 tsq)
614 {
615 l1s_dsp_com.dsp_db_w_ptr->d_task_d = rx_task; // Write RX task Identifier.
616 l1s_dsp_com.dsp_db_w_ptr->d_burst_d = burst_id; // Write RX burst Identifier.
617 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; // Write end of task DSP state.
618 }
619
620 /*-------------------------------------------------------*/
621 /* l1ddsp_load_tx_task() */
622 /*-------------------------------------------------------*/
623 /* Parameters : */
624 /* Return : */
625 /* Functionality : */
626 /*-------------------------------------------------------*/
627 void l1ddsp_load_tx_task(API tx_task, UWORD8 burst_id, UWORD8 tsq)
628 {
629 l1s_dsp_com.dsp_db_w_ptr->d_task_u = tx_task; // write TX task Identifier.
630 l1s_dsp_com.dsp_db_w_ptr->d_burst_u = burst_id; // write TX burst Identifier.
631 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_system |= tsq << B_TSQ; // Write end of task DSP state.
632 }
633
634 /*-------------------------------------------------------*/
635 /* l1ddsp_load_ra_task() */
636 /*-------------------------------------------------------*/
637 /* Parameters : */
638 /* Return : */
639 /* Functionality : */
640 /*-------------------------------------------------------*/
641 void l1ddsp_load_ra_task(API ra_task)
642 {
643 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = ra_task; // write RA task Identifier.
644 }
645
646 /*-------------------------------------------------------*/
647 /* l1ddsp_load_tch_mode() */
648 /*-------------------------------------------------------*/
649 /* Parameters : */
650 /* Return : */
651 /* Functionality : */
652 /*-------------------------------------------------------*/
653 void l1ddsp_load_tch_mode(UWORD8 dai_mode, BOOL dtx_allowed)
654 {
655 // TCH mode register.
656 // bit[0] -> b_eotd.
657 // bit[1] -> b_audio_async only for WCP
658 // bit [2] -> b_dtx.
659 // bit[3] -> play_ul when set to 1
660 // bit[4] -> play_dl when set to 1
661 // bit[5] -> DTX selection for voice memo
662 // bit[6] -> Reserved for ciphering debug
663 // bit[7..10] -> Reserved for ramp up control
664 // bit[11] -> Reserved for analog device selection
665
666 #if (DSP == 32)
667 UWORD16 mask = 0xfffb;
668 #else // NO OP_WCP
669 UWORD16 mask = 0xfff8;
670 #endif
671
672 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = (l1s_dsp_com.dsp_ndb_ptr->d_tch_mode & mask)
673 | (dtx_allowed<<2);
674 #if (L1_EOTD == 1)
675 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
676 #endif
677 }
678
679 #if (AMR == 1)
680 /*-------------------------------------------------------*/
681 /* l1ddsp_load_tch_param() */
682 /*-------------------------------------------------------*/
683 /* Parameters : */
684 /* Return : */
685 /* Functionality : */
686 /*-------------------------------------------------------*/
687 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
688 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
689 UWORD8 chan_type, UWORD8 subchannel,
690 UWORD8 tch_loop, UWORD8 sync_tch,
691 UWORD8 sync_amr,
692 UWORD8 reset_sacch,
693 #if !FF_L1_IT_DSP_DTX
694 UWORD8 vocoder_on)
695 #else
696 UWORD8 vocoder_on,
697 BOOL dtx_dsp_interrupt)
698 #endif
699 #else
700 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
701 UWORD8 chan_type, UWORD8 subchannel,
702 UWORD8 tch_loop, UWORD8 sync_tch,
703 #if !FF_L1_IT_DSP_DTX
704 UWORD8 sync_amr)
705 #else
706 UWORD8 sync_amr, BOOL dtx_dsp_interrupt)
707 #endif
708 #endif
709 {
710 UWORD32 count_0;
711 UWORD32 count_1;
712 UWORD32 d_ctrl_tch;
713 UWORD32 d_fn;
714
715 // d_ctrl_tch
716 // ----------
717 // bit [0..3] -> b_chan_mode
718 // bit [4..7] -> b_chan_type
719 // bit [8] -> b_sync_tch_ul
720 // bit [9] -> b_sync_amr
721 // bit [10] -> b_stop_tch_ul
722 // bit [11] -> b_stop_tch_dl
723 // bit [12..14] -> b_tch_loop
724 // bit [15] -> b_subchannel
725 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
726 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
727 (sync_tch<<B_SYNC_TCH_UL) | (sync_amr<<B_SYNC_AMR) |
728 (tch_loop<<B_TCH_LOOP) | (reset_sacch<<B_RESET_SACCH) | (vocoder_on<<B_VOCODER_ON);
729 #else
730 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
731 (sync_tch<<B_SYNC_TCH_UL) | (sync_amr<<B_SYNC_AMR) |
732 (tch_loop<<B_TCH_LOOP);
733 #endif
734
735 // d_fn
736 // ----
737 // bit [0..7] -> b_fn_report
738 // bit [8..15] -> b_fn_sid
739 d_fn = (next_time->fn_in_report) | ((next_time->fn%104)<<8);
740
741 // a_a5fn
742 // ------
743 // count_0 (a_a5fn[0]), bit [0..4] -> T2.
744 // count_0 (a_a5fn[1]), bit [5..10] -> T3.
745 // count_1 (a_a5fn[0]), bit [0..10] -> T1.
746 count_0 = ((UWORD16)next_time->t3 << 5) | (next_time->t2);
747 count_1 = (next_time->t1);
748
749 l1s_dsp_com.dsp_db_w_ptr->d_fn = d_fn; // write both Fn_sid, Fn_report.
750 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[0] = count_0; // cyphering FN part 1.
751 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[1] = count_1; // cyphering FN part 2.
752 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = d_ctrl_tch; // Channel config.
753 #if FF_L1_IT_DSP_DTX
754 // ### TBD: report this block below in the other instance of this function
755 // DTX interrupt request is latched by DSP in TDMA3 (TCH-AFS, TCH-AHS0) or TDMA0 (TCH-AHS1)
756 if ((chan_mode == TCH_AFS_MODE) || (chan_mode == TCH_AHS_MODE))
757 {
758 if (((next_time->fn_mod13_mod4 == 3) &&
759 ((chan_mode == TCH_AFS_MODE) || ((subchannel == 0)))) ||
760 ((next_time->fn_mod13_mod4 == 0) &&
761 ((chan_mode == TCH_AHS_MODE) && (subchannel == 1)))
762 )
763 {
764 if (dtx_dsp_interrupt)
765 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=1;
766 else
767 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=0;
768
769 }
770 }
771 // Fast DTX not supported
772 else
773 {
774 // No interrupt genaration
775 l1s_dsp_com.dsp_ndb_ptr->d_fast_dtx_enable=0;
776 }
777 #endif
778 }
779 #else
780 /*-------------------------------------------------------*/
781 /* l1ddsp_load_tch_param() */
782 /*-------------------------------------------------------*/
783 /* Parameters : */
784 /* Return : */
785 /* Functionality : */
786 /*-------------------------------------------------------*/
787 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
788 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
789 UWORD8 chan_type, UWORD8 subchannel,
790 UWORD8 tch_loop, UWORD8 sync_tch,
791 #if !FF_L1_IT_DSP_DTX
792 UWORD8 reset_sacch, UWORD8 vocoder_on)
793 #else
794 UWORD8 reset_sacch, UWORD8 vocoder_on,
795 BOOL dtx_dsp_interrupt)
796 #endif
797 #else
798 void l1ddsp_load_tch_param(T_TIME_INFO *next_time, UWORD8 chan_mode,
799 UWORD8 chan_type, UWORD8 subchannel,
800 #if !FF_L1_IT_DSP_DTX
801 UWORD8 tch_loop, UWORD8 sync_tch)
802 #else
803 UWORD8 tch_loop, UWORD8 sync_tch,
804 BOOL dtx_dsp_interrupt)
805 #endif
806 #endif
807 {
808 UWORD32 count_0;
809 UWORD32 count_1;
810 UWORD32 d_ctrl_tch;
811 UWORD32 d_fn;
812
813 // d_ctrl_tch
814 // ----------
815 // bit [0..3] -> b_chan_mode
816 // bit [4..7] -> b_chan_type
817 // bit [8] -> b_sync_tch_ul
818 // bit [9] -> b_sync_tch_dl
819 // bit [10] -> b_stop_tch_ul
820 // bit [11] -> b_stop_tch_dl
821 // bit [12..14] -> b_tch_loop
822 // bit [15] -> b_subchannel
823 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
824 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
825 (sync_tch<<B_SYNC_TCH_UL) | (sync_tch<<B_SYNC_TCH_DL) |
826 (tch_loop<<B_TCH_LOOP) | (reset_sacch<<B_RESET_SACCH) | (vocoder_on<<B_VOCODER_ON);
827 #else
828 d_ctrl_tch = (chan_mode<<B_CHAN_MODE) | (chan_type<<B_CHAN_TYPE) | (subchannel<<B_SUBCHANNEL) |
829 (sync_tch<<B_SYNC_TCH_UL) | (sync_tch<<B_SYNC_TCH_DL) |
830 (tch_loop<<B_TCH_LOOP);
831 #endif
832
833 // d_fn
834 // ----
835 // bit [0..7] -> b_fn_report
836 // bit [8..15] -> b_fn_sid
837 d_fn = (next_time->fn_in_report) | ((next_time->fn%104)<<8);
838
839 // a_a5fn
840 // ------
841 // count_0 (a_a5fn[0]), bit [0..4] -> T2.
842 // count_0 (a_a5fn[1]), bit [5..10] -> T3.
843 // count_1 (a_a5fn[0]), bit [0..10] -> T1.
844 count_0 = ((UWORD16)next_time->t3 << 5) | (next_time->t2);
845 count_1 = (next_time->t1);
846
847 l1s_dsp_com.dsp_db_w_ptr->d_fn = d_fn; // write both Fn_sid, Fn_report.
848 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[0] = count_0; // cyphering FN part 1.
849 l1s_dsp_com.dsp_db_w_ptr->a_a5fn[1] = count_1; // cyphering FN part 2.
850 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = d_ctrl_tch; // Channel config.
851 }
852 #endif
853
854 #if (L1_VOCODER_IF_CHANGE == 0)
855 // TODO: to be moved in API file (see BUG3093)
856 BOOL enable_tch_vocoder(BOOL vocoder)
857 {
858 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
859 // To enable the vocoder, we set the trigger => then handled in l1s_dedicated_mode_manager
860 #if (W_A_DSP_PR20037 == 1)
861 if ((vocoder==TRUE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_DISABLED))
862 {
863 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ;
864
865 #if ( W_A_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)
866 NU_Sleep(DSP_VOCODER_ON_TRANSITION); // DSP transition
867 #endif
868 }
869 // When vocoder_on = FALSE, vocoder module is not executed
870 else if ((vocoder==FALSE) && (l1a_l1s_com.dedic_set.start_vocoder == TCH_VOCODER_ENABLED))
871 {
872 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_DISABLE_REQ;
873 }
874 #else // W_A_DSP_PR20037 == 0
875 if (vocoder)
876 {
877 l1a_l1s_com.dedic_set.start_vocoder = TRUE;
878 }
879 // When vocoder_on = FALSE, vocoder module is not executed
880 else
881 {
882 l1a_l1s_com.dedic_set.vocoder_on = FALSE;
883 }
884 #endif // W_A_DSP_PR20037
885
886 return TRUE;
887 #else
888 return FALSE;
889 #endif
890 }
891 #endif // L1_VOCODER_IF_CHANGE
892 BOOL l1_select_mcsi_port(UWORD8 port)
893 {
894 #if ( (CHIPSET == 12) && (RF_FAM != 61) )
895 l1s_dsp_com.dsp_ndb_ptr->d_mcsi_select = (API)port;
896 return TRUE;
897 #else
898 return FALSE;
899 #endif
900 }
901
902 // TODO: to be moved in API file
903
904 /*-------------------------------------------------------*/
905 /* l1ddsp_load_ciph_param() */
906 /*-------------------------------------------------------*/
907 /* Parameters : */
908 /* Return : */
909 /* Functionality : */
910 /*-------------------------------------------------------*/
911 void l1ddsp_load_ciph_param(UWORD8 a5mode,
912 T_ENCRYPTION_KEY *ciph_key)
913 {
914 // Store ciphering mode (0 for no ciphering) in MCU-DSP com.
915 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = a5mode; // A5 algorithm (0 for none).
916 // Store ciphering key.
917
918 #if (L1_A5_3 == 1)
919
920 if(a5mode == 3)
921 {
922 #if(OP_L1_STANDALONE != 1)
923 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
924 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
925 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
926 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
927 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[4] = (ciph_key->A[8]) | (ciph_key->A[9] << 8);
928 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[5] = (ciph_key->A[10]) | (ciph_key->A[11] << 8);
929 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[6] = (ciph_key->A[12]) | (ciph_key->A[13] << 8);
930 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[7] = (ciph_key->A[14]) | (ciph_key->A[15] << 8);
931 #else // (OP_L1_STANDALONE == 1)
932 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
933 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
934 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
935 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
936 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[4] = (ciph_key->A[8]) | (ciph_key->A[1] << 8);
937 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[5] = (ciph_key->A[10]) | (ciph_key->A[3] << 8);
938 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[6] = (ciph_key->A[12]) | (ciph_key->A[5] << 8);
939 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[7] = (ciph_key->A[14]) | (ciph_key->A[7] << 8);
940 #endif
941 }
942 else // a5mode == 1 or 2
943 {
944 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
945 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
946 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
947 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
948 }
949
950 #else
951
952 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[0] = (ciph_key->A[0]) | (ciph_key->A[1] << 8);
953 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[1] = (ciph_key->A[2]) | (ciph_key->A[3] << 8);
954 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[2] = (ciph_key->A[4]) | (ciph_key->A[5] << 8);
955 l1s_dsp_com.dsp_ndb_ptr->a_a5_kc[3] = (ciph_key->A[6]) | (ciph_key->A[7] << 8);
956
957 #endif
958 }
959
960 /*-------------------------------------------------------*/
961 /* l1ddsp_stop_tch() */
962 /*-------------------------------------------------------*/
963 /* Parameters : */
964 /* Return : */
965 /* Functionality : */
966 /*-------------------------------------------------------*/
967 void l1ddsp_stop_tch(void)
968 {
969 // Tch channel description.
970 // bit [10] -> b_stop_tch_ul, stop TCH/UL.
971 // bit [11] -> b_stop_tch_dl, stop TCH/DL.
972
973 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch |= 3 << B_STOP_TCH_UL;
974 }
975
976 /*-------------------------------------------------------*/
977 /* l1ddsp_meas_read() */
978 /*-------------------------------------------------------*/
979 /* Parameters : */
980 /* Return : */
981 /* Functionality : */
982 /*-------------------------------------------------------*/
983 void l1ddsp_meas_read(UWORD8 nbmeas, UWORD16 *pm)
984 {
985 UWORD8 i;
986
987 for (i= 0; i < nbmeas; i++)
988 {
989 pm[i] = ((l1s_dsp_com.dsp_db_r_ptr->a_pm[i] & 0xffff));
990 }
991
992 #if TESTMODE
993 if(l1_config.TestMode)
994 l1tm.tmode_stats.pm_recent = l1s_dsp_com.dsp_db_r_ptr->a_pm[0] & 0xffff;
995 #endif
996 }
997
998 #if (AMR == 1)
999 /*-------------------------------------------------------*/
1000 /* l1ddsp_load_amr_param() */
1001 /*-------------------------------------------------------*/
1002 /* Parameters : AMR configuration */
1003 /* Return : none */
1004 /* Functionality : Download the AMR configuration to the */
1005 /* DSP via API */
1006 /*-------------------------------------------------------*/
1007 void l1ddsp_load_amr_param(T_AMR_CONFIGURATION amr_param, UWORD8 cmip)
1008 {
1009 // Clear the AMR API buffer
1010 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = (API)0;
1011 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = (API)0;
1012 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = (API)0;
1013 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = (API)0;
1014
1015 // Set the AMR parameters
1016 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[NSCB_INDEX] |= (API)((amr_param.noise_suppression_bit & NSCB_MASK ) << NSCB_SHIFT);
1017 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMUL_INDEX] |= (API)((amr_param.initial_codec_mode & ICM_MASK ) << ICMUL_SHIFT);
1018 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMDL_INDEX] |= (API)((amr_param.initial_codec_mode & ICM_MASK ) << ICMDL_SHIFT);
1019 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMIUL_INDEX] |= (API)((amr_param.initial_codec_mode_indicator & ICMI_MASK ) << ICMIUL_SHIFT);
1020 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ICMIDL_INDEX] |= (API)((amr_param.initial_codec_mode_indicator & ICMI_MASK ) << ICMIDL_SHIFT);
1021 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ACSUL_INDEX] |= (API)((amr_param.active_codec_set & ACS_MASK ) << ACSUL_SHIFT);
1022 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[ACSDL_INDEX] |= (API)((amr_param.active_codec_set & ACS_MASK ) << ACSDL_SHIFT);
1023 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR1_INDEX] |= (API)((amr_param.threshold[0] & THR_MASK ) << THR1_SHIFT);
1024 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR2_INDEX] |= (API)((amr_param.threshold[1] & THR_MASK ) << THR2_SHIFT);
1025 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[THR3_INDEX] |= (API)((amr_param.threshold[2] & THR_MASK ) << THR3_SHIFT);
1026 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST1_INDEX] |= (API)((amr_param.hysteresis[0] & HYST_MASK ) << HYST1_SHIFT);
1027 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST2_INDEX] |= (API)((amr_param.hysteresis[1] & HYST_MASK ) << HYST2_SHIFT);
1028 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[HYST3_INDEX] |= (API)((amr_param.hysteresis[2] & HYST_MASK ) << HYST3_SHIFT);
1029 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[CMIP_INDEX] |= (API)((cmip & CMIP_MASK ) << CMIP_SHIFT);
1030 }
1031 #endif
1032
1033 #if (L1_SAIC != 0)
1034 /*-------------------------------------------------------*/
1035 /* l1ddsp_load_swh_flag() */
1036 /*-------------------------------------------------------*/
1037 /* Parameters : SWH (Spatial Whitening) Flag */
1038 /* Return : none */
1039 /* Functionality : To write the d_swh_ApplyWhitening flag*/
1040 /*-------------------------------------------------------*/
1041 void l1ddsp_load_swh_flag (UWORD16 SWH_flag, UWORD16 SAIC_flag)
1042 {
1043
1044 if(SAIC_flag)
1045 {
1046 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db = SAIC_ENABLE_DB;
1047 if(SWH_flag)
1048 {
1049 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db |= (0x01<< B_SWH_DB);
1050 }
1051 }
1052 else
1053 {
1054 l1s_dsp_com.dsp_db_common_w_ptr->d_swh_ctrl_db = 0;
1055 }
1056 }
1057 #endif
1058
1059 /*-------------------------------------------------------*/
1060 /* l1ddsp_end_scenario() */
1061 /*-------------------------------------------------------*/
1062 /* Parameters : */
1063 /* Return : */
1064 /* Functionality : */
1065 /*-------------------------------------------------------*/
1066 void l1ddsp_end_scenario(UWORD8 type)
1067 {
1068 #if (CODE_VERSION == SIMULATION)
1069 #if (AUDIO_SIMULATION)
1070 switch(type)
1071 {
1072 case GSM_CTL:
1073 case GSM_MISC_CTL:
1074 // a DSP control for a GSM task or
1075 // a DSP control for a GSM and a MISC tasks
1076 //-----------------------------
1077 {
1078 // set DSP_ENB and DSP_PAG for communication interrupt
1079 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page;
1080 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1081
1082 // change DSP page pointer for next controle
1083 l1s_dsp_com.dsp_w_page ^= 1;
1084 }
1085 break;
1086
1087 case MISC_CTL:
1088 // a DSP control for a MISC task
1089 //------------------------------
1090 {
1091 // set only MISC task and reset MISC page
1092 // (don't change GSM PAGE).
1093 // set DSP communication Interrupt.
1094 // set DSP_ENB and the same DSP_PAG for communication interrupt
1095 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page^1;
1096 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1097 }
1098 break;
1099 }
1100 #else // NO AUDIO_SIMULATION
1101 // set DSP_ENB and DSP_PAG for communication interrupt
1102 l1s_tpu_com.reg_cmd->dsp_pag_bit = l1s_dsp_com.dsp_w_page;
1103 l1s_tpu_com.reg_cmd->dsp_enb_bit = ON;
1104
1105 // change DSP page pointer for next control
1106 l1s_dsp_com.dsp_w_page ^= 1;
1107 #endif // AUDIO_SIMULATION
1108
1109 #else // NOT_SIMULATION
1110 UWORD32 dsp_task=0 ;//omaps00090550;
1111 switch(type)
1112 {
1113 case GSM_CTL:
1114 // a DSP control for a GSM task
1115 //-----------------------------
1116 {
1117 // set only GSM task and GSM page
1118 dsp_task = B_GSM_TASK | l1s_dsp_com.dsp_w_page;
1119 // change DSP page pointer for next controle
1120 l1s_dsp_com.dsp_w_page ^= 1;
1121 }
1122 break;
1123
1124 case MISC_CTL:
1125 // a DSP control for a MISC task
1126 //------------------------------
1127 {
1128 UWORD32 previous_page = l1s_dsp_com.dsp_w_page ^ 1;
1129
1130 // set only MISC task and reset MISC page
1131 // (don't change GSM PAGE).
1132 // set DSP communication Interrupt.
1133 dsp_task = B_MISC_TASK | previous_page;
1134
1135 // Rem: DSP makes the DB header feedback even in case
1136 // of MISC task (like TONES). This created some
1137 // side effect which are "work-around" passing
1138 // the correct DB page to the DSP.
1139 }
1140 break;
1141
1142 case GSM_MISC_CTL:
1143 // a DSP control for a GSM and a MISC tasks
1144 //-----------------------------------------
1145 {
1146 // set GSM task, MISC task and GSM page bit.....
1147 dsp_task = B_GSM_TASK | B_MISC_TASK | l1s_dsp_com.dsp_w_page;
1148 // change DSP page pointer for next controle
1149 l1s_dsp_com.dsp_w_page ^= 1;
1150 }
1151 break;
1152 }
1153
1154 // write dsp tasks.....
1155 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
1156 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = (API) dsp_task;
1157 #else
1158 l1s_dsp_com.dsp_param_ptr->d_dsp_page = (API) dsp_task;
1159 #endif
1160
1161 // Enable frame IT on next TDMA
1162 l1dmacro_set_frame_it();
1163
1164 // DSP CPU load measurement - write logic (provide TDMA frame number to DSP)
1165 (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_TDMA_FN))) = (API)l1s.actual_time.fn_mod42432;
1166
1167 #endif // NOT_SIMULATION
1168 }
1169
1170 /*-------------------------------------------------------*/
1171 /* l1dtpu_meas() */
1172 /*-------------------------------------------------------*/
1173 /* Parameters : */
1174 /* Return : */
1175 /* Functionality : */
1176
1177 /* Locosto : should take additional Param of task */
1178
1179 /*-------------------------------------------------------*/
1180 void l1dtpu_meas(UWORD16 radio_freq,
1181 WORD8 agc,
1182 UWORD8 lna_off,
1183 UWORD16 win_id,
1184 UWORD16 tpu_synchro, UWORD8 adc_active
1185 #if(RF_FAM == 61)
1186 ,UWORD8 afc_mode
1187 ,UWORD8 if_ctl
1188 #endif
1189 )
1190
1191 {
1192
1193 WORD16 offset;
1194 WORD16 when;
1195 UWORD16 offset_chg;
1196
1197 #if TESTMODE
1198 if (!l1_config.agc_enable)
1199 {
1200 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1201 // corresponds to the lna_off bit
1202 agc = l1_config.tmode.rx_params.agc;
1203 lna_off = l1_config.tmode.rx_params.lna_off;
1204 }
1205 #endif // TESTMODE
1206
1207 // Compute offset
1208 offset_chg = ((win_id * BP_DURATION) >> BP_SPLIT_PW2);
1209 offset = tpu_synchro + offset_chg;
1210 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE;
1211
1212 // Compute offset change timing
1213 when = offset_chg + PROVISION_TIME - (l1_config.params.rx_synth_setup_time + EPSILON_OFFS);
1214 if(when < 0) when += TPU_CLOCK_RANGE;
1215
1216 // Program TPU scenario
1217 l1dmacro_offset (offset, when); // change TPU offset according to win_id
1218 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1219 if(adc_active == ACTIVE)
1220 l1dmacro_adc_read_rx(); // pgme ADC measurement
1221
1222 l1dmacro_agc (radio_freq, agc,lna_off
1223 #if (RF_FAM == 61)
1224 ,if_ctl
1225 #endif
1226 ); // pgme AGC.
1227 #if (CODE_VERSION == SIMULATION)
1228 l1dmacro_rx_ms (radio_freq, 0); // pgm PWR acquisition.
1229 #else
1230 #if (L1_MADC_ON == 1)
1231 #if (RF_FAM == 61)
1232 l1dmacro_rx_ms (radio_freq,adc_active); // pgm PWR acquisition.
1233 #endif
1234 #else
1235 l1dmacro_rx_ms (radio_freq); // pgm PWR acquisition.
1236 #endif
1237 #endif
1238 l1dmacro_offset (tpu_synchro, IMM); // restore offset
1239
1240 //Locosto
1241 #if(RF_FAM == 61)
1242 // L1_AFC_SCRIPT_MODE - This is specific to Locosto to make AFC script run after
1243 // the second power measurement during FBNEW
1244 if ((win_id == 0) || (afc_mode == L1_AFC_SCRIPT_MODE))
1245 #else
1246 if (win_id == 0)
1247 #endif
1248 {
1249 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
1250 // NOTE: In Locosto AFC is in DRP not in triton
1251 l1ddsp_load_afc(l1s.afc);
1252 #endif
1253
1254 //Locosto
1255 #if(RF_FAM == 61)
1256 if(afc_mode != L1_AFC_NONE)
1257 {
1258 if(afc_mode == L1_AFC_SCRIPT_MODE)
1259 {
1260 l1dtpu_load_afc(l1s.afc); //Load the Initial afc value to the TPU. TPU would copy it to the DRP Wrapper Mem.
1261 }
1262 else
1263 {
1264 l1ddsp_load_afc(l1s.afc);
1265 }
1266 }
1267 #endif
1268 // end Locosto
1269 }
1270 }
1271
1272 /*-------------------------------------------------------*/
1273 /* l1dtpu_neig_fb() */
1274 /*-------------------------------------------------------*/
1275 /* Parameters : */
1276 /* Return : */
1277 /* Functionality : */
1278 /*-------------------------------------------------------*/
1279 void l1dtpu_neig_fb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off)
1280 {
1281 #if TESTMODE
1282 if (!l1_config.agc_enable)
1283 {
1284 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1285 // corresponds to the lna_off bit
1286 agc = l1_config.tmode.rx_params.agc;
1287 lna_off = l1_config.tmode.rx_params.lna_off;
1288 }
1289 #endif
1290
1291 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1292 l1dmacro_agc (radio_freq,agc, lna_off
1293 #if (RF_FAM == 61)
1294 ,IF_120KHZ_DSP
1295 #endif
1296 ); // pgme AGC.
1297 #if (L1_MADC_ON == 1)
1298 #if (RF_FAM == 61)
1299 l1dmacro_rx_fb (radio_freq,INACTIVE); // pgm FB acquisition.
1300 #endif
1301 #else
1302 l1dmacro_rx_fb (radio_freq); // pgm FB acquisition.
1303 #endif
1304 }
1305
1306 /*-------------------------------------------------------*/
1307 /* l1dtpu_neig_fb26() */
1308 /*-------------------------------------------------------*/
1309 /* Parameters : */
1310 /* Return : */
1311 /* Functionality : */
1312 /*-------------------------------------------------------*/
1313 void l1dtpu_neig_fb26(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, UWORD32 offset_serv)
1314 {
1315 WORD16 offset;
1316
1317 #if TESTMODE
1318 if (!l1_config.agc_enable)
1319 {
1320 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1321 // corresponds to the lna_off bit
1322 agc = l1_config.tmode.rx_params.agc;
1323 lna_off = l1_config.tmode.rx_params.lna_off;
1324 }
1325 #endif
1326
1327 // Compute offset
1328 offset = offset_serv + l1_config.params.fb26_anchoring_time;
1329 if(offset >= TPU_CLOCK_RANGE) offset -= TPU_CLOCK_RANGE;
1330
1331 // Program TPU scenario
1332 l1dmacro_offset (offset, l1_config.params.fb26_change_offset_time);
1333 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1334 l1dmacro_agc (radio_freq,agc, lna_off
1335 #if (RF_FAM == 61)
1336 ,IF_120KHZ_DSP
1337 #endif
1338 ); // pgme AGC.
1339 #if (L1_MADC_ON == 1)
1340 #if (RF_FAM == 61)
1341 l1dmacro_rx_fb26 (radio_freq, INACTIVE); // pgm FB acquisition.
1342 #endif
1343 #else
1344 l1dmacro_rx_fb26 (radio_freq); // pgm FB acquisition.
1345 #endif
1346 l1dmacro_offset (offset_serv, IMM); // restore offset
1347 }
1348
1349 /*-------------------------------------------------------*/
1350 /* l1dtpu_neig_sb() */
1351 /*-------------------------------------------------------*/
1352 /* Parameters : */
1353 /* Return : */
1354 /* Functionality : */
1355 /*-------------------------------------------------------*/
1356 void l1dtpu_neig_sb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1357 UWORD32 time_alignmt, UWORD32 offset_serv, UWORD8 reload_flag,
1358 UWORD8 attempt
1359 #if (RF_FAM == 61)
1360 ,UWORD8 if_ctl
1361 #endif
1362 )
1363 {
1364 UWORD16 offset_neigh;
1365
1366 #if TESTMODE
1367 if (!l1_config.agc_enable)
1368 {
1369 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1370 // corresponds to the lna_off bit
1371 agc = l1_config.tmode.rx_params.agc;
1372 lna_off = l1_config.tmode.rx_params.lna_off;
1373 }
1374 #endif
1375
1376 // compute offset neighbour...
1377 offset_neigh = offset_serv + time_alignmt;
1378 if(offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1379
1380 // load OFFSET with NEIGHBOUR value.
1381 l1dmacro_offset (offset_neigh, l1_config.params.rx_change_offset_time);
1382
1383 // Insert 1 NOP to correct the EPSILON_SYNC side effect.
1384 if(attempt != 2)
1385 if(time_alignmt >= (TPU_CLOCK_RANGE - EPSILON_SYNC))
1386 l1dmacro_offset (offset_neigh, 0); // load OFFSET with NEIGHBOUR value.
1387
1388 l1dmacro_rx_synth(radio_freq); // pgme SYNTH.
1389 l1dmacro_agc (radio_freq, agc, lna_off
1390 #if (RF_FAM == 61)
1391 ,if_ctl
1392 #endif
1393 ); // pgme AGC.
1394 #if (L1_MADC_ON == 1)
1395 #if (RF_FAM == 61)
1396 l1dmacro_rx_sb (radio_freq,INACTIVE); // pgm SB acquisition.
1397 #endif
1398 #else
1399 l1dmacro_rx_sb (radio_freq); // pgm SB acquisition.
1400 #endif
1401
1402 // Restore offset with serving value.
1403 if(reload_flag == TRUE)
1404 {
1405 l1dmacro_offset (offset_serv, IMM);
1406 }
1407 }
1408 /*-------------------------------------------------------*/
1409 /* l1dtpu_neig_fbsb() */
1410 /*-------------------------------------------------------*/
1411 /* Parameters : */
1412 /* Return : */
1413 /* Functionality : */
1414 /*-------------------------------------------------------*/
1415 #if ((REL99 == 1) && (FF_BHO == 1))
1416 /*void l1dtpu_neig_fbsb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off
1417 #if (RF_FAM == 61)
1418 ,UWORD8 if_ctl
1419 #endif
1420 )*/
1421 void l1dtpu_neig_fbsb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off)
1422 {
1423 #if TESTMODE
1424 if (!l1_config.agc_enable)
1425 {
1426 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1427 // corresponds to the lna_off bit
1428 agc = l1_config.tmode.rx_params.agc;
1429 lna_off = l1_config.tmode.rx_params.lna_off;
1430 }
1431 #endif // TESTMODE
1432
1433 l1dmacro_rx_synth (radio_freq); // pgme SYNTH.
1434 /*l1dmacro_agc(radio_freq, agc, lna_off
1435 #if (RF_FAM == 61)
1436 ,if_ctl
1437 #endif
1438 ); // pgme AGC.
1439 */
1440 l1dmacro_agc (radio_freq,agc, lna_off
1441 #if (RF_FAM == 61)
1442 ,L1_CTL_LOW_IF
1443 #endif
1444 ); // pgme AGC.
1445 #if (L1_MADC_ON == 1)
1446 #if (RF_FAM == 61)
1447 l1dmacro_rx_fbsb(radio_freq,INACTIVE); // pgm FB acquisition.
1448 #endif
1449 #else
1450 l1dmacro_rx_fbsb(radio_freq); // pgm FB acquisition.- sajal commented
1451 #endif
1452 }
1453 #endif // #if ((REL99 == 1) && (FF_BHO == 1))
1454 /*-------------------------------------------------------*/
1455 /* l1dtpu_neig_sb26() */
1456 /*-------------------------------------------------------*/
1457 /* Parameters : */
1458 /* Return : */
1459 /* Functionality : */
1460 /*-------------------------------------------------------*/
1461 void l1dtpu_neig_sb26(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off, UWORD32 time_alignmt,
1462 UWORD32 fn_offset, UWORD32 offset_serv
1463 #if (RF_FAM == 61)
1464 ,UWORD8 if_ctl
1465 #endif
1466 )
1467 {
1468 UWORD16 offset_neigh;
1469
1470 #if TESTMODE
1471 if (!l1_config.agc_enable)
1472 {
1473 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1474 // corresponds to the lna_off bit
1475 agc = l1_config.tmode.rx_params.agc;
1476 lna_off = l1_config.tmode.rx_params.lna_off;
1477 }
1478 #endif
1479
1480 // compute offset neighbour...
1481 offset_neigh = offset_serv + time_alignmt;
1482 if(offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1483
1484 if(fn_offset != 0)
1485 l1dmacro_offset (offset_neigh, 0); // 1 NOP in some case
1486 else
1487 l1dmacro_offset (offset_neigh, l1_config.params.fb26_change_offset_time);
1488
1489 l1dmacro_rx_synth(radio_freq); // pgme SYNTH.
1490 l1dmacro_agc(radio_freq, agc, lna_off
1491 #if (RF_FAM == 61)
1492 ,if_ctl
1493 #endif
1494 ); // pgme AGC.
1495 #if (L1_MADC_ON == 1)
1496 #if (RF_FAM == 61)
1497 l1dmacro_rx_sb (radio_freq, INACTIVE); // pgm SB acquisition.
1498 #endif
1499 #else
1500 l1dmacro_rx_sb (radio_freq); // pgm SB acquisition.
1501 #endif
1502 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1503 }
1504
1505 /*-------------------------------------------------------*/
1506 /* l1dtpu_serv_rx_nb() */
1507 /*-------------------------------------------------------*/
1508 /* Parameters : */
1509 /* Return : */
1510 /* Functionality : */
1511 /*-------------------------------------------------------*/
1512 void l1dtpu_serv_rx_nb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1513 UWORD32 synchro_serv,UWORD32 new_offset,BOOL change_offset,
1514 UWORD8 adc_active, UWORD8 csf_filter_choice
1515 #if(RF_FAM == 61)
1516 , UWORD8 if_ctl
1517 #endif
1518 #if (NEW_SNR_THRESHOLD == 1)
1519 , UWORD8 saic_flag
1520 #endif/* NEW_SNR_THRESHOLD == 1*/
1521 )
1522 {
1523
1524 #if (CODE_VERSION == SIMULATION)
1525 UWORD32 tpu_w_page;
1526
1527 if (hw.tpu_r_page==0)
1528 tpu_w_page=1;
1529 else
1530 tpu_w_page=0;
1531
1532 // Give the Ts related to the L1s
1533 hw.rx_id[tpu_w_page][0]= ((TPU_CLOCK_RANGE+new_offset-synchro_serv)%TPU_CLOCK_RANGE)/TN_WIDTH;
1534 hw.num_rx[tpu_w_page][0]=1;
1535 hw.rx_group_id[tpu_w_page]=1;
1536 #endif
1537
1538 #if TESTMODE
1539 if (!l1_config.agc_enable)
1540 {
1541 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1542 // corresponds to the lna_off bit
1543 agc = l1_config.tmode.rx_params.agc;
1544 lna_off = l1_config.tmode.rx_params.lna_off;
1545 }
1546 #endif
1547
1548 l1dmacro_synchro (l1_config.params.rx_change_synchro_time, synchro_serv); // Adjust serving OFFSET.
1549
1550 #if L2_L3_SIMUL
1551 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1552 buffer_trace(3, 0x43, synchro_serv,l1s.actual_time.fn,0);
1553 #endif
1554 #endif
1555
1556 // Need to slide offset to cope with the new synchro.
1557 if(change_offset)
1558 l1dmacro_offset(new_offset, l1_config.params.rx_change_offset_time);
1559
1560 l1dmacro_rx_synth(radio_freq); // load SYNTH.
1561 if(adc_active == ACTIVE)
1562 l1dmacro_adc_read_rx(); // pgme ADC measurement
1563
1564 l1dmacro_agc (radio_freq, agc, lna_off
1565 #if (RF_FAM == 61)
1566 ,if_ctl
1567 #endif
1568 );
1569
1570 #if TESTMODE && (CODE_VERSION != SIMULATION)
1571 // Continuous mode: Rx continuous scenario only on START_RX state.
1572 if ((l1_config.TestMode) &&
1573 (l1_config.tmode.rf_params.tmode_continuous == TM_START_RX_CONTINUOUS))
1574 #if (L1_MADC_ON == 1)
1575 #if (RF_FAM == 61)
1576 l1dmacro_rx_cont (FALSE, radio_freq,adc_active,csf_filter_choice
1577 #if (NEW_SNR_THRESHOLD == 1)
1578 ,saic_flag
1579 #endif /* NEW_SNR_THRESHOLD*/
1580 );
1581 #endif /* RF_FAM == 61*/
1582 #else /* L1_MADC_ON == 1 */
1583 l1dmacro_rx_cont (FALSE, radio_freq,csf_filter_choice);
1584 #endif
1585 //TBD Danny New MAcro for Cont Tx reqd, to use only External Trigger
1586 else
1587 #endif
1588 #if ( L1_MADC_ON == 1)
1589 #if (RF_FAM == 61)
1590 l1dmacro_rx_nb (radio_freq, adc_active, csf_filter_choice
1591 #if (NEW_SNR_THRESHOLD == 1)
1592 ,saic_flag
1593 #endif /* NEW_SNR_THRESHOLD*/
1594 ); // RX window for NB.
1595 #endif /* RF_FAM == 61*/
1596 #else /* L1_MADC_ON == 1*/
1597 l1dmacro_rx_nb (radio_freq, csf_filter_choice); // RX window for NB.
1598 #endif
1599
1600 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
1601 l1ddsp_load_afc(l1s.afc);
1602 #endif
1603 #if (RF_FAM == 61)
1604 l1dtpu_load_afc(l1s.afc);
1605 #endif
1606
1607
1608 if(change_offset)
1609 l1dmacro_offset(synchro_serv, IMM); // Restore offset.
1610 }
1611
1612 /*-------------------------------------------------------*/
1613 /* l1dtpu_serv_tx_nb() */
1614 /*-------------------------------------------------------*/
1615 /* Parameters : */
1616 /* Return : */
1617 /* Functionality : */
1618 /*-------------------------------------------------------*/
1619 void l1dtpu_serv_tx_nb(UWORD16 radio_freq, UWORD8 timing_advance,
1620 UWORD32 offset_serv, UWORD8 txpwr, UWORD8 adc_active)
1621 {
1622 WORD32 time;
1623 UWORD32 offset_tx;
1624 UWORD32 timing_advance_in_qbit = (UWORD32)timing_advance << 2;
1625
1626 #if (CODE_VERSION == SIMULATION)
1627 UWORD32 tpu_w_page;
1628
1629 if (hw.tpu_r_page==0)
1630 tpu_w_page=1;
1631 else
1632 tpu_w_page=0;
1633
1634 hw.tx_id[tpu_w_page][0]=3;// MS synchronized on TN=0 for RX => TN=3 for TX
1635 hw.num_tx[tpu_w_page][0]=1;
1636 hw.tx_group_id[tpu_w_page]=1;
1637 #endif
1638
1639 // Reset timing advance if TA_ALGO not enabled.
1640 #if !TA_ALGO
1641 timing_advance_in_qbit = 0;
1642 #endif
1643
1644 // Compute offset value for TX.
1645 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX !
1646 offset_tx = (offset_serv + TIME_OFFSET_TX-l1_config.params.prg_tx_gsm - timing_advance_in_qbit) ;
1647 if (offset_tx >= TPU_CLOCK_RANGE) offset_tx -= TPU_CLOCK_RANGE;
1648
1649 // Check that RX controle has been already installed.
1650 // Offset for TX must be set an immediately if RX is there else
1651 // it must be performed EPSILON_SYNC before current offset time.
1652 if( l1s.tpu_ctrl_reg & CTRL_RX )
1653 time = l1_config.params.tx_change_offset_time - l1_config.params.prg_tx_gsm;
1654 else
1655 time = TPU_CLOCK_RANGE - EPSILON_SYNC;
1656
1657 l1dmacro_offset (offset_tx, time); // load OFFSET for TX before each burst.
1658
1659 #if L2_L3_SIMUL
1660 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1661 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0);
1662 #endif
1663 #endif
1664
1665 l1dmacro_tx_synth(radio_freq); // load SYNTH.
1666 #if TESTMODE && (CODE_VERSION != SIMULATION)
1667 // Continuous mode: Tx continuous scenario only on START_TX state.
1668 #if (RF_FAM != 61)
1669 if ((l1_config.TestMode) &&
1670 (l1_config.tmode.rf_params.tmode_continuous == TM_START_TX_CONTINUOUS))
1671 l1dmacro_tx_cont (radio_freq, txpwr); // TX window for NB.
1672 else
1673 #endif // RF_FAM != 61
1674 #if (RF_FAM == 61)
1675 // NOTE: In Test Mode and in TX Continuous, APC control is in manual mode
1676 // This is done in l1tm_async.c
1677 if ((l1_config.TestMode) &&
1678 (l1_config.tmode.rf_params.tmode_continuous == TM_START_TX_CONTINUOUS))
1679 {
1680 // NOTE: APC is set in manual mode from l1tm_async.c
1681 l1dmacro_tx_cont (radio_freq, txpwr); // TX window for NB.
1682 }
1683 else
1684 #endif // RF_FAM == 61
1685 #endif
1686 l1dmacro_tx_nb (radio_freq, txpwr, adc_active); // TX window for NB.
1687 // TX window for NB.
1688 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1689
1690 #if L2_L3_SIMUL
1691 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1692 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0);
1693 #endif
1694 #endif
1695 }
1696
1697 /*-------------------------------------------------------*/
1698 /* l1dtpu_neig_rx_nb() */
1699 /*-------------------------------------------------------*/
1700 /* Parameters : */
1701 /* Return : */
1702 /* Functionality : */
1703 /*-------------------------------------------------------*/
1704 void l1dtpu_neig_rx_nb(UWORD16 radio_freq, WORD8 agc, UWORD8 lna_off,
1705 UWORD32 time_alignmt, UWORD32 offset_serv, UWORD8 reload_flag,
1706 UWORD8 nop
1707 #if (RF_FAM == 61)
1708 ,UWORD8 if_ctl
1709 #endif
1710 #if (NEW_SNR_THRESHOLD == 1)
1711 ,UWORD8 saic_flag
1712 #endif /* NEW_SNR_THRESHOLD*/
1713 )
1714 {
1715 UWORD32 offset_neigh;
1716 // By default we choose the hardware filter for neighbour Normal Bursts
1717 UWORD8 csf_filter_choice = L1_SAIC_HARDWARE_FILTER;
1718
1719 #if TESTMODE
1720 if (!l1_config.agc_enable)
1721 {
1722 // AGC gain can only be controlled in 2dB steps as the bottom bit (bit zero)
1723 // corresponds to the lna_off bit
1724 agc = l1_config.tmode.rx_params.agc;
1725 lna_off = l1_config.tmode.rx_params.lna_off;
1726 }
1727 #endif
1728
1729 // compute offset neighbour...
1730 offset_neigh = (offset_serv + time_alignmt) ;
1731 if (offset_neigh >= TPU_CLOCK_RANGE) offset_neigh -= TPU_CLOCK_RANGE;
1732
1733 l1dmacro_offset (offset_neigh, l1_config.params.rx_change_offset_time); // load OFFSET with NEIGHBOUR value.
1734 // Insert 1 NOP to correct the EPSILON_SYNC side effect
1735 if (nop ==1) l1dmacro_offset (offset_neigh,0);
1736
1737
1738 l1dmacro_rx_synth(radio_freq); // load SYNTH.
1739 l1dmacro_agc (radio_freq, agc, lna_off
1740 #if (RF_FAM == 61)
1741 ,if_ctl
1742 #endif
1743 );
1744 #if (L1_MADC_ON == 1)
1745 #if (RF_FAM == 61)
1746 l1dmacro_rx_nb (radio_freq, INACTIVE, csf_filter_choice
1747 #if (NEW_SNR_THRESHOLD == 1)
1748 ,saic_flag
1749 #endif /* NEW_SNR_THRESHOLD*/
1750 ) ; // RX window for NB.
1751 #endif /* RF_FAM == 61*/
1752 #else /* L1_MADC_ON == 1*/
1753 l1dmacro_rx_nb (radio_freq, csf_filter_choice); // RX window for NB.
1754 #endif
1755
1756 // Restore offset with serving value.
1757 if(reload_flag == TRUE)
1758 l1dmacro_offset (offset_serv, IMM);
1759
1760 }
1761
1762 /*-------------------------------------------------------*/
1763 /* l1dtpu_serv_tx_ra() */
1764 /*-------------------------------------------------------*/
1765 /* Parameters : "burst_id" gives the burst identifier */
1766 /* which is used for offset management. */
1767 /* Return : */
1768 /* Functionality : */
1769 /*-------------------------------------------------------*/
1770 void l1dtpu_serv_tx_ra(UWORD16 radio_freq, UWORD32 offset_serv, UWORD8 txpwr, UWORD8 adc_active)
1771 {
1772 WORD32 time;
1773 UWORD32 offset_tx;
1774
1775 // Compute offset value for TX.
1776 // Rem: Timing Advance is always 0 for a RA.
1777 // PRG_TX has become variable, no longer contained in TIME_OFFSET_TX !
1778 offset_tx = (offset_serv + TIME_OFFSET_TX-l1_config.params.prg_tx_gsm);
1779 if (offset_tx >= TPU_CLOCK_RANGE) offset_tx -= TPU_CLOCK_RANGE;
1780
1781 // Check that RX controle has been already installed.
1782 // Offset for TX must be set an immediately if RX is there else
1783 // it must be performed EPSILON_SYNC before current offset time.
1784 if( l1s.tpu_ctrl_reg & CTRL_RX )
1785 time = l1_config.params.tx_change_offset_time - l1_config.params.prg_tx_gsm;
1786 else
1787 time = TPU_CLOCK_RANGE - EPSILON_SYNC;
1788
1789 l1dmacro_offset (offset_tx, time); // load OFFSET for TX before each burst.
1790 #if L2_L3_SIMUL
1791 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1792 buffer_trace(2, offset_tx,l1s.actual_time.fn,0,0);
1793 #endif
1794 #endif
1795 l1dmacro_tx_synth(radio_freq); // load SYNTH.
1796 l1dmacro_tx_ra (radio_freq, txpwr,adc_active); // TX window for RA.
1797 l1dmacro_offset (offset_serv, IMM); // Restore offset with serving value.
1798 #if L2_L3_SIMUL
1799 #if (DEBUG_TRACE == BUFFER_TRACE_OFFSET)
1800 buffer_trace(2, offset_serv,l1s.actual_time.fn,0,0);
1801 #endif
1802 #endif
1803 }
1804
1805 /*-------------------------------------------------------*/
1806 /* l1dtpu_end_scenario() */
1807 /*-------------------------------------------------------*/
1808 /* Parameters : */
1809 /* Return : */
1810 /* Functionality : */
1811 /*-------------------------------------------------------*/
1812 void l1dtpu_end_scenario(void)
1813 {
1814
1815 // write IDLE at end of TPU page
1816 // TPU_ENB and TPU_PAG are set in L1DMACRO_IDLE(). The TPU change
1817 // is executed by the TPU itself and the TPU pointer is reset to
1818 // start of page by l1dmacro_idle();
1819 l1dmacro_idle();
1820
1821 #if (CODE_VERSION == SIMULATION)
1822 #if LOGTPU_TRACE
1823 log_macro();
1824 #endif
1825 #endif
1826 // init pointer within new TPU page at 1st line
1827 #if (CODE_VERSION == SIMULATION)
1828 // set TPU_ENB, TPU_PAG for communication interrupt
1829 l1s_tpu_com.reg_cmd->tpu_pag_bit = l1s_tpu_com.tpu_w_page;
1830 l1s_tpu_com.reg_cmd->tpu_enb_bit = ON;
1831
1832 // change TPU and DSP page pointer for next control
1833 l1s_tpu_com.tpu_w_page ^= 1;
1834
1835 // points on new "write TPU page"...
1836 l1s_tpu_com.tpu_page_ptr=&(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
1837
1838 #endif
1839
1840 }
1841
1842 /*-------------------------------------------------------*/
1843 /* l1d_reset_hw() */
1844 /*-------------------------------------------------------*/
1845 /* Parameters : */
1846 /* Return : */
1847 /* Functionality : */
1848 /*-------------------------------------------------------*/
1849 void l1d_reset_hw(UWORD32 offset_value)
1850 {
1851 #if (CODE_VERSION == SIMULATION)
1852 // Reset DSP write/read page, Reset TPU write page, reset "used" flag.
1853 l1s_dsp_com.dsp_w_page = 0;
1854 l1s_dsp_com.dsp_r_page = 0;
1855 l1s_tpu_com.tpu_w_page = 0;
1856 l1s_dsp_com.dsp_r_page_used = 0;
1857
1858 // Reset communication pointers.
1859 l1s_dsp_com.dsp_ndb_ptr = &(buf.ndb); // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
1860 l1s_dsp_com.dsp_db_r_ptr = &(buf.mcu_rd[l1s_dsp_com.dsp_r_page]); // MCU<->DSP comm. read page (Double Buffered comm. memory).
1861 l1s_dsp_com.dsp_db_w_ptr = &(buf.mcu_wr[l1s_dsp_com.dsp_w_page]); // MCU<->DSP comm. write page (Double Buffered comm. memory).
1862
1863 // Reset task commands.
1864 l1s_dsp_com.dsp_db_w_ptr->d_task_d = NO_DSP_TASK; // Init. RX task to NO TASK.
1865 l1s_dsp_com.dsp_db_w_ptr->d_task_u = NO_DSP_TASK; // Init. TX task to NO TASK.
1866 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = NO_DSP_TASK; // Init. RA task to NO TASK.
1867 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NO_DSP_TASK; // Init. MONITORING task to NO TASK.
1868
1869
1870 //Reset the TCH channel description
1871 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = 0;
1872
1873 #if (L1_GPRS)
1874 // Reset communication pointers.
1875 l1ps_dsp_com.pdsp_db_r_ptr = &(buf.mcu_rd_gprs[l1s_dsp_com.dsp_r_page]);
1876 l1ps_dsp_com.pdsp_db_w_ptr = &(buf.mcu_wr_gprs[l1s_dsp_com.dsp_w_page]);
1877
1878 // Reset MCU->DSP page.
1879 l1ps_reset_db_mcu_to_dsp(l1ps_dsp_com.pdsp_db_w_ptr);
1880 #endif // L1_GPRS
1881
1882 // Direct access to TPU_RESET_BIT.
1883 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // Reset TPU.
1884
1885 // Reset TPU_ENB, DSP_ENB and TPU_PAG, DSP_PAG for communication interrupt
1886 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
1887 l1s_tpu_com.reg_cmd->dsp_pag_bit = 0;
1888 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
1889 l1s_tpu_com.reg_cmd->dsp_enb_bit = OFF;
1890
1891 // Init pointer within TPU page 0 at 1st line
1892 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[0].line[0]);
1893
1894 // Load offset register according to serving cell.
1895 l1dmacro_offset(offset_value, IMM);
1896
1897 #else // NOT_SIMULATION
1898
1899 // Reset DSP write/read page, Reset TPU write page, reset "used" flag.
1900 l1s_dsp_com.dsp_w_page = 0;
1901 l1s_dsp_com.dsp_r_page = 0;
1902 l1s_tpu_com.tpu_w_page = 0;
1903 l1s_dsp_com.dsp_r_page_used = 0;
1904
1905 // Reset communication pointers.
1906 l1s_dsp_com.dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR; // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
1907 l1s_dsp_com.dsp_db_r_ptr = (T_DB_DSP_TO_MCU *) DB_R_PAGE_0; // MCU<->DSP comm. read page (Double Buffered comm. memory).
1908 l1s_dsp_com.dsp_db_w_ptr = (T_DB_MCU_TO_DSP *) DB_W_PAGE_0; // MCU<->DSP comm. write page (Double Buffered comm. memory).
1909 l1s_dsp_com.dsp_param_ptr= (T_PARAM_MCU_DSP *) PARAM_ADR;
1910
1911 #if (DSP == 38) || (DSP == 39)
1912 l1s_dsp_com.dsp_db_common_w_ptr = (T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_0;
1913 #endif
1914
1915 // Reset task commands.
1916 l1s_dsp_com.dsp_db_w_ptr->d_task_d = NO_DSP_TASK; // Init. RX task to NO TASK.
1917 l1s_dsp_com.dsp_db_w_ptr->d_task_u = NO_DSP_TASK; // Init. TX task to NO TASK.
1918 l1s_dsp_com.dsp_db_w_ptr->d_task_ra = NO_DSP_TASK; // Init. RA task to NO TASK.
1919 l1s_dsp_com.dsp_db_w_ptr->d_task_md = NO_DSP_TASK; // Init. MONITORING task to NO TASK.
1920
1921 //Reset the TCH channel description
1922 l1s_dsp_com.dsp_db_w_ptr->d_ctrl_tch = 0;
1923
1924 // Clear DSP_PAG bit
1925 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
1926 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = 0;
1927 #else
1928 l1s_dsp_com.dsp_param_ptr->d_dsp_page = 0;
1929 #endif
1930
1931 #if (L1_GPRS)
1932 // Reset communication pointers.
1933 l1ps_dsp_com.pdsp_ndb_ptr = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS;
1934 l1ps_dsp_com.pdsp_db_r_ptr = (T_DB_DSP_TO_MCU_GPRS *) DB_R_PAGE_0_GPRS;
1935 l1ps_dsp_com.pdsp_db_w_ptr = (T_DB_MCU_TO_DSP_GPRS *) DB_W_PAGE_0_GPRS;
1936 l1ps_dsp_com.pdsp_param_ptr= (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS;
1937
1938 // Reset MCU->DSP page.
1939 l1ps_reset_db_mcu_to_dsp(l1ps_dsp_com.pdsp_db_w_ptr);
1940 #endif // L1_GPRS
1941
1942 #if (DSP_DEBUG_TRACE_ENABLE == 1)
1943 l1s_dsp_com.dsp_db2_current_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_0;
1944 l1s_dsp_com.dsp_db2_other_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_1;
1945 #endif
1946
1947 // Reset TPU and Reload offset register with Serving value.
1948 // Clear TPU_PAG
1949 l1dmacro_reset_hw(offset_value);
1950 #endif // NOT_SIMULATION
1951 }
1952
1953
1954 #if(RF_FAM == 61)
1955
1956 /*-------------------------------------------------------*/
1957 /* l1apc_init_ramp_tables() */
1958 /*-------------------------------------------------------*/
1959 /* Parameters : void */
1960 /* Return : void */
1961 /* Functionality : This would copy the Ramp table */
1962 /* values to the MCU DSP API */
1963 /*-------------------------------------------------------*/
1964 void l1dapc_init_ramp_tables(void)
1965 {
1966
1967 #if (CODE_VERSION == SIMULATION)
1968 // Do Nothing there is no APC task
1969 #else
1970 #if ( DSP == 38) || (DSP == 39)
1971 // Load RAMP up/down in NDB memory...
1972 if (l1_config.tx_pwr_code == 0)
1973 {
1974 Cust_get_ramp_tab( l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp,
1975 0 /* not used */,
1976 0 /* not used */,
1977 1 /* arbitrary value for arfcn*/);
1978
1979 }
1980 else
1981 {
1982 Cust_get_ramp_tab( l1s_dsp_com.dsp_ndb_ptr->a_drp_ramp,
1983 5 /* arbitrary value working in any case */,
1984 5 /* arbitrary value working in any case */,
1985 1 /* arbitrary value for arfcn*/);
1986 }
1987 #endif
1988 // Is it required to load ramptables for GPRS a_drp2_ramp_gprs
1989
1990 #endif
1991
1992 }
1993
1994
1995
1996 /*-------------------------------------------------------*/
1997 /* l1ddsp_apc_load_apcctrl2 */
1998 /*-------------------------------------------------------*/
1999 /* Parameters : void */
2000 /* Return : void */
2001 /* Functionality : This would copy the Ramp table */
2002 /* values to the MCU DSP API */
2003 /*-------------------------------------------------------*/
2004 void l1ddsp_apc_load_apcctrl2(UWORD16 apcctrl2)
2005 {
2006 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 = ((apcctrl2) | (0x8000));
2007 }
2008
2009 /*-------------------------------------------------------*/
2010 /* l1ddsp_apc_set_manual_mode */
2011 /*-------------------------------------------------------*/
2012 /* Parameters : void */
2013 /* Return : void */
2014 /* Functionality : This would set the APC in manual */
2015 /* OR external trigger mode */
2016 /*-------------------------------------------------------*/
2017 void l1ddsp_apc_set_manual_mode(void)
2018 {
2019 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 |= ((APC_APC_MODE) | (0x8000));
2020 }
2021
2022 /*-------------------------------------------------------*/
2023 /* l1ddsp_apc_set_automatic_mode */
2024 /*-------------------------------------------------------*/
2025 /* Parameters : void */
2026 /* Return : void */
2027 /* Functionality : This would set APC in automatic */
2028 /* OR internal sequencer mode */
2029 /*-------------------------------------------------------*/
2030 void l1ddsp_apc_set_automatic_mode(void)
2031 {
2032 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 &= ~(APC_APC_MODE);
2033 l1s_dsp_com.dsp_ndb_ptr->d_apcctrl2 |= (0x8000);
2034 }
2035
2036 #ifdef TESTMODE
2037
2038 /*-------------------------------------------------------*/
2039 /* l1ddsp_apc_load_apclev */
2040 /*-------------------------------------------------------*/
2041 /* Parameters : void */
2042 /* Return : void */
2043 /* Functionality : This function writes the apclev */
2044 /* val into the APCLEV register via DSP */
2045 /* NOTE: Used only in TESTMODE and only when */
2046 /* l1_config.tmode.rf_params.down_up == TMODE_UPLINK; */
2047 /*-------------------------------------------------------*/
2048 void l1ddsp_apc_load_apclev(UWORD16 apclev)
2049 {
2050 l1s_dsp_com.dsp_ndb_ptr->d_apclev = ((apclev) | (0x8000));
2051 }
2052
2053
2054 #endif // TESTMODE
2055
2056 #endif
2057 #if FF_L1_IT_DSP_DTX
2058 /*-------------------------------------------------------*/
2059 /* l1ddsp_dtx_interrupt_pending() */
2060 /*-------------------------------------------------------*/
2061 /* Parameters : */
2062 /* Return : DTX interrupt status */
2063 /* Functionality : Test and clear the DTX IT pending */
2064 /* flag for DSP ISR screening purpose */
2065 /*-------------------------------------------------------*/
2066 BOOL l1ddsp_dtx_interrupt_pending(void)
2067 {
2068 if (l1s_dsp_com.dsp_ndb_ptr->d_dsp_hint_flag & (2 << B_DTX_HINT_ISSUED))
2069 {
2070 // Flag HISR to be scheduled
2071 l1a_apihisr_com.dtx.pending = TRUE;
2072 // Clear API ISR condition
2073 l1s_dsp_com.dsp_ndb_ptr->d_dsp_hint_flag &= ~(2 << B_DTX_HINT_ISSUED);
2074 return TRUE;
2075 }
2076 else
2077 return FALSE;
2078 }
2079 #endif
2080
2081
2082 #define L1_DEBUG_IQ_DUMP 0
2083
2084 #if (L1_DEBUG_IQ_DUMP == 1)
2085
2086 #define IQ_DUMP_MAX_LOG_SIZE (400) /* i.e. 200 I-Q Sample Pair */
2087 #define IQ_DUMP_BUFFER_SIZE (1280)
2088 #define L1_DSP_DUMP_IQ_BUFFER_PAGE0 (0xFFD00000 + ((0x2000 - 0x800)*2))
2089 #define L1_DSP_DUMP_IQ_BUFFER_PAGE1 (0xFFD00000 + ((0x2190 - 0x800)*2))
2090
2091 typedef struct
2092 {
2093 UWORD8 task;
2094 UWORD8 hole;
2095 UWORD16 size;
2096 UWORD16 fn_mod42432;
2097 UWORD16 iq_sample[IQ_DUMP_MAX_LOG_SIZE];
2098 }T_IQ_LOG_BUFFER;
2099
2100 #pragma DATA_SECTION(iq_dump_buffer,".debug_data");
2101 T_IQ_LOG_BUFFER iq_dump_buffer[IQ_DUMP_BUFFER_SIZE];
2102
2103 UWORD32 iq_dump_buffer_log_index = 0;
2104 UWORD32 iq_overflow_ind=0;
2105
2106 #endif
2107
2108 void l1ddsp_read_iq_dump(UWORD8 task)
2109 {
2110
2111 #if (L1_DEBUG_IQ_DUMP == 1)
2112 UWORD16 *p_dsp_iq_buffer_ptr;
2113 UWORD16 size;
2114 int i;
2115
2116 /* get the page logic*/
2117 p_dsp_iq_buffer_ptr = (UWORD16 *)(L1_DSP_DUMP_IQ_BUFFER_PAGE0);
2118 if(l1s_dsp_com.dsp_r_page){
2119 p_dsp_iq_buffer_ptr = (UWORD16 *)(L1_DSP_DUMP_IQ_BUFFER_PAGE1);
2120 }
2121
2122 /* */
2123 size = *p_dsp_iq_buffer_ptr;
2124
2125 if(size == 0)
2126 return;
2127
2128 /* size given by DSP is in units of I-Q sample pair */
2129 if(size > (IQ_DUMP_MAX_LOG_SIZE /2)){
2130 size = (IQ_DUMP_MAX_LOG_SIZE/2);
2131 }
2132
2133 /* make size as zero again */
2134 *p_dsp_iq_buffer_ptr++ = 0;
2135
2136 if(iq_dump_buffer_log_index >= IQ_DUMP_BUFFER_SIZE){
2137 iq_overflow_ind=1;
2138 iq_dump_buffer_log_index = 0;
2139 }
2140
2141 iq_dump_buffer[iq_dump_buffer_log_index].task = task;
2142 iq_dump_buffer[iq_dump_buffer_log_index].hole = 0;
2143 iq_dump_buffer[iq_dump_buffer_log_index].size = size;
2144 iq_dump_buffer[iq_dump_buffer_log_index].fn_mod42432 = l1s.actual_time.fn_mod42432;
2145
2146 memcpy(&iq_dump_buffer[iq_dump_buffer_log_index].iq_sample[0],
2147 p_dsp_iq_buffer_ptr,
2148 size*2*2); /* size * 2 (as size is in IQsample pair) * 2 (to convert to bytes) */
2149
2150 iq_dump_buffer_log_index = iq_dump_buffer_log_index + 1;
2151
2152 #endif
2153 }
2154
2155