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comparison gsm-fw/L1/cfile/l1_init.c @ 544:96a96ec34139

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gsm-fw/L1/cfile: initial import from LoCosto source
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 03 Aug 2014 06:06:45 +0000
parents
children 67ab5f240b7d
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543:2dccd2b4e5a2 544:96a96ec34139
1 /************ Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_INIT.C
4 *
5 * Filename l1_init.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #define L1_INIT_C
11
12 #include "l1_confg.h"
13
14 #if (CODE_VERSION == SIMULATION)
15 #include <string.h>
16 #include "l1_types.h"
17 #include "sys_types.h"
18 #include "l1_const.h"
19 #include "l1_time.h"
20 #include "l1_signa.h"
21
22 #if TESTMODE
23 #include "l1tm_defty.h"
24 #endif
25 #if (AUDIO_TASK == 1)
26 #include "l1audio_const.h"
27 #include "l1audio_cust.h"
28 #include "l1audio_defty.h"
29 #endif
30 #if (L1_GTT == 1)
31 #include "l1gtt_const.h"
32 #include "l1gtt_defty.h"
33 #endif
34
35 #if (L1_MP3 == 1)
36 #include "l1mp3_defty.h"
37 #endif
38
39 #if (L1_MIDI == 1)
40 #include "l1midi_defty.h"
41 #endif
42 //ADDED FOR AAC
43 #if (L1_AAC == 1)
44 #include "l1aac_defty.h"
45 #endif
46 #if (L1_DYN_DSP_DWNLD == 1)
47 #include "l1_dyn_dwl_proto.h"
48 #endif
49
50 #include "l1_defty.h"
51 #include "cust_os.h"
52 #include "l1_msgty.h"
53 #include "l1_varex.h"
54 #include "l1_proto.h"
55 #include "l1_mftab.h"
56 #include "l1_tabs.h"
57 #include "l1_ver.h"
58 #include "ulpd.h"
59
60 #include "l1_proto.h"
61
62 #if L1_GPRS
63 #include "l1p_cons.h"
64 #include "l1p_msgt.h"
65 #include "l1p_deft.h"
66 #include "l1p_vare.h"
67 #include "l1p_tabs.h"
68 #include "l1p_macr.h"
69 #include "l1p_ver.h"
70 #endif
71
72 #if TESTMODE
73 #include "l1tm_ver.h"
74 #endif
75
76 #include <stdio.h>
77 #include "sim_cfg.h"
78 #include "sim_cons.h"
79 #include "sim_def.h"
80 #include "sim_var.h"
81
82 #else // NO SIMULATION
83
84 #include <string.h>
85 #include "tm_defs.h"
86 #include "l1_types.h"
87 #include "sys_types.h"
88 #include "leadapi.h"
89 #include "l1_const.h"
90 #include "l1_macro.h"
91 #include "l1_time.h"
92 #include "l1_signa.h"
93 #if (AUDIO_TASK == 1)
94 #include "l1audio_const.h"
95 #include "l1audio_cust.h"
96 #include "l1audio_defty.h"
97 #endif
98
99
100 #include "spi_drv.h"
101 #include "abb.h"
102 #if (ANLG_FAM != 11)
103 #include "abb_core_inth.h"
104 #endif
105
106 #if TESTMODE
107 #include "l1tm_defty.h"
108 #endif
109
110 #if (L1_GTT == 1)
111 #include "l1gtt_const.h"
112 #include "l1gtt_defty.h"
113 #endif
114
115 #if (L1_MP3 == 1)
116 #include "l1mp3_defty.h"
117 #endif
118
119 #if (L1_MIDI == 1)
120 #include "l1midi_defty.h"
121 #endif
122 //ADDED FOR AAC
123 #if (L1_AAC == 1)
124 #include "l1aac_defty.h"
125 #endif
126 #if (L1_DYN_DSP_DWNLD == 1)
127 #include "l1_dyn_dwl_proto.h"
128 #endif
129
130 #include "l1_defty.h"
131 #include "cust_os.h"
132 #include "l1_msgty.h"
133 #include "l1_varex.h"
134 #include "l1_proto.h"
135 #include "l1_mftab.h"
136 #include "l1_tabs.h"
137 #include "l1_ver.h"
138 #include "tpudrv.h"
139
140 #if (CHIPSET == 12) || (CHIPSET == 15)
141 #include "sys_inth.h"
142 #else
143 #include "mem.h"
144 #include "inth.h"
145 #include "dma.h"
146 #include "iq.h"
147 #endif
148
149 #include "clkm.h"
150 #include "rhea_arm.h"
151 #include "ulpd.h"
152
153 #include "l1_proto.h"
154
155 #if L1_GPRS
156 #include "l1p_cons.h"
157 #include "l1p_msgt.h"
158 #include "l1p_deft.h"
159 #include "l1p_vare.h"
160 #include "l1p_tabs.h"
161 #include "l1p_macr.h"
162 #include "l1p_ver.h"
163 #endif
164
165 #if TESTMODE
166 #include "l1tm_ver.h"
167 #endif
168
169 #endif // NOT SIMULATION
170
171
172
173 #if (RF_FAM == 61)
174 #if (DRP_FW_EXT==0)
175 #include "drp_drive.h"
176 #include "drp_api.h"
177 #include "l1_rf61.h"
178 #include "apc.h"
179 #else
180 #include "l1_rf61.h"
181 #include "l1_drp_inc.h"
182 #endif
183 #endif
184
185
186 #if (RF_FAM == 60)
187 #include "drp_drive.h"
188 #include "drp_api.h"
189 #include "l1_rf60.h"
190 #endif
191
192 #if (TRACE_TYPE == 1)||(TRACE_TYPE == 4)
193 #include "l1_trace.h"
194 #endif
195
196 #include <string.h>
197 #include <stdio.h>
198
199 #if (ANLG_FAM == 11)
200 #include "bspTwl3029_I2c.h"
201 #include "bspTwl3029_Aud_Map.h"
202 #include "bspTwl3029_Madc.h"
203 #endif
204 //OMAPS148175
205 #include "l1_drp_if.h"
206 #include "drp_main.h"
207 //
208 #if (ANLG_FAM == 11)
209 #if (L1_MADC_ON == 1)
210 extern BspTwl3029_MadcResults l1_madc_results;
211 extern void l1a_madc_callback(void);
212 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
213 extern UWORD32 Cust_navc_ctrl_status(UWORD8 d_navc_start_stop_read);//NAVC
214 #endif
215 #endif
216
217 #if (AUDIO_DEBUG == 1)
218 extern UWORD8 audio_reg_read_status;
219 #endif
220
221 #endif
222
223 #if (AUDIO_TASK == 1)
224 /**************************************/
225 /* External audio prototypes */
226 /**************************************/
227 extern void l1audio_initialize_var (void);
228 #endif
229
230 extern void l1audio_dsp_init (void);
231 extern void initialize_wait_loop(void);
232
233 #if (L1_GPRS)
234 // external functions from GPRS implementation
235 void initialize_l1pvar(void);
236 void l1pa_reset_cr_freq_list(void);
237 #endif // L1_GPRS
238 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38)|| (DSP == 39))&& (CODE_VERSION != SIMULATION))
239 extern void l1_api_dump(void);
240 #endif
241
242 #if (TRACE_TYPE==3)
243 void reset_stats();
244 #endif // TRACE_TYPE
245
246 #if (L1_GTT == 1)
247 extern void l1gtt_initialize_var(void);
248 #endif
249
250 #if (L1_MP3 == 1)
251 extern void l1mp3_initialize_var(void);
252 #endif
253
254 #if (L1_MIDI == 1)
255 extern void l1midi_initialize_var(void);
256 #endif
257 //ADDED FOR AAC
258 #if (L1_AAC == 1)
259 extern void l1aac_initialize_var(void);
260 #endif
261
262 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
263 extern void L1_trace_string(char *s);
264 #endif
265
266 #if ((TRACE_TYPE==1) || (TRACE_TYPE==2) || (TRACE_TYPE==3) || (TRACE_TYPE==4) || (TRACE_TYPE==7))
267 extern void L1_trace_string(char *s);
268 #endif
269
270 #if (RF_FAM == 60 || RF_FAM == 61)
271 extern const UWORD8 drp_ref_sw[] ;
272 extern T_DRP_REGS_STR *drp_regs;
273 extern T_DRP_SRM_API* drp_srm_api;
274
275 extern T_DRP_SW_DATA drp_sw_data_calib;
276 extern T_DRP_SW_DATA drp_sw_data_init;
277
278 #endif
279
280 /*-------------------------------------------------------*/
281 /* l1_dsp_init() */
282 /*-------------------------------------------------------*/
283 /* Parameters : */
284 /* Return : */
285 /* Functionality : */
286 /*-------------------------------------------------------*/
287 void l1_dsp_init(void)
288 {
289 //int i;-OMAPS90550- new
290 #if (CODE_VERSION == SIMULATION)
291 // L1S <-> DSP communication...
292 //====================================================
293 l1s_dsp_com.dsp_ndb_ptr = &(buf.ndb);
294 l1s_dsp_com.dsp_db_r_ptr = &(buf.mcu_rd[0]);
295 l1s_dsp_com.dsp_db_w_ptr = &(buf.mcu_wr[0]);
296 l1s_dsp_com.dsp_param_ptr = &(buf.param);
297 l1s_dsp_com.dsp_w_page = 0;
298 l1s_dsp_com.dsp_r_page = 0;
299 l1s_dsp_com.dsp_r_page_used = 0;
300
301 #if (L1_GPRS)
302 l1ps_dsp_com.pdsp_ndb_ptr = &(buf.ndb_gprs);
303 l1ps_dsp_com.pdsp_db_r_ptr = &(buf.mcu_rd_gprs[0]);
304 l1ps_dsp_com.pdsp_db_w_ptr = &(buf.mcu_wr_gprs[0]);
305 l1ps_dsp_com.pdsp_param_ptr = &(buf.param_gprs);
306 #endif
307
308 // Reset DSP page bit and DSP enable bit...
309 //====================================================
310 l1s_tpu_com.reg_cmd->dsp_enb_bit = OFF;
311 l1s_tpu_com.reg_cmd->dsp_pag_bit = 0;
312
313 // Set EOTD bit if required
314 //====================================================
315 #if (L1_EOTD ==1)
316 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
317 #endif
318
319
320 #else // NO SIMULATION
321
322 // L1S <-> DSP communication...
323 //====================================================
324 l1s_dsp_com.dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
325 l1s_dsp_com.dsp_db_r_ptr = (T_DB_DSP_TO_MCU *) DB_R_PAGE_0;
326 l1s_dsp_com.dsp_db_w_ptr = (T_DB_MCU_TO_DSP *) DB_W_PAGE_0;
327 l1s_dsp_com.dsp_param_ptr = (T_PARAM_MCU_DSP *) PARAM_ADR;
328 l1s_dsp_com.dsp_w_page = 0;
329 l1s_dsp_com.dsp_r_page = 0;
330 l1s_dsp_com.dsp_r_page_used = 0;
331
332 #if (DSP == 38) || (DSP == 39)
333 l1s_dsp_com.dsp_db_common_w_ptr = (T_DB_COMMON_MCU_TO_DSP *)DB_COMMON_W_PAGE_0;
334 #endif
335
336 /* DSP CPU load measurement */
337 #if (DSP == 38) || (DSP == 39)
338 l1s_dsp_com.dsp_cpu_load_db_w_ptr = (T_DB_MCU_TO_DSP_CPU_LOAD *)DSP_CPU_LOAD_DB_W_PAGE_0;
339 (*((volatile UWORD16 *)(DSP_CPU_LOAD_MCU_W_CTRL))) = (API)0x0001; // enable DSP CPU load measurement
340 #endif
341
342 #if (L1_GPRS)
343 l1ps_dsp_com.pdsp_ndb_ptr = (T_NDB_MCU_DSP_GPRS *) NDB_ADR_GPRS;
344 l1ps_dsp_com.pdsp_db_r_ptr = (T_DB_DSP_TO_MCU_GPRS *) DB_R_PAGE_0_GPRS;
345 l1ps_dsp_com.pdsp_db_w_ptr = (T_DB_MCU_TO_DSP_GPRS *) DB_W_PAGE_0_GPRS;
346 l1ps_dsp_com.pdsp_param_ptr = (T_PARAM_MCU_DSP_GPRS *) PARAM_ADR_GPRS;
347 #endif
348
349 #if (DSP_DEBUG_TRACE_ENABLE == 1)
350 l1s_dsp_com.dsp_db2_current_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_0;
351 l1s_dsp_com.dsp_db2_other_r_ptr = (T_DB2_DSP_TO_MCU *) DB2_R_PAGE_1;
352 #endif
353
354 // Reset DSP page bit and DSP enable bit...
355 //====================================================
356
357 (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) &= ~TPU_CTRL_D_ENBL;
358
359 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
360 l1s_dsp_com.dsp_ndb_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
361 #else
362 l1s_dsp_com.dsp_param_ptr->d_dsp_page = l1s_dsp_com.dsp_w_page;
363 #endif
364
365 // NDB init : Reset buffers and set flags...
366 //====================================================
367 l1s_dsp_com.dsp_ndb_ptr->d_fb_mode = FB_MODE_1;
368 l1s_dsp_com.dsp_ndb_ptr->d_fb_det = FALSE; // D_FB_DET =0
369 l1s_dsp_com.dsp_ndb_ptr->a_cd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
370 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[0] = 0; // BLUD = 0
371 l1s_dsp_com.dsp_ndb_ptr->a_dd_0[2] = 0xffff; // NERR = 0xffff
372 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[0] = 0; // BLUD = 0
373 l1s_dsp_com.dsp_ndb_ptr->a_dd_1[2] = 0xffff; // NERR = 0xffff
374 l1s_dsp_com.dsp_ndb_ptr->a_du_0[0] = 0; // BLUD = 0
375 l1s_dsp_com.dsp_ndb_ptr->a_du_0[2] = 0xffff; // NERR = 0xffff
376 l1s_dsp_com.dsp_ndb_ptr->a_du_1[0] = 0; // BLUD = 0
377 l1s_dsp_com.dsp_ndb_ptr->a_du_1[2] = 0xffff; // NERR = 0xffff
378 l1s_dsp_com.dsp_ndb_ptr->a_fd[0] = (1<<B_FIRE1); // B_FIRE1 =1, B_FIRE0 =0 , BLUD =0
379 l1s_dsp_com.dsp_ndb_ptr->a_fd[2] = 0xffff; // NERR = 0xffff
380 l1s_dsp_com.dsp_ndb_ptr->d_a5mode = 0;
381
382 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11))
383 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode = 0x0800; // Analog base band selected = Nausica, Iota, Syren (bit 11)
384 #endif
385
386 #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
387 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits - 4) & 0x000F) << 7); //Bit 7..10: guard bits
388 #endif
389 #if (ANLG_FAM == 11)
390 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= (((l1_config.params.guard_bits) & 0x000F) << 7); //Bit 7..10: guard bits
391 #endif
392
393 #if (DSP == 32)
394 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= 0x2;
395 #endif // OP_WCP
396
397 l1s_dsp_com.dsp_ndb_ptr->a_sch26[0] = (1<<B_SCH_CRC);// B_SCH_CRC =1, BLUD =0
398 l1audio_dsp_init();
399
400 #if IDS
401 l1s_dsp_com.dsp_ndb_ptr->d_ra_conf = 0; // IDS
402 l1s_dsp_com.dsp_ndb_ptr->d_ra_act = 0; // IDS
403 l1s_dsp_com.dsp_ndb_ptr->d_ra_test = 0; // IDS
404 l1s_dsp_com.dsp_ndb_ptr->d_ra_statu = 0; // IDS
405 l1s_dsp_com.dsp_ndb_ptr->d_ra_statd = 0; // IDS
406 l1s_dsp_com.dsp_ndb_ptr->d_fax = 0; // IDS
407 #endif
408
409 #if(RF_FAM != 61)
410 // interrupt rif TX on FIFO <= threshold with threshold = 0
411 l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179;
412 #else
413 // l1s_dsp_com.dsp_ndb_ptr->d_spcx_rif = 0x179; TBD put hte replacement here... Danny
414
415 #endif
416
417 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
418 // Initialize V42b variables
419 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego0 = 0;
420 l1s_dsp_com.dsp_ndb_ptr->d_v42b_nego1 = 0;
421 l1s_dsp_com.dsp_ndb_ptr->d_v42b_control = 0;
422 l1s_dsp_com.dsp_ndb_ptr->d_v42b_ratio_ind = 0;
423 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control = 0;
424 l1s_dsp_com.dsp_ndb_ptr->d_mcu_control_sema = 0;
425
426 #if !(W_A_DSP_SR_BGD)
427 // Initialize background control variable to No background. Background tasks can be launch in GPRS
428 // as in GSM.
429 l1s_dsp_com.dsp_ndb_ptr->d_max_background = 0;
430 #endif
431
432 #if (L1_GPRS)
433 #if (DSP == 36) || (DSP == 37)
434 // Initialize GEA module
435 l1ps_dsp_com.pdsp_ndb_ptr->d_gea_mode = 0;
436 #endif
437 #endif
438
439 #else
440 #if (L1_GPRS)
441 // Initialize background control variable to No background
442 l1ps_dsp_com.pdsp_ndb_ptr->d_max_background = 0;
443 #endif
444 #endif
445
446 #if (L1_GPRS)
447 l1ps_dsp_com.pdsp_ndb_ptr->d_sched_mode_gprs = GSM_SCHEDULER;
448
449 // Initialize the poll response buffer to "no poll request"
450 l1ps_dsp_com.pdsp_ndb_ptr->a_pu_gprs[0][0] = CS_NONE_TYPE;
451 #else // L1_GPRS
452 #if ((DSP == 31) || (DSP == 32) || (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39))
453 l1s_dsp_com.dsp_ndb_ptr->d_sched_mode_gprs_ovly = GSM_SCHEDULER;
454 #endif
455 #endif // L1_GPRS
456
457 // Set EOTD bit if required
458 //=============================================
459 #if (L1_EOTD ==1)
460 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_EOTD;
461 #endif // L1_EOTD
462
463 #if (DSP == 33)
464 #if DCO_ALGO
465 // Set DCO bit
466 if (l1_config.params.dco_enabled == TRUE)
467 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
468 #endif
469 #endif
470
471 // DCO algo in case of DSP 17/32
472 #if (DCO_ALGO == 1)
473 #if ((DSP == 17)||(DSP == 32))
474 l1s_dsp_com.dsp_ndb_ptr->d_tch_mode |= B_DCO_ON;
475 #endif // DSP
476 #endif // DCO_ALGO
477
478 #if ((DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38)) || (DSP == 39)
479 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[0] = 0;
480 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[1] = 0;
481 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[2] = 0;
482 l1s_dsp_com.dsp_ndb_ptr->a_amr_config[3] = 0;
483 #endif
484
485 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
486 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_afs = 400; // thresh detection ONSET AFS
487 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_first_afs = 150; // thresh detection SID_FIRST AFS
488 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_afs = 450; // thresh detection RATSCCH AFS
489 l1s_dsp_com.dsp_ndb_ptr->d_thr_update_afs = 300; // thresh detection SID_UPDATE AFS
490 l1s_dsp_com.dsp_ndb_ptr->d_thr_onset_ahs = 200; // thresh detection ONSET AHS
491 l1s_dsp_com.dsp_ndb_ptr->d_thr_sid_ahs = 150; // thresh detection SID frames AHS
492 l1s_dsp_com.dsp_ndb_ptr->d_thr_ratscch_marker = 500; // thresh detection RATSCCH MARKER
493 l1s_dsp_com.dsp_ndb_ptr->d_thr_sp_dgr = 3; // thresh detection SPEECH DEGRADED/NO_DATA
494 l1s_dsp_com.dsp_ndb_ptr->d_thr_soft_bits = 0; // thresh detection SPEECH DEGRADED/NO_DATA
495 #endif
496
497 #if ((DSP==36 || (DSP == 37) || (DSP == 38) || (DSP == 39))&&(W_A_AMR_THRESHOLDS==1))
498 // init of the afs thresholds parameters
499 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[0]=0;
500 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[1]=0;
501 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[2]=0;
502 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[3]=0;
503 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[4]=0;
504 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[5]=0;
505 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[6]=0;
506 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_afs[7]=1950;
507
508 // init of the ahs thresholds parameters
509 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[0]=1500;
510 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[1]=1500;
511 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[2]=1500;
512 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[3]=1500;
513 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[4]=1500;
514 l1s_dsp_com.dsp_ndb_ptr->a_d_macc_thr_ahs[5]=1500;
515 #endif
516
517 // init of of the threshold for USF detection
518 #if (L1_FALSE_USF_DETECTION == 1)
519 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 2300;
520 #else
521 l1s_dsp_com.dsp_ndb_ptr->d_thr_usf_detect = 0;
522 #endif
523
524 #if (CHIPSET == 12) || (CHIPSET == 15)
525 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
526 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0;
527 #endif
528 #endif
529
530 #if ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1))) // Calypso+ or Perseus2 or locosto
531 #if (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
532 // Note: for locosto there is only one MCSI port
533 l1s_dsp_com.dsp_ndb_ptr->d_mcsi_select = MCSI_PORT1;
534 #endif
535
536 #if(DSP == 36) || (DSP == 37)
537 l1s_dsp_com.dsp_ndb_ptr->d_vol_ul_level = 0x1000;
538 l1s_dsp_com.dsp_ndb_ptr->d_vol_dl_level = 0x1000;
539 l1s_dsp_com.dsp_ndb_ptr->d_vol_speed = 0x68;
540 l1s_dsp_com.dsp_ndb_ptr->d_sidetone_level = 0;
541 #endif
542 #endif // ((CHIPSET == 15) || (CHIPSET == 12) || (CHIPSET == 4) || ((CHIPSET == 10) && (OP_WCP == 1)))
543
544 // DB Init DB : Reset all pages, set TX power and reset SCH buffer...
545 //====================================================
546 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_0);
547 l1s_reset_db_mcu_to_dsp((T_DB_MCU_TO_DSP *) DB_W_PAGE_1);
548 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_0);
549 l1s_reset_db_dsp_to_mcu((T_DB_DSP_TO_MCU *) DB_R_PAGE_1);
550 #if (DSP == 38) || (DSP == 39)
551 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_0);
552 l1s_reset_db_common_mcu_to_dsp((T_DB_COMMON_MCU_TO_DSP *) DB_COMMON_W_PAGE_1);
553 #endif
554
555 #endif // NO_SIMULATION
556
557 #if ((DSP==17)||(DSP == 32))
558 // init the DC offset values
559 l1s_dsp_com.dsp_ndb_ptr->d_dco_type = 0x0000; // Tide off
560 l1s_dsp_com.dsp_ndb_ptr->p_start_IQ = 0x0000;
561 l1s_dsp_com.dsp_ndb_ptr->d_level_off = 0x0000;
562 l1s_dsp_com.dsp_ndb_ptr->d_dco_dbg = 0x0000;
563 l1s_dsp_com.dsp_ndb_ptr->d_tide_resa = 0x0000;
564 #endif
565
566 //Initialize DSP DCO
567 #if (((DSP == 38) || (DSP == 39)) && (RF_FAM == 61))
568 l1s_dsp_com.dsp_ndb_ptr->d_dco_samples_per_symbol = C_DCO_SAMPLES_PER_SYMBOL;
569 l1s_dsp_com.dsp_ndb_ptr->d_dco_fcw = C_DCO_FCW;
570
571 // APCDEL1 will be initialized on rach only ....
572 l1s_dsp_com.dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1;
573 l1s_dsp_com.dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
574 // APCCTRL2 alone initialize on the next TDMA frame possible
575 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2);
576
577 l1dapc_init_ramp_tables();
578
579 #if ((FF_REPEATED_SACCH == 1) || (FF_REPEATED_DL_FACCH == 1 ))
580
581 /* Chase combining feature flag Initialise */
582 l1s_dsp_com.dsp_ndb_ptr->d_chase_comb_ctrl |= 0x0001;
583 #endif /* FF_REPEATED_SACCH or FF_REPEATED_DL_FACCH */
584
585 #endif // DSP == 38
586
587 // Intialize the AFC
588 #if (DSP == 38) || (DSP == 39)
589 #if (CODE_VERSION != SIMULATION)
590 l1s_dsp_com.dsp_ndb_ptr->d_drp_afc_add_api = C_DRP_DCXO_XTAL_DSP_ADDRESS;
591 #endif
592 #endif
593
594 #if (L1_DRP_IQ_SCALING == 1)
595 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 1;
596 #else
597 l1s_dsp_com.dsp_ndb_ptr->d_dsp_iq_scaling_factor = 0;
598 #endif
599
600 }
601
602 /*-------------------------------------------------------*/
603 /* l1_tpu_init() */
604 /*-------------------------------------------------------*/
605 /* Parameters : */
606 /* Return : */
607 /* Functionality : */
608 /*-------------------------------------------------------*/
609 void l1_tpu_init(void)
610 {
611 #if (CODE_VERSION == SIMULATION)
612 // L1S -> TPU communication...
613 //=============================
614 l1s_tpu_com.tpu_w_page = 0;
615 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
616 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd);
617 l1s_tpu_com.reg_com_int = &(hw.reg_com_int);
618 l1s_tpu_com.offset = &(hw.offset);
619
620 // Reset TPU.
621 //=============================
622 *(l1s_tpu_com.offset) = 0;
623 *(l1s_tpu_com.reg_com_int) = 0;
624 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF;
625 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
626 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF;
627 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF;
628 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
629
630 // Init. OFFSET and SYNC registers
631 //================================
632 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active
633 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT
634 l1dtpu_end_scenario(); // Close TPU scenario
635
636 #else
637 // bit TPU_RESET set
638 // OFFSET and SYNCHRO initialized at 0
639 // TSP_ACT bits reset
640 // Sleep added and TPU_ENABLE set...
641 l1dmacro_init_hw();
642
643 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL;
644 #endif
645 }
646
647 void l1_tpu_init_light(void)
648 {
649 #if (CODE_VERSION == SIMULATION)
650 // L1S -> TPU communication...
651 //=============================
652 l1s_tpu_com.tpu_w_page = 0;
653 l1s_tpu_com.tpu_page_ptr = &(tpu.buf[l1s_tpu_com.tpu_w_page].line[0]);
654 l1s_tpu_com.reg_cmd = (T_reg_cmd*) &(hw.reg_cmd);
655 l1s_tpu_com.reg_com_int = &(hw.reg_com_int);
656 l1s_tpu_com.offset = &(hw.offset);
657
658 // Reset TPU.
659 //=============================
660 *(l1s_tpu_com.offset) = 0;
661 *(l1s_tpu_com.reg_com_int) = 0;
662 l1s_tpu_com.reg_cmd->tpu_idle_bit = OFF;
663 l1s_tpu_com.reg_cmd->tpu_enb_bit = OFF;
664 l1s_tpu_com.reg_cmd->tpu_stat_bit = OFF;
665 l1s_tpu_com.reg_cmd->tpu_reset_bit = OFF;
666 l1s_tpu_com.reg_cmd->tpu_pag_bit = 0;
667
668 // Init. OFFSET and SYNC registers
669 //================================
670 l1s_tpu_com.reg_cmd->tpu_reset_bit = ON; // bit TPU_RESET active
671 l1dmacro_synchro(IMM, 0); // OFFSET=SYNCHRO=0 without any AT
672 l1dtpu_end_scenario(); // Close TPU scenario
673
674 #else
675 // bit TPU_RESET set
676 // OFFSET and SYNCHRO initialized at 0
677 // TSP_ACT bits reset
678 // Sleep added and TPU_ENABLE set...
679 l1dmacro_init_hw_light();
680
681 l1s_tpu_com.reg_cmd = (UWORD16 *) TPU_CTRL;
682 #endif
683 }
684
685 /*-------------------------------------------------------*/
686 /* l1_abb_power_on() */
687 /*-------------------------------------------------------*/
688 /* Parameters : */
689 /* Return : */
690 /* Functionality : */
691 /* Initialize the global structure for spi communication */
692 /* with ABB. */
693 /* Set up ABB connection (CLK 13M free) */
694 /* Aknowledge the ABB status register */
695 /* Configure ABB modules */
696 /* Program the ramp parameters into the NDB */
697 /* Load in the NDB registers' value to be programmed in */
698 /* ABB at first communication it */
699 /*-------------------------------------------------------*/
700
701 //Locosto This funciton would change drastically due to Triton introduction and instead of SPI we have i2c
702 void l1_abb_power_on(void)
703 {
704 #if (CODE_VERSION != SIMULATION)
705 #if (CHIPSET == 12)
706 T_SPI_DEV *Abb;
707 T_SPI_DEV init_spi_device;
708 UWORD16 Abb_Status;
709 T_NDB_MCU_DSP * dsp_ndb_ptr;
710
711 Abb = &init_spi_device; /* Pointer initialization to device communication structure */
712 Abb->PrescVal = SPI_CLOCK_DIV_1; /* ABB transmission parameters initialization */
713 Abb->DataTrLength = SPI_WNB_15;
714 Abb->DevAddLength = 5;
715 Abb->DevId = ABB;
716 Abb->ClkEdge = SPI_CLK_EDG_RISE;
717 Abb->TspEnLevel = SPI_NTSPEN_NEG_LEV;
718 Abb->TspEnForm = SPI_NTSPEN_LEV_TRIG;
719
720 SPI_InitDev(Abb); /* Initialize the spi to work with ABB */
721
722 ABB_free_13M(); /* Set up Abb connection (CLK 13M free).*/
723 Abb_Status = ABB_Read_Status(); /* Aknowledge the Abb status register. */
724
725 /*------------------------------------------------------------------*/
726 /* Add here SW to manage Abb VRPCSTS status register informations */
727 /*------------------------------------------------------------------*/
728
729 ABB_Read_Register_on_page(PAGE0,ITSTATREG); /* Aknowledge the interrupt status register */
730 /* to clear any pending interrupt */
731
732 ABB_on(AFC | MADC, l1a_l1s_com.recovery_flag);
733
734 // ADC init: Configuration of the channels to be converted and enable the ADC Interrupt
735 ABB_Conf_ADC(ALL,EOC_INTENA);
736
737 //in case of reset due to a recovery process do not create the HISR
738 if (l1a_l1s_com.recovery_flag == FALSE)
739 {
740 Create_ABB_HISR();
741 }
742
743 // Load RAMP up/down in NDB memory...
744 dsp_ndb_ptr = (T_NDB_MCU_DSP *) NDB_ADR;
745
746 if (l1_config.tx_pwr_code == 0)
747 {
748 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp,
749 0 /* not used */,
750 0 /* not used */,
751 1 /* arbitrary value for arfcn*/);
752 }
753 else
754 {
755 Cust_get_ramp_tab(dsp_ndb_ptr->a_ramp,
756 5 /* arbitrary value working in any case */,
757 5 /* arbitrary value working in any case */,
758 1 /* arbitrary value for arfcn*/);
759 }
760 #endif
761
762
763 #if (ANLG_FAM == 1)
764 // Omega registers values will be programmed at 1st DSP communication interrupt
765
766 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
767 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
768 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
769 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
770 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
771 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
772 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
773 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
774 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
775 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
776 dsp_ndb_ptr->d_vbctrl = l1_config.params.vbctrl; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
777
778 // APCDEL1 will be initialized on rach only ....
779 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
780
781 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
782 // To increase the robustness the IOTA register are reseted to 0
783 // if OMEGA, NAUSICA is used
784 dsp_ndb_ptr->d_bulgcal = 0x0000;
785 dsp_ndb_ptr->d_vbctrl2 = 0x0000;
786 dsp_ndb_ptr->d_apcdel2 = 0x0000;
787 #endif
788 #endif
789 #if (ANLG_FAM == 2)
790 // Iota registers values will be programmed at 1st DSP communication interrupt
791
792 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
793 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
794 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
795 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
796 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
797 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset
798 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
799 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
800 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
801 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
802 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
803 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0, VDLAUX=1, VDLEAR=1.
804 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0
805
806 // APCDEL1 will be initialized on rach only ....
807 dsp_ndb_ptr->d_apcdel1 =l1_config.params.apcdel1;
808 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
809 #endif
810 #if (ANLG_FAM == 3)
811 // Syren registers values will be programmed at 1st DSP communication interrupt
812
813 dsp_ndb_ptr->d_debug1 = l1_config.params.debug1; // Enable f_tx delay of 400000 cyc DEBUG
814 dsp_ndb_ptr->d_afcctladd = l1_config.params.afcctladd; // Value at reset
815 dsp_ndb_ptr->d_vbuctrl = l1_config.params.vbuctrl; // Uplink gain amp 0dB, Sidetone gain to mute
816 dsp_ndb_ptr->d_vbdctrl = l1_config.params.vbdctrl; // Downlink gain amp 0dB, Volume control 0 dB
817 dsp_ndb_ptr->d_bbctrl = l1_config.params.bbctrl; // value at reset
818 dsp_ndb_ptr->d_bulgcal = l1_config.params.bulgcal; // value at reset
819 dsp_ndb_ptr->d_apcoff = l1_config.params.apcoff; // value at reset
820 dsp_ndb_ptr->d_bulioff = l1_config.params.bulioff; // value at reset
821 dsp_ndb_ptr->d_bulqoff = l1_config.params.bulqoff; // value at reset
822 dsp_ndb_ptr->d_dai_onoff = l1_config.params.dai_onoff; // value at reset
823 dsp_ndb_ptr->d_auxdac = l1_config.params.auxdac; // value at reset
824 dsp_ndb_ptr->d_vbctrl1 = l1_config.params.vbctrl1; // VULSWITCH=0
825 dsp_ndb_ptr->d_vbctrl2 = l1_config.params.vbctrl2; // MICBIASEL=0, VDLHSO=0, MICAUX=0
826
827 // APCDEL1 will be initialized on rach only ....
828 dsp_ndb_ptr->d_apcdel1 = l1_config.params.apcdel1;
829 dsp_ndb_ptr->d_apcdel2 = l1_config.params.apcdel2;
830
831 // Additional registers management brought by SYREN
832 dsp_ndb_ptr->d_vbpop = l1_config.params.vbpop; // HSOAUTO enabled only
833 dsp_ndb_ptr->d_vau_delay_init = l1_config.params.vau_delay_init; // vaud_init_delay init 2 frames
834 dsp_ndb_ptr->d_vaud_cfg = l1_config.params.vaud_cfg; // Init to zero
835 dsp_ndb_ptr->d_vauo_onoff = l1_config.params.vauo_onoff; // Init to zero
836 #if ((L1_AUDIO_MCU_ONOFF == 1)&&(OP_L1_STANDALONE == 1)&&(CHIPSET == 12))
837 ABB_Write_Register_on_page(PAGE1, VAUOCTRL, 0x0015A);
838 #endif // E Sample testing of audio on off
839 dsp_ndb_ptr->d_vaus_vol = l1_config.params.vaus_vol; // Init to zero
840 dsp_ndb_ptr->d_vaud_pll = l1_config.params.vaud_pll; // Init to zero
841 dsp_ndb_ptr->d_togbr2 = 0; // TOGBR2 initial value handled by the DSP (this value doesn't nake any sense)
842
843 #endif
844
845 #if (ANLG_FAM == 11)
846 // The following settings need to be done only in L1 StandALoen as PSP would
847 // do in the case of full PS Build...
848
849 //Set the CTRL3 register
850 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
851 l1_config.params.ctrl3,NULL);
852
853 #if (OP_L1_STANDALONE == 1)
854 // THESE REGISTERS ARE INITIALIZED IN STANDALONE AND PS BUILDS FOR AUDIO PATH
855
856 // ************ START REG INIT FOR PS build/STANDALONE *************
857 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_TOGB_OFFSET,
858 0x15,NULL);
859 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VULGAIN_OFFSET,
860 l1_config.params.vulgain,NULL);
861 //Set the VDLGAIN register
862 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_VDLGAIN_OFFSET,
863 l1_config.params.vdlgain,NULL);
864 //Set the SIDETONE register
865 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_SIDETONE_OFFSET,
866 l1_config.params.sidetone,NULL);
867 //Set the CTRL1 register
868 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL1_OFFSET,
869 l1_config.params.ctrl1,NULL);
870 //Set the CTRL2 register
871 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL2_OFFSET,
872 l1_config.params.ctrl2,NULL);
873
874 //Set the CTRL4 register
875 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL4_OFFSET,
876 l1_config.params.ctrl4,NULL);
877 //Set the CTRL5 register
878 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL5_OFFSET,
879 l1_config.params.ctrl5,NULL);
880 //Set the CTRL6 register
881 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_CTRL6_OFFSET,
882 l1_config.params.ctrl6,NULL);
883 //Set the POPAUTO register
884 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_POPAUTO_OFFSET,
885 l1_config.params.popauto,NULL);
886
887 // ************ END REG INIT FOR PS build/STANDALONE ****************
888
889
890
891 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
892 l1_config.params.outen1,NULL);
893 //Set the OUTEN2 register
894 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
895 l1_config.params.outen2,NULL);
896 //Set the OUTEN3 register
897 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
898 l1_config.params.outen3,NULL);
899
900
901
902 //Set the AUDLGAIN register
903 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDLGAIN_OFFSET,
904 l1_config.params.aulga,NULL);
905 //Set the AUDRGAIN register
906 BspTwl3029_I2c_WriteSingle(BSP_TWL3029_I2C_AUD,BSP_TWL_3029_MAP_AUDIO_AUDRGAIN_OFFSET,
907 l1_config.params.aurga,NULL);
908 #endif
909
910
911 #if (OP_L1_STANDALONE == 1)
912 #if (L1_MADC_ON == 1)
913 //MADC Real time initialization for all the 11 ADCs
914 bspTwl3029_Madc_enableRt( NULL, 0x7ff, l1a_madc_callback, &l1_madc_results);
915 #endif
916 #endif
917
918 #endif
919 #endif //CODE_VERSION != SIMULATION
920 }
921
922 /*-------------------------------------------------------*/
923 /* l1_pwr_mgt_init() */
924 /*-------------------------------------------------------*/
925 /* Parameters : */
926 /* ------------- */
927 /* Return : */
928 /* ------------- */
929 /* Description : */
930 /* ------------- */
931 /* This routine is used to initialize the gauging */
932 /* related variables. */
933 /*-------------------------------------------------------*/
934 void l1_pwr_mgt_init(void)
935 {
936
937 //++++++++++++++++++++++++++++++++++++++++++
938 // Power management variables
939 //++++++++++++++++++++++++++++++++++++++++++
940
941 // flags for wake-up ....
942 l1s.pw_mgr.Os_ticks_required = FALSE;
943 l1s.pw_mgr.frame_adjust = FALSE;
944 l1s.pw_mgr.wakeup_time = 0;
945
946 // variables for sleep ....
947 l1s.pw_mgr.sleep_duration = 0;
948 l1s.pw_mgr.sleep_performed = DO_NOT_SLEEP;
949 l1s.pw_mgr.modules_status = 0; // all clocks ON
950 l1s.pw_mgr.paging_scheduled = FALSE;
951
952 // variable for afc bypass mode
953 l1s.pw_mgr.afc_bypass_mode = AFC_BYPASS_MODE;
954
955 // 32 Khz gauging ....
956 l1s.pw_mgr.gaug_count = 0;
957 l1s.pw_mgr.enough_gaug = FALSE;
958 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
959 l1s.force_gauging_next_paging_due_to_CCHR = 0;
960 l1s.pw_mgr.gauging_task = INACTIVE;
961
962 // GAUGING duration
963 #if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
964 if (l1_config.dpll <8 )
965 l1s.pw_mgr.gaug_duration = 9; // 9 frames (no more CTRL with DSP)
966 else // with a dpll >= 104Mhz the HF counter is too small: gauging limitation to 6 frames.
967 #if(CHIPSET == 15)
968 // Gauging duration could be reduced to 4 frames (from 5 frames) as fast paging (FF_L1_FAST_DECODING) is available
969 l1s.pw_mgr.gaug_duration = 4; // 4 frames
970 #else
971 l1s.pw_mgr.gaug_duration = 6; // 6 frames
972 #endif
973 #else
974 l1s.pw_mgr.gaug_duration = 11; // 1CTRL + 9 frames +1CTRL
975 #endif
976
977
978 //-------------------------------------------------
979 // INIT state:
980 // 32.768Khz is in the range [-500 ppm,+100 ppm]
981 // due to temperature variation.
982 // LF_100PPM = 32.7712768 Khz
983 // LF_500PPM = 32.751616 Khz
984 //
985 // ACQUIS STATE :
986 // 32.768Khz variations allowed from INIT value
987 // are [-50 ppm,+50ppm]. Same delta on ideal 32khz
988 // during 9 frames (gauging duration) represents 1348*T32.
989 // LF_50PPM = 32.7696384 Khz
990 // 1348/32.768 - 1348/32.7696384 = 0.002056632 ms
991 // At 78 Mhz it means : 0.002056632ms/0.000012820513ms= 160 T
992 //
993 // UPDATE state :
994 // allowed variations are [-6 ppm,+6ppm] jitter
995 // LF_6PPM = 32.76819661 Khz
996 // 1348/32.768 - 1348/32.76819661 = 0.00024691 ms
997 // At 78 Mhz it means : 0.00024691 / 0.000012820513ms= 19 T
998 //
999 // 78 Mhz 65 Mhz 84.5 Mhz
1000 // ===========================
1001 // C_CLK_MIN 2380 1983 2578
1002 // C_CLK_INIT_MIN 8721 29113 31293
1003 // C_CLK_MAX 2381 1984 2580
1004 // C_CLK_INIT_MAX 36823 41608 1662
1005 // C_DELTA_HF_ACQUIS 160 130 173
1006 // C_DELTA_HF_UPDATE 19 15 20
1007 //-------------------------------------------------
1008 #if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
1009 l1s.pw_mgr.c_clk_min = C_CLK_MIN;
1010 l1s.pw_mgr.c_clk_init_min = C_CLK_INIT_MIN;
1011 l1s.pw_mgr.c_clk_max = C_CLK_MAX;
1012 l1s.pw_mgr.c_clk_init_max = C_CLK_INIT_MAX;
1013 l1s.pw_mgr.c_delta_hf_acquis = C_DELTA_HF_ACQUIS;
1014 l1s.pw_mgr.c_delta_hf_update = C_DELTA_HF_UPDATE;
1015 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1016 // 78000/32.7712768 = 2380.13308
1017 l1s.pw_mgr.c_clk_min = (UWORD32)((l1_config.dpll*MCUCLK)/LF_100PPM);
1018 // 0.13308*2^16
1019 l1s.pw_mgr.c_clk_init_min =(UWORD32) ((UWORD32)((UWORD32)(((UWORD32)(l1_config.dpll*MCUCLK))-
1020 (l1s.pw_mgr.c_clk_min*LF_100PPM))*
1021 65536)/LF_100PPM); //omaps00090550
1022
1023 // 78000/32.751616 = 2381.561875
1024 l1s.pw_mgr.c_clk_max = (UWORD32)((l1_config.dpll*MCUCLK)/LF_500PPM); //omaps00090550
1025 // 0.561875*2^16
1026 l1s.pw_mgr.c_clk_init_max =(UWORD32)((UWORD32)(((double)(l1_config.dpll*MCUCLK)-
1027 (double)(l1s.pw_mgr.c_clk_max*LF_500PPM))*
1028 65536)/LF_500PPM);//omaps00090550
1029
1030 // remember hf is expressed in nbr of clock in hz (ex 65Mhz,104Mhz)
1031 l1s.pw_mgr.c_delta_hf_acquis =(UWORD32) (((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_50PPM))*(l1_config.dpll*MCUCLK));//omaps00090550
1032 l1s.pw_mgr.c_delta_hf_update =(UWORD32)( ((GAUG_IN_32T/LF)-(GAUG_IN_32T/LF_6PPM ))*(l1_config.dpll*MCUCLK));//omaps00090550
1033 #endif
1034
1035 } /* l1_pwr_mgt_init() */
1036
1037 /*-------------------------------------------------------*/
1038 /* l1_initialize_var() */
1039 /*-------------------------------------------------------*/
1040 /* Parameters : */
1041 /* ------------- */
1042 /* Return : */
1043 /* ------------- */
1044 /* Description : */
1045 /* ------------- */
1046 /* This routine is used to initialize the l1a, l1s and */
1047 /* l1a_l1s_com global structures. */
1048 /*-------------------------------------------------------*/
1049 void l1_initialize_var(void)
1050 {
1051 UWORD32 i;
1052 UWORD8 task_id;
1053
1054 //++++++++++++++++++++++++++++++++++++++++++
1055 // Power management variables
1056 //++++++++++++++++++++++++++++++++++++++++++
1057 l1_pwr_mgt_init();
1058
1059 //++++++++++++++++++++++++++++++++++++++++++
1060 // Reset "l1s" structure.
1061 //++++++++++++++++++++++++++++++++++++++++++
1062
1063 // time counter used for debug and by L3 scenario...
1064 l1s.debug_time = 0;
1065
1066 // L1S tasks management...
1067 //-----------------------------------------
1068 for(task_id=0; task_id<NBR_DL_L1S_TASKS; task_id++)
1069 {
1070 if (!((task_id == ADC_CSMODE0) && (l1a_l1s_com.recovery_flag != FALSE)))
1071 {
1072 l1s.task_status[task_id].new_status = NOT_PENDING;
1073 l1s.task_status[task_id].current_status = INACTIVE;
1074 }
1075 }
1076 l1s.frame_count = 0;
1077 l1s.forbid_meas = 0;
1078 #if L1_GPRS
1079 l1s.tcr_prog_done=0;
1080 #endif
1081 #if (AUDIO_DEBUG == 1)
1082 audio_reg_read_status=0;
1083 #endif
1084 // MFTAB management variables...
1085 //-----------------------------------------
1086 l1s.afrm = 0;
1087 l1s_clear_mftab(l1s.mftab.frmlst);
1088
1089 // Controle parameters... (miscellaneous)
1090 //-----------------------------------------
1091 #if (RF_FAM != 61)
1092 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>3); //F13.3 -> F16.0
1093 #endif
1094 #if (RF_FAM == 61)
1095 l1s.afc = ((WORD16)l1_config.params.eeprom_afc>>2); //F13.3 -> F14.0
1096 #endif
1097
1098
1099 l1s.afc_frame_count = 0;
1100
1101 #if (TOA_ALGO == 2)
1102 l1s.toa_var.toa_shift = ISH_INVALID;
1103 l1s.toa_var.toa_snr_mask = 0;
1104 l1s.toa_var.toa_frames_counter = 0;
1105 l1s.toa_var.toa_accumul_counter = 0;
1106 l1s.toa_var.toa_accumul_value = 0;
1107 l1s.toa_var.toa_update_fn = 0;
1108 l1s.toa_var.toa_update_flag = FALSE;
1109 #else
1110 l1s.toa_shift = ISH_INVALID;
1111 l1s.toa_snr_mask = 0;
1112 #if L1_GPRS
1113 l1s.toa_period_count = 0;
1114 l1s.toa_update = FALSE;
1115 #endif
1116 #endif
1117
1118 #if (L1_GPRS == 1)
1119 l1s.algo_change_synchro_active = FALSE;
1120 #endif
1121
1122 #if (L1_RF_KBD_FIX == 1)
1123 l1s.total_kbd_on_time = 5000;
1124 l1s.correction_ratio = 1;
1125 #endif
1126 /* Initialising the repeated SACCH variables */
1127 #if (FF_REPEATED_SACCH == 1 )
1128 l1s.repeated_sacch.srr = 0;/* SACCH Repetiton Request */
1129 l1s.repeated_sacch.sro = 0;/* SACCH Repetiton Order */
1130 l1s.repeated_sacch.buffer_empty = TRUE;
1131 #endif /* FF_REPEATED_SACCH ==1*/
1132
1133 #if (FF_REPEATED_DL_FACCH == 1)
1134 l1s.repeated_facch.pipeline[0].buffer_empty=l1s.repeated_facch.pipeline[1].buffer_empty=TRUE;
1135 l1s.repeated_facch.counter_candidate=0;
1136 l1s.repeated_facch.counter=1;
1137 #endif/* (FF_REPEATED_DL_FACCH == 1) */
1138
1139 // Init the spurious_fb_detected flag
1140 l1s.spurious_fb_detected = FALSE;
1141
1142 // Flag registers for RF task controle...
1143 //-----------------------------------------
1144 l1s.tpu_ctrl_reg = 0;
1145 l1s.dsp_ctrl_reg = 0;
1146
1147 // Serving...
1148 //============
1149
1150 // Serving frame number management.
1151 //---------------------------------
1152 if (l1a_l1s_com.recovery_flag == FALSE)
1153 {
1154 l1s.actual_time.tc = 0;
1155 l1s.actual_time.fn = 0;
1156 l1s.actual_time.t1 = 0;
1157 l1s.actual_time.t2 = 0;
1158 l1s.actual_time.t3 = 0;
1159 l1s.actual_time.fn_in_report = 0;
1160 l1s.actual_time.fn_mod42432 = 0;
1161
1162 l1s.next_time.tc = 0;
1163 l1s.next_time.fn = 0;
1164 l1s.next_time.t1 = 0;
1165 l1s.next_time.t2 = 0;
1166 l1s.next_time.t3 = 0;
1167 l1s.next_time.fn_in_report = 0;
1168 l1s.next_time.fn_mod42432 = 0;
1169
1170 #if L1_GPRS
1171 l1s.actual_time.block_id = 0;
1172 l1s.next_time.block_id = 0;
1173 l1s.next_plus_time = l1s.next_time;
1174 l1s_increment_time(&(l1s.next_plus_time),1);
1175 l1s.ctrl_synch_before = FALSE;
1176 l1s.next_gauging_scheduled_for_PNP= 0;
1177 #endif
1178 }
1179
1180 // TXPWR management.
1181 //-------------------
1182 l1s.reported_txpwr = 0;
1183 l1s.applied_txpwr = 0;
1184
1185 // Last RXQUAL value.
1186 //-------------------
1187 l1s.rxqual = 0;
1188
1189 // Hardware info.
1190 //---------------
1191 l1s.tpu_offset = 0;
1192 l1s.tpu_offset_hw = 0;
1193
1194 l1s.tpu_win = 0;
1195
1196 // Initialize TXPWR info.
1197 l1s.last_used_txpwr = NO_TXPWR;
1198
1199 #if (AMR == 1)
1200 // Reset DTX AMR status
1201 //---------------------
1202 l1s.dtx_amr_dl_on=FALSE;
1203 #endif
1204
1205 // Code version structure
1206 //-------------------------
1207
1208 // DSP versions & checksum
1209 l1s.version.dsp_code_version = 0;
1210 l1s.version.dsp_patch_version = 0;
1211 l1s.version.dsp_checksum = 0; // checksum patch+code DSP
1212
1213 l1s.version.mcu_tcs_program_release = PROGRAM_RELEASE_VERSION;
1214 l1s.version.mcu_tcs_internal = INTERNAL_VERSION;
1215 l1s.version.mcu_tcs_official = MAINTENANCE_VERSION;
1216
1217 #if TESTMODE
1218 l1s.version.mcu_tm_version = TESTMODEVERSION;
1219 #else
1220 l1s.version.mcu_tm_version = 0;
1221 #endif
1222
1223 //++++++++++++++++++++++++++++++++++++++++++
1224 // Reset "l1a" structure.
1225 //++++++++++++++++++++++++++++++++++++++++++
1226
1227 // Downlink tasks management...
1228 // Uplink tasks management...
1229 // Measurement tasks management...
1230 //-----------------------------------------
1231
1232 if (l1a_l1s_com.recovery_flag == FALSE)
1233 {
1234 for(i=0; i<NBR_L1A_PROCESSES; i++)
1235 {
1236 l1a.l1a_en_meas[i] = 0;
1237 l1a.state[i] = 0; // RESET state.
1238 }
1239 }
1240 else
1241 {
1242 // L1A state for full list meas has to be maintained in case of recovery
1243 for(i=0; i<NBR_L1A_PROCESSES; i++)
1244 {
1245 if ((i != FULL_MEAS) && (i!= I_ADC))
1246 {
1247 l1a.l1a_en_meas[i] = 0;
1248 l1a.state[i] = 0; // RESET state.
1249 }
1250 }
1251 }
1252
1253 l1a.confirm_SignalCode = 0;
1254
1255 // Flag for forward/delete message management.
1256 //---------------------------------------------
1257 if (l1a_l1s_com.recovery_flag == FALSE)
1258 {
1259 l1a.l1_msg_forwarded = 0;
1260 }
1261
1262 #if (L1_VOCODER_IF_CHANGE == 1)
1263 // Reset new vocoder interface L1A global variables: automatic disabling and vocoder enabling flag.
1264 l1a.vocoder_state.automatic_disable = FALSE;
1265 l1a.vocoder_state.enabled = FALSE;
1266 #endif // if L1_VOCODER_IF_CHANGE == 1
1267 //++++++++++++++++++++++++++++++++++++++++++
1268 // Reset "l1a_l1s_com" structure.
1269 //++++++++++++++++++++++++++++++++++++++++++
1270
1271 l1a_l1s_com.l1a_activity_flag = TRUE;
1272 l1a_l1s_com.time_to_next_l1s_task = 0;
1273
1274 // Serving Cell...
1275 //=================
1276
1277 // Serving Cell identity and information.
1278 //---------------------------------------
1279 l1a_reset_cell_info(&(l1a_l1s_com.Scell_info));
1280
1281 l1a_l1s_com.Smeas_dedic.acc_sub = 0;
1282 l1a_l1s_com.Smeas_dedic.nbr_meas_sub = 0;
1283 l1a_l1s_com.Smeas_dedic.qual_acc_full = 0;
1284 l1a_l1s_com.Smeas_dedic.qual_acc_sub = 0;
1285 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_full = 0;
1286 l1a_l1s_com.Smeas_dedic.qual_nbr_meas_sub = 0;
1287 l1a_l1s_com.Smeas_dedic.dtx_used = 0;
1288
1289 #if REL99
1290 #if FF_EMR
1291 // Serving Cell identity EMR information.
1292 //---------------------------------------
1293 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_acc = 0;
1294 l1a_l1s_com.Smeas_dedic_emr.rxlev_val_nbr_meas = 0;
1295 l1a_l1s_com.Smeas_dedic_emr.nbr_rcvd_blocks = 0;
1296 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_acc = 0;
1297 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_acc = 0;
1298 l1a_l1s_com.Smeas_dedic_emr.mean_bep_block_num = 0;
1299 l1a_l1s_com.Smeas_dedic_emr.cv_bep_block_num = 0;
1300
1301 #endif
1302 #endif
1303
1304
1305 l1a_l1s_com.Scell_used_IL.input_level = l1_config.params.il_min;
1306 l1a_l1s_com.Scell_used_IL_d.input_level = l1_config.params.il_min;
1307 l1a_l1s_com.Scell_used_IL_dd.input_level = l1_config.params.il_min;
1308
1309 l1a_l1s_com.Scell_used_IL.lna_off = FALSE;
1310 l1a_l1s_com.Scell_used_IL_d.lna_off = FALSE;
1311 l1a_l1s_com.Scell_used_IL_dd.lna_off = FALSE;
1312
1313 // Synchro information.
1314 //---------------------------------------
1315 l1a_l1s_com.tn_difference = 0;
1316 l1a_l1s_com.dl_tn = 0;
1317 #if L1_FF_WA_OMAPS00099442
1318 l1a_l1s_com.change_tpu_offset_flag = FALSE;
1319 #endif
1320
1321 #if L1_GPRS
1322 l1a_l1s_com.dsp_scheduler_mode = GSM_SCHEDULER;
1323 #endif
1324
1325 // Idle parameters.
1326 //-----------------
1327 l1a_l1s_com.nbcchs.schedule_array_size=0;
1328 l1a_l1s_com.ebcchs.schedule_array_size=0;
1329 l1a_l1s_com.bcchn.current_list_size=0;
1330 l1a_l1s_com.nsync.current_list_size=0;
1331
1332 #if (GSM_IDLE_RAM != 0)
1333 l1s.gsm_idle_ram_ctl.l1s_full_exec = TRUE;
1334
1335 #if GSM_IDLE_RAM_DEBUG
1336 #if (CHIPSET == 10) && (OP_WCP == 1)
1337 l1s.gsm_idle_ram_ctl.TC_true_control=0;
1338 #endif // CHIPSET && OP_WCP
1339 #endif // GSM_IDLE_RAM_DEBUG
1340 #endif // GSM_IDLE_RAM
1341
1342 #if (L1_12NEIGH ==1)
1343 for (i=0;i<NBR_NEIGHBOURS+1;i++)
1344 #else
1345 for (i=0;i<6;i++)
1346 #endif
1347 {
1348 l1a_l1s_com.nsync.list[i].status=NSYNC_FREE;
1349 }
1350 for (i=0;i<6;i++)
1351 {
1352 l1a_l1s_com.bcchn.list[i].status=NSYNC_FREE;
1353 }
1354
1355 // EOTD variables
1356 #if (L1_EOTD==1)
1357 l1a_l1s_com.nsync.eotd_meas_session=FALSE;
1358 l1a_l1s_com.nsync.fn_sb_serv;
1359 l1a_l1s_com.nsync.ta_sb_serv;
1360 #endif
1361
1362 // CBCH parameters.
1363 // ----------------
1364 // nothing to reset.
1365
1366 // Random Access information.
1367 // ----------------------------
1368 // nothing to reset.
1369
1370 // ADC management
1371 //---------------
1372 if (l1a_l1s_com.recovery_flag == FALSE)
1373 l1a_l1s_com.adc_mode = ADC_DISABLED;
1374
1375 // TXPWR management.
1376 //-------------------
1377 #if(L1_FF_MULTIBAND == 0)
1378 l1a_l1s_com.powerclass_band1 = 0;
1379 l1a_l1s_com.powerclass_band2 = 0;
1380 #else
1381 for( i = 0; i< (NB_MAX_SUPPORTED_BANDS); i++)
1382 {
1383 l1a_l1s_com.powerclass[i] = 0;
1384 }
1385 #endif
1386
1387 // Dedicated parameters.
1388 //----------------------
1389 l1a_l1s_com.dedic_set.aset = NULL;
1390 l1a_l1s_com.dedic_set.fset = NULL;
1391 l1a_l1s_com.dedic_set.SignalCode = 0;
1392 l1a_l1s_com.dedic_set.sync_tch = 0;
1393 l1a_l1s_com.dedic_set.stop_tch = 0;
1394 l1a_l1s_com.dedic_set.reset_facch = FALSE;
1395 #if (FF_L1_TCH_VOCODER_CONTROL)
1396 l1a_l1s_com.dedic_set.reset_sacch = FALSE;
1397 #if (L1_VOCODER_IF_CHANGE == 0)
1398 l1a_l1s_com.dedic_set.vocoder_on = TRUE;
1399 #if (W_A_DSP_PR20037 == 1)
1400 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_ENABLE_REQ;
1401 #else // W_A_DSP_PR20037 == 0
1402 l1a_l1s_com.dedic_set.start_vocoder = FALSE;
1403 #endif // W_A_DSP_PR20037
1404 #else // L1_VOCODER_IF_CHANGE
1405 l1a_l1s_com.dedic_set.vocoder_on = FALSE;
1406 l1a_l1s_com.dedic_set.start_vocoder = TCH_VOCODER_RESET_COMMAND;
1407 #endif // L1_VOCODER_IF_CHANGE
1408 #endif // FF_L1_TCH_VOCODER_CONTROL
1409
1410 l1a_l1s_com.dedic_set.radio_freq = 0;
1411 l1a_l1s_com.dedic_set.radio_freq_d = 0;
1412 l1a_l1s_com.dedic_set.radio_freq_dd = 0;
1413 #if ((REL99 == 1) && (FF_BHO == 1))
1414 // blind handover params in dedic set
1415 // Initialize the handover type to default value that is Normal Handover.
1416 l1a_l1s_com.dedic_set.handover_type = 0;
1417 l1a_l1s_com.dedic_set.long_rem_handover_type = 0;
1418 l1a_l1s_com.dedic_set.bcch_carrier_of_nbr_cell = 0;
1419 l1a_l1s_com.dedic_set.fn_offset = 0;
1420 l1a_l1s_com.dedic_set.time_alignment = 0;
1421 #endif
1422
1423 #if (L1_12NEIGH ==1)
1424 for (i=0;i<NBR_NEIGHBOURS+1;i++)
1425 #else
1426 for (i=0;i<6;i++)
1427 #endif
1428 {
1429 l1a_l1s_com.nsync.list[i].sb26_offset = 0;
1430 }
1431
1432 l1a_l1s_com.dedic_set.pwrc = 0;
1433 l1a_l1s_com.dedic_set.handover_fail_mode = FALSE;
1434 #if (AMR == 1)
1435 l1a_l1s_com.dedic_set.sync_amr = FALSE;
1436 #endif
1437
1438 // Handover parameters.
1439 //---------------------
1440 // nothing to reset.
1441
1442 // Neighbour Cells...
1443 //====================
1444
1445 // FULL list.
1446 //-----------
1447 l1a_reset_full_list();
1448
1449 // BA list.
1450 //---------
1451 l1a_reset_ba_list();
1452 l1a_l1s_com.ba_list.new_list_present = FALSE;
1453
1454 #if L1_GPRS
1455 // Packet measurement: Reset of the frequency list.
1456 //-------------------------------------------------
1457 l1pa_reset_cr_freq_list();
1458 #endif
1459
1460 // L1S scheduler...
1461 //====================
1462
1463 // L1S tasks management...
1464 //-----------------------------------------
1465 {
1466 UWORD8 mem;
1467 mem = l1a_l1s_com.l1s_en_task[ADC_CSMODE0];
1468
1469 for(i=0; i<NBR_DL_L1S_TASKS; i++)
1470 {
1471 l1a_l1s_com.task_param[i] = SEMAPHORE_RESET;
1472 l1a_l1s_com.l1s_en_task[i] = TASK_DISABLED;
1473 }
1474
1475 // in case of recovery do not change the ADC initialization
1476 if (l1a_l1s_com.recovery_flag != FALSE)
1477 l1a_l1s_com.l1s_en_task[ADC_CSMODE0] = mem;
1478 }
1479
1480 // Measurement tasks management...
1481 //-----------------------------------------
1482 l1a_l1s_com.meas_param = 0;
1483 l1a_l1s_com.l1s_en_meas = 0;
1484
1485 // L1 mode...
1486 //-----------------------------------------
1487 if (l1a_l1s_com.recovery_flag == FALSE) // do not restart from CS_MODE0 after a recovery
1488 l1a_l1s_com.mode = CS_MODE0;
1489
1490 // Control algo variables.
1491 //-----------------------------------------
1492 l1a_l1s_com.fb_mode = 0;
1493 l1a_l1s_com.toa_reset = FALSE;
1494
1495 #if(L1_FF_MULTIBAND == 0)
1496 for(i=0; i<=l1_config.std.nbmax_carrier; i++)
1497 #else
1498 for(i=0; i<= NBMAX_CARRIER; i++)
1499 #endif
1500 {
1501 l1a_l1s_com.last_input_level[i].input_level = l1_config.params.il_min;
1502 l1a_l1s_com.last_input_level[i].lna_off = FALSE;
1503 }
1504
1505 #if FF_L1_IT_DSP_DTX
1506 // Fast DTX variables.
1507 //-----------------------------------------
1508 // Clear DTX interrupt condition
1509 l1a_apihisr_com.dtx.pending = FALSE;
1510 // Enable TX activity
1511 l1a_apihisr_com.dtx.tx_active = TRUE;
1512 // No DTX status awaited
1513 l1a_apihisr_com.dtx.dtx_status = DTX_AVAILABLE;
1514 // Fast DTX service latency timer
1515 l1a_apihisr_com.dtx.fast_dtx_ready_timer = 0;
1516 // Fast DTX service available
1517 l1a_apihisr_com.dtx.fast_dtx_ready = FALSE;
1518 #endif
1519 #if L1_RECOVERY
1520 l1s.recovery.frame_count = 0;
1521 #endif
1522
1523 #if (AUDIO_TASK == 1)
1524 l1audio_initialize_var();
1525 #endif
1526
1527 #if (L1_GTT == 1)
1528 l1gtt_initialize_var();
1529 #endif
1530
1531 #if (L1_MP3 == 1)
1532 l1mp3_initialize_var();
1533 #endif
1534
1535 #if (L1_MIDI == 1)
1536 l1midi_initialize_var();
1537 #endif
1538 //ADDED FOR AAC
1539 #if (L1_AAC == 1)
1540 l1aac_initialize_var();
1541 #endif
1542 #if (L1_DYN_DSP_DWNLD == 1)
1543 l1_dyn_dwnld_initialize_var();
1544 #endif
1545 #if (FF_L1_FAST_DECODING == 1)
1546 l1a_apihisr_com.fast_decoding.pending = FALSE;
1547 l1a_apihisr_com.fast_decoding.crc_error = FALSE;
1548 l1a_apihisr_com.fast_decoding.status = 0;
1549 l1a_apihisr_com.fast_decoding.deferred_control_req = FALSE;
1550 l1a_apihisr_com.fast_decoding.task = 0;
1551 l1a_apihisr_com.fast_decoding.burst_id = 0;
1552 l1a_apihisr_com.fast_decoding.contiguous_decoding = FALSE;
1553 #endif /* FF_L1_FAST_DECODING */
1554
1555
1556 #if(L1_CHECK_COMPATIBLE == 1)
1557 l1a.vcr_wait = FALSE;
1558 l1a.stop_req = FALSE;
1559 l1a.vcr_msg_param = TRUE;
1560 l1a.vch_auto_disable = FALSE;
1561
1562 #endif
1563
1564
1565 }
1566
1567
1568 /*---------------------------------------------------------*/
1569 /* l1_dpll_init_var() */
1570 /*---------------------------------------------------------*/
1571 /* Parameters : None */
1572 /* Return : None */
1573 /* Functionality : Initialize L1 DPLL variable for gauging */
1574 /* processing */
1575 /*---------------------------------------------------------*/
1576 void l1_dpll_init_var(void) {
1577
1578 #if (CODE_VERSION != SIMULATION)
1579 // Init DPLL variable
1580 //===================
1581 #if (CHIPSET == 2 || CHIPSET == 3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9)
1582 l1_config.dpll=PLL;
1583 #elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
1584 {
1585 UWORD16 dpll_div;
1586 UWORD16 dpll_mul;
1587 #if (CHIPSET == 12)
1588 // not required for Locosto: There is NO CNTL_CLK_DSP in Locosto
1589 double dsp_div = CLKM_GET_DSP_DIV_VALUE;
1590 #endif
1591
1592 dpll_div=DPLL_READ_DPLL_DIV;
1593 dpll_mul=DPLL_READ_DPLL_MUL;
1594
1595 #if (CHIPSET == 12)
1596 // Not required for locsto due to the reason mentioned above.
1597 l1_config.dpll= ((double)(dpll_mul)/(double)(dpll_div+1))/(double)(dsp_div);
1598 #else
1599 l1_config.dpll= (double)(dpll_mul)/(double)(dpll_div+1);
1600 #endif
1601 }
1602 #endif
1603 #endif
1604
1605 } /* l1_dpll_init_var() */
1606
1607 /*-------------------------------------------------------------*/
1608 /* FUNCTION: l1_drp_wrapper_init */
1609
1610 /*-------------------------------------------------------------*/
1611
1612 void l1_drp_wrapper_init (void)
1613 {
1614 #if(RF_FAM == 61)
1615 l1ddsp_apc_load_apcctrl2(l1_config.params.apcctrl2);
1616 #endif
1617
1618 }
1619
1620 /*-------------------------------------------------------------*/
1621 /* FUNCTION: l1_drp_init */
1622 /* Params: Void */
1623 /*
1624 Functionality: This function does the following
1625 1. Initialize Misc variables wrt DRP
1626 2a Copy the RAMP Tables into the DSP MCU API
1627 2b. Initialize other APIs wrt DCO
1628 3. Download Reference Software
1629 4. Call the function to : Start the REG_ON Script in the DRP
1630 */
1631 /*-------------------------------------------------------------*/
1632
1633 #if (L1_DRP == 1)
1634 #if (DRP_FW_EXT==1)
1635 #pragma DATA_SECTION(l1_drp_int_mem, ".drp_ptr")
1636 void * l1_drp_int_mem;
1637 #pragma DATA_SECTION(l1_drp_ext_mem, ".drp_ptr")
1638 void *l1_drp_ext_mem;
1639 #endif
1640 void l1_drp_init()
1641 {
1642 //int i;- OMAPS90550-new
1643 #if (DRP_FW_EXT==1)
1644 uint32 size_int=0;
1645 uint32 size_ext=0;
1646 #endif
1647 #if (RF_FAM == 61)
1648 volatile UWORD16 *ptr_drp_init16;
1649 UWORD16 drp_maj_version;
1650 UWORD16 drp_min_version;
1651
1652 //Initialize the following SRM_API, REG related address drp_srm_data = DRP_SRM_DATA_ADD,
1653 //drp_regs = DRP_REGS_BASE_ADD;, drp_srm_api = DRP_SRM_API_ADD
1654
1655 drp_api_addr_init();
1656
1657 #if (DRP_FW_EXT==1)
1658 drp_maj_version = (drp_ref_sw_ver >> 8) & 0xFF;
1659 drp_min_version = (drp_ref_sw_ver & 0xFF);
1660 #endif
1661
1662 //Initialize the following variables... TBD Danny
1663 //SRM_CW = 0x00000040, IRQ_CNT= 0x00000040 , TX_PTR_START_END_ADDR = 0X00200025,
1664 //RX_PTR_START_END_ADDR = 0X0000001F , 0XFFFE0806= 16
1665 //The registers are 32 bit since its a RHEA peripheral has to be writtin in 16 bit writes
1666 // This is done by the DRP script download
1667
1668 // The counter for # of DRP_DBB_RX_IRQs (in the wrapper) to be masked
1669 ptr_drp_init16 = (UWORD16 *) (DRP_DBB_RX_IRQ_MASK);
1670 (*ptr_drp_init16) = DRP_DBB_RX_IRQ_COUNT;
1671
1672 #endif //RF_FAM == 61
1673 l1s.boot_result=0;
1674 #if (DRP_FW_EXT==1)
1675 if(!((drp_min_version >= L1_DRP_COMPAT_MINOR_VER) && (drp_maj_version == L1_DRP_COMPAT_MAJOR_VER))) {
1676 l1s.boot_result = 1;
1677 return;
1678 }
1679 drp_get_memory_size(&size_int,&size_ext);
1680 /* FIXME FIXME ERROR handling for memory allocation failure */
1681 if(size_int)
1682 {
1683 l1_drp_int_mem=os_alloc_sig(size_int);
1684 if(l1_drp_int_mem==NULL)
1685 {
1686 /*FIXME Error Handling Here */
1687 l1s.boot_result = 1;
1688 return;
1689 }
1690 }
1691 if(size_ext)
1692 {
1693 l1_drp_ext_mem=os_alloc_sig(size_ext);
1694
1695 if(l1_drp_ext_mem==NULL)
1696 {
1697 /*FIXME Error Handling Here */
1698 l1s.boot_result = 1;
1699 return;
1700 }
1701 }
1702
1703 // Populate pointers
1704 if(drpfw_init(&modem_func_jump_table,&modem_var_jump_table))
1705 {
1706 // This condition should not be reached in phase 1 of DRP FW
1707 // Extraction. DRP and L1 software should always be compatible
1708 l1s.boot_result = 1;
1709 return;
1710 }
1711
1712 ((T_DRP_ENV_INT_BLK *)l1_drp_int_mem)->g_pcb_config = RF_BAND_SYSTEM_INDEX; //OMAPS148175
1713
1714 #endif // DRP_FW_EXT==1
1715 // This function would takes care of drp_ref_sw download till that is in place this would be a dummy function
1716 // Testing PLD_WriteRegister(0x0440, 0x165c);
1717 #if (RF_FAM == 60) // PLD board
1718 // for PLD board script downloading will happen through USP driver
1719 // load ref_sw_main
1720 // drp_ref_sw_upload(drp_ref_sw);
1721 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw);
1722 #elif (RF_FAM == 61) // Locosto based board
1723 // load ref_sw_main
1724 // drp_ref_sw_upload(drp_ref_sw); // TBD replace with DRP Copy function...
1725 drp_copy_ref_sw_to_drpsrm( (unsigned char *) drp_ref_sw);
1726 #endif
1727
1728 #if (L1_DRP_DITHERING == 1)
1729 (*(volatile UINT8 *)CONF_MUX_VIEW8) = 0x01;
1730 (*(volatile UINT8 *)CONF_DEBUG_SEL_TST_8) = 0x07;
1731 (*(volatile UINT8 *)CONF_GPIO_17) = 0x02;
1732 (*(volatile UINT8 *)CONF_LOCOSTO_DEBUG) = 0x00;
1733 #endif
1734
1735 }
1736 #endif // L1_DRP
1737
1738 /*-------------------------------------------------------*/
1739 /* l1_initialize() */
1740 /*-------------------------------------------------------*/
1741 /* Parameters : */
1742 /* Return : */
1743 /* Functionality : */
1744 /*-------------------------------------------------------*/
1745 void l1_initialize(T_MMI_L1_CONFIG *mmi_l1_config)
1746 {
1747 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4) || (TRACE_TYPE == 5)
1748 l1_trace_init();
1749 #endif
1750
1751 // this is not a recovery initialization .
1752 l1a_l1s_com.recovery_flag = FALSE;
1753
1754 // initialize the ratio of the wait loop
1755 // must be initialized before using the wait_ARM_cycles() function !!!
1756 #if (CODE_VERSION != SIMULATION)
1757 initialize_wait_loop();
1758 #endif
1759
1760 // Init Layer 1 configuration
1761 //===========================
1762 #if(L1_FF_MULTIBAND == 0)
1763 l1_config.std.id = mmi_l1_config->std;
1764 #endif
1765
1766 l1_config.tx_pwr_code = mmi_l1_config->tx_pwr_code;
1767 #if IDS
1768 l1_config.ids_enable = mmi_l1_config->ids_enable;
1769 #endif
1770 l1_config.facch_test.enable = mmi_l1_config->facch_test.enable;
1771 l1_config.facch_test.period = mmi_l1_config->facch_test.period;
1772 l1_config.dwnld = mmi_l1_config->dwnld;
1773
1774 #if TESTMODE
1775 // Initialize TestMode params: must be done after Omega power-on
1776 l1_config.TestMode = FALSE;
1777 // Enable control algos and ADC
1778 l1_config.agc_enable = 1;
1779 l1_config.afc_enable = 1;
1780 l1_config.adc_enable = 1;
1781 #if (FF_REPEATED_SACCH == 1)
1782 l1_config.repeat_sacch_enable = 1; /* Repeated SACCH mode enabled */
1783 #endif /* (FF_REPEATED_SACCH == 1) */
1784 #if (FF_REPEATED_DL_FACCH == 1)
1785 l1_config.repeat_facch_dl_enable = 1; /* Repeated SACCH mode enabled */
1786 #endif /* ( FF_REPEATED_DL_FACCH == 1) */
1787 #endif
1788
1789 // sleep management configuration
1790 //===============================
1791 l1s.pw_mgr.mode_authorized = mmi_l1_config->pwr_mngt_mode_authorized;
1792 l1s.pw_mgr.clocks = mmi_l1_config->pwr_mngt_clocks;
1793 l1_config.pwr_mngt = mmi_l1_config->pwr_mngt;
1794
1795 Cust_init_std();
1796 Cust_init_params();
1797
1798
1799
1800 // Init DPLL variable
1801 //===================
1802 l1_dpll_init_var();
1803
1804 // Reset hardware (DSP,Analog Baseband device , TPU) ....
1805 //========================================================
1806 #if (CODE_VERSION != SIMULATION)
1807 dsp_power_on();
1808 l1_abb_power_on();
1809 #if (L1_DRP == 1)
1810 l1_drp_init();
1811 //required for interworking with Isample 2.1 and Isample 2.5
1812 #if (DRP_FW_EXT == 1)
1813 if (!l1s.boot_result)
1814 {
1815 #endif
1816 //for DRP Calibration
1817 Cust_init_params_drp();
1818 drp_efuse_init();
1819 #if (DRP_FW_EXT == 1)
1820 } /* end if boot_result != 0 */
1821 #endif
1822
1823 #endif
1824
1825 #endif
1826
1827 // Initialize hardware....(DSP, TPU)....
1828 //=================================================
1829 l1_tpu_init();
1830 l1_dsp_init();
1831
1832 // Initialize L1 variables (l1a, l1s, l1a_l1s_com).
1833 //=================================================
1834 l1_initialize_var();
1835
1836 // API check function
1837 #if ((OP_L1_STANDALONE == 1) && ((DSP == 38) || (DSP == 39)) && (CODE_VERSION != SIMULATION))
1838 l1_api_dump();
1839 #endif
1840
1841 #if (L1_GPRS)
1842 // Initialize L1 variables used in packet mode (l1pa, l1ps, l1pa_l1ps_com).
1843 //========================================================================
1844 initialize_l1pvar();
1845 #endif
1846
1847 // Initialize statistics mode.......
1848 //=================================================
1849 #if TRACE_TYPE==3
1850 reset_stats();
1851 #endif
1852 #if(OP_L1_STANDALONE == 1 || L1_NAVC == 1 )//NAVC
1853 Cust_navc_ctrl_status(1);//start - NAVC
1854 #endif//end of (OP_L1_STANDALONE == 1 || L1_NAVC == 1 )
1855
1856 }
1857
1858 /*-------------------------------------------------------*/
1859 /* l1_initialize_for_recovery */
1860 /*-------------------------------------------------------*/
1861 /* Parameters : */
1862 /* Return : */
1863 /* Functionality : This function is called for L1 */
1864 /* recovery after a Crash. When there are 100 COM error */
1865 /* or if ther are 100 PM =0 from the DSP Successively. */
1866 /* The Layer 1 Crashes. The next time the Protocol stack */
1867 /* requests for Full Rx Measurement (viz Cell selection) */
1868 /* This function gets called and the L1 recovery is */
1869 /* initiated. */
1870 /*-------------------------------------------------------*/
1871 #if L1_RECOVERY
1872 void l1_initialize_for_recovery(void)
1873 {
1874 LA_ResetLead(); // set DSP in reset mode
1875 initialize_wait_loop();
1876
1877 dsp_power_on(); // the reset mode is disabled here
1878 l1_abb_power_on();
1879 #if (L1_DRP == 1)
1880 l1_drp_init();
1881 //Required for interworking with Isample 2.1 and Isample 2.5
1882 Cust_init_params_drp();
1883 drp_efuse_init();
1884 #endif
1885 l1_tpu_init();
1886 wait_ARM_cycles(convert_nanosec_to_cycles(11000000)); // wait of 5.5 msec
1887 l1_dsp_init();
1888 l1_initialize_var();
1889
1890 #if L1_GPRS
1891 initialize_l1pvar();
1892 #endif
1893
1894 l1a_l1s_com.recovery_flag = FALSE;
1895
1896 // clear pending IQ_FRAME it and enable it
1897 #if (CHIPSET >= 4 )
1898 #if (CHIPSET == 12) || (CHIPSET == 15)
1899 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
1900 #else
1901 * (volatile UWORD16 *) INTH_IT_REG1 &= ~(1 << IQ_FRAME); // clear TDMA IRQ
1902 #endif
1903 #else
1904 * (volatile UWORD16 *) INTH_IT_REG &= ~(1 << IQ_FRAME); // clear TDMA IRQ
1905 #endif
1906
1907 }
1908 #endif
1909
1910
1911