FreeCalypso > hg > freecalypso-sw

comparison gsm-fw/L1/cfile/l1_pwmgr.c @ 544:96a96ec34139

Find changesets by keywords (author, files, the commit message), revision number or hash, or revset expression.
gsm-fw/L1/cfile: initial import from LoCosto source
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 03 Aug 2014 06:06:45 +0000
parents
children 67ab5f240b7d
comparison
equal deleted inserted replaced
543:2dccd2b4e5a2 544:96a96ec34139
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_PWMGR.C
4 *
5 * Filename l1_pwmgr.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9 // pinghua add these programe code section to put some sleep code into internal ram.
10 #pragma CODE_SECTION(l1s_sleep_manager,".emifconf")
11 #pragma CODE_SECTION(EMIF_SetConfReg,".emifconf")
12 #pragma CODE_SECTION(audio_madc_sleep,".emifconf")
13 #pragma CODE_SECTION(Check_Peripheral_App,".emifconf")
14 #pragma CODE_SECTION(DBB_Configure_DS,".emifconf")
15 #pragma CODE_SECTION(DBB_Wakeup_DS,".emifconf")
16 #pragma CODE_SECTION(l1ctl_pgm_clk32,".emifconf")
17 #pragma CODE_SECTION(l1ctl_gauging,".emifconf")
18 #pragma CODE_SECTION(GAUGING_Handler,".emifconf")
19 #pragma CODE_SECTION(l1s_get_HWTimers_ticks,".emifconf")
20 #pragma CODE_SECTION(l1s_adapt_traffic_controller,".emifconf")
21 #pragma CODE_SECTION(l1s_wakeup,".emifconf")
22 #pragma CODE_SECTION(l1s_wakeup_adjust,".emifconf")
23 #pragma CODE_SECTION(l1s_compute_wakeup_ticks,".emifconf")
24 #pragma CODE_SECTION(l1s_recover_Frame,".emifconf")
25 #pragma CODE_SECTION(l1s_recover_HWTimers,".emifconf")
26 #pragma CODE_SECTION(l1s_get_next_gauging_in_Packet_Idle,".emifconf")
27 #pragma CODE_SECTION(l1s_gauging_decision_with_PNP,".emifconf")
28 #pragma CODE_SECTION(l1s_gauging_decision_with_NP,".emifconf")
29 #pragma CODE_SECTION(l1s_gauging_task,".emifconf")
30 #pragma CODE_SECTION(l1s_gauging_task_end,".emifconf")
31 // 2-03-2007 pinghua added end
32 #define L1_PWMGR_C
33 //#pragma DUPLICATE_FOR_INTERNAL_RAM_START
34
35 //sajal added .....................................
36 #if (CODE_VERSION == SIMULATION)
37 //#include "l1_pwmgr.h"
38 //omaps00090550 #303 warning removal typedef unsigned char UWORD_8;
39
40 // typedef volatile unsigned short REG_UWORD16; //omaps00090550
41 // #define REG16(A) (*(REG_UWORD16*)(A)) //omaps00090550
42 // typedef volatile unsigned short REGISTER_UWORD16; //omaps00090550
43
44 #define MAP_ULPD_REG 0xFFFE2000 //ULPD registers start address (CS4)
45 #define ULPD_SETUP_CLK13_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 14))
46 #define ULPD_SETUP_SLICER_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 15))
47 #define ULPD_SETUP_VTCXO_REG (*(REGISTER_UWORD16*)((REGISTER_UWORD16 *)(MAP_ULPD_REG) + 16))
48
49 #define MAP_CLKM_REG 0xFFFFFD00 //CLOCKM registers start address (CS31)
50 #define CLKM_CNTL_CLK_OFFSET 0x02
51 #define CLKM_CNTL_CLK_REG REG16 (MAP_CLKM_REG + CLKM_CNTL_CLK_OFFSET)
52
53 #define EMIF_CONFIG_PWD_POS 0
54 #define EMIF_CONFIG_PDE_POS 1
55 #define EMIF_CONFIG_PREFETCH_POS 3
56 #define EMIF_CONFIG_FLUSH_PREFETCH_POS 5
57 #define EMIF_CONFIG_WP_POS 6
58
59 #define EMIF_CONFIG REG16(EMIF_CONFIG_BASE_ADDR+EMIF_CONFIG_REG_OFFSET)
60 #define EMIF_CONFIG_BASE_ADDR 0xFFFFFB00 //External Memory inter registers address (CS31) (NEW)
61 #define EMIF_CONFIG_REG_OFFSET 0x02 // Emif configuration register
62
63 #endif
64 //sajal added till here......
65
66
67
68 #include "timer/timer2.h"
69 #include "armio/armio.h"
70
71 //omaps00090550 #include "l1_macro.h"
72 #include "l1_confg.h"
73
74 #if (OP_L1_STANDALONE == 1)
75 #include "uart/serialswitch_core.h"
76 #else
77 #include "uart/serialswitch.h"
78 #endif
79
80 #if (OP_L1_STANDALONE == 0)
81 #include "sim/sim.h"
82 #include "rv_swe.h"
83 #endif
84
85
86 #if (CODE_VERSION == SIMULATION)
87 #include "l1_types.h"
88 #include "l1_const.h"
89
90 #if (CHIPSET == 12) || (CHIPSET == 15)
91 #include "inth/sys_inth.h"
92 #include "sys_dma.h"
93 #include "ulpd.h"
94 #include "clkm.h"
95
96 // typedef volatile unsigned short REG_UWORD16; //omaps00090550
97 #define REG16(A) (*(REG_UWORD16*)(A))
98
99 #else
100 #include "inth/iq.h"
101 #endif
102
103 #if TESTMODE
104 #include "l1tm_defty.h"
105 #endif // TESTMODE
106
107 #if (AUDIO_TASK == 1)
108 #include "l1audio_const.h"
109 #include "l1audio_cust.h"
110 #include "l1audio_defty.h"
111 #endif // AUDIO_TASK
112
113 #if (L1_GTT == 1)
114 #include "l1gtt_const.h"
115 #include "l1gtt_defty.h"
116 #endif
117
118 #if (L1_MP3 == 1)
119 #include "l1mp3_defty.h"
120 #endif
121
122 #if (L1_MIDI == 1)
123 #include "l1midi_defty.h"
124 #endif
125 //ADDED FOR AAC
126 #if (L1_AAC == 1)
127 #include "l1aac_defty.h"
128 #endif
129 #include "l1_defty.h"
130 #include "l1_varex.h"
131 #include "l1_tabs.h"
132 #include "cust_os.h"
133 #include "l1_msgty.h"
134 #include "l1_proto.h"
135 #include "ulpd.h"
136 #include "l1_trace.h"
137
138 #if L1_GPRS
139 #include "l1p_cons.h"
140 #include "l1p_msgt.h"
141 #include "l1p_deft.h"
142 #include "l1p_vare.h"
143 #endif // L1_GPRS
144
145 #include <stdio.h>
146 #include "sim_cfg.h"
147 #include "sim_cons.h"
148 #include "sim_def.h"
149 #include "sim_var.h"
150 //omaps00090550
151 #include "nucleus.h"
152
153 extern NU_TASK L1S_task;
154 STATUS status;
155
156
157
158 #else // NO SIMULATION
159
160
161
162 #include "l1_types.h"
163 #include "l1_const.h"
164
165 #include "abb/abb.h"
166 #include "dma/sys_dma.h"
167
168 #if (OP_BT == 1)
169 #include "hci_ll_simul.h"
170 #endif
171
172 #if TESTMODE
173 #include "l1tm_defty.h"
174 #endif // TESTMODE
175
176 #if (AUDIO_TASK == 1)
177 #include "l1audio_const.h"
178 #include "l1audio_cust.h"
179 #include "l1audio_defty.h"
180 #endif // AUDIO_TASK
181
182 #if (L1_GTT == 1)
183 #include "l1gtt_const.h"
184 #include "l1gtt_defty.h"
185 #endif
186
187 #if (L1_MP3 == 1)
188 #include "l1mp3_defty.h"
189 #endif
190
191 #if (L1_MIDI == 1)
192 #include "l1midi_defty.h"
193 #endif
194 //ADDED FOR AAC
195 #if (L1_AAC == 1)
196 #include "l1aac_defty.h"
197 #endif
198 #include "l1_defty.h"
199 #include "l1_varex.h"
200 #include "l1_tabs.h"
201 #include "sys_types.h"
202 #include "tpudrv.h"
203 #include "cust_os.h"
204 #include "l1_msgty.h"
205 #include "l1_proto.h"
206 #include "l1_trace.h"
207 #include "timer/timer.h"
208
209
210 #if (CHIPSET == 12) || (CHIPSET == 15)
211 #include "timer/timer_sec.h"
212 #include "inth/sys_inth.h"
213
214
215
216 #if(CHIPSET == 15)
217 #include "l1_pwmgr.h"
218 #if (OP_L1_STANDALONE == 0)
219 #include "lcc/lcc_api.h"
220 #endif
221
222 /* If NAND is enabled */
223 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
224 unsigned int temp_NAND_Reg1;
225 unsigned int temp_NAND_Reg2;
226 unsigned int temp_NAND_Reg3;
227 #endif
228
229
230
231
232
233 #if (OP_L1_STANDALONE == 1)
234
235 const t_peripheral_interface Peripheral_interface [MAX_PERIPHERAL]=
236 {
237 f_peripheral_interface_dummy,
238 f_peripheral_interface_dummy,
239 f_peripheral_interface_dummy,
240 f_peripheral_interface_dummy,
241 f_peripheral_interface_dummy,
242 f_peripheral_interface_dummy,
243 f_peripheral_interface_dummy,
244 f_peripheral_interface_dummy,
245 madc_outen_check, /* MADC_AS_ID = 8 */
246 f_peripheral_interface_dummy,
247 f_peripheral_interface_dummy,
248 f_peripheral_interface_dummy,
249 f_peripheral_interface_dummy,
250 f_peripheral_interface_dummy,
251 f_peripheral_interface_dummy,
252 f_peripheral_interface_dummy,
253 };
254
255 const t_application_interface Application_interface [MAX_APPLICATIONS] =
256 {
257 f_application_interface_dummy,
258 f_application_interface_dummy,
259 f_application_interface_dummy,
260 f_application_interface_dummy,
261 f_application_interface_dummy,
262 f_application_interface_dummy,
263 f_application_interface_dummy,
264 f_application_interface_dummy,
265 f_application_interface_dummy,
266 f_application_interface_dummy,
267 f_application_interface_dummy,
268 f_application_interface_dummy,
269 f_application_interface_dummy,
270 f_application_interface_dummy,
271 f_application_interface_dummy,
272 f_application_interface_dummy,
273 };
274 #else // For integrated Build
275 const t_peripheral_interface Peripheral_interface [MAX_PERIPHERAL]=
276 {
277 uart_pwr_interface,
278 #ifdef RVM_USB_SWE
279 usb_pwr_interface,
280 #else
281 f_peripheral_interface_dummy,
282 #endif
283 usim_pwr_interface,
284 i2c_pwr_interface,
285 lcd_pwr_interface,
286 #ifdef RVM_CAMD_SWE
287 #if (OP_L1_STANDALONE == 0)
288 camera_pwr_interface,
289 #endif
290 #else
291 f_peripheral_interface_dummy,
292 #endif
293 backlight_pwr_interface,
294 f_peripheral_interface_dummy,
295 audio_madc_sleep, /* MADC_AS_ID = 8 */
296 lcc_pwr_interface,
297 f_peripheral_interface_dummy,
298 f_peripheral_interface_dummy,
299 f_peripheral_interface_dummy,
300 f_peripheral_interface_dummy,
301 f_peripheral_interface_dummy,
302 f_peripheral_interface_dummy,
303 };
304
305 const t_application_interface Application_interface [MAX_APPLICATIONS] =
306 {
307 #ifdef BTS
308
309 BTHAL_PM_HandleSleepManagerReq,
310 #else
311 f_application_interface_dummy,
312 #endif
313 f_application_interface_dummy,
314 f_application_interface_dummy,
315 f_application_interface_dummy,
316 f_application_interface_dummy,
317 f_application_interface_dummy,
318 f_application_interface_dummy,
319 f_application_interface_dummy,
320 f_application_interface_dummy,
321 f_application_interface_dummy,
322 f_application_interface_dummy,
323 f_application_interface_dummy,
324 f_application_interface_dummy,
325 f_application_interface_dummy,
326 f_application_interface_dummy,
327 f_application_interface_dummy,
328 };
329
330
331 #endif // (OP_L1_STANDALONE == 1)
332
333 #endif // omaps00090550 #14 -d removal (CHIPSET = 15)
334
335
336 #else //(CHIPSET == 12) || (CHIPSET == 15)
337 #include "inth/iq.h"
338 #include "inth/inth.h"
339 #endif
340 // #include "timer1.h"
341 #include "ulpd/ulpd.h"
342 #include "clkm/clkm.h"
343 #include "memif/mem.h"
344 #if L2_L3_SIMUL
345 #include "hw_debug.h"
346 #endif
347
348 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
349 #include "csmi/sleep.h"
350 #endif // OP_WCP
351 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
352 #include "sys_memif.h"
353 #endif
354
355 #if (GSM_IDLE_RAM != 0)
356 #if (OP_L1_STANDALONE == 1)
357 #include "csmi_simul.h"
358 #else
359 #include "csmi/csmi.h"
360 #endif
361 #endif
362
363 #include "drp_api.h"
364
365 #endif // NO SIMULATION
366
367 #if (CODE_VERSION != SIMULATION)
368 // for PTOOL compatibility
369 extern void INT_DisableIRQ(void);
370 extern void INT_EnableIRQ(void);
371 extern void l1dmacro_RF_sleep(void);
372 extern void l1dmacro_RF_wakeup(void);
373 WORD32 l1s_get_HWTimers_ticks(void);
374
375 // file timer1.h
376 SYS_UWORD16 Dtimer1_Get_cntlreg(void);
377 void Dtimer1_AR(unsigned short Ar);
378 void Dtimer1_PTV(unsigned short Ptv);
379 void Dtimer1_Clken(unsigned short En);
380 void Dtimer1_Start (unsigned short startStop);
381 void Dtimer1_Init_cntl (SYS_UWORD16 St, SYS_UWORD16 Reload, SYS_UWORD16 clockScale, SYS_UWORD16 clkon);
382 SYS_UWORD16 Dtimer1_WriteValue (SYS_UWORD16 value);
383 SYS_UWORD16 Dtimer1_ReadValue (void);
384 #endif
385
386 void l1s_wakeup(void);
387 BOOL l1s_compute_wakeup_ticks(void);
388 void l1s_recover_Frame(void);
389 UWORD8 Cust_recover_Os(void);
390 void l1s_recover_HWTimers(void);
391 UWORD8 Cust_check_system(void);
392 void f_arm_sleep_cmd(UWORD8 d_sleep_mode);
393
394 //#if (TRACE_TYPE == 2) || (TRACE_TYPE == 3)
395 extern void L1_trace_string(char *s);
396 extern void L1_trace_char (char s);
397 //#endif
398 extern UWORD16 slp_debug_flag;
399
400 #if (GSM_IDLE_RAM != 0)
401 extern void l1s_trace_mftab(void);
402 #endif
403
404 #if (CODE_VERSION != SIMULATION)
405 extern T_DRP_REGS_STR *drp_regs;
406 #endif
407
408 #if L1_GPRS
409 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void);
410 #endif
411 //#pragma DUPLICATE_FOR_INTERNAL_RAM_END
412
413 #if !((MOVE_IN_INTERNAL_RAM == 1) && (GSM_IDLE_RAM !=0)) // MOVE TO INTERNAL MEM IN CASE GSM_IDLE_RAM enabled
414 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_START // KEEP IN EXTERNAL MEM otherwise
415
416 /************************************************************/
417 /* Macros for power management */
418 /************************************************************/
419 #define MIN(min, operand1) \
420 if (operand1 <= min) min = operand1;
421
422 // ex: RATIO T32khz/T4.33Mhz = 132.2428385417
423 // => root = integer part of the ratio
424 // = 132
425 // => frac = fractionnal part of the ratio multiplied by 65536 rounded to make it integer
426 // = 0.2428385417 * 65536 (Cf. ULPD specification)
427 // = 0.2428385417 * 2^16
428 // = 15914.66666689 = 15914
429
430 #define RATIO(HF,LF, root, frac) \
431 root = (UWORD32)(HF/LF); \
432 frac = (UWORD32)(((HF - (root*LF)) << 16) / LF);
433
434 // previous ratio with frac + 0.5
435 #define RATIO2(HF,LF, root, frac) \
436 if(LF){ \
437 root = (UWORD32)(HF/LF); \
438 frac = (UWORD32)((((HF - (root*LF)) << 16) + 0.5*LF) / LF);}
439
440 #define HFTHEO(LF, root, frac, hftheo) \
441 hftheo = root*LF + ((frac*LF) >>16);
442
443 #define SUM(HF, LF, nb, ind) \
444 LF=HF=0; \
445 for(ind=0; ind<nb; ind++) \
446 { \
447 LF = LF +l1s.pw_mgr.histo[ind][0]; \
448 HF = HF +l1s.pw_mgr.histo[ind][1]; \
449 }
450
451
452
453 #if (CODE_VERSION!=SIMULATION)
454 T_PWMGR_DEBUG l1_pwmgr_debug;
455 #endif // NOT SIMULATION
456
457 #if(CHIPSET == 15)
458
459 /************************************************************/
460 /* Configure EMIF for optimal consumption */
461 /************************************************************/
462
463
464 void EMIF_SetConfReg(const UWORD8 wp,const UWORD8 flush_prefetch,const UWORD8 Prefetch_mode,const UWORD8 pde,const UWORD8 pwd_en)
465 {
466 UWORD16 Emif_config_Reg;
467 Emif_config_Reg = (pwd_en << EMIF_CONFIG_PWD_POS | pde << EMIF_CONFIG_PDE_POS | Prefetch_mode << EMIF_CONFIG_PREFETCH_POS | flush_prefetch << EMIF_CONFIG_FLUSH_PREFETCH_POS | wp << EMIF_CONFIG_WP_POS);
468 /*p_Emifreg -> EMIF_Config = (Emif_config_Reg & EMIF_CONFIG_REG_MASK );*/
469 EMIF_CONFIG = Emif_config_Reg;
470 } // End of EMIF_SetConfReg
471
472
473
474 #if (OP_L1_STANDALONE == 1) // API for Audio and MADC
475
476
477
478 T_AUDIO_OUTEN_REG audio_outen_pm;
479
480 // L1 Standalone function for Configuring Audio registers.
481 // Argument CLK_MASK checks if Audio path is active
482 // Argument SLEEP_CMD configures Audio registers for optimal consumption
483 // Argument WAKE_CMD reconfigure audio registers after wakeup
484
485 Uint8 madc_outen_check(Uint8 cmd) {
486 BspTwl3029_ReturnCode returnVal = BSP_TWL3029_RETURN_CODE_FAILURE;
487 /* I2C array */
488 Bsp_Twl3029_I2cTransReqArray i2cTransArray;
489 Bsp_Twl3029_I2cTransReqArrayPtr i2cTransArrayPtr= &i2cTransArray;
490
491 /* twl3029 I2C reg info struct */
492 BspTwl3029_I2C_RegisterInfo regInfo[8] ;
493 BspTwl3029_I2C_RegisterInfo* regInfoPtr = regInfo;
494 BspTwl3029_I2C_RegData shadow_pwronstatus, ston_bit;
495 Uint8 count = 0;//OMAPS90550-new
496
497
498 switch( cmd ) {
499
500 case CLK_MASK:
501 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_PWRONSTATUS_OFFSET,
502 &shadow_pwronstatus);
503 ston_bit = (shadow_pwronstatus & (1 << BSP_TWL3029_LLIF_AUDIO_PWRONSTATUS_STON_OFFSET));
504
505 if (ston_bit == 1) return DCXO_CLOCK;
506 else return NO_CLOCK;
507 // omaps00090550 break;
508
509 case SLEEP_CMD:
510 /* store the output enable 1 register */
511 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
512 &audio_outen_pm.outen1);
513
514 /* store the output enable 2 register */
515 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
516 &audio_outen_pm.outen2);
517
518 /* store the output enable 3 register */
519 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
520 &audio_outen_pm.outen3);
521
522
523 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
524 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
525 BSP_TWL_3029_MAP_AUDIO_OUTEN1_DEFAULT,regInfoPtr++);
526 count++;
527
528 /* store the output enable 2 register */
529 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
530 BSP_TWL_3029_MAP_AUDIO_OUTEN2_DEFAULT,regInfoPtr++);
531 count++;
532
533 /* store the output enable 3 register */
534 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
535 BSP_TWL_3029_MAP_AUDIO_OUTEN3_DEFAULT,regInfoPtr++);
536 count++;
537
538
539 /* now request to I2C manager to write to Triton registers */
540 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
541 {
542 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
543 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
544 }
545
546 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
547 else return FAILURE;
548
549 // omaps00090550 break;
550
551 case WAKE_CMD:
552 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
553 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
554 audio_outen_pm.outen1,regInfoPtr++);
555 count++;
556
557 /* store the output enable 2 register */
558 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
559 audio_outen_pm.outen2,regInfoPtr++);
560 count++;
561
562 /* store the output enable 3 register */
563 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
564 audio_outen_pm.outen3,regInfoPtr++);
565 count++;
566
567
568
569 /* now request to I2C manager to write to Triton registers */
570 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
571 {
572 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
573 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
574 }
575
576 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
577 else return FAILURE;
578 // omaps00090550 break;
579 }
580 return SUCCESS;//omaps00090550
581 }
582 #else // Integrated build API for Audio and MADC
583
584 // Full PS build function for Configuring Audio registers.
585 // Argument CLK_MASK checks if Audio path is active
586 // Argument SLEEP_CMD configures Audio registers for optimal consumption
587 // Argument WAKE_CMD reconfigure audio registers after wakeup
588
589
590 T_AUDIO_OUTEN_REG audio_outen_pm;
591 BspTwl3029_I2C_RegData audio_ctrl3;
592
593 Uint8 audio_madc_sleep(Uint8 cmd) {
594 BspTwl3029_ReturnCode returnVal = BSP_TWL3029_RETURN_CODE_FAILURE;
595 /* I2C array */
596 //Bsp_Twl3029_I2cTransReqArray i2cTransArray;
597 //Bsp_Twl3029_I2cTransReqArrayPtr i2cTransArrayPtr= &i2cTransArray;
598
599 /* twl3029 I2C reg info struct */
600 //BspTwl3029_I2C_RegisterInfo regInfo[8] ;
601 //BspTwl3029_I2C_RegisterInfo* regInfoPtr = regInfo;
602 BspTwl3029_I2C_RegData shadow_pwronstatus, ston_bit;
603
604
605 Uint8 count = 0;
606
607
608 switch( cmd ) {
609
610 case CLK_MASK:
611 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_PWRONSTATUS_OFFSET,
612 &shadow_pwronstatus);
613 ston_bit = (shadow_pwronstatus & (1 << BSP_TWL3029_LLIF_AUDIO_PWRONSTATUS_STON_OFFSET));
614
615 if (ston_bit == 1) return DCXO_CLOCK;
616 else return NO_CLOCK;
617 //omaps00090550 break;
618
619 case SLEEP_CMD:
620 #if 0
621 /* store the output enable 1 register */
622 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
623 &audio_outen_pm.outen1);
624
625 /* store the output enable 2 register */
626 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
627 &audio_outen_pm.outen2);
628
629 /* store the output enable 3 register */
630 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
631 &audio_outen_pm.outen3);
632
633 returnVal = BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
634 &audio_ctrl3);
635
636 if( audio_outen_pm.outen1 )
637 {
638 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
639 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
640 BSP_TWL_3029_MAP_AUDIO_OUTEN1_DEFAULT,regInfoPtr++);
641 count++;
642 }
643
644 if( audio_outen_pm.outen2 )
645 {
646
647 /* store the output enable 2 register */
648 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
649 BSP_TWL_3029_MAP_AUDIO_OUTEN2_DEFAULT,regInfoPtr++);
650 count++;
651 }
652
653 if( audio_outen_pm.outen3 )
654 {
655 /* store the output enable 3 register */
656 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
657 BSP_TWL_3029_MAP_AUDIO_OUTEN3_DEFAULT,regInfoPtr++);
658 count++;
659 }
660
661 /* Selectively checking if INMODE is set or not. Write is queued only when INMODE(0-3)
662 is non-zero */
663 if( audio_ctrl3 & 0xf)
664 {
665 /* store the output enable 3 register */
666 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
667 BSP_TWL_3029_MAP_AUDIO_CTRL3_DEFAULT,regInfoPtr++);
668 count++;
669 }
670
671 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUX,BSP_TWL3029_MAP_AUX_REG_TOGGLE1_OFFSET,
672 1 << BSP_TWL3029_LLIF_AUX_REG_TOGGLE1_MADCR_OFFSET, regInfoPtr++);
673 count++;
674
675 //Turn off the USB leakage currrent
676
677 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0, BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0xb6,regInfoPtr++);
678 // count++;
679
680 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2, BSP_TWL3029_MAP_USB_PSM_EN_TEST_SET_OFFSET,0x80,regInfoPtr++);
681 //count++;
682
683 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_VBUS_EN_TEST_OFFSET,0x00,regInfoPtr++);
684 // count++;
685
686 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0, BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0x00,regInfoPtr++);
687 //count++;
688
689 // now request to I2C manager to write to Triton registers
690 //if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE && !is_i2c_bus_locked())
691 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
692 {
693 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
694 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
695 }
696
697 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
698 else return FAILURE;
699
700 #endif
701
702 //omaps00090550 break;
703
704 case WAKE_CMD:
705 #if 0
706
707 if( audio_outen_pm.outen1 )
708 {
709 /* write default values into OUTEN1,OUTEN2 & OUTEN3 */
710 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN1_OFFSET,
711 audio_outen_pm.outen1,regInfoPtr++);
712 count++;
713 }
714
715 if( audio_outen_pm.outen2 )
716 {
717
718 /* store the output enable 2 register */
719 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN2_OFFSET,
720 audio_outen_pm.outen2,regInfoPtr++);
721 count++;
722 }
723
724 if( audio_outen_pm.outen3 )
725 {
726 /* store the output enable 3 register */
727 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_OUTEN3_OFFSET,
728 audio_outen_pm.outen3,regInfoPtr++);
729 count++;
730 }
731
732 /* Selectively checking if INMODE is set or not. Write is queued only when INMODE(0-3)
733 is non-zero */
734 if( audio_ctrl3 & 0xf)
735 {
736 /* store the output enable 3 register */
737 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUD, BSP_TWL_3029_MAP_AUDIO_CTRL3_OFFSET,
738 audio_ctrl3,regInfoPtr++);
739 count++;
740 }
741
742
743 //wake up mode: Enable MADC
744 returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_AUX,BSP_TWL3029_MAP_AUX_REG_TOGGLE1_OFFSET,
745 1 << BSP_TWL3029_LLIF_AUX_REG_TOGGLE1_MADCS_OFFSET, regInfoPtr++);
746
747 count++; //TI_SH added to set the madc on correctly
748
749 //Enable the USB leakage current after wake up
750
751 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0,BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0xb6,regInfoPtr++);
752 // count++;
753
754 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_VBUS_EN_TEST_OFFSET,0x0F,regInfoPtr++);
755 // count++;
756
757 //returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE2,BSP_TWL3029_MAP_USB_PSM_EN_TEST_CLR_OFFSET,0x80,regInfoPtr++);
758 //count++;
759
760 // returnVal = BspTwl3029_I2c_regQueWrite(BSP_TWL3029_I2C_PAGE0,BSP_TWL_3029_MAP_CKG_TESTUNLOCK_OFFSET,0x00,regInfoPtr++);
761 // count++;
762
763 // now request to I2C manager to write to Triton registers
764 //if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE && !is_i2c_bus_locked())
765 if (returnVal != BSP_TWL3029_RETURN_CODE_FAILURE)
766 {
767 returnVal = BspTwl3029_I2c_regInfoSend(regInfo,(Uint16)count,NULL,
768 (BspI2c_TransactionRequest*)i2cTransArrayPtr);
769 }
770
771 if (returnVal == BSP_TWL3029_RETURN_CODE_SUCCESS) return SUCCESS;
772 else return FAILURE;
773 #endif
774 break;
775 }
776 return SUCCESS;
777 }
778 #endif // API for Audio and MADC
779
780
781
782 //Function to check status of Backlight Only Argument 0 is valid
783
784
785 Uint8 backlight_pwr_interface(Uint8 cmd)
786 {
787 BspTwl3029_I2C_RegData regData;
788
789
790 if(cmd == 0)
791 {
792 BspTwl3029_I2c_shadowRegRead(BSP_TWL3029_I2C_PAGE0,PWDNSTATUS,&regData);
793 if((regData) & 0x70)
794 {
795 return(DCXO_CLOCK);
796 }
797 else
798 {
799 return(NO_CLOCK);
800 }
801
802 }
803 else
804 {
805 return(SUCCESS);
806 }
807 }
808
809 //Dummy Function for peripheral check to populate Function pointer table for unused APIs
810
811
812 Uint8 f_peripheral_interface_dummy(Uint8 cmd)
813 {
814 if(cmd == 0)
815 {
816 return(NO_CLOCK);
817 }
818 else
819 {
820 return(SUCCESS);
821 }
822
823 }
824
825 //Dummy Function for Application check to populate Function pointer table for unused APIs
826
827 Uint8 f_application_interface_dummy(Uint8 cmd)
828 {
829 if(cmd == 0)
830 {
831 return(PM_INACTIVE);
832 }
833 else
834 {
835 return(SUCCESS);
836 }
837 }
838
839 //Function not used as of now //OMAPS00090550
840 void Update_Sleep_Status( Uint8 ID, Uint8 state)
841 {
842 if(state)
843 {
844 SLEEP_STATE |= (state << ID); //omaps00090550 ! was present before
845 }
846 else
847 {
848 SLEEP_STATE &=((Uint8)~1 <<ID); //omaps00090550
849 }
850 }
851
852 //Function polls the status of the following peripherals to take
853 //Sleep Decision:
854 //UART, USB, I2C, LCD, Camera, Backlight, Audio Stereo path,
855 //Bluetooth and USIM.
856 //All peripherals either cause Deep Sleep or No Sleep.
857 //Only USIM can also cause Big Sleep.
858
859
860
861 UWORD32 Check_Peripheral_App(void)
862 {
863 #if (CODE_VERSION!=SIMULATION)
864 UWORD8 ret_value;
865 /* Check Peripherals */
866 ret_value = Peripheral_interface[UART_ID](CLK_MASK);
867 if(ret_value)
868 {
869 l1_pwmgr_debug.fail_id = UART_ID;
870 l1_pwmgr_debug.fail_ret_val = ret_value;
871 return(DO_NOT_SLEEP);
872 }
873 ret_value = Peripheral_interface[USB_ID](CLK_MASK);
874 if(ret_value)
875 {
876 l1_pwmgr_debug.fail_id = USB_ID;
877 l1_pwmgr_debug.fail_ret_val = ret_value;
878 return(DO_NOT_SLEEP);
879 }
880 ret_value = Peripheral_interface[I2C_ID](CLK_MASK);
881 if(ret_value)
882 {
883 l1_pwmgr_debug.fail_id = I2C_ID;
884 l1_pwmgr_debug.fail_ret_val = ret_value;
885 return(DO_NOT_SLEEP);
886 }
887 ret_value = Peripheral_interface[LCD_ID](CLK_MASK);
888 if(ret_value)
889 {
890 l1_pwmgr_debug.fail_id = LCD_ID;
891 l1_pwmgr_debug.fail_ret_val = ret_value;
892 return(DO_NOT_SLEEP);
893 }
894 ret_value = Peripheral_interface[CAMERA_ID](CLK_MASK);
895 if(ret_value)
896 {
897 l1_pwmgr_debug.fail_id = CAMERA_ID;
898 l1_pwmgr_debug.fail_ret_val = ret_value;
899 return(DO_NOT_SLEEP);
900 }
901 ret_value = Peripheral_interface[BACKLIGHT_ID](CLK_MASK);
902 if(ret_value)
903 {
904 l1_pwmgr_debug.fail_id = BACKLIGHT_ID;
905 l1_pwmgr_debug.fail_ret_val = ret_value;
906 return(DO_NOT_SLEEP);
907 }
908 ret_value = Peripheral_interface[MADC_AS_ID](CLK_MASK);
909 if(ret_value)
910 {
911 l1_pwmgr_debug.fail_id = MADC_AS_ID;
912 l1_pwmgr_debug.fail_ret_val = ret_value;
913 return(DO_NOT_SLEEP);
914 }
915 /* check battery charger */
916 ret_value = Peripheral_interface[BCI_ID](CLK_MASK);
917 if(ret_value)
918 {
919 l1_pwmgr_debug.fail_id = BCI_ID;
920 l1_pwmgr_debug.fail_ret_val = ret_value;
921 return(DO_NOT_SLEEP);
922 }
923
924 /* Check Applications */
925 ret_value = Application_interface[BT_Stack_ID](APP_ACTIVITY);
926 if(ret_value)
927 {
928 // L1_APPLICATION_OFFSET is added to distinguish Application interface
929 l1_pwmgr_debug.fail_id = BT_Stack_ID + (L1_PWMGR_APP_OFFSET);
930 l1_pwmgr_debug.fail_ret_val = ret_value;
931 return(DO_NOT_SLEEP);
932 }
933 ret_value = Peripheral_interface[USIM_ID](CLK_MASK);
934 if(ret_value)
935 {
936 l1_pwmgr_debug.fail_id = USIM_ID;
937 l1_pwmgr_debug.fail_ret_val = ret_value;
938 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_SIM;
939 return(FRAME_STOP);
940 }
941 else
942 {
943 return(CLOCK_STOP);
944 }
945 #endif //NOT SIMULATION
946 }
947
948 //This function Configures DBB for optimal Power Consumption
949 //during Deep Sleep
950
951
952
953 void DBB_Configure_DS()
954 {
955 // FDP enabling and disabling of burst configuration in flash not required in Locosto
956 // Hardware Settings as per Power Bench
957
958 // Stop RNG oscillators
959 RNG_CONFIG &= 0xF03F;
960
961
962 /* Set GPIOs 19 to 22 as outputs to avoid floating pins */
963 GPIO1_CNTL_REG &= ~0x0078;
964
965 /* Set PD on VDR and VFSRX for VSP bus to avoid floating pins */
966 CONF_VDR |= 0x0008;
967 CONF_VFSRX |= 0x0008;
968
969 /* Set HASH in auto-idle */
970 SHA_MASK = 0x0001;
971
972 /* Set DES in auto-idle */
973 DES_MASK = 0x0001;
974
975 /* Set RNG in auto-idle */
976 RNG_MASK = 0x0001;
977
978
979 /* uart_in_pull_down(); */
980
981 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
982
983
984 temp_NAND_Reg1 = COMMAND_REG;
985 temp_NAND_Reg2 = CONTROL_REG;
986 temp_NAND_Reg3 = STATUS_IT_REG;
987
988 COMMAND_REG = 0x06;
989 CONTROL_REG = 0x0;
990 STATUS_IT_REG = 0x0;
991
992 #endif
993 // RANGA: All these bit fields should be replaced by macros
994 // Set DPLL in idle mode
995 // Cut C-PORT (new), IRQ, BRIDGE and TIMER clocks
996 /* Set DPLL in idle mode */
997 /* Cut C-PORT (new), IRQ, BRIDGE and TIMER clocks */
998 CLKM_CNTL_CLK_REG &= ~0x0010 ;
999 CLKM_CNTL_CLK_REG |= 0x000F ;
1000
1001 CNTL_APLL_DIV_CLK &= ~0x0001; /* Disable APLL */
1002
1003 // Statements below are not required for the current hardware version.
1004 // This was done to solve the problem of DCXO taking 10 frames
1005 // to wake-up from Deep Sleep in older hardware versions.
1006
1007 //DCXO_THRESH_L = 0xC040; // Setting DCXO Thresholds
1008 //DCXO_THRESH_H = 0x051F; // to solve Deep Sleep problem
1009 }
1010
1011 //This function Restores DBB after wakeup from Deep Sleep
1012
1013
1014 void DBB_Wakeup_DS()
1015 {
1016 // FDP re-enabling and burst re-configuration are not required if FDP is disabled
1017 // during deep-sleep
1018
1019 CLKM_CNTL_CLK_REG |= 0x0010 ; // Enable CPORT Clock
1020
1021 CNTL_APLL_DIV_CLK |= 0x0001; // Enable APLL clock
1022
1023 #if defined(RVM_DATALIGHT_SWE) || defined(RVM_NAN_SWE)
1024
1025 // Restoring NAND
1026 COMMAND_REG = temp_NAND_Reg1;
1027 CONTROL_REG = temp_NAND_Reg2;
1028 STATUS_IT_REG = temp_NAND_Reg3;
1029 // Restoring NAND
1030 #endif
1031
1032
1033 }
1034
1035
1036 //This function shuts down APC Bandgap.Cannot be used for PG 1.0 Can be used only for PG 2.0
1037
1038
1039 void Disable_APC_BG() //omaps00090550
1040 {
1041 while (RHSW_ARM_CNF & DSP_PERIPH_LOCK)
1042 RHSW_ARM_CNF |= ARM_PERIPH_LOCK;
1043 APCCTRL2 &= ~BGEN;
1044 return;
1045 }
1046
1047 //This function enables APC Bandgap.Cannot be used for PG 1.0 Can be used only for PG 2.0
1048
1049 void Enable_APC_BG() //omaps00090550
1050 {
1051 while (RHSW_ARM_CNF & DSP_PERIPH_LOCK)
1052 RHSW_ARM_CNF |= ARM_PERIPH_LOCK;
1053 APCCTRL2 |= BGEN;
1054 return;
1055 }
1056
1057 #endif //CHIPSET = 15
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068 // l1ctl_pgm_clk32()
1069 // convert ratio in 4.33Mhz and pgm INC_FRAC,INC_SIXTEEN.
1070
1071 void l1ctl_pgm_clk32(UWORD32 nb_hf, UWORD32 nb_32khz)
1072 {
1073 #if (CODE_VERSION != SIMULATION)
1074 if (l1_config.pwr_mngt == PWR_MNGT)
1075 {
1076 UWORD32 inc_sixteen= 0, inc_frac=0, lf;
1077
1078 // REM: nb_hf is the real value of the high frequency (ex in nbr of 65Mhz clock)
1079 // To compute the ratio, nb_hf must be expressed in nbr of clock 4.33 Mhz
1080 // that's why nb_hf is divided by 3*l1_config.dpll
1081 // RATIO2(nb_hf/(3*l1_config.dpll),nb_32khz,inc_sixteen,inc_frac);
1082 // this line above is equal to the ligne below:
1083 lf=(UWORD32)((UWORD32)(3*((UWORD32)((UWORD32)(l1_config.dpll)*nb_32khz)))); //OMAPS00090550
1084 RATIO2(nb_hf,lf,inc_sixteen,inc_frac);
1085
1086 // integer part
1087 ULDP_INCSIXTEEN_UPDATE(inc_sixteen);
1088
1089 // fractional part
1090 ULDP_INCFRAC_UPDATE(inc_frac);
1091 }
1092 #endif
1093 }
1094
1095
1096 // l1ctl_gauging()
1097 // Description: management of the gauging results
1098 // At RESET state reset histogram and then go to INIT.
1099 // At INIT state, go back to RESET on each */
1100 // gauging > +- 100 ppm. If NB_INIT good gauging go to ACQUIS state.
1101 // At ACQUIS state, go back to RESET on each gauging > (+- 20ppm +- 1us). If NB_ACQU good gauging */
1102 // go to UPDATE state. Allow deep sleep feature.
1103 // At UPDATE state, count consecutive gauging >+- 1 us.
1104 // If MAX_BAD_GAUGING results go back to RESET.
1105 // Otherwise re-enable deep sleep feature and reset bad results counter.
1106
1107 void l1ctl_gauging ( UWORD32 nb_32khz, UWORD32 nb_hf)
1108 {
1109 if (l1_config.pwr_mngt == PWR_MNGT)
1110 {
1111 enum states
1112 {
1113 RESET = 0,
1114 INIT = 1,
1115 ACQUIS = 2,
1116 UPDATE = 3
1117 };
1118
1119 static UWORD8 bad_count; // bad gauging values
1120 static UWORD8 gauging_state= RESET; // RESET,INIT, ACQUIS, UPDATE
1121 static UWORD8 nb_gaug; // number of gauging in ACQUIS
1122 static UWORD8 idx,i; // index
1123 static UWORD32 root, frac; // ratio of HF and LF average
1124 UWORD32 sumLF=0 , sumHF=0; // sum of HF and LF counts
1125 double nbHF_theo;
1126
1127
1128 // AFC or TEMPERATURE variation
1129
1130 //if ( (ABS( (WORD32)(l1s.pw_mgr.previous_afc-l1s.afc) ) > AFC_VARIATION) ||
1131 // (ABS( (WORD32)(l1s.pw_mgr.previous_temp-l1s.afc) > TEMP_VARIATION) )
1132 // gauging_state = RESET;
1133
1134 // reset state machine if not in IDLE mode
1135 #if L1_GPRS
1136 if ((l1a_l1s_com.l1s_en_task[NP] != TASK_ENABLED) && (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED))
1137 gauging_state = RESET;
1138 #else
1139 if ((l1a_l1s_com.l1s_en_task[NP] != TASK_ENABLED) )
1140 gauging_state = RESET;
1141
1142 #endif
1143
1144 switch (gauging_state)
1145 {
1146
1147 case RESET:
1148 {
1149 UWORD8 i;
1150
1151 // Reset Histogram
1152 for (i=0; i < SIZE_HIST; i++)
1153 {
1154 l1s.pw_mgr.histo[i][0] = 0;
1155 l1s.pw_mgr.histo[i][1] = 0;
1156 }
1157 idx = 0;
1158 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep
1159 gauging_state = INIT;
1160 nb_gaug = NB_INIT; // counter for ACQUIS state
1161 bad_count = 0; // reset count of BAD gauging
1162
1163 #if (TRACE_TYPE != 0)
1164 l1_trace_gauging_reset();
1165 #endif
1166 }
1167
1168
1169 case INIT:
1170 {
1171
1172 // Acquire NB_INIT gauging wtw +- 100 ppm
1173
1174 if (l1a_l1s_com.mode != I_MODE) return;
1175
1176 // compute clocks ratio from measurements.
1177 RATIO(nb_hf,nb_32khz,root,frac)
1178
1179
1180 // allow [-500ppm,+100ppm] derive on 32Khz at startup.
1181 // Commenting section below for OMAPS00148004
1182 /* if (
1183 (root > l1s.pw_mgr.c_clk_min ||
1184 (root == l1s.pw_mgr.c_clk_min &&
1185 frac >= l1s.pw_mgr.c_clk_init_min) ) &&
1186 (root < l1s.pw_mgr.c_clk_max ||
1187 (root == l1s.pw_mgr.c_clk_max &&
1188 frac <= l1s.pw_mgr.c_clk_init_max ) )
1189 */
1190 if (
1191 ( l1s.pw_mgr.c_clk_min == l1s.pw_mgr.c_clk_max &&
1192 frac >= l1s.pw_mgr.c_clk_init_min &&
1193 frac <= l1s.pw_mgr.c_clk_init_max )
1194 ||
1195 ( l1s.pw_mgr.c_clk_min != l1s.pw_mgr.c_clk_max &&
1196 ( (root == l1s.pw_mgr.c_clk_min &&
1197 frac >= l1s.pw_mgr.c_clk_init_min ) ||
1198 (root > l1s.pw_mgr.c_clk_min &&
1199 root < l1s.pw_mgr.c_clk_max ) ||
1200 (root == l1s.pw_mgr.c_clk_max &&
1201 frac <= l1s.pw_mgr.c_clk_init_max ) ) )
1202 )
1203 {
1204 l1s.pw_mgr.histo[idx ][0] = nb_32khz; // init histo with the number of 32kHz
1205 l1s.pw_mgr.histo[idx++][1] = nb_hf; // init histo with the number of hf (13Mhz)
1206
1207 #if (CODE_VERSION == SIMULATION)
1208 #if (TRACE_TYPE==5)
1209 trace_ULPD("Gauging INIT Case ", l1s.actual_time.fn);
1210 #endif
1211 #endif
1212
1213 }
1214 else
1215 {
1216 // out of the allowed derive -> reset
1217 idx=0;
1218 #if (TRACE_TYPE != 0)
1219 l1_trace_gauging_reset();
1220 #endif
1221 }
1222
1223 if (idx == NB_INIT)
1224 {
1225 // enough measurement -> ACQUIS state
1226 gauging_state = ACQUIS;
1227 // compute clk ratio on count average
1228 SUM(sumHF,sumLF, NB_INIT,i) // returns sumHF and sumLF
1229 RATIO(sumHF,sumLF,root, frac) // returns root and frac*2E16, computed on the average
1230 }
1231 }
1232 break;
1233
1234
1235 case ACQUIS:
1236 {
1237 // Acquire NB_ACQU gauging at +-25ppm
1238 // with jitter +- 1 us
1239 UWORD8 n;
1240
1241 // from nb_32khz "measured"
1242 // compute nbHF_theo
1243 HFTHEO(nb_32khz,root,frac,nbHF_theo)
1244
1245 if ( (nb_hf >= (nbHF_theo - l1s.pw_mgr.c_delta_hf_acquis)) &&
1246 (nb_hf <= (nbHF_theo + l1s.pw_mgr.c_delta_hf_acquis)) )
1247 {
1248 l1s.pw_mgr.histo[idx][0] = nb_32khz;
1249 l1s.pw_mgr.histo[idx++][1] = nb_hf;
1250 idx = idx % SIZE_HIST;
1251
1252 // compute clk ratio on count average
1253 if(++nb_gaug >= SIZE_HIST) n=SIZE_HIST;
1254 else n= nb_gaug;
1255 SUM(sumHF,sumLF, n,i)
1256 RATIO(sumHF,sumLF,root, frac)
1257
1258 #if (CODE_VERSION == SIMULATION)
1259 #if (TRACE_TYPE==5)
1260 trace_ULPD("Gauging ACQUIS Case ", l1s.actual_time.fn);
1261 #endif
1262 #endif
1263
1264 if ( nb_gaug == (NB_INIT+NB_ACQU)) // NB_ACQU good gauging
1265 {
1266 gauging_state = UPDATE; // UPDATE state
1267 l1s.pw_mgr.enough_gaug = TRUE; // allow Deep sleep
1268 l1ctl_pgm_clk32(sumHF,sumLF); // clocks ratio in 4.33Mhz
1269 }
1270 }
1271 else
1272 {
1273 gauging_state = RESET;
1274 }
1275 }
1276 break;
1277
1278 case UPDATE:
1279 {
1280
1281 // Update gauging histogram
1282 // compute nbHF theoric for ratio_avg
1283 HFTHEO(nb_32khz,root,frac,nbHF_theo)
1284
1285 if ( (nb_hf >= (nbHF_theo-l1s.pw_mgr.c_delta_hf_update)) &&
1286 (nb_hf <= (nbHF_theo+l1s.pw_mgr.c_delta_hf_update)) )
1287 {
1288 l1s.pw_mgr.histo[idx][0] = nb_32khz;
1289 l1s.pw_mgr.histo[idx++][1] = nb_hf;
1290
1291 // compute clk ratio on count average
1292 SUM(sumHF,sumLF, SIZE_HIST,i)
1293 l1ctl_pgm_clk32(sumHF,sumLF); // clocks ratio in 4.33Mhz
1294
1295 l1s.pw_mgr.enough_gaug = TRUE; // allow Deep sleep
1296 bad_count = 0; // reset count of BAD gauging
1297
1298 #if (CODE_VERSION == SIMULATION)
1299 #if (TRACE_TYPE==5)
1300 trace_ULPD("Gauging UPDATE Case ", l1s.actual_time.fn);
1301 #endif
1302 #endif
1303
1304 }
1305 else
1306 {
1307 bad_count ++;
1308 if (bad_count >= MAX_BAD_GAUGING) gauging_state = RESET;
1309 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep
1310 }
1311 idx = idx % SIZE_HIST;
1312 }
1313 break;
1314 }
1315 #if (TRACE_TYPE != 0) // Trace gauging
1316 // save parameters in the corresponding structure
1317 l1s.pw_mgr.state = gauging_state;
1318 l1s.pw_mgr.lf = nb_32khz ;
1319 // WARNING WARNING, this case gauging_state == UPDATE modify the algo.
1320 // In case of trace the parameter root and frac are refresh.
1321 // it is not the case if no trace and it seems there is mistake
1322 if (gauging_state == UPDATE)
1323 {
1324 RATIO2(sumHF,sumLF,root,frac);
1325 }
1326 //End of Warning.
1327 l1s.pw_mgr.hf = nb_hf ;
1328 l1s.pw_mgr.root = root ;
1329 l1s.pw_mgr.frac = frac ;
1330 #endif // End Trace gauging
1331 }
1332 }
1333
1334
1335
1336
1337 /* GAUGING_Handler() */
1338 /* Description: update increment counter for 32Khz */
1339 /* This interrupt function computes the ratio between */
1340 /* HF/32Khz gauging counters and program ULPD increment */
1341 /* values. */
1342
1343 void GAUGING_Handler(void)
1344 {
1345 #if (CODE_VERSION != SIMULATION)
1346 if (l1_config.pwr_mngt == PWR_MNGT)
1347 {
1348 UWORD32 nb_32khz, nb_hf;
1349
1350 // Gauging task is ended
1351 l1s.pw_mgr.gauging_task = INACTIVE;
1352 #if (CHIPSET == 12) || (CHIPSET == 15)
1353 F_INTH_DISABLE_ONE_IT(C_INTH_ULPD_GAUGING_IT); // Mask ULPD GAUGING int.
1354 #else
1355 INTH_DISABLEONEIT(IQ_ULPD_GAUGING); // Mask ULPD GAUGING int.
1356 #endif
1357
1358 // Number of 32 Khz clock at the end of the gauging
1359 nb_32khz = ((*( UWORD16 *)ULDP_COUNTER_32_MSB_REG) * 65536) +
1360 (*( UWORD16 *)ULDP_COUNTER_32_LSB_REG);
1361
1362 // Number of high frequency clock at the end of the gauging
1363 // Convert it in nbr of 13 Mhz clocks (5*13=65Mhz)
1364 nb_hf = ( ((*( UWORD16 *)ULDP_COUNTER_HI_FREQ_MSB_REG) * 65536) +
1365 (*( UWORD16 *)ULDP_COUNTER_HI_FREQ_LSB_REG) ); // Divide by PLL ratio
1366
1367 l1ctl_gauging(nb_32khz, nb_hf);
1368 }
1369 #else //Simulation part
1370
1371 // Gauging task is ended
1372 l1s.pw_mgr.gauging_task = INACTIVE;
1373
1374 l1ctl_gauging(DEFAULT_32KHZ_VALUE,DEFAULT_HFMHZ_VALUE);
1375 #endif
1376 }
1377
1378
1379
1380
1381 // l1s_get_HWTimers_ticks()
1382 // Description:
1383 // evaluate the loading of the HW Timers for dep sleep
1384 // BIG SLEEP: timers CLK may be stopped (user dependant)
1385 // DEEP SLEEP:timers CLK and WTCHDOG CLK are stopped
1386 // CLKS are enabled after VTCX0+SLICER+13MHZ
1387 // setup time
1388
1389 WORD32 l1s_get_HWTimers_ticks(void)
1390 {
1391 #if (CODE_VERSION != SIMULATION)
1392 if (l1_config.pwr_mngt == PWR_MNGT)
1393 {
1394 WORD32 timer1,timer2,watchdog,HWTimer;
1395 #if (CHIPSET == 12) || (CHIPSET == 15)
1396 WORD32 watchdog_sec;
1397 #endif
1398 UWORD16 cntlreg;
1399 UWORD16 modereg;
1400 WORD32 old = 0;
1401
1402 // read Hercules Timers & Watchdog
1403 //=================================================
1404 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1)
1405 // Tclk = 1.2308us for Fclk=13Mhz
1406 // PTV = X (pre-scaler field)
1407 //-------------------------------------------------
1408 timer1 = timer2 = watchdog = HWTimer = -1;
1409 #if (CHIPSET == 12) || (CHIPSET == 15)
1410 watchdog_sec = -1;
1411 #endif
1412
1413 cntlreg = Dtimer1_Get_cntlreg(); // AND 0x1F
1414 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
1415 {
1416 cntlreg = cntlreg&0x1F;
1417 cntlreg >>= 2; // take PTV
1418 cntlreg = 1 << (cntlreg+1);
1419 timer1 = (WORD32) ( ((Dtimer1_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 );
1420 if (timer1 <= MIN_SLEEP_TIME) return(0);
1421 old = Dtimer1_ReadValue();
1422 HWTimer = timer1;
1423 }
1424
1425 cntlreg = Dtimer2_Get_cntlreg();
1426 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
1427 {
1428 cntlreg = cntlreg&0x1F;
1429 cntlreg >>= 2; // take PTV
1430 cntlreg = 1 << (cntlreg+1);
1431 timer2 = (WORD32) ( ((Dtimer2_ReadValue()+1) * cntlreg * 0.0012308) / 4.615 );
1432 if (timer2 <= MIN_SLEEP_TIME) return(0);
1433 if (HWTimer == -1) HWTimer = timer2;
1434 else MIN(HWTimer,timer2)
1435 }
1436
1437 cntlreg = TIMER_Read(0); // AND 0x0f80
1438 modereg = TIMER_Read(2);
1439
1440 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
1441 {
1442 // in watchdog mode PTV is forced to 7
1443 if ( modereg & TIMER_WDOG )
1444 cntlreg |= TIMER_PTV;
1445
1446 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
1447 cntlreg = 1 << (cntlreg+1);
1448 watchdog = (WORD32) ( ((TIMER_ReadValue()+1) * cntlreg * 0.001078) / 4.615 );
1449 if (watchdog <= MIN_SLEEP_TIME) return(0);
1450 if (HWTimer == -1) HWTimer = watchdog;
1451 else MIN(HWTimer,watchdog)
1452 }
1453
1454 #if (CHIPSET == 12) || (CHIPSET == 15)
1455 /*
1456 * Secure Watchdog Timer management
1457 */
1458 cntlreg = TIMER_SEC_Read(0); // AND 0x0f80
1459 modereg = TIMER_SEC_Read(2);
1460 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
1461 {
1462 // in watchdog mode PTV is forced to 7
1463 if ( modereg & TIMER_WDOG )
1464 cntlreg |= TIMER_PTV;
1465
1466 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
1467 cntlreg = 1 << (cntlreg+1);
1468 watchdog_sec = (WORD32) ( ((TIMER_SEC_ReadValue()+1) * cntlreg * 0.001078) / 4.615 );
1469 if (watchdog_sec <= MIN_SLEEP_TIME) return(0);
1470 if (HWTimer == -1) HWTimer = watchdog_sec;
1471 else MIN(HWTimer,watchdog_sec)
1472 }
1473
1474 #endif
1475
1476 return (HWTimer);
1477 }
1478 #else // simulation part
1479 return (-1); // no HW timer in simulation
1480 #endif
1481 return(-1); //omaps00090550
1482 }
1483
1484 #if (GSM_IDLE_RAM != 0) // Compile only if GSM_IDLE_RAM enabled
1485
1486 void l1s_adapt_traffic_controller(void)
1487 {
1488 BOOL l1s_extram;
1489 UWORD8 nb_bitmap;
1490 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
1491
1492 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl);
1493
1494 l1s_extram = FALSE;
1495
1496 for(nb_bitmap=0; ((nb_bitmap < SIZE_TAB_L1S_MONITOR) && (l1s_extram == FALSE)); nb_bitmap++)
1497 {
1498 if (nb_bitmap == 1)
1499 {
1500 l1s_extram |= (((INT_RAM_GSM_IDLE_L1S_PROCESSES1 ^ gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap]) & gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap]) != 0);
1501 }else
1502 {
1503 l1s_extram |= (gsm_idle_ram_ctl->task_bitmap_idle_ram[nb_bitmap] != 0);
1504 }
1505 }
1506
1507 if ((l1s_extram != FALSE) && (!READ_TRAFFIC_CONT_STATE))
1508 {
1509 CSMI_TrafficControllerOn();
1510 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
1511 {
1512 l1s_trace_mftab();
1513 }
1514 #endif
1515 }
1516 }
1517 #endif
1518
1519
1520 // l1s_sleep_manager()
1521 // Description:
1522 // evaluate the loading of the system
1523 // - SIM, UART, LCD ....
1524 // - Nucleus tasks, Hisrs, timers
1525 // - Timer1, Timer2, Watchdog
1526 // program Big or Deep sleep
1527
1528 void l1s_sleep_manager()
1529 {
1530 //UWORD8 temp=0; OMAPS00090550
1531
1532 UWORD16 temp_clear_intr;
1533
1534 // fn when l1s_sleep_manager function is called
1535 #if (CODE_VERSION != SIMULATION)
1536 UWORD32 sleep_time = l1s.actual_time.fn_mod42432;
1537 #else
1538 UWORD32 sleep_time = l1s.actual_time.fn;
1539 #endif
1540
1541 #if(CHIPSET == 15)
1542 Uint8 sleep_status;
1543 #endif
1544
1545 #if (GSM_IDLE_RAM != 0)
1546 T_L1S_GSM_IDLE_INTRAM * gsm_idle_ram_ctl;
1547 BOOL flag_traffic_controller_state = 0;
1548 gsm_idle_ram_ctl = &(l1s.gsm_idle_ram_ctl);
1549
1550 #if (AUDIO_TASK == 1)
1551 gsm_idle_ram_ctl->l1s_full_exec = l1s.l1_audio_it_com;
1552 #endif
1553
1554 if (gsm_idle_ram_ctl->l1s_full_exec == TRUE)
1555 return;
1556 #endif
1557
1558 if (l1_config.pwr_mngt == PWR_MNGT)
1559 {
1560 // Power management is enabled
1561 WORD32 min_time, OSload, HWtimer,wake_up_time,min_time_gauging;
1562 UWORD32 sleep_mode;
1563 #if (ANLG_FAM != 11)
1564 WORD32 afc_fix;
1565 #endif
1566 UWORD32 uw32_store_next_time;
1567 #if (CHIPSET != 15)
1568 static UWORD32 previous_sleep = FRAME_STOP;
1569 #endif
1570 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
1571 BOOL extended_page_mode_state = 0; //Store state of extended page mode
1572 #endif
1573 #if (CHIPSET != 15)
1574 WORD32 time_from_last_wakeup=0;
1575 #endif
1576
1577 #if (OP_BT == 1)
1578 WORD32 hci_ll_status;
1579 #endif
1580
1581 // init for trace and debug
1582 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_UNDEFINED;
1583 l1s.pw_mgr.wakeup_type = WAKEUP_FOR_UNDEFINED;
1584
1585 #if (CHIPSET != 15)
1586 time_from_last_wakeup = (sleep_time - l1s.pw_mgr.wakeup_time + 42432) % 42432;
1587 #endif
1588
1589
1590 #if (CODE_VERSION != SIMULATION)
1591 //=================================================
1592 // Protect System structures
1593 // must be called BEFORE INT_DisableIRQ() while
1594 // Nucleus does not restore IRQ/FIQ bits !!!!
1595 //=================================================
1596 OS_system_protect();
1597 //=================================================
1598 // Disable IRQ
1599 //=================================================
1600 INT_DisableIRQ();
1601 #endif // NOT SIMULATION
1602 //=================================================
1603 // check System (SIM, UART, LDC ..... )
1604 //=================================================
1605 #if (CHIPSET == 15)
1606 #if (WCP_PROF == 0)
1607 sleep_mode = Check_Peripheral_App(); /* For Locosto */
1608 #else
1609 sleep_mode = DO_NOT_SLEEP; //Check_Peripheral_App(); /* For Locosto */
1610 #endif
1611 #else
1612 sleep_mode = Cust_check_system();
1613 #endif
1614
1615 #if (GSM_IDLE_RAM != 0)
1616 //=================================================
1617 // check System (SIM, UART, LDC ..... )
1618 //=================================================
1619 gsm_idle_ram_ctl->sleep_mode = sleep_mode;
1620 #endif
1621
1622 if (sleep_mode == DO_NOT_SLEEP)
1623 {
1624 OS_system_Unprotect();
1625 // free System structure
1626 // Enable all IRQ
1627 //l1_pwmgr_irq_dis_flag = 0;
1628 #if (CODE_VERSION!=SIMULATION)
1629 INT_EnableIRQ();
1630 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_CHECK, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1631 #endif
1632 #if (GSM_IDLE_RAM != 0)
1633 gsm_idle_ram_ctl->os_load = 0;
1634 gsm_idle_ram_ctl->hw_timer = 0;
1635 #endif // GSM_IDLE_RAM
1636 return;
1637 }
1638
1639
1640 #if (OP_L1_STANDALONE == 0)
1641 /*GC_Sleep(); OMAPS00134004*/
1642 #endif
1643 //=================================================
1644 // check OS loading
1645 //=================================================
1646 OSload = OS_get_inactivity_ticks();
1647 #if (CODE_VERSION!=SIMULATION)
1648 if ((OSload >= 0) && (OSload <= MIN_SLEEP_TIME)){
1649 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_OSLOAD;
1650 l1_pwmgr_debug.fail_ret_val = OSload;
1651 }
1652 #endif //NOT SIMULATION
1653
1654 //=================================================
1655 // check HW Timers loading
1656 //=================================================
1657 HWtimer= l1s_get_HWTimers_ticks();
1658 #if (CODE_VERSION!=SIMULATION)
1659 if (HWtimer == 0){
1660 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_HWTIMER;
1661 l1_pwmgr_debug.fail_ret_val = 0;
1662 }
1663 #endif //NOT SIMULATION
1664
1665 #if (GSM_IDLE_RAM != 0)
1666 //=================================================
1667 // check OS loading
1668 //=================================================
1669 gsm_idle_ram_ctl->os_load = OSload;
1670
1671 //=================================================
1672 // check HW Timers loading
1673 //=================================================
1674 gsm_idle_ram_ctl->hw_timer = HWtimer;
1675 #endif // GSM_IDLE_RAM
1676
1677 if ((OSload > 0) && (OSload <= MIN_SLEEP_TIME))
1678 OSload =0;
1679
1680 //=================================================
1681 // check next gauging task for Packet Idle
1682 //=================================================
1683 #if L1_GPRS
1684 min_time_gauging = l1s_get_next_gauging_in_Packet_Idle();
1685 #else
1686 min_time_gauging = -1; // not used
1687 #endif
1688 #if (CODE_VERSION!=SIMULATION)
1689 if (min_time_gauging == 0){
1690 l1_pwmgr_debug.fail_id = FAIL_SLEEP_DUE_TO_MINTIMEGAUGING;
1691 l1_pwmgr_debug.fail_ret_val = 0;
1692 }
1693 #endif // NOT SIMULATION
1694
1695
1696 #if (OP_BT == 1)
1697 hci_ll_status = hci_ll_ok_for_sleep();
1698 #endif
1699 // check if immediate activity planned
1700 // 0 means immediate activity
1701 // in case big sleep is choosen (sleep mode == FRAME_STOP) because of UART or SIM,
1702 // return and wait end of this activity (few TDMA frames) then check on next TDMA frames
1703 // if MS can go in deep sleep
1704 if ( !OSload
1705 || !HWtimer
1706 || !min_time_gauging
1707 #if (CHIPSET != 15)
1708 || ((sleep_mode != CLOCK_STOP) && ((l1s.pw_mgr.why_big_sleep == BIG_SLEEP_DUE_TO_UART) || (l1s.pw_mgr.why_big_sleep == BIG_SLEEP_DUE_TO_SIM)))
1709 #endif
1710 #if (OP_BT == 1)
1711 || !hci_ll_status
1712 #endif
1713 )
1714 {
1715
1716
1717
1718 #if (OP_L1_STANDALONE == 0)
1719 /*GC_Wakeup(); OMAPS00134004*/
1720 #endif
1721
1722 #if (CODE_VERSION != SIMULATION)
1723 OS_system_Unprotect();
1724 // free System structure
1725 // Enable all IRQ
1726 INT_EnableIRQ();
1727 // Wake up UART
1728 #if (GSM_IDLE_RAM != 0)
1729 // Traffic controller has to be enabled before calling SER_WakeUpUarts
1730 // as this function can access the external RAM.
1731 // Reset the flag that will indicates if an interrup will put the traffic
1732 // controller ON during that time.
1733 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
1734 if (!READ_TRAFFIC_CONT_STATE)
1735 {
1736 flag_traffic_controller_state = 1;
1737 CSMI_TrafficControllerOn();
1738 }
1739 #endif
1740
1741 #if (CHIPSET != 15)
1742 SER_WakeUpUarts(); // Wake up Uarts
1743 #else
1744 // To be checked if this needs a change
1745 #endif
1746
1747 #if (GSM_IDLE_RAM != 0)
1748 // The traffic controller state shall be restored as it was before
1749 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1750 // in between and activated the traffic controller.
1751 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
1752 {
1753 CSMI_TrafficControllerOff();
1754 }
1755 flag_traffic_controller_state = 0;
1756 #endif
1757 #endif
1758 #if (CODE_VERSION!=SIMULATION)
1759 l1_trace_fail_sleep(FAIL_SLEEP_OSTIMERGAUGE, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1760 #endif
1761 return;
1762 }
1763 //=================================================
1764 // Select sleep duration ....
1765 //=================================================
1766 // remember: -1 means no activity planned
1767 min_time = OSload;
1768 //l1a_l1s_com.time_to_next_l1s_task is UW32, min_time is W32. Max value of l1a_l1s_com.time_to_next_l1s_task will be 2p31
1769 //and ,min_time max value will be 2p30. If min_time > l1a_l1s_com.time_to_next_l1s_task,
1770 //means MSB of l1a_l1s_com.time_to_next_l1s_task is zero. so, we can use- uw32_store_next_time & 0x7FFFFFFF
1771 uw32_store_next_time = l1a_l1s_com.time_to_next_l1s_task;
1772
1773 if (min_time == -1) min_time = (WORD32)uw32_store_next_time;
1774 //else MIN(min_time, (WORD32)l1a_l1s_com.time_to_next_l1s_task)
1775 else
1776 {
1777 if(min_time > l1a_l1s_com.time_to_next_l1s_task) min_time = uw32_store_next_time & 0x7FFFFFFF;
1778 //else min_time = min_time;
1779 }
1780 if (HWtimer != -1) MIN(min_time, HWtimer)
1781 if (min_time_gauging != -1) MIN(min_time, min_time_gauging)
1782
1783 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
1784 // to trace the Wake up source
1785 // depending of min_time choose the wakeup_type
1786 l1s.pw_mgr.wakeup_type = WAKEUP_FOR_L1_TASK;
1787 if (min_time == l1a_l1s_com.time_to_next_l1s_task) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_L1_TASK;
1788 if (min_time == HWtimer) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_HW_TIMER_TASK;
1789 if (min_time == min_time_gauging) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_GAUGING_TASK;
1790 if (min_time == OSload) l1s.pw_mgr.wakeup_type = WAKEUP_FOR_OS_TASK;
1791 #endif
1792
1793 //=================================================
1794 // Choose DEEP or BIG SLEEP
1795 //=================================================
1796 if ( ((l1s.pw_mgr.mode_authorized == DEEP_SLEEP) && (sleep_mode == CLOCK_STOP)) ||
1797 ((l1s.pw_mgr.mode_authorized == ALL_SLEEP) && (sleep_mode == CLOCK_STOP)) )
1798 {
1799 // Check now gauging histogramme or if in inactive period of cell selection
1800 #if (W_A_DSP_IDLE3 == 1) && (CODE_VERSION!=SIMULATION)
1801 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
1802 ( l1s_dsp_com.dsp_ndb_ptr->d_dsp_state == C_DSP_IDLE3))
1803 #else
1804 #if (CHIPSET == 12) || (CHIPSET == 15)
1805 if (((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0)) &&
1806 !CLKM_READ_nIDLE3)
1807 #else
1808 if ((l1s.pw_mgr.enough_gaug == TRUE) || (l1a_l1s_com.mode == CS_MODE0))
1809 #endif
1810 #endif
1811 l1s.pw_mgr.sleep_performed = CLOCK_STOP;
1812 else
1813 {
1814 // BIG SLEEP is chosen : check the reason
1815 l1s.pw_mgr.sleep_performed = FRAME_STOP;
1816 if ((l1s.pw_mgr.enough_gaug != TRUE) && (l1a_l1s_com.mode != CS_MODE0))
1817 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_GAUGING;
1818 else
1819 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_DSP_TRACES;
1820 }
1821 }
1822 if (l1s.pw_mgr.mode_authorized == BIG_SLEEP)
1823 l1s.pw_mgr.why_big_sleep = BIG_SLEEP_DUE_TO_SLEEP_MODE;
1824
1825 if ( ((l1s.pw_mgr.mode_authorized == BIG_SLEEP) && (sleep_mode >= FRAME_STOP)) ||
1826 ((l1s.pw_mgr.mode_authorized >= DEEP_SLEEP) && (sleep_mode == FRAME_STOP)) )
1827 l1s.pw_mgr.sleep_performed = FRAME_STOP;
1828
1829
1830
1831 #if (CHIPSET != 15)
1832 if ((previous_sleep == CLOCK_STOP) && (time_from_last_wakeup < 7))
1833 {
1834 #if (CODE_VERSION != SIMULATION)
1835 OS_system_Unprotect(); // free System structure
1836 INT_EnableIRQ(); // Enable all IRQ
1837 #if (GSM_IDLE_RAM != 0)
1838 // Traffic controller has to be enabled before calling SER_WakeUpUarts
1839 // as this function can access the external RAM.
1840 // Reset the flag that will indicates if an interrup will put the traffic
1841 // controller ON during that time.
1842 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
1843 if (!READ_TRAFFIC_CONT_STATE)
1844 {
1845 flag_traffic_controller_state = 1;
1846 CSMI_TrafficControllerOn();
1847 }
1848 #endif
1849
1850
1851 SER_WakeUpUarts(); // Wake up Uarts
1852
1853
1854
1855 #if (GSM_IDLE_RAM != 0)
1856 // The traffic controller state shall be restored as it was before
1857 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
1858 // in between and activated the traffic controller.
1859 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
1860 {
1861 CSMI_TrafficControllerOff();
1862 }
1863 flag_traffic_controller_state = 0;
1864 #endif
1865 #endif // NOT SIMULATION
1866 return;
1867 }
1868 #else // CHIPSET == 15
1869
1870
1871
1872 if (l1s.pw_mgr.sleep_performed == CLOCK_STOP)
1873 {
1874
1875 #if (CODE_VERSION != SIMULATION)
1876 UWORD8 local_sleep_status;
1877
1878
1879 local_sleep_status = Peripheral_interface[UART_ID](SLEEP_CMD);
1880 sleep_status = local_sleep_status;
1881 if(local_sleep_status == 0)
1882 {
1883 l1_pwmgr_debug.fail_id = UART_ID;
1884 l1_pwmgr_debug.fail_ret_val = sleep_status;
1885 }
1886
1887 OS_system_Unprotect();
1888 local_sleep_status = Peripheral_interface[MADC_AS_ID](SLEEP_CMD); /* Call MADC & Stereo Sleep before I2C */
1889 OS_system_protect();
1890 sleep_status &= local_sleep_status;
1891 if(local_sleep_status == 0)
1892 {
1893 l1_pwmgr_debug.fail_id = MADC_AS_ID;
1894 l1_pwmgr_debug.fail_ret_val = sleep_status;
1895 }
1896
1897 local_sleep_status = Peripheral_interface[USB_ID](SLEEP_CMD);
1898 sleep_status &= local_sleep_status;
1899 if(local_sleep_status == 0)
1900 {
1901 l1_pwmgr_debug.fail_id = USB_ID;
1902 l1_pwmgr_debug.fail_ret_val = sleep_status;
1903 }
1904
1905 local_sleep_status = Peripheral_interface[USIM_ID](SLEEP_CMD);
1906 sleep_status &= local_sleep_status;
1907 if(local_sleep_status == 0)
1908 {
1909 l1_pwmgr_debug.fail_id = USIM_ID;
1910 l1_pwmgr_debug.fail_ret_val = sleep_status;
1911 }
1912
1913 local_sleep_status = Peripheral_interface[I2C_ID](SLEEP_CMD);
1914 sleep_status &= local_sleep_status;
1915 if(local_sleep_status == 0)
1916 {
1917 l1_pwmgr_debug.fail_id = I2C_ID;
1918 l1_pwmgr_debug.fail_ret_val = sleep_status;
1919 }
1920
1921 local_sleep_status = Peripheral_interface[LCD_ID](SLEEP_CMD);
1922 sleep_status &= local_sleep_status;
1923 if(local_sleep_status == 0)
1924 {
1925 l1_pwmgr_debug.fail_id = LCD_ID;
1926 l1_pwmgr_debug.fail_ret_val = sleep_status;
1927 }
1928
1929 local_sleep_status = Peripheral_interface[CAMERA_ID](SLEEP_CMD);
1930 sleep_status &= local_sleep_status;
1931 if(local_sleep_status == 0)
1932 {
1933 l1_pwmgr_debug.fail_id = CAMERA_ID;
1934 l1_pwmgr_debug.fail_ret_val = sleep_status;
1935 }
1936 local_sleep_status = Peripheral_interface[BCI_ID](SLEEP_CMD);
1937 sleep_status &= local_sleep_status;
1938 if(local_sleep_status == 0)
1939 {
1940 l1_pwmgr_debug.fail_id = BCI_ID;
1941 l1_pwmgr_debug.fail_ret_val = sleep_status;
1942 }
1943
1944 #endif // NOT SIMULATION
1945 if(!sleep_status)
1946 {
1947
1948 #if (OP_L1_STANDALONE == 0)
1949 /*GC_Wakeup(); OMAPS00134004*/
1950 #endif
1951
1952 #if (CODE_VERSION != SIMULATION)
1953 OS_system_Unprotect();
1954 l1_trace_fail_sleep(FAIL_SLEEP_PERIPH_SLEEP, l1_pwmgr_debug.fail_id, l1_pwmgr_debug.fail_ret_val);
1955 #endif // NOT SIMULATION
1956 local_sleep_status = Peripheral_interface[UART_ID](WAKE_CMD); //OMAPS00090550
1957 local_sleep_status = Peripheral_interface[USB_ID](WAKE_CMD); //OMAPS00090550
1958 local_sleep_status = Peripheral_interface[USIM_ID](WAKE_CMD); //OMAPS00090550
1959 local_sleep_status = Peripheral_interface[I2C_ID](WAKE_CMD);//OMAPS00090550
1960 local_sleep_status = Peripheral_interface[LCD_ID](WAKE_CMD);//OMAPS00090550
1961 local_sleep_status = Peripheral_interface[CAMERA_ID](WAKE_CMD);//OMAPS00090550
1962 local_sleep_status = Peripheral_interface[MADC_AS_ID](WAKE_CMD);//OMAPS00090550
1963 local_sleep_status = Peripheral_interface[BCI_ID](WAKE_CMD); //wake up for battery charger interface//OMAPS00090550
1964 INT_EnableIRQ();
1965 return;
1966 }
1967 }
1968
1969 #endif // CHIPSET == 15
1970
1971 #if (CHIPSET != 15)
1972 // update previous sleep
1973 previous_sleep = l1s.pw_mgr.sleep_performed;
1974 #endif
1975
1976
1977 #if (CODE_VERSION != SIMULATION)
1978
1979 #if (CHIPSET == 12) || (CHIPSET == 15)
1980 F_INTH_DISABLE_ONE_IT(C_INTH_FRAME_IT); // mask Frame int.
1981 #else
1982 INTH_DISABLEONEIT(IQ_FRAME); // mask Frame int.
1983 #endif
1984 #endif
1985
1986 //=====================================================
1987 // if CLOCK_STOP : stop RF, TPU, asleep Omega, DPLL, SPI
1988 // if FRAME_STOP : asleep Omega, SPI
1989 //=====================================================
1990 #if (CODE_VERSION != SIMULATION)
1991 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
1992 {
1993 // ==== STop RF and TPU..... ===================
1994
1995 //L1_trace_string("Proceeding to Deep Sleep\n");
1996
1997
1998 l1dmacro_RF_sleep();
1999
2000 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =TPU_CTRL_RESET |
2001 // TSP_CTRL_RESET |TPU_CTRL_CLK_EN;
2002 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) =0;
2003
2004 //===== SET default value for gauging =========
2005 // If we have come in here during the inactive period of cell
2006 // selection, then load the ULPD timers with default values
2007 // (used when the MS lost the network: in this case the deep sleep may be used)
2008 if (l1a_l1s_com.mode == CS_MODE0)
2009 {
2010 l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE*8,DEFAULT_32KHZ_VALUE);
2011 }
2012
2013 #if (CHIPSET == 15)
2014
2015
2016 /* These APIs are to be provided by BSP */
2017 // Disable_APC_BG();
2018 gpio_sleep(); //LCD_Floating Pin Fix
2019 DBB_Configure_DS();
2020
2021 //gpio_sleep(); //LCD_Floating Pin Fix
2022
2023 #endif
2024
2025
2026 }
2027 #if (CHIPSET == 15)
2028 else
2029 {
2030 //DBB_Configure_BS(); // Not used
2031 }
2032 #endif
2033
2034
2035 #if (CHIPSET == 15)
2036 // The following command writes '0' into CKM_OCPCLK register in DRP;
2037 // This is done before disabling DPLL
2038 // CKM_OCPCLK (R/W) = Address 0xFFFF040C
2039 // Bit 0: 0 ?OCP clock is the DCXO clock.
2040 // 1 ?OCP clock is the divided DSP clock
2041 // Bit 31:1 Not Used
2042 (drp_regs->CKM_OCPCLKL) &= (~(0x1));
2043 asm(" NOP");
2044 asm(" NOP");
2045 #endif
2046
2047
2048
2049 //==============================================
2050 // disable DPLL (do not provide clk to DSP & RIF (RIF))
2051 //==============================================
2052 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
2053 // disable DPLL (do not provide clk to DSP & RIF (Bridge))
2054 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= CLKM_DPLL_DIS ; /* CLKM_BRIDGE_DIS removed by Ranga*/
2055 #endif
2056
2057 //==============================================
2058 // if CLOCK_STOP or FRAME-STOP : Asleep OMEGA (ABB)
2059 //==============================================
2060 #if (ANLG_FAM != 11)
2061 afc_fix = ABB_sleep(l1s.pw_mgr.sleep_performed, l1s.afc,l1s.pw_mgr.afc_bypass_mode);
2062 #else
2063 // Nothing to be done as it should be handled by BSP_TWL3029_Configure_DS/BS
2064 #endif
2065
2066 #if (OP_BT == 1)
2067 hci_ll_go_to_sleep();
2068 #endif
2069 //=================================================
2070 // STop SPI .....
2071 //=================================================
2072
2073 #if(CHIPSET != 15)
2074 *((volatile UWORD16 *)MEM_SPI)&=0xFFFE; // SPI CLK DISABLED
2075 #endif
2076 #endif // NOT SIMULATION
2077
2078
2079 //=================================================
2080 // CQ19599: For Calypso+ chipset, extended page mode
2081 // shall be disabled before entering deep sleep and
2082 // restored at wake up
2083 //=================================================
2084 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
2085 extended_page_mode_state = (BOOL) f_memif_extended_page_mode_read_bit();
2086 f_memif_extended_page_mode_disable();
2087 #endif
2088
2089 //=================================================
2090 // Init the timer :
2091 //
2092 // a margin of 4 frames (>MIN_SLEEP_TIME) is taken
2093 // when evaluating system loading, because 1 frame
2094 // is lost for wakeup only, and because sleep
2095 // duration less than 1 frame is not worth ....
2096 //
2097 // 1 2 3 4 5 6 7 8
2098 // SLEEP_CTRL SLEEP WAKEUP TASK (RF,Timer, ...)
2099 //
2100 //=================================================
2101 //ULPD Timer can be loaded up to MAX_GSM_TIMER (possible in CS_MODE0)
2102 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2103 {
2104 // DEEP SLEEP -> need time to setup afc and rf
2105 wake_up_time = min_time - l1_config.params.rf_wakeup_tpu_scenario_duration;
2106 #if (CODE_VERSION == NOT_SIMULATION)
2107 // Sleep one more TDMA - this is done as part of merging init and TPU control
2108 wake_up_time += 1;
2109 #endif
2110
2111 }
2112 else
2113 // BIG SLEEP
2114 wake_up_time = min_time - 1;
2115
2116
2117
2118 #if (CODE_VERSION != SIMULATION)
2119 if ( wake_up_time >= MAX_GSM_TIMER)
2120 ULDP_TIMER_INIT(MAX_GSM_TIMER);
2121 else
2122 ULDP_TIMER_INIT(wake_up_time);
2123
2124 ULDP_TIMER_LD; // Load the timer
2125
2126 // BUG3060. Clear pending IQ_TGSM from ULPD. This could happen in case ULPD was frozen
2127 // with zero into its GSM counter. In that case, the interrupt is still pending
2128 // and if it is not cleared, it wakes the board up just after switching the clock.
2129 // Clear it into the ULPD...
2130 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on
2131 //reading the register.
2132 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
2133 // ... and next into the INTH. (must be done in this order
2134
2135 #if (CHIPSET == 12) || (CHIPSET == 15)
2136 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
2137 F_INTH_ENABLE_ONE_IT(C_INTH_TGSM_IT);
2138 #else
2139 INTH_RESETONEIT(IQ_TGSM); // clear TDMA IRQ
2140 INTH_ENABLEONEIT(IQ_TGSM); // Unmask ULPD GSM int.
2141 #endif
2142
2143 #if (GSM_IDLE_RAM != 0)
2144 if (READ_TRAFFIC_CONT_STATE)
2145 {
2146 CSMI_TrafficControllerOff();
2147 }
2148 #endif
2149
2150 ULDP_TIMER_START; // start count down
2151
2152
2153 #if (GSM_IDLE_RAM_DEBUG == 1)
2154 (*( volatile unsigned short* )(0xFFFE4802)) &= ~ (1 << 2); // GPIO-2=0
2155 #endif
2156
2157 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2158 // DEEP SLEEP
2159 {
2160 #if (OP_WCP == 1) && (OP_L1_STANDALONE != 1)
2161 // specific sleep for WCP
2162 arm7_deep_sleep();
2163 #else // NO OP_WCP
2164 #if (W_A_CALYPSO_BUG_01435 == 1)
2165 f_arm_sleep_cmd(DEEP_SLEEP);
2166 #else
2167 //EMIF_SetConfReg ( 0, 0, 2 ,1 ,0);
2168 asm(" NOP");
2169 asm(" NOP");
2170 asm(" NOP");
2171 asm(" NOP");
2172 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_DEEP_SLEEP); // set deep sleep mode
2173 asm(" NOP");
2174 asm(" NOP");
2175 asm(" NOP");
2176 asm(" NOP");
2177 // set deep sleep mode in case it is not set back by hardware
2178 *((volatile UWORD16 *)CLKM_ARM_CLK) |= (CLKM_DEEP_SLEEP);
2179
2180 //EMIF_SetConfReg ( 0, 0, 2 ,0 ,0);
2181 // *((volatile UWORD16 *)CLKM_ARM_CLK) &= 0xFFFF; // set deep sleep mode
2182 // *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_MCLK_EN); // For Debug only
2183
2184
2185 #endif
2186 #endif // OP_WCP
2187 }
2188 else
2189 {
2190 // BIG SLEEP / l1s.pw_mgr.sleep_performed == FRAME_STOP
2191
2192 //==========================================================
2193 //Shut down PERIPHERALS clocks UWIRE and ARMIO if authorized
2194 //==========================================================
2195
2196 #if(CHIPSET != 15)
2197 UWORD16 clocks_stopped; //OMAPS90550- new
2198 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
2199 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
2200 *((volatile UWORD16 *)ARMIO_CNTL_REG) &= ~(ARMIO_CLOCKEN);
2201 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
2202 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) &= ~(0x0001);
2203 #else
2204 // Nothing to be done as it is taken care by Locosto_Configure_BS
2205 #endif
2206
2207 #if (W_A_CALYPSO_BUG_01435 == 1)
2208 f_arm_sleep_cmd(BIG_SLEEP);
2209 #else
2210
2211 *((volatile UWORD16 *)CLKM_ARM_CLK) &= ~(CLKM_MCLK_EN); // set big sleep mode
2212 #endif
2213 }
2214 #else // Simulation part
2215 l1s.pw_mgr.sleep_duration = wake_up_time;
2216 hw.deep_sleep_en = 1;
2217 status = NU_Suspend_Task(&L1S_task);
2218 // check status value...
2219 if (status)
2220 {
2221 #if (TRACE_TYPE==5)
2222 sprintf(errormsg,"Error somewhere in the L1S application to suspend : deep sleep\n");
2223 log_sim_error(ERR);
2224 #endif
2225 EXIT;
2226 }
2227 #endif // SIMULATION
2228
2229 //=================================================
2230 // Wake-up procedure
2231 //=================================================
2232 // Restore L1 data base, Nucleus, HW Timers ....
2233 //=================================================
2234
2235 #if (GSM_IDLE_RAM_DEBUG == 1)
2236 (*( volatile unsigned short* )(0xFFFE4802)) |= (1 << 2); // GPIO-2=1
2237 #endif
2238
2239
2240 l1s_wakeup();
2241
2242 #if (CHIPSET == 15)
2243 // The following command writes '1' into CKM_OCPCLK register in DRP;
2244 // This is done after the DPLL is up
2245 // CKM_OCPCLK (R/W) = Address 0xFFFF040C
2246 // Bit 0: 0 ?OCP clock is the DCXO clock.
2247 // 1 ?OCP clock is the divided DSP clock
2248 // Bit 31:1 Not Used
2249 (drp_regs->CKM_OCPCLKL) |= (0x1);
2250 asm(" NOP");
2251 asm(" NOP");
2252 #endif
2253
2254 l1s.pw_mgr.wakeup_time = l1s.actual_time.fn_mod42432;
2255
2256 if (l1s.pw_mgr.wakeup_time == sleep_time)
2257 // sleep duration == 0 -> wakeup in the same frame as sleep
2258 l1s.pw_mgr.wakeup_type = WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0;
2259
2260 #if (GSM_IDLE_RAM != 0)
2261 // Update counters with sleep duration -> will be used case expiration in next wake up phase before traffic controller is enabled by msg sending
2262 gsm_idle_ram_ctl->os_load -= (l1s.pw_mgr.sleep_duration);
2263 gsm_idle_ram_ctl->hw_timer -= (l1s.pw_mgr.sleep_duration);
2264
2265 if (l1s.pw_mgr.wakeup_type != WAKEUP_FOR_L1_TASK)
2266 {
2267 if (!READ_TRAFFIC_CONT_STATE)
2268 {
2269 CSMI_TrafficControllerOn();
2270 }
2271 }
2272 #endif
2273 //=================================================
2274 //if CLOCK_STOP : restart TPU and RF....
2275 //=================================================
2276 #if (CODE_VERSION != SIMULATION)
2277 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2278 {
2279 // (*(volatile UWORD16 *)l1s_tpu_com.reg_cmd) = TPU_CTRL_CLK_EN;
2280 UWORD8 local_sleep_status;
2281
2282
2283 #if (CHIPSET == 15)
2284
2285 DBB_Wakeup_DS();
2286
2287 gpio_wakeup(); //LCD_Floating Pin Fix
2288
2289 /* These APIs to be provided by BSP */
2290 //Enable_APC_BG();
2291 //BT_Wakeup();
2292 //IRDA_Wakeup();
2293 local_sleep_status = Peripheral_interface[UART_ID](WAKE_CMD); //OMAPS00090550
2294 local_sleep_status = Peripheral_interface[USB_ID](WAKE_CMD);//OMAPS00090550
2295 local_sleep_status = Peripheral_interface[USIM_ID](WAKE_CMD);//OMAPS00090550
2296 local_sleep_status = Peripheral_interface[I2C_ID](WAKE_CMD);//OMAPS00090550
2297 local_sleep_status = Peripheral_interface[LCD_ID](WAKE_CMD);//OMAPS00090550
2298 local_sleep_status = Peripheral_interface[CAMERA_ID](WAKE_CMD);//OMAPS00090550
2299
2300 OS_system_Unprotect();
2301 local_sleep_status = Peripheral_interface[MADC_AS_ID](WAKE_CMD);//OMAPS00090550
2302 local_sleep_status = Peripheral_interface[BCI_ID](WAKE_CMD); //wake up for battery charger//OMAPS00090550
2303 OS_system_protect();
2304 //added for OMAPS00090550 warning removal
2305 if(local_sleep_status == 0)
2306 {
2307 l1_pwmgr_debug.fail_ret_val = local_sleep_status;
2308 }
2309 //upto this OMAPS00090550
2310
2311
2312 #endif
2313 l1dmacro_RF_wakeup();
2314
2315 }
2316
2317 #if ((CHIPSET ==4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
2318 // enable DPLL (provide clk to DSP & RIF(Bridge) in small/big sleep)
2319 // On CALYPSO, BRIDGE clock can be cut according to the ARM sleep mode even during DMA transfer
2320 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS | CLKM_BRIDGE_DIS);
2321 #elif (CHIPSET == 12)
2322 // Nothing to be done because if DSP wants clock, it will exit from IDLE3 mode, which wakes up the DPLL
2323 #elif (CHIPSET == 15)
2324 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS);
2325 #endif
2326
2327 //=================================================
2328 //if CLOCK_STOP or FRAME-STOP : ReStart SPI
2329 //=================================================
2330 #if(CHIPSET != 15)
2331 *((volatile UWORD16 *)MEM_SPI)|=0x0001; // SPI CLK ENABLED
2332 #endif
2333
2334 //=================================================
2335 // Wake up ABB
2336 //=================================================
2337 #if (ANLG_FAM != 11)
2338 ABB_wakeup(l1s.pw_mgr.sleep_performed,l1s.afc,l1s.pw_mgr.afc_bypass_mode);
2339 #else
2340 // Nothing to be done here as it will be handled by BSP_TWL3029_Wakeup_DS/BS
2341 #endif
2342
2343 #if (OP_BT == 1)
2344 hci_ll_wake_up();
2345 #endif
2346 #endif //CODE VERSION
2347
2348 //=================================================
2349 // CQ19599: For Calypso+ chipset, restore the extended
2350 // page mode if it was enabled before entering in sleep
2351 //=================================================
2352 #if (W_A_CALYPSO_PLUS_SPR_19599 == 1)
2353 if ( extended_page_mode_state != 0 )
2354 f_memif_extended_page_mode_enable();
2355 #endif
2356
2357 #if (OP_L1_STANDALONE == 0)
2358 /*GC_Wakeup(); OMAPS00134004*/
2359 #endif
2360
2361 #if (CODE_VERSION != SIMULATION)
2362 //=================================================
2363 // enable IRQ
2364 //=================================================
2365 OS_system_Unprotect();
2366 #endif
2367
2368 #if (TRACE_TYPE != 0)
2369 if (l1a_l1s_com.mode != CS_MODE0) // in this mode the trace prevent from going to deep sleep due to UART activity
2370 {
2371 #if (GSM_IDLE_RAM == 0)
2372 l1_trace_sleep(sleep_time,l1s.actual_time.fn_mod42432,l1s.pw_mgr.sleep_performed,l1s.pw_mgr.wakeup_type,l1s.pw_mgr.why_big_sleep, l1s.pw_mgr.wake_up_int_id);
2373 #else
2374 l1_trace_sleep_intram(sleep_time,l1s.actual_time.fn_mod42432,l1s.pw_mgr.sleep_performed,l1s.pw_mgr.wakeup_type,l1s.pw_mgr.why_big_sleep, l1s.pw_mgr.wake_up_int_id);
2375 #if (TRACE_TYPE==1) || (TRACE_TYPE==4)
2376 l1s_trace_mftab();
2377 #endif
2378 #endif
2379 }
2380 l1s.pw_mgr.wake_up_int_id = 0;
2381 #endif
2382
2383 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
2384 trace_info.sleep_performed = TRUE;
2385 #endif
2386
2387 #if (CODE_VERSION != SIMULATION)
2388
2389 //=================================================
2390 // enable IRQ
2391 //=================================================
2392 INT_EnableIRQ();
2393
2394 //=================================================
2395 // Be careful:in case of asynchronous wake-up after sleep
2396 // an IT_TDMA may be unmasked and executed just after OS_system_Unprotect().
2397 // As we already are inside an hisr(), it implies the execution of an another hisr().
2398 // In order to avoid issues with the execution of an hisr() inside the hisr()
2399 // do not add code here after !!!
2400 // if possible respect this rule !
2401 //=================================================
2402
2403 //=================================================
2404 // wake-up UARTs
2405 //this function must be call after the UART interrupt,
2406 //it means after the function INT_EnableIRQ()
2407 //=================================================
2408 {
2409 #if (GSM_IDLE_RAM != 0)
2410 // Traffic controller has to be enabled before calling SER_WakeUpUarts
2411 // as this function can access the external RAM.
2412 // Reset the flag that will indicates if an interrup will put the traffic
2413 // controller ON during that time.
2414 l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int = FALSE;
2415 if (!READ_TRAFFIC_CONT_STATE)
2416 {
2417 flag_traffic_controller_state = 1;
2418 CSMI_TrafficControllerOn();
2419 }
2420 #endif
2421
2422
2423
2424 #if (CHIPSET != 15)
2425 SER_WakeUpUarts(); // Wake up Uarts
2426 #else
2427 // To be checked if this needs a change
2428 #endif
2429
2430
2431 #if (GSM_IDLE_RAM != 0)
2432 // The traffic controller state shall be restored as it was before
2433 // calling SER_WakeUpUarts. Do not disable it if an interrup occured
2434 // in between and activated the traffic controller.
2435 if ((flag_traffic_controller_state == 1) && (l1s.gsm_idle_ram_ctl.trff_ctrl_enable_cause_int == FALSE))
2436 {
2437 CSMI_TrafficControllerOff();
2438 }
2439 flag_traffic_controller_state = 0;
2440 #endif
2441 }
2442 #endif // NOT SIMULATION
2443 }
2444 }
2445
2446 // l1s_wakeup() */
2447 // Description: wake-up of the MCU from GSM Timer it OR unscheduled wake-up
2448 // This function read the TPU timer and fix the :
2449 // - system clock
2450 // - Nucleus timers
2451 // - L1 frame counter
2452 // - L1 next task counter
2453 // - Hardware timers
2454
2455 void l1s_wakeup(void)
2456 {
2457 #if (CODE_VERSION != SIMULATION)
2458 if (l1_config.pwr_mngt == PWR_MNGT)
2459 {
2460 // Restore interrupts ....
2461
2462 #if (CHIPSET == 12) || (CHIPSET == 15)
2463 // mask TGSM int.
2464 F_INTH_DISABLE_ONE_IT(C_INTH_TGSM_IT);
2465 #else
2466 INTH_DISABLEONEIT(IQ_TGSM); // mask TGSM int.
2467 #endif
2468
2469 #if (CHIPSET == 12) || (CHIPSET == 15)
2470 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) C_INTH_B_IRQ_REG) & C_INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
2471 if ( l1s.pw_mgr.wake_up_int_id >= 256 )
2472 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) C_INTH_B_FIQ_REG) & C_INTH_SRC_NUM)+100;
2473 #else
2474 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);// For debug: Save IRQ that causes the waking up
2475 if ( l1s.pw_mgr.wake_up_int_id >= 256 )
2476 l1s.pw_mgr.wake_up_int_id = ((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)+100;
2477 #endif
2478
2479 // clear pending IQ_FRAME it and unmask it
2480 #if (CHIPSET == 12) || (CHIPSET == 15)
2481 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
2482 F_INTH_ENABLE_ONE_IT(C_INTH_FRAME_IT); // Unmask FRAME int.
2483 #else
2484 INTH_RESETONEIT(IQ_FRAME); // clear TDMA IRQ
2485 INTH_ENABLEONEIT(IQ_FRAME); // Unmask FRAME int.
2486 #endif
2487
2488 #if (CHIPSET == 8)
2489 // if deep sleep
2490 if ( l1s.pw_mgr.sleep_performed == CLOCK_STOP )
2491 {
2492 UWORD8 i;
2493
2494 // Loop with check whether DPLL is locked: 100 us max.
2495 for (i=0;i<16;i++)
2496 {
2497 if (DPLL_READ_DPLL_LOCK)
2498 break;
2499 }
2500 wait_ARM_cycles(convert_nanosec_to_cycles(50000)); // 50us
2501
2502 // Enable DPLL
2503 //--------------------------------------------------
2504 DPLL_SET_PLL_ENABLE;
2505
2506 // Loop with check whether DPLL is locked: 100 us max.
2507 for (i=0;i<16;i++)
2508 {
2509 if (DPLL_READ_DPLL_LOCK)
2510 break;
2511 }
2512 wait_ARM_cycles(convert_nanosec_to_cycles(50000)); // 50us
2513 } // if deep sleep
2514
2515 #endif // CHIPSET == 8
2516
2517 //=================================================
2518 //Restart PERIPHERALS clocks if necessary after a big sleep period
2519 // WARNING: restart other clocks modules!!!
2520 //=================================================
2521
2522
2523 #if(CHIPSET == 15)
2524 if(l1s.pw_mgr.sleep_performed == FRAME_STOP )
2525 {
2526
2527 //ABB_Wakeup_BS(); //Not Used
2528 //DBB_Wakeup_BS(); //Not Used
2529 }
2530 #else
2531 // if big sleep
2532 if ( l1s.pw_mgr.sleep_performed == FRAME_STOP )
2533 {
2534
2535 UWORD16 clocks_stopped;
2536 clocks_stopped = (l1s.pw_mgr.clocks & l1s.pw_mgr.modules_status);
2537 if((clocks_stopped & ARMIO_CLK_CUT) == ARMIO_CLK_CUT)
2538 *((volatile UWORD16 *)ARMIO_CNTL_REG) |= ARMIO_CLOCKEN;
2539 if((clocks_stopped & UWIRE_CLK_CUT) == UWIRE_CLK_CUT)
2540 *((volatile UWORD16 *)(MEM_UWIRE + 0x8)) |= 0x0001;
2541
2542 }
2543 #endif
2544
2545
2546 /***************************************************/
2547 /* Compute effective sleeping time .... */
2548 /* */
2549 /* sleep duration is */
2550 /* - TIMER_INIT */
2551 /* - or TIMER_INIT - TIMER_VALUE */
2552 /* */
2553 /* "frame_adjust" = TRUE for unschedules wake-up */
2554 /* FALSE for scheduled wake-up */
2555 /***************************************************/
2556 l1s.pw_mgr.frame_adjust = l1s_compute_wakeup_ticks();
2557
2558 #if (TRACE_TYPE !=0 ) && (TRACE_TYPE != 2) && (TRACE_TYPE != 3)
2559 if ((l1s.pw_mgr.frame_adjust == TRUE))
2560 l1s.pw_mgr.wakeup_type = WAKEUP_BY_ASYNC_INTERRUPT;
2561 #endif
2562
2563
2564 /* Fix Frame */
2565
2566 l1s_recover_Frame();
2567
2568
2569 /* Fix Hardware Timers */
2570 /* */
2571 /* GSM 1.0 : ntd - timer clock not cut */
2572 /* */
2573 /* GSM 1.5 : deep sleep - need to fix timers */
2574
2575 if (l1s.pw_mgr.sleep_performed == CLOCK_STOP)
2576 l1s_recover_HWTimers();
2577
2578
2579 /* Fix Os */
2580
2581 if (Cust_recover_Os()) l1s.pw_mgr.Os_ticks_required = TRUE;
2582 }
2583 #else // SIMULATION part
2584 // update L1 timers (FN,...)
2585 l1s_recover_Frame();
2586 #endif
2587 }
2588
2589
2590
2591 /* l1s_wakeup_adjust() */
2592 /* Description: 1 frame adjust a fter unscheduled wake-up */
2593 /* This function fix the : */
2594 /* - system clock */
2595 /* - Nucleus timers */
2596 /* - L1 frame counter */
2597 /* - L1 next task counter */
2598 /* - Hardware timers */
2599
2600
2601 void l1s_wakeup_adjust ()
2602 {
2603 #if (CODE_VERSION != SIMULATION)
2604 if (l1_config.pwr_mngt == PWR_MNGT)
2605 {
2606
2607 UWORD32 previous_sleep_time;
2608
2609 /***************************************************/
2610 // Freeze GSM Timer .... */
2611 /***************************************************/
2612 ULDP_TIMER_FREEZE;
2613
2614 /***************************************************/
2615 // Compute effective sleeping time ....
2616 //
2617 // compute sleep duration
2618 // - TIMER_INIT
2619 // - or TIMER_INIT - TIMER_VALUE
2620 /***************************************************/
2621 // save sleep duration that was computed at "unscheduled wakeup"
2622 previous_sleep_time = l1s.pw_mgr.sleep_duration;
2623
2624 l1s_compute_wakeup_ticks();
2625
2626 // reset flag for adjustment request ....
2627 l1s.pw_mgr.frame_adjust = FALSE;
2628
2629 // fix sleep duration
2630 // => compute difference with duration computed at
2631 // "unscheduled wakeup"
2632 l1s.pw_mgr.sleep_duration -= previous_sleep_time;
2633
2634 // adjust system with 1 frame IF NECESSARY ....
2635 if (l1s.pw_mgr.sleep_duration)
2636 {
2637 /***************************************************/
2638 /* Fix Frame */
2639 /***************************************************/
2640 l1s_recover_Frame();
2641
2642 /***************************************************/
2643 /* Fix Os */
2644 /***************************************************/
2645 if (Cust_recover_Os()) l1s.pw_mgr.Os_ticks_required = TRUE;
2646 }
2647 }
2648 #endif
2649 }
2650
2651
2652 /*-------------------------------------------------------*/
2653 /* l1s_compute_wakeup_Ticks() */
2654 /*-------------------------------------------------------*/
2655 /* */
2656 /* Description: wake-up */
2657 /* ------------ */
2658 /* This function compute the sleep duration according to */
2659 /* current value of count down counter. */
2660 /* - if TIMER_VALUE = 0 it returns TIMER_INIT */
2661 /* - else it returns TIMER_INIT-TIMER_VALUE*/
2662 /* */
2663 /*-------------------------------------------------------*/
2664 BOOL l1s_compute_wakeup_ticks(void)
2665 {
2666 UWORD16 temp_clear_intr;
2667 #if (CODE_VERSION != SIMULATION)
2668 if (l1_config.pwr_mngt == PWR_MNGT)
2669 {
2670 // read current value of count down counter
2671 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_VALUE;
2672
2673 // if count down=0 it's a scheduled wake-up....
2674 if (l1s.pw_mgr.sleep_duration == 0)
2675 {
2676 // read sleeping planned value in TPU INIT register
2677 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT;
2678 // INTH is different from the ULPD interrupt -> aynchronous wakeup
2679 #if (CHIPSET == 12) || (CHIPSET == 15)
2680 if (l1s.pw_mgr.wake_up_int_id != C_INTH_TGSM_IT)
2681 #else
2682 if (l1s.pw_mgr.wake_up_int_id != IQ_TGSM)
2683 #endif
2684 {
2685 l1s.pw_mgr.wakeup_type = WAKEUP_ASYNCHRONOUS_ULPD_0;
2686 // RESET IT_ULPD in ULPD module
2687 // The ULDP_GSM_TIMER_IT_REG is a read only register and is cleared on reading the register
2688 temp_clear_intr =(* (volatile UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM;
2689 #if (CHIPSET == 12) || (CHIPSET == 15)
2690 // RESET IQ_TGSM (IT_ULPD) in IT register
2691 F_INTH_RESET_ONE_IT(C_INTH_TGSM_IT);
2692 // RESET IQ_FRAME in IT register
2693 F_INTH_RESET_ONE_IT(C_INTH_FRAME_IT);
2694 l1s.pw_mgr.wake_up_int_id = C_INTH_TGSM_IT;
2695 #else
2696 // RESET IQ_TGSM (IT_ULPD) in IT register
2697 INTH_RESETONEIT(IQ_TGSM);
2698 // RESET IQ_FRAME in IT register
2699 INTH_RESETONEIT(IQ_FRAME);
2700 l1s.pw_mgr.wake_up_int_id = IQ_TGSM;
2701 #endif
2702 return(FALSE);
2703 }
2704 else
2705 return(FALSE);
2706 }
2707 else // Unscheduled wakeup
2708 {
2709 // read sleeping planned value in TPU INIT register & compute time elapsed
2710 l1s.pw_mgr.sleep_duration = READ_ULDP_TIMER_INIT - l1s.pw_mgr.sleep_duration;
2711 return(TRUE);
2712 }
2713 }
2714 #endif
2715 return(FALSE);//omaps00090550
2716 }
2717
2718 /*-------------------------------------------------------*/
2719 /* l1s_recover_Frame() */
2720 /*-------------------------------------------------------*/
2721 /* */
2722 /* Description: adjust layer1 data from sleep duration */
2723 /* ------------ */
2724 /*-------------------------------------------------------*/
2725 void l1s_recover_Frame(void)
2726 {
2727 if (l1_config.pwr_mngt == PWR_MNGT)
2728 {
2729 /***************************************************/
2730 /* Fix Frame counters . */
2731 /***************************************************/
2732 l1s.debug_time += l1s.pw_mgr.sleep_duration; // used for debug and by L3 scenario.
2733
2734 // Time...
2735 // Update "actual time".
2736 l1s_increment_time(&(l1s.actual_time), l1s.pw_mgr.sleep_duration);
2737
2738 // Update "next time".
2739 l1s.next_time = l1s.actual_time;
2740 l1s_increment_time(&(l1s.next_time), 1); // Next time is actual_time + 1
2741
2742 #if L1_GPRS
2743 // Update "next plus time".
2744 l1s.next_plus_time = l1s.next_time;
2745 l1s_increment_time(&(l1s.next_plus_time), 1); // Next_plus time is next_time + 1
2746 #endif
2747
2748 #if (TRACE_TYPE == 1) || (TRACE_TYPE == 4)
2749 trace_fct(CST_L1S_ADJUST_TIME, (UWORD32)(-1));
2750 #endif
2751
2752 // Multiframe table...
2753 // Increment active frame % mftab size.
2754 l1s.afrm = (l1s.afrm + l1s.pw_mgr.sleep_duration) % MFTAB_SIZE;
2755
2756 // Control function counters...
2757 // Increment frame count from last AFC update.
2758 l1s.afc_frame_count+= l1s.pw_mgr.sleep_duration;
2759 // reset counter to mask SNR/TOA results for 2 fr.
2760 #if (TOA_ALGO == 2)
2761 l1s.toa_var.toa_snr_mask=0;
2762 #else
2763 l1s.toa_snr_mask=0;
2764 #endif
2765
2766 /***************************************************/
2767 /* Fix next L1S task counter */
2768 /***************************************************/
2769 // Decrement time to next L1S task.
2770 if((l1a_l1s_com.time_to_next_l1s_task > 0) &&
2771 (l1a_l1s_com.time_to_next_l1s_task < MAX_FN))
2772 l1a_l1s_com.time_to_next_l1s_task -= l1s.pw_mgr.sleep_duration;
2773 } // l1_config.pwr_mngt == PWR_MNGT
2774 }
2775
2776
2777 /*-------------------------------------------------------*/
2778 /* l1s_recover_HWTimers() */
2779 /*-------------------------------------------------------*/
2780 /* */
2781 /* Description: adjust hardware timers from sleep */
2782 /* ------------ duration */
2783 /* */
2784 /* Timers clocks are enabled after VTCX0+SLICER+13MHZ */
2785 /* setup times. So sleep duration is : */
2786 /* GSM TIMER - SETUP_FRAME + SETUP_SLICER + SETUP_VTCXO */
2787 /* + SETUP_CLK13 */
2788 /*-------------------------------------------------------*/
2789
2790 void l1s_recover_HWTimers(void)
2791 {
2792 #if (CODE_VERSION != SIMULATION)
2793
2794 #define SETUP_FRAME_IN_CLK32 (SETUP_FRAME*4.615*32.768)
2795 #if (CHIPSET == 15)
2796 #define DELTA_TIME (0)
2797 #else
2798 #define DELTA_TIME (SETUP_FRAME_IN_CLK32 -SETUP_SLICER - SETUP_VTCXO)
2799 #endif
2800
2801
2802 if (l1_config.pwr_mngt == PWR_MNGT)
2803 {
2804 WORD32 timer1,timer2,timer;
2805 #if (CHIPSET == 12) || (CHIPSET == 15)
2806 WORD32 timer_sec;
2807 #endif
2808 UWORD16 cntlreg;
2809 UWORD16 modereg;
2810 double duration;
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
2822
2823 //WORD32 old;- OMAPS 90550 new
2824
2825 // read Hercules Timers & Watchdog
2826 //=================================================
2827 // Tint = Tclk * (LOAD_TIM+1) * 2^(PTV+1)
2828 // Tclk = 1.2308us for Fclk=13Mhz
2829 // PTV = 7 (pre-scaler field)
2830 //-------------------------------------------------
2831
2832 cntlreg = Dtimer1_Get_cntlreg();
2833 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
2834 {
2835 cntlreg = cntlreg&0x1F;
2836 cntlreg >>= 2; // take PTV
2837 cntlreg = 1 << (cntlreg+1); // compute 2^(PTV+1)
2838 // convert sleep duration in HWTimers ticks....
2839 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308);
2840 if (duration < 0.0){
2841 duration = 0.0; // This needs to be done for all the timers
2842 }
2843 timer1 = Dtimer1_ReadValue() - (UWORD16) duration;
2844
2845 Dtimer1_Start(0);
2846 Dtimer1_WriteValue(timer1);
2847 Dtimer1_Start(1);
2848 }
2849
2850 cntlreg = Dtimer2_Get_cntlreg();
2851 if ( (cntlreg & D_TIMER_RUN) == D_TIMER_RUN)
2852 {
2853 cntlreg = cntlreg&0x1F;
2854 cntlreg >>= 2; // take PTV
2855 cntlreg = 1 << (cntlreg+1);
2856 // convert sleep duration in HWTimers ticks....
2857 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.0012308);
2858 if (duration < 0.0){
2859 duration = 0.0; // This needs to be done for all the timers
2860 }
2861 timer2 = Dtimer2_ReadValue() - (UWORD16) duration;
2862 Dtimer2_Start(0);
2863 Dtimer2_WriteValue(timer2);
2864 Dtimer2_Start(1);
2865 }
2866
2867 cntlreg = TIMER_Read(0);
2868 modereg = TIMER_Read(2);
2869 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
2870 {
2871 // in watchdog mode PTV is forced to 7
2872 if ( modereg & TIMER_WDOG )
2873 cntlreg |= TIMER_PTV;
2874
2875 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
2876 cntlreg = 1 << (cntlreg+1);
2877 // convert sleep duration in HWTimers ticks....
2878 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.001078);
2879
2880 timer = TIMER_ReadValue() - (UWORD16) duration;
2881 TIMER_START_STOP(0);
2882 TIMER_WriteValue(timer);
2883 TIMER_START_STOP(1);
2884 }
2885
2886 #if (CHIPSET == 12) || (CHIPSET == 15)
2887 cntlreg = TIMER_SEC_Read(0);
2888 modereg = TIMER_SEC_Read(2);
2889 if ( (cntlreg & TIMER_ST) || (modereg & TIMER_WDOG))
2890 {
2891 // in watchdog mode PTV is forced to 7
2892 if ( modereg & TIMER_WDOG )
2893 cntlreg |= TIMER_PTV;
2894
2895 cntlreg = (cntlreg & TIMER_PTV) >> 9; // take PTV
2896 cntlreg = 1 << (cntlreg+1);
2897 // convert sleep duration in HWTimers ticks....
2898 duration = (l1s.pw_mgr.sleep_duration * 4.615 - (DELTA_TIME/32.768)) / (cntlreg * 0.001078);
2899
2900 timer_sec = TIMER_SEC_ReadValue() - (UWORD16) duration;
2901 TIMER_SEC_START_STOP(0);
2902 TIMER_SEC_WriteValue(timer_sec);
2903 TIMER_SEC_START_STOP(1);
2904 }
2905 #endif
2906
2907 }
2908 #endif
2909 }
2910 /*-------------------------------------------------------*/
2911 /* l1s_get_next_gauging_in_Packet_Idle() */
2912 /*-------------------------------------------------------*/
2913 /* */
2914 /* Description: */
2915 /* ------------ */
2916 /* return the nbr of frames before the next gauging */
2917 /* return -1 means no activity planned */
2918 /*-------------------------------------------------------*/
2919 #if L1_GPRS
2920 UWORD32 l1s_get_next_gauging_in_Packet_Idle(void)
2921 {
2922 WORD32 next_gauging;
2923
2924 // gauging performed with Normal Paging (we are in Idle mode)
2925 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
2926 return ((UWORD32)(-1)); // no activity planned //omaps00090550
2927
2928 // we are not in Packet Idle Mode
2929 if (l1a_l1s_com.l1s_en_task[PNP] != TASK_ENABLED)
2930 return ((UWORD32)(-1)); // no activity planned //omaps00090550
2931
2932 next_gauging = l1s.next_gauging_scheduled_for_PNP - l1s.actual_time.fn ;
2933 if (next_gauging < 0)
2934 next_gauging+=MAX_FN;
2935
2936 if (next_gauging <= MIN_SLEEP_TIME)
2937 return(0);
2938
2939 return (next_gauging);
2940 }
2941 #endif
2942 /*-------------------------------------------------------*/
2943 /* l1s_gauging_decision_with_PNP() */
2944 /*-------------------------------------------------------*/
2945 /* */
2946 /* Description: */
2947 /* ------------ */
2948 /* */
2949 /*-------------------------------------------------------*/
2950 #if L1_GPRS
2951 BOOL l1s_gauging_decision_with_PNP(void)
2952 {
2953 #define TWO_SECONDS_IN_FRAME (UWORD16)(2000/4.615)
2954 WORD32 time_to_next_gauging=0; //changed to WORD32- sajal
2955 // It's time to perform the next gauging
2956 time_to_next_gauging = l1s.next_gauging_scheduled_for_PNP - l1s.actual_time.fn;
2957 if (time_to_next_gauging < 0)
2958 {
2959 time_to_next_gauging += MAX_FN;
2960 }
2961
2962 if( (time_to_next_gauging == 0) || (time_to_next_gauging > TWO_SECONDS_IN_FRAME))
2963 {
2964
2965 l1s.next_gauging_scheduled_for_PNP = l1s.actual_time.fn + TWO_SECONDS_IN_FRAME;
2966 if (l1s.next_gauging_scheduled_for_PNP >= MAX_FN) l1s.next_gauging_scheduled_for_PNP -= MAX_FN;
2967 return (TRUE);
2968 }
2969
2970 return (FALSE); // do not perform gauging
2971 }
2972 #endif
2973 /*-------------------------------------------------------*/
2974 /* l1s_gauging_decision_with_NP() */
2975 /*-------------------------------------------------------*/
2976 /* */
2977 /* Description: */
2978 /* ------------ */
2979 /* */
2980 /*-------------------------------------------------------*/
2981 BOOL l1s_gauging_decision_with_NP(void)
2982 {
2983
2984 static UWORD8 time_to_gaug;
2985
2986 // a paging is scheduled or , was scheduled but discarded by a higher priority task
2987 if (l1s.pw_mgr.paging_scheduled == TRUE)
2988 {
2989 l1s.pw_mgr.paging_scheduled = FALSE; // reset Flag.
2990
2991 // A gauging session is needed : start gauging session with this paging bloc !
2992
2993 //Nina modify to save power, not forbid deep sleep, only force gauging in next paging
2994 #if 0
2995 if (l1s.pw_mgr.enough_gaug != TRUE)
2996 time_to_gaug = 0;
2997 #else
2998 if ((l1s.pw_mgr.enough_gaug != TRUE)||(l1s.force_gauging_next_paging_due_to_CCHR == 1))
2999 {
3000 time_to_gaug = 0;
3001 l1s.force_gauging_next_paging_due_to_CCHR = 0;
3002 }
3003 #endif
3004 if (time_to_gaug > 0)
3005 {
3006 time_to_gaug--; // perform the gauging with an another paging.
3007 }
3008 else // perform the gauging with this paging
3009 {
3010 if (l1s.task_status[NP].current_status == ACTIVE )
3011 {
3012 time_to_gaug = GAUG_VS_PAGING_RATE[l1a_l1s_com.bs_pa_mfrms-2]-1;
3013
3014 return (TRUE); // gauging allowed
3015 }
3016 else // a gauging is scheduled to be perform here but the paging is missing
3017 { // (paging discarded by a higher priority task ?)
3018 l1s.pw_mgr.enough_gaug= FALSE; // forbid Deep sleep until next gauging
3019 }
3020 }
3021 }
3022 return (FALSE); // gauging not allowed
3023 }
3024
3025 /*************************************************************/
3026 /* Gauging task management : */
3027 /* */
3028 /* CALYPSO */
3029 /* */
3030 /* 9 8 7 6 5 4 3 2 1 0 */
3031 /* C0 C1 C2 C3 C4 W R - - - */
3032 /* | | */
3033 /* | | */
3034 /* |_ start gauging |_ stop gauging */
3035 /* */
3036 /*OTHERS: */
3037 /* */
3038 /* 11 10 9 8 7 6 5 4 3 2 1 0 */
3039 /* C0 C1 C2 C3 C4 W R - - - - - */
3040 /* | | | | | */
3041 /* | | |_ start gauging |_ stop gauging */
3042 /* | | | | */
3043 /* | |_ (ITCOM) | |(ITCOM) */
3044 /* | | */
3045 /* |_ pgm PLL |_restore PLL */
3046 /* */
3047 /* */
3048 /*************************************************************/
3049 void l1s_gauging_task(void)
3050 {
3051 if (l1_config.pwr_mngt == PWR_MNGT)
3052 {
3053 /*************************************************************/
3054 if (l1s.pw_mgr.gauging_task == ACTIVE)
3055 {
3056 /*************************************************************/
3057 // COUNT = 10 ==> PLL is at 65 Mhz, start the gauging
3058 /*************************************************************/
3059 #if (CHIPSET==7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
3060 // the gauging was started with the begining of the paging
3061 #else
3062 if (l1s.pw_mgr.gaug_count == (l1s.pw_mgr.gaug_duration-1))
3063 {
3064 #if (CODE_VERSION != SIMULATION)
3065 ULDP_GAUGING_START; // start gauging
3066 #endif
3067
3068 #if (TRACE_TYPE != 0)
3069 #if (GSM_IDLE_RAM != 0)
3070 l1_trace_gauging_intram();
3071 #else
3072 l1_trace_gauging();
3073 #endif
3074 #endif
3075 }
3076 #endif
3077
3078 l1s.pw_mgr.gaug_count--; // decrement counter
3079
3080
3081 // When a MISC task is enabled L1S must be ran every frame
3082 // to be able to enable the frame interrupt for DSP
3083 l1a_l1s_com.time_to_next_l1s_task = 0;
3084 }
3085
3086 /*************************************************************/
3087 // REQUEST A GAUGING PROCESS ON EACH PAGING BLOCK
3088 // IN IDLE MODE .....
3089 /*************************************************************/
3090
3091 else if (l1s.pw_mgr.gauging_task == INACTIVE )
3092 {
3093 BOOL decision = FALSE;
3094
3095 if (l1a_l1s_com.l1s_en_task[NP] == TASK_ENABLED)
3096 decision = l1s_gauging_decision_with_NP();
3097 #if L1_GPRS
3098 else
3099 if (l1a_l1s_com.l1s_en_task[PNP] == TASK_ENABLED)
3100 decision = l1s_gauging_decision_with_PNP();
3101 #endif
3102
3103 if (decision == TRUE)
3104 {
3105 // gauging duration
3106 l1s.pw_mgr.gaug_count = l1s.pw_mgr.gaug_duration;
3107
3108 #if (CHIPSET==7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
3109 // start ULPD gauging immediately with Calypso because we needn't IT_COM.
3110 #if (CODE_VERSION != SIMULATION)
3111 ULDP_GAUGING_START;
3112 #if (CHIPSET == 12) || (CHIPSET == 15)
3113 // Force the DPLL to be active
3114 ( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) &= ~(CLKM_DPLL_DIS);
3115 #endif
3116 #endif
3117
3118 #if (TRACE_TYPE != 0)
3119 #if (GSM_IDLE_RAM != 0)
3120 l1_trace_gauging_intram();
3121 #else
3122 l1_trace_gauging();
3123 #endif
3124 #endif
3125 #endif
3126
3127 // DSP programmation .......
3128 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
3129 #if (CHIPSET==4)
3130 l1s_dsp_com.dsp_ndb_ptr->d_pll_config |= B_32KHZ_CALIB;
3131 #endif
3132 #else
3133 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD2; // IDLE1 only for DSP
3134 #endif
3135
3136 l1s.pw_mgr.gauging_task = ACTIVE;
3137 }
3138 }
3139 }
3140 }
3141 /*-------------------------------------------------------*/
3142 /* l1s_gauging_task_end() */
3143 /*-------------------------------------------------------*/
3144 /* */
3145 /* Description: */
3146 /* ------------ */
3147 /* stop the gauging activity */
3148 /*-------------------------------------------------------*/
3149 void l1s_gauging_task_end(void)
3150 {
3151 if (l1_config.pwr_mngt == PWR_MNGT)
3152 {
3153 /*************************************************************/
3154 if (l1s.pw_mgr.gauging_task == ACTIVE)
3155 {
3156 /*************************************************************/
3157 // COUNT = 1 ==> stop the gauging and free DSP idle modes....
3158 /*************************************************************/
3159 if (l1s.pw_mgr.gaug_count == 1)
3160 {
3161 // wait for end of gauging interrupt ...
3162 l1s.pw_mgr.gauging_task = WAIT_IQ;
3163
3164 // Unmask ULPD GAUGING int.
3165 #if (CODE_VERSION != SIMULATION)
3166 #if (CHIPSET == 12) || (CHIPSET == 15)
3167 F_INTH_ENABLE_ONE_IT(C_INTH_ULPD_GAUGING_IT);
3168 #else
3169 INTH_ENABLEONEIT(IQ_ULPD_GAUGING);
3170 #endif
3171 ULDP_GAUGING_STOP; // stop ULPD gauging
3172 #if (CHIPSET == 12) || (CHIPSET == 15)
3173 // Allow the DPLL to be cut according to ARM sleep mode
3174 //( * (volatile SYS_UWORD16 *) CLKM_CNTL_CLK) |= (CLKM_DPLL_DIS);
3175 #endif
3176 #endif
3177
3178 // DSP programmation : free IDLE modes...
3179 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
3180 #if (CHIPSET==4)
3181 l1s_dsp_com.dsp_ndb_ptr->d_pll_config &= ~B_32KHZ_CALIB;
3182 #endif
3183 #else
3184 l1s_dsp_com.dsp_ndb_ptr->d_pll_clkmod1 = CLKMOD1;
3185 #endif
3186
3187
3188 #if (CODE_VERSION == SIMULATION)
3189 // in order to simulate the Gauging interrupt
3190 GAUGING_Handler();
3191
3192 #if (TRACE_TYPE==5)
3193 trace_ULPD("Stop Gauging", l1s.actual_time.fn);
3194 #endif
3195 #endif
3196 }
3197 }
3198 }
3199 }
3200
3201 //#pragma GSM_IDLE_DUPLICATE_FOR_INTERNAL_RAM_END
3202 #endif
3203
3204
3205