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comparison gsm-fw/cdg/cdginc-conservative/p_cgrlc.h @ 656:9ba088a875bd

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gsm-fw/cdg: "conservative" version created
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Thu, 25 Sep 2014 10:00:35 +0000
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655:6c363c453db2 656:9ba088a875bd
1 /*
2 +--------------------------------------------------------------------------+
3 | PROJECT : PROTOCOL STACK |
4 | FILE : p_cgrlc.h |
5 | SOURCE : "sap\cgrlc.pdf" |
6 | LastModified : "2004-05-17" |
7 | IdAndVersion : "8010.119.008.04" |
8 | SrcFileTime : "Thu Nov 29 09:38:02 2007" |
9 | Generated by CCDGEN_2.5.5A on Thu Sep 25 09:52:55 2014 |
10 | !!DO NOT MODIFY!!DO NOT MODIFY!!DO NOT MODIFY!! |
11 +--------------------------------------------------------------------------+
12 */
13
14 /* PRAGMAS
15 * PREFIX : CGRLC
16 * COMPATIBILITY_DEFINES : NO
17 * ALWAYS_ENUM_IN_VAL_FILE: NO
18 * ENABLE_GROUP: NO
19 * CAPITALIZE_TYPENAME: NO
20 */
21
22
23 #ifndef P_CGRLC_H
24 #define P_CGRLC_H
25
26
27 #define CDG_ENTER__P_CGRLC_H
28
29 #define CDG_ENTER__FILENAME _P_CGRLC_H
30 #define CDG_ENTER__P_CGRLC_H__FILE_TYPE CDGINC
31 #define CDG_ENTER__P_CGRLC_H__LAST_MODIFIED _2004_05_17
32 #define CDG_ENTER__P_CGRLC_H__ID_AND_VERSION _8010_119_008_04
33
34 #define CDG_ENTER__P_CGRLC_H__SRC_FILE_TIME _Thu_Nov_29_09_38_02_2007
35
36 #include "CDG_ENTER.h"
37
38 #undef CDG_ENTER__P_CGRLC_H
39
40 #undef CDG_ENTER__FILENAME
41
42
43 #include "p_cgrlc.val"
44
45 #ifndef __T_CGRLC_fix_alloc_struct__
46 #define __T_CGRLC_fix_alloc_struct__
47 /*
48 * Fixed Allocation structure
49 * CCDGEN:WriteStruct_Count==1637
50 */
51 typedef struct
52 {
53 U8 bitmap_len; /*< 0: 1> Bitmap length */
54 U8 bitmap_array[127]; /*< 1:127> Bitmap array */
55 U32 end_fn; /*<128: 4> End of bitmap framenumber */
56 U8 final_alloc; /*<132: 1> Final allocation */
57 U8 _align0; /*<133: 1> alignment */
58 U8 _align1; /*<134: 1> alignment */
59 U8 _align2; /*<135: 1> alignment */
60 } T_CGRLC_fix_alloc_struct;
61 #endif
62
63 #ifndef __T_CGRLC_freq_param__
64 #define __T_CGRLC_freq_param__
65 /*
66 * Frequency Parameters
67 * CCDGEN:WriteStruct_Count==1638
68 */
69 typedef struct
70 {
71 U16 bcch_arfcn; /*< 0: 2> ARFCN of the BCCH */
72 U8 pdch_hopping; /*< 2: 1> Hopping or no hopping is used on the assigned PDCH */
73 U8 pdch_band; /*< 3: 1> PDCH band */
74 } T_CGRLC_freq_param;
75 #endif
76
77 #ifndef __T_CGRLC_pwr_ctrl_param__
78 #define __T_CGRLC_pwr_ctrl_param__
79 /*
80 * Power Control Parameters
81 * CCDGEN:WriteStruct_Count==1639
82 */
83 typedef struct
84 {
85 U8 alpha; /*< 0: 1> Alpha */
86 U8 gamma_ch[CGRLC_MAX_TIMESLOTS]; /*< 1: 8> Gamma */
87 U8 _align0; /*< 9: 1> alignment */
88 U8 _align1; /*< 10: 1> alignment */
89 U8 _align2; /*< 11: 1> alignment */
90 } T_CGRLC_pwr_ctrl_param;
91 #endif
92
93 #ifndef __T_CGRLC_c_value__
94 #define __T_CGRLC_c_value__
95 /*
96 * C-Value
97 * CCDGEN:WriteStruct_Count==1640
98 */
99 typedef struct
100 {
101 S32 c_lev; /*< 0: 4> C-value raw data level */
102 U16 c_idx; /*< 4: 2> C-value raw data index */
103 U16 c_acrcy; /*< 6: 2> C-value raw data accuracy */
104 } T_CGRLC_c_value;
105 #endif
106
107 #ifndef __T_CGRLC_pan_struct__
108 #define __T_CGRLC_pan_struct__
109 /*
110 * Pan Structure
111 * CCDGEN:WriteStruct_Count==1641
112 */
113 typedef struct
114 {
115 U8 inc; /*< 0: 1> Pan increment */
116 U8 dec; /*< 1: 1> Pan decrement */
117 U8 pmax; /*< 2: 1> Pan maximum */
118 U8 _align0; /*< 3: 1> alignment */
119 } T_CGRLC_pan_struct;
120 #endif
121
122 #ifndef __T_CGRLC_glbl_pwr_ctrl_param__
123 #define __T_CGRLC_glbl_pwr_ctrl_param__
124 /*
125 * Global Power Control Parameters
126 * CCDGEN:WriteStruct_Count==1642
127 */
128 typedef struct
129 {
130 U8 alpha; /*< 0: 1> Alpha */
131 U8 t_avg_t; /*< 1: 1> T_AVG_T */
132 U8 pb; /*< 2: 1> Power reduction value */
133 U8 pc_meas_chan; /*< 3: 1> PC_MEAS_CHAN */
134 U8 pwr_max; /*< 4: 1> Maximum output power of the MS. */
135 U8 _align0; /*< 5: 1> alignment */
136 U8 _align1; /*< 6: 1> alignment */
137 U8 _align2; /*< 7: 1> alignment */
138 } T_CGRLC_glbl_pwr_ctrl_param;
139 #endif
140
141 #ifndef __T_CGRLC_pwr_ctrl__
142 #define __T_CGRLC_pwr_ctrl__
143 /*
144 * Power Control Information
145 * CCDGEN:WriteStruct_Count==1643
146 */
147 typedef struct
148 {
149 U8 _align0; /*< 0: 1> alignment */
150 U8 _align1; /*< 1: 1> alignment */
151 U8 _align2; /*< 2: 1> alignment */
152 U8 v_pwr_ctrl_param; /*< 3: 1> valid-flag */
153 T_CGRLC_pwr_ctrl_param pwr_ctrl_param; /*< 4: 12> Power Control Parameters */
154 U8 _align3; /*< 16: 1> alignment */
155 U8 _align4; /*< 17: 1> alignment */
156 U8 _align5; /*< 18: 1> alignment */
157 U8 v_glbl_pwr_ctrl_param; /*< 19: 1> valid-flag */
158 T_CGRLC_glbl_pwr_ctrl_param glbl_pwr_ctrl_param; /*< 20: 8> Global Power Control Parameters */
159 U8 _align6; /*< 28: 1> alignment */
160 U8 _align7; /*< 29: 1> alignment */
161 U8 _align8; /*< 30: 1> alignment */
162 U8 v_freq_param; /*< 31: 1> valid-flag */
163 T_CGRLC_freq_param freq_param; /*< 32: 4> Frequency Parameters */
164 U8 _align9; /*< 36: 1> alignment */
165 U8 _align10; /*< 37: 1> alignment */
166 U8 _align11; /*< 38: 1> alignment */
167 U8 v_c_value; /*< 39: 1> valid-flag */
168 T_CGRLC_c_value c_value; /*< 40: 8> C-Value */
169 } T_CGRLC_pwr_ctrl;
170 #endif
171
172
173 /*
174 * End of substructure section, begin of primitive definition section
175 */
176
177 #ifndef __T_CGRLC_ENABLE_REQ__
178 #define __T_CGRLC_ENABLE_REQ__
179 /*
180 *
181 * CCDGEN:WriteStruct_Count==1644
182 */
183 typedef struct
184 {
185 U8 enable_cause; /*< 0: 1> Enable Cause */
186 U8 _align0; /*< 1: 1> alignment */
187 U8 _align1; /*< 2: 1> alignment */
188 U8 _align2; /*< 3: 1> alignment */
189 U32 ul_tlli; /*< 4: 4> Uplink TLLI value. */
190 U32 dl_tlli; /*< 8: 4> Downlink TLLI value. */
191 U8 _align3; /*< 12: 1> alignment */
192 U8 _align4; /*< 13: 1> alignment */
193 U8 _align5; /*< 14: 1> alignment */
194 U8 v_pan_struct; /*< 15: 1> valid-flag */
195 T_CGRLC_pan_struct pan_struct; /*< 16: 4> Pan Structure */
196 U8 queue_mode; /*< 20: 1> Type of Queue Mode. */
197 U8 burst_type; /*< 21: 1> Default burst type */
198 U8 ab_type; /*< 22: 1> Default access burst type */
199 U8 t3168_val; /*< 23: 1> T3168 Value */
200 U8 cu_cause; /*< 24: 1> Cell update cause */
201 U8 ac_class; /*< 25: 1> Access control class */
202 U8 change_mark; /*< 26: 1> Change mark value */
203 // ELEM-FF: REL99
204 // U8 nw_rel; /*< 0: 0> Network Release Flag */
205 // ELEM-FF: REL99
206 // U8 pfi_support; /*< 0: 0> Basic Element */
207 U8 _align6; /*< 27: 1> alignment */
208 } T_CGRLC_ENABLE_REQ;
209 #endif
210
211 #ifndef __T_CGRLC_DISABLE_REQ__
212 #define __T_CGRLC_DISABLE_REQ__
213 /*
214 *
215 * CCDGEN:WriteStruct_Count==1645
216 */
217 typedef struct
218 {
219 U8 disable_class; /*< 0: 1> Disable class. */
220 U8 prim_status; /*< 1: 1> Primitive Queue Handler. */
221 U8 _align0; /*< 2: 1> alignment */
222 U8 _align1; /*< 3: 1> alignment */
223 } T_CGRLC_DISABLE_REQ;
224 #endif
225
226 #ifndef __T_CGRLC_UL_TBF_RES__
227 #define __T_CGRLC_UL_TBF_RES__
228 /*
229 *
230 * CCDGEN:WriteStruct_Count==1646
231 */
232 typedef struct
233 {
234 U32 starting_time; /*< 0: 4> TBF starting time. */
235 U8 tbf_mode; /*< 4: 1> Type of TBF. */
236 U8 prim_status; /*< 5: 1> Primitive Queue Handler. */
237 U8 polling_bit; /*< 6: 1> Polling bit */
238 U8 cs_mode; /*< 7: 1> Type of Coding Scheme. */
239 U8 mac_mode; /*< 8: 1> Type of MAC mode. */
240 U8 nts_max; /*< 9: 1> Number of Timeslots. */
241 U8 tn_mask; /*< 10: 1> timeslot mask */
242 U8 tfi; /*< 11: 1> TFI value. */
243 U8 ti; /*< 12: 1> TLLI indicator. */
244 U8 bs_cv_max; /*< 13: 1> Maximum Countdown value. */
245 U8 tlli_cs_mode; /*< 14: 1> Type of Coding Scheme in Contention Resolution. */
246 U8 r_bit; /*< 15: 1> R bit */
247 T_CGRLC_fix_alloc_struct fix_alloc_struct; /*< 16:136> Fixed Allocation structure */
248 U16 rlc_db_granted; /*<152: 2> RLCdata block granted */
249 U8 _align0; /*<154: 1> alignment */
250 U8 _align1; /*<155: 1> alignment */
251 T_CGRLC_pwr_ctrl pwr_ctrl; /*<156: 48> Power Control Information */
252 } T_CGRLC_UL_TBF_RES;
253 #endif
254
255 #ifndef __T_CGRLC_DL_TBF_REQ__
256 #define __T_CGRLC_DL_TBF_REQ__
257 /*
258 *
259 * CCDGEN:WriteStruct_Count==1647
260 */
261 typedef struct
262 {
263 U32 starting_time; /*< 0: 4> TBF starting time. */
264 U8 rlc_mode; /*< 4: 1> Type of RLC mode. */
265 U8 cs_mode; /*< 5: 1> Type of Coding Scheme. */
266 U8 mac_mode; /*< 6: 1> Type of MAC mode. */
267 U8 nts_max; /*< 7: 1> Number of Timeslots. */
268 U8 tn_mask; /*< 8: 1> timeslot mask */
269 U8 tfi; /*< 9: 1> TFI value. */
270 U8 t3192_val; /*< 10: 1> Value of T3192. */
271 U8 ctrl_ack_bit; /*< 11: 1> Ctrl ack bit */
272 U8 polling_bit; /*< 12: 1> Polling bit */
273 U8 _align0; /*< 13: 1> alignment */
274 U8 _align1; /*< 14: 1> alignment */
275 U8 _align2; /*< 15: 1> alignment */
276 T_CGRLC_pwr_ctrl pwr_ctrl; /*< 16: 48> Power Control Information */
277 } T_CGRLC_DL_TBF_REQ;
278 #endif
279
280 #ifndef __T_CGRLC_TBF_REL_REQ__
281 #define __T_CGRLC_TBF_REL_REQ__
282 /*
283 *
284 * CCDGEN:WriteStruct_Count==1648
285 */
286 typedef struct
287 {
288 U8 tbf_mode; /*< 0: 1> Type of TBF. */
289 U8 tbf_rel_cause; /*< 1: 1> TBF Release Cause. */
290 U8 _align0; /*< 2: 1> alignment */
291 U8 _align1; /*< 3: 1> alignment */
292 U32 rel_fn; /*< 4: 4> Release after Poll with fn. */
293 } T_CGRLC_TBF_REL_REQ;
294 #endif
295
296 #ifndef __T_CGRLC_TBF_REL_IND__
297 #define __T_CGRLC_TBF_REL_IND__
298 /*
299 *
300 * CCDGEN:WriteStruct_Count==1649
301 */
302 typedef struct
303 {
304 U8 tbf_mode; /*< 0: 1> Type of TBF. */
305 U8 tbf_rel_cause; /*< 1: 1> TBF Release Cause. */
306 U8 _align0; /*< 2: 1> alignment */
307 U8 v_c_value; /*< 3: 1> valid-flag */
308 T_CGRLC_c_value c_value; /*< 4: 8> C-Value */
309 U8 dl_trans_id; /*< 12: 1> DL Assignmnet ID */
310 U8 _align1; /*< 13: 1> alignment */
311 U8 _align2; /*< 14: 1> alignment */
312 U8 _align3; /*< 15: 1> alignment */
313 } T_CGRLC_TBF_REL_IND;
314 #endif
315
316 #ifndef __T_CGRLC_TBF_REL_RES__
317 #define __T_CGRLC_TBF_REL_RES__
318 /*
319 *
320 * CCDGEN:WriteStruct_Count==1650
321 */
322 typedef struct
323 {
324 U8 tbf_mode; /*< 0: 1> Type of TBF. */
325 U8 _align0; /*< 1: 1> alignment */
326 U8 _align1; /*< 2: 1> alignment */
327 U8 _align2; /*< 3: 1> alignment */
328 } T_CGRLC_TBF_REL_RES;
329 #endif
330
331 #ifndef __T_CGRLC_UL_TBF_IND__
332 #define __T_CGRLC_UL_TBF_IND__
333 /*
334 *
335 * CCDGEN:WriteStruct_Count==1651
336 */
337 typedef struct
338 {
339 U8 access_type; /*< 0: 1> Access Type. */
340 U8 ra_prio; /*< 1: 1> Radio priority */
341 U8 nr_blocks; /*< 2: 1> Number of blocks */
342 U8 llc_prim_type; /*< 3: 1> LLC Primitive type */
343 U16 peak; /*< 4: 2> Peak value */
344 U16 rlc_oct_cnt; /*< 6: 2> Number of bytes for TBF */
345 // ELEM-FF: REL99 AND TI_PS_FF_TBF_EST_PACCH
346 // U8 tbf_est_pacch; /*< 0: 0> TBF establishment on PACCH */
347 } T_CGRLC_UL_TBF_IND;
348 #endif
349
350 #ifndef __T_CGRLC_DATA_REQ__
351 #define __T_CGRLC_DATA_REQ__
352 /*
353 *
354 * CCDGEN:WriteStruct_Count==1652
355 */
356 typedef struct
357 {
358 U8 blk_owner; /*< 0: 1> Block owner. */
359 U8 data_array[CGRLC_MAX_CTRL_MSG_SIZE]; /*< 1: 23> Data Array. */
360 } T_CGRLC_DATA_REQ;
361 #endif
362
363 #ifndef __T_CGRLC_DATA_IND__
364 #define __T_CGRLC_DATA_IND__
365 /*
366 *
367 * CCDGEN:WriteStruct_Count==1653
368 */
369 typedef struct
370 {
371 U32 fn; /*< 0: 4> Received frame number. */
372 U8 tn; /*< 4: 1> Timeslot number */
373 U8 data_array[CGRLC_MAX_CTRL_MSG_SIZE]; /*< 5: 23> Data Array. */
374 } T_CGRLC_DATA_IND;
375 #endif
376
377 #ifndef __T_CGRLC_POLL_REQ__
378 #define __T_CGRLC_POLL_REQ__
379 /*
380 *
381 * CCDGEN:WriteStruct_Count==1654
382 */
383 typedef struct
384 {
385 U32 poll_fn; /*< 0: 4> Poll frame number. */
386 U8 tn; /*< 4: 1> Timeslot number */
387 U8 poll_b_type; /*< 5: 1> Poll burst type */
388 U8 ctrl_ack; /*< 6: 1> Ctrl_ack */
389 U8 _align0; /*< 7: 1> alignment */
390 } T_CGRLC_POLL_REQ;
391 #endif
392
393 #ifndef __T_CGRLC_ACCESS_STATUS_REQ__
394 #define __T_CGRLC_ACCESS_STATUS_REQ__
395 /*
396 *
397 * CCDGEN:WriteStruct_Count==1655
398 */
399 typedef struct
400 {
401 U8 dummy; /*< 0: 1> no parameters */
402 } T_CGRLC_ACCESS_STATUS_REQ;
403 #endif
404
405 #ifndef __T_CGRLC_CTRL_MSG_SENT_IND__
406 #define __T_CGRLC_CTRL_MSG_SENT_IND__
407 /*
408 *
409 * CCDGEN:WriteStruct_Count==1656
410 */
411 typedef struct
412 {
413 U8 dummy; /*< 0: 1> no parameters */
414 } T_CGRLC_CTRL_MSG_SENT_IND;
415 #endif
416
417 #ifndef __T_CGRLC_STARTING_TIME_IND__
418 #define __T_CGRLC_STARTING_TIME_IND__
419 /*
420 *
421 * CCDGEN:WriteStruct_Count==1657
422 */
423 typedef struct
424 {
425 U8 tbf_mode; /*< 0: 1> Type of TBF. */
426 U8 tfi; /*< 1: 1> TFI value. */
427 U8 _align0; /*< 2: 1> alignment */
428 U8 _align1; /*< 3: 1> alignment */
429 } T_CGRLC_STARTING_TIME_IND;
430 #endif
431
432 #ifndef __T_CGRLC_T3192_STARTED_IND__
433 #define __T_CGRLC_T3192_STARTED_IND__
434 /*
435 *
436 * CCDGEN:WriteStruct_Count==1658
437 */
438 typedef struct
439 {
440 U8 dummy; /*< 0: 1> no parameters */
441 } T_CGRLC_T3192_STARTED_IND;
442 #endif
443
444 #ifndef __T_CGRLC_CONT_RES_DONE_IND__
445 #define __T_CGRLC_CONT_RES_DONE_IND__
446 /*
447 *
448 * CCDGEN:WriteStruct_Count==1659
449 */
450 typedef struct
451 {
452 U8 dummy; /*< 0: 1> no parameters */
453 } T_CGRLC_CONT_RES_DONE_IND;
454 #endif
455
456 #ifndef __T_CGRLC_TA_VALUE_IND__
457 #define __T_CGRLC_TA_VALUE_IND__
458 /*
459 *
460 * CCDGEN:WriteStruct_Count==1660
461 */
462 typedef struct
463 {
464 U8 ta_value; /*< 0: 1> Timing Advance Value. */
465 U8 _align0; /*< 1: 1> alignment */
466 U8 _align1; /*< 2: 1> alignment */
467 U8 _align2; /*< 3: 1> alignment */
468 } T_CGRLC_TA_VALUE_IND;
469 #endif
470
471 #ifndef __T_CGRLC_STATUS_IND__
472 #define __T_CGRLC_STATUS_IND__
473 /*
474 *
475 * CCDGEN:WriteStruct_Count==1661
476 */
477 typedef struct
478 {
479 U8 failure; /*< 0: 1> Lower layer failure. */
480 U8 _align0; /*< 1: 1> alignment */
481 U8 _align1; /*< 2: 1> alignment */
482 U8 _align2; /*< 3: 1> alignment */
483 } T_CGRLC_STATUS_IND;
484 #endif
485
486 #ifndef __T_CGRLC_TEST_MODE_REQ__
487 #define __T_CGRLC_TEST_MODE_REQ__
488 /*
489 *
490 * CCDGEN:WriteStruct_Count==1662
491 */
492 typedef struct
493 {
494 U16 no_of_pdus; /*< 0: 2> Number of PDUs. */
495 U8 dl_timeslot_offset; /*< 2: 1> Downlink Timeslot Offset. */
496 U8 test_mode_flag; /*< 3: 1> Test mode flag. */
497 } T_CGRLC_TEST_MODE_REQ;
498 #endif
499
500 #ifndef __T_CGRLC_TEST_MODE_CNF__
501 #define __T_CGRLC_TEST_MODE_CNF__
502 /*
503 *
504 * CCDGEN:WriteStruct_Count==1663
505 */
506 typedef struct
507 {
508 U8 dummy; /*< 0: 1> no parameters */
509 } T_CGRLC_TEST_MODE_CNF;
510 #endif
511
512 #ifndef __T_CGRLC_TEST_END_REQ__
513 #define __T_CGRLC_TEST_END_REQ__
514 /*
515 *
516 * CCDGEN:WriteStruct_Count==1664
517 */
518 typedef struct
519 {
520 U8 dummy; /*< 0: 1> no parameters */
521 } T_CGRLC_TEST_END_REQ;
522 #endif
523
524 #ifndef __T_CGRLC_TRIGGER_IND__
525 #define __T_CGRLC_TRIGGER_IND__
526 /*
527 *
528 * CCDGEN:WriteStruct_Count==1665
529 */
530 typedef struct
531 {
532 U8 prim_type; /*< 0: 1> Type of primitive. */
533 U8 _align0; /*< 1: 1> alignment */
534 U8 _align1; /*< 2: 1> alignment */
535 U8 _align2; /*< 3: 1> alignment */
536 } T_CGRLC_TRIGGER_IND;
537 #endif
538
539 #ifndef __T_CGRLC_STANDBY_STATE_IND__
540 #define __T_CGRLC_STANDBY_STATE_IND__
541 /*
542 *
543 * CCDGEN:WriteStruct_Count==1666
544 */
545 typedef struct
546 {
547 U8 dummy; /*< 0: 1> no parameters */
548 } T_CGRLC_STANDBY_STATE_IND;
549 #endif
550
551 #ifndef __T_CGRLC_READY_STATE_IND__
552 #define __T_CGRLC_READY_STATE_IND__
553 /*
554 *
555 * CCDGEN:WriteStruct_Count==1667
556 */
557 typedef struct
558 {
559 U8 dummy; /*< 0: 1> no parameters */
560 } T_CGRLC_READY_STATE_IND;
561 #endif
562
563 #ifndef __T_CGRLC_TA_VALUE_REQ__
564 #define __T_CGRLC_TA_VALUE_REQ__
565 /*
566 *
567 * CCDGEN:WriteStruct_Count==1668
568 */
569 typedef struct
570 {
571 U8 ta_value; /*< 0: 1> Timing Advance Value. */
572 U8 _align0; /*< 1: 1> alignment */
573 U8 _align1; /*< 2: 1> alignment */
574 U8 _align2; /*< 3: 1> alignment */
575 } T_CGRLC_TA_VALUE_REQ;
576 #endif
577
578 #ifndef __T_CGRLC_INT_LEVEL_REQ__
579 #define __T_CGRLC_INT_LEVEL_REQ__
580 /*
581 *
582 * CCDGEN:WriteStruct_Count==1669
583 */
584 typedef struct
585 {
586 U8 ilev[CGRLC_MAX_TIMESLOTS]; /*< 0: 8> Interference level */
587 } T_CGRLC_INT_LEVEL_REQ;
588 #endif
589
590 #ifndef __T_CGRLC_TEST_MODE_IND__
591 #define __T_CGRLC_TEST_MODE_IND__
592 /*
593 *
594 * CCDGEN:WriteStruct_Count==1670
595 */
596 typedef struct
597 {
598 U8 test_mode_flag; /*< 0: 1> Test mode flag. */
599 U8 _align0; /*< 1: 1> alignment */
600 U8 _align1; /*< 2: 1> alignment */
601 U8 _align2; /*< 3: 1> alignment */
602 } T_CGRLC_TEST_MODE_IND;
603 #endif
604
605 #ifndef __T_CGRLC_READY_TIMER_CONFIG_REQ__
606 #define __T_CGRLC_READY_TIMER_CONFIG_REQ__
607 /*
608 *
609 * CCDGEN:WriteStruct_Count==1671
610 */
611 typedef struct
612 {
613 U32 t3314_val; /*< 0: 4> Value of T3314. */
614 } T_CGRLC_READY_TIMER_CONFIG_REQ;
615 #endif
616
617 #ifndef __T_CGRLC_FORCE_TO_STANDBY_REQ__
618 #define __T_CGRLC_FORCE_TO_STANDBY_REQ__
619 /*
620 *
621 * CCDGEN:WriteStruct_Count==1672
622 */
623 typedef struct
624 {
625 U8 dummy; /*< 0: 1> no parameters */
626 } T_CGRLC_FORCE_TO_STANDBY_REQ;
627 #endif
628
629 #ifndef __T_CGRLC_PWR_CTRL_REQ__
630 #define __T_CGRLC_PWR_CTRL_REQ__
631 /*
632 *
633 * CCDGEN:WriteStruct_Count==1673
634 */
635 typedef struct
636 {
637 T_CGRLC_pwr_ctrl pwr_ctrl; /*< 0: 48> Power Control Information */
638 } T_CGRLC_PWR_CTRL_REQ;
639 #endif
640
641 #ifndef __T_CGRLC_PWR_CTRL_CNF__
642 #define __T_CGRLC_PWR_CTRL_CNF__
643 /*
644 *
645 * CCDGEN:WriteStruct_Count==1674
646 */
647 typedef struct
648 {
649 U8 dummy; /*< 0: 1> no parameters */
650 } T_CGRLC_PWR_CTRL_CNF;
651 #endif
652
653
654 #include "CDG_LEAVE.h"
655
656
657 #endif