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comparison gsm-fw/nucleus/init.S @ 313:9df7f9c72e17

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ARM exception handling: stack setup added
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Mon, 17 Mar 2014 07:47:18 +0000
parents afceeeb2cba1
children
comparison
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312:f05ae34f7ca0 313:9df7f9c72e17
259 ORR r0,r0,#FIQ_MODE @ Set the FIQ mode bits 259 ORR r0,r0,#FIQ_MODE @ Set the FIQ mode bits
260 MSR CPSR,r0 @ Move to the FIQ mode 260 MSR CPSR,r0 @ Move to the FIQ mode
261 261
262 LDR sp,FIQ_Stack_SP @ Setup FIQ stack pointer 262 LDR sp,FIQ_Stack_SP @ Setup FIQ stack pointer
263 263
264 @ set up abort and undef mode stacks - code from TI
265 MRS a1,CPSR @ Pickup current CPSR
266 BIC a1,a1,#MODE_MASK @ Clear the mode bits
267 ORR a1,a1,#ABORT_MODE @ Set the Abort mode bits
268 MSR CPSR,a1 @ Move to the Abort mode
269 LDR sp,=_Except_Stack_SP @ Setup Abort stack pointer
270
271 MRS a1,CPSR @ Pickup current CPSR
272 BIC a1,a1,#MODE_MASK @ Clear the mode bits
273 ORR a1,a1,#UNDEF_MODE @ Set the Undefined mode bits
274 MSR CPSR,a1 @ Move to the Undefined mode
275 LDR sp,=_Except_Stack_SP @ Setup Undefined stack pointer
276 @ (should never be used)
277
278 @ original Nucleus code continues
264 MRS r0,CPSR @ Pickup current CPSR 279 MRS r0,CPSR @ Pickup current CPSR
265 BIC r0,r0,#MODE_MASK @ Clear mode bits 280 BIC r0,r0,#MODE_MASK @ Clear mode bits
266 ORR r0,r0,#SUP_MODE @ Set the supervisor mode bits 281 ORR r0,r0,#SUP_MODE @ Set the supervisor mode bits
267 MSR CPSR,r0 @ All interrupt stacks are setup, 282 MSR CPSR,r0 @ All interrupt stacks are setup,
268 @ return to supervisor mode 283 @ return to supervisor mode