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comparison gsm-fw/L1/include/l1_const.h @ 143:afceeeb2cba1

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Our nuc-fw is destined to become gsm-fw, so I went ahead and did the big hg mv
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Tue, 12 Nov 2013 05:35:48 +0000
parents nuc-fw/L1/include/l1_const.h@1e41550feec5
children 1affe428bf72
comparison
equal deleted inserted replaced
142:15d5977390c2 143:afceeeb2cba1
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1_CONST.H
4 *
5 * Filename l1_const.h
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 #ifdef __MSDOS__ // Running BORLANDC compiler.
11 #ifdef MVC
12 #define EXIT exit(0)
13 #define FAR
14 #else
15 #define EXIT DOS_Exit(0)
16 #define FAR far
17 #endif
18 #else // Running ARM compiler.
19 #define FAR
20 #define EXIT exit(0)
21 #define stricmp strcmp
22 #endif
23
24
25 #if (CODE_VERSION != SIMULATION)
26 #define NULL 0
27 #endif
28
29 #define NO_PAR 0
30
31 #define NO_TASK 0
32 #define ALL_TASK 0xffffffff
33 #define ALL_PARAM 0xffffffff
34
35 #define TRUE 1
36 #define TRUE_L 1L
37 #define FALSE 0
38
39 #define NOT_PENDING 0
40 #define PENDING 1
41
42 #define INACTIVE 2
43 #define ACTIVE 3
44 #define RE_ENTERED 4
45 #define WAIT_IQ 5
46
47 //---------------------------------------------
48 // MCU-DSP bit-field bit position definitions
49 //---------------------------------------------
50 #if L1_GPRS
51 #define GPRS_SCHEDULER 1 // Select GPRS scheduler
52 #endif
53 #define GSM_SCHEDULER 2 // Select GSM scheduler
54
55 //-----------------------------
56 // POWER MANAGEMENT............
57 //-----------------------------
58 #define MIN_SLEEP_TIME (SETUP_FRAME+2+l1_config.params.setup_afc_and_rf) //HW WAKE-UP+MIN_SLEEP(2)+AFC RESTORE(2)
59 #define TPU_LOAD 01
60 #define TPU_FREEZE 02
61
62 // SLEEP ALGO SWITCH
63 #define NO_SLEEP 00 // ------ + ------ + ------
64 #define SMALL_SLEEP 01 // SMALL + ------ + ------
65 #define BIG_SLEEP 02 // ------ + BIG + ------
66 #define DEEP_SLEEP 03 // ------ + BIG + DEEP
67 #define ALL_SLEEP 04 // SMALL + BIG + DEEP
68
69 // GAUGING SAMPLES
70 #define SIZE_HIST 10
71 #define MAX_BAD_GAUGING 3
72
73 // GAUG_IN_32T = (HF in clock of 13Mhz*dpll) * ( LF in Khz)
74 #define GAUG_IN_32T 1348 // gauging duration is 1348*T32 measured on eva4
75
76 // DSP state need to be used to enter Deep Sleep mode
77 #if (W_A_DSP_IDLE3 == 1)
78 #define C_DSP_IDLE3 3
79 #endif
80
81 //-------------------------------------------------
82 // INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
83 // to face temperature variation
84 //
85 // ACQUIS: variations allowed 32.768Khz +- 50 ppm
86 // 9 frames gauging is 1348*T32 (measured on eva4)
87 // UPDATE: variation allowed is +- 6 ppm jitter
88 //-------------------------------------------------
89
90 #define MCUCLK 13000 // 13 Mhz
91 #define LF 32.768
92 #define LF_100PPM 32.7712768 // 32.768*(1+100*10E-6)
93 #define LF_500PPM 32.751616 // 32.768*(1-500*10E-6)
94 #define LF_50PPM 32.7696384 // 32.768*(1+50*10E-6)
95 #define LF_6PPM 32.76819661 // 32.768*(1+6*10E-6)
96
97 #define NB_INIT 5 // nbr of gauging to pass to ACQUIS
98 #define NB_ACQU 10 // nbr of gauging to pass to UPDATE
99
100 #if (CHIPSET ==2 || CHIPSET ==3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9) // PLL is at 65 Mhz !!!!!!
101 #define PLL 5 // 5*13Mhz = 65 Mhz
102 //-------------------------------------------------
103 // INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
104 //
105 // ACQUIS: variations allowed 32.768Khz +- 50 ppm
106 // 9 frames gauging is 1348*T32 (measured on eva4)
107 // UPDATE: variation allowed is +- 6 ppm jitter
108 //-------------------------------------------------
109 #define C_CLK_MIN 1983 // 65000/32.7712768 = 1983.444234
110 #define C_CLK_INIT_MIN 29113 // 0.444234*2^16
111 #define C_CLK_MAX 1984 // 65000 / 32.751616 = 1984.634896
112 #define C_CLK_INIT_MAX 41608 // 0.634896*2^16
113 #define C_DELTA_HF_ACQUIS 130 // 1348/32.768-1348/32.7696384 = 0.002056632ms
114 // 0.002056632/0.0001538 = 130 T65Mhz
115 #define C_DELTA_HF_UPDATE 15 // 1348/32.768-1348/32.76819661 =0.00024691ms
116 // 0.00024691/0.0001538 = 15 T65Mhz
117 #endif
118
119 #define ARMIO_CLK_CUT 0x0001
120 #define UWIRE_CLK_CUT 0x0002
121
122 //-----------------------------
123 // Neighbour cell sync. reading
124 //-----------------------------
125 #if (L1_12NEIGH)
126 #define NBR_NEIGHBOURS 12
127 #else
128 #define NBR_NEIGHBOURS 6
129 #endif
130
131 //-----------------------------
132 // LAYER 1 MEASUREMENT TASKS...
133 //-----------------------------
134 #define NBR_L1S_MEAS_TASKS 4
135
136 #define FSMS 0
137 #define I_BAMS 1
138 #define D_BAMS 2
139 #define SERVMS 3
140
141 #define FSMS_MEAS (TRUE_L << FSMS) // Measurement task on FULL list (Cell Selection/Idle).
142 #define I_BAMS_MEAS (TRUE_L << I_BAMS) // Measurement task on BA list in Idle.
143 #define D_BAMS_MEAS (TRUE_L << D_BAMS) // Measurement task on BA list in Dedicated.
144 #define SERVMS_MEAS (TRUE_L << SERVMS) // Measurement task for Serving.
145
146 #define FSMS_MEAS_MASK ALL_TASK ^ FSMS_MEAS
147 #define I_BAMS_MEAS_MASK ALL_TASK ^ I_BAMS_MEAS
148 #define D_BAMS_MEAS_MASK ALL_TASK ^ D_BAMS_MEAS
149 #define SERVMS_MEAS_MASK ALL_TASK ^ SERVMS_MEAS
150
151 #define A_D_BLEN 456 // SACCH/SDCCH data block length (GSM 5.01 $7)
152 #define TCH_FS_BLEN 378 // TCH FULL SPEECH block length
153 #define TCH_HS_BLEN 211 // TCH HALF SPEECH block length
154 #define TCH_F_D_BLEN 456 // FACCH, TCH_DATA block length
155
156 // Define max PM/TDMA according to DSP code and TPU RAM size
157 //----------------------------------------------------------
158
159 // NOTE: we should use a global variable initialized at L1 start and function of rx synth setup time.
160
161 #if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 4))
162
163 // TPU RAM size limitation
164
165 #define NB_MEAS_MAX 4
166 #define NB_MEAS_MAX_GPRS 4
167
168 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
169
170 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
171
172 // DSP code 33: upto 8 PMs with GSM and GPRS scheduler
173
174 #define NB_MEAS_MAX 8
175 #define NB_MEAS_MAX_GPRS 8
176
177 #elif (DSP == 32)
178
179 // DSP code prior to code 33 support upto 4 PMs with GSM scheduler
180 // and 8 PMs with GPRS scheduler, 6 for DSP 32 because of CPU load
181
182 #define NB_MEAS_MAX 4
183 #define NB_MEAS_MAX_GPRS 6
184
185 #else
186
187
188 // DSP code prior to code 33 support upto 4 PMs with GSM scheduler
189 // and 8 PMs with GPRS scheduler
190
191 #define NB_MEAS_MAX 4
192 #define NB_MEAS_MAX_GPRS 8
193
194 #endif
195 #endif
196 #if (AMR == 1)
197 #define SID_UPDATE_BLEN 212 // SID UPDATE block length
198 #define RATSCCH_BLEN 212 // RATSCCH block length
199 #define TCH_AFS_BLEN 448 // TCH Adaptative Full rate Speech block length
200 // Note: the d_nerr value is calculated thanks to the bit class 1 of the block.
201 // But the number AHS bit class 1 depends on the type of vocoder currently used (c.f. 5.03 &3.10.7.2)
202 #define TCH_AHS_7_95_BLEN 188 // TCH AHS 7.95 Speech block length
203 #define TCH_AHS_7_4_BLEN 196 // TCH AHS 7.4 Speech block length
204 #define TCH_AHS_6_7_BLEN 200 // TCH AHS 6.7 Speech block length
205 #define TCH_AHS_5_9_BLEN 208 // TCH AHS 5.9 Speech block length
206 #define TCH_AHS_5_15_BLEN 212 // TCH AHS 5.15 Speech block length
207 #define TCH_AHS_4_75_BLEN 212 // TCH AHS 4.75 Speech block length
208 #endif
209 //----------------------------------------
210 // LAYER 1 Asynchronous processes names...
211 //----------------------------------------
212 #if (TESTMODE) && !(L1_GPRS)
213 #if (AUDIO_TASK == 1)
214 #if (L1_GTT)
215 #if (OP_L1_STANDALONE == 1)
216 #define NBR_L1A_PROCESSES 45
217 #else
218 #define NBR_L1A_PROCESSES 44
219 #endif
220 #else
221 #if (OP_L1_STANDALONE == 1)
222 #define NBR_L1A_PROCESSES 44
223 #else
224 #define NBR_L1A_PROCESSES 43
225 #endif
226 #endif
227 #else
228 #if (L1_GTT)
229 #if (OP_L1_STANDALONE == 1)
230 #define NBR_L1A_PROCESSES 27
231 #else
232 #define NBR_L1A_PROCESSES 26
233 #endif
234 #else
235 #if (OP_L1_STANDALONE == 1)
236 #define NBR_L1A_PROCESSES 26
237 #else
238 #define NBR_L1A_PROCESSES 25
239 #endif
240 #endif
241 #endif
242 #endif
243
244 #if (TESTMODE) && (L1_GPRS)
245 #if (AUDIO_TASK == 1)
246 #if (L1_GTT)
247 #if (OP_L1_STANDALONE == 1)
248 #define NBR_L1A_PROCESSES 46
249 #else
250 #define NBR_L1A_PROCESSES 45
251 #endif
252 #else
253 #if (OP_L1_STANDALONE == 1)
254 #define NBR_L1A_PROCESSES 45
255 #else
256 #define NBR_L1A_PROCESSES 44
257 #endif
258 #endif
259 #else
260 #if (L1_GTT)
261 #if (OP_L1_STANDALONE == 1)
262 #define NBR_L1A_PROCESSES 28
263 #else
264 #define NBR_L1A_PROCESSES 27
265 #endif
266 #else
267 #if (OP_L1_STANDALONE == 1)
268 #define NBR_L1A_PROCESSES 27
269 #else
270 #define NBR_L1A_PROCESSES 26
271 #endif
272 #endif
273 #endif
274 #endif
275
276 #if !(TESTMODE)
277 #if (AUDIO_TASK == 1)
278 #if (L1_GTT)
279 #if (OP_L1_STANDALONE == 1)
280 #define NBR_L1A_PROCESSES 37
281 #else
282 #define NBR_L1A_PROCESSES 36
283 #endif
284 #else
285 #if (OP_L1_STANDALONE == 1)
286 #define NBR_L1A_PROCESSES 36
287 #else
288 #define NBR_L1A_PROCESSES 35
289 #endif
290 #endif
291 #else
292 #if (L1_GTT)
293 #if (OP_L1_STANDALONE == 1)
294 #define NBR_L1A_PROCESSES 19
295 #else
296 #define NBR_L1A_PROCESSES 18
297 #endif
298 #else
299 #if (OP_L1_STANDALONE == 1)
300 #define NBR_L1A_PROCESSES 18
301 #else
302 #define NBR_L1A_PROCESSES 17
303 #endif
304 #endif
305 #endif
306 #endif
307
308
309 #define FULL_MEAS 0 // l1a_full_list_meas_process(msg)
310 #define CS_NORM 1 // l1a_cs_bcch_process(msg)
311 #define I_6MP 2 // l1a_idle_6strongest_monitoring_process(msg)
312 #define I_SCP 3 // l1a_idle_serving_cell_paging_process(msg)
313 #define I_SCB 4 // l1a_idle_serving_cell_bcch_reading_process(msg)
314 #define I_SMSCB 5 // l1a_idle_smscb_process(msg)
315 #define CR_B 6 // l1a_cres_process(msg)
316 #define ACCESS 7 // l1a_access_process(msg)
317 #define DEDICATED 8 // l1a_dedicated_process(msg)
318 #define I_FULL_MEAS 9 // l1a_dedicated_process(msg)
319 #define I_NMEAS 10 // l1a_idle_ba_meas_process(msg)
320 #define DEDIC_6 11 // l1a_dedic6_process(msg)
321 #define D_NMEAS 12 // l1a_dedic_ba_list_meas_process(msg)
322 #define HW_TEST 13 // l1a_test_process(msg)
323 #define I_BCCHN 14 // l1a_idle_neighbour_cell_bcch_reading_process(msg)
324 #define I_ADC 15 // l1a_mmi_adc_req(msg)
325
326 #if (TESTMODE) && !(L1_GPRS)
327 #define TMODE_FB0 16 // l1a_tmode_fb0_process(msg)
328 #define TMODE_FB1 17 // l1a_tmode_fb1_process(msg)
329 #define TMODE_SB 18 // l1a_tmode_sb_process(msg)
330 #define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg)
331 #define TMODE_RA 20 // l1a_tmode_access_process(msg)
332 #define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg)
333 #define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg)
334 #define TMODE_PM 23 // l1a_tmode_meas_process(msg)
335 #if (AUDIO_TASK == 1)
336 #define L1A_KEYBEEP_STATE 24 // l1a_mmi_keybeep_process(msg)
337 #define L1A_TONE_STATE 25 // l1a_mmi_tone_process(msg)
338 #define L1A_MELODY0_STATE 26 // l1a_mmi_melody0_process(msg)
339 #define L1A_MELODY1_STATE 27 // l1a_mmi_melody1_process(msg)
340 #define L1A_VM_PLAY_STATE 28 // l1a_mmi_vm_playing_process(msg)
341 #define L1A_VM_RECORD_STATE 29 // l1a_mmi_vm_recording_process(msg)
342 #define L1A_SR_ENROLL_STATE 30 // l1a_mmi_sr_enroll_process(msg)
343 #define L1A_SR_UPDATE_STATE 31 // l1a_mmi_sr_update_process(msg)
344 #define L1A_SR_RECO_STATE 32 // l1a_mmi_sr_reco_process(msg)
345 #define L1A_SR_UPDATE_CHECK_STATE 33 // l1a_mmi_sr_update_check_process(msg)
346 #define L1A_AEC_STATE 34 // l1a_mmi_aec_process(msg)
347 #define L1A_FIR_STATE 35 // l1a_mmi_fir_process(msg)
348 #define L1A_AUDIO_MODE_STATE 36 // l1a_mmi_audio_mode_process(msg)
349 #define L1A_MELODY0_E2_STATE 37 // l1a_mmi_melody0_e2_process(msg)
350 #define L1A_MELODY1_E2_STATE 38 // l1a_mmi_melody1_e2_process(msg)
351 #define L1A_VM_AMR_PLAY_STATE 39 // l1a_mmi_vm_amr_playing_process(msg)
352 #define L1A_VM_AMR_RECORD_STATE 40 // l1a_mmi_vm_amr_recording_process(msg)
353 #define L1A_CPORT_STATE 41 // l1a_mmi_cport_process(msg)
354 #if (L1_GTT == 1)
355 #define L1A_GTT_STATE 42 // l1a_mmi_gtt_process(msg)
356 #define INIT_L1 43 // l1a_init_layer1_process(msg)
357 #if (OP_L1_STANDALONE == 1)
358 #define HSW_CONF 44 // l1a_test_config_process(msg)
359 #endif
360 #else
361 #define INIT_L1 42 // l1a_init_layer1_process(msg)
362 #if (OP_L1_STANDALONE == 1)
363 #define HSW_CONF 43 // l1a_test_config_process(msg)
364 #endif
365 #endif
366 #else
367 #if (L1_GTT == 1)
368 #define L1A_GTT_STATE 24 // l1a_mmi_gtt_process(msg)
369 #define INIT_L1 25 // l1a_init_layer1_process(msg)
370 #if (OP_L1_STANDALONE == 1)
371 #define HSW_CONF 26 // l1a_test_config_process(msg)
372 #endif
373 #else
374 #define INIT_L1 24 // l1a_init_layer1_process(msg)
375 #if (OP_L1_STANDALONE == 1)
376 #define HSW_CONF 25 // l1a_test_config_process(msg)
377 #endif
378 #endif
379 #endif
380 #endif
381
382 #if (TESTMODE) && (L1_GPRS)
383 #define TMODE_FB0 16 // l1a_tmode_fb0_process(msg)
384 #define TMODE_FB1 17 // l1a_tmode_fb1_process(msg)
385 #define TMODE_SB 18 // l1a_tmode_sb_process(msg)
386 #define TMODE_BCCH 19 // l1a_tmode_bcch_reading_process(msg)
387 #define TMODE_RA 20 // l1a_tmode_access_process(msg)
388 #define TMODE_DEDICATED 21 // l1a_tmode_dedicated_process(msg)
389 #define TMODE_FULL_MEAS 22 // l1a_tmode_full_list_meas_process(msg)
390 #define TMODE_PM 23 // l1a_tmode_meas_process(msg)
391 #define TMODE_TRANSFER 24 // l1a_tmode_transfer_process(msg)
392 #if (AUDIO_TASK == 1)
393 #define L1A_KEYBEEP_STATE 25 // l1a_mmi_keybeep_process(msg)
394 #define L1A_TONE_STATE 26 // l1a_mmi_tone_process(msg)
395 #define L1A_MELODY0_STATE 27 // l1a_mmi_melody0_process(msg)
396 #define L1A_MELODY1_STATE 28 // l1a_mmi_melody1_process(msg)
397 #define L1A_VM_PLAY_STATE 29 // l1a_mmi_vm_playing_process(msg)
398 #define L1A_VM_RECORD_STATE 30 // l1a_mmi_vm_recording_process(msg)
399 #define L1A_SR_ENROLL_STATE 31 // l1a_mmi_sr_enroll_process(msg)
400 #define L1A_SR_UPDATE_STATE 32 // l1a_mmi_sr_update_process(msg)
401 #define L1A_SR_RECO_STATE 33 // l1a_mmi_sr_reco_process(msg)
402 #define L1A_SR_UPDATE_CHECK_STATE 34 // l1a_mmi_sr_update_check_process(msg)
403 #define L1A_AEC_STATE 35 // l1a_mmi_aec_process(msg)
404 #define L1A_FIR_STATE 36 // l1a_mmi_fir_process(msg)
405 #define L1A_AUDIO_MODE_STATE 37 // l1a_mmi_audio_mode_process(msg)
406 #define L1A_MELODY0_E2_STATE 38 // l1a_mmi_melody0_e2_process(msg)
407 #define L1A_MELODY1_E2_STATE 39 // l1a_mmi_melody1_e2_process(msg)
408 #define L1A_VM_AMR_PLAY_STATE 40 // l1a_mmi_vm_amr_playing_process(msg)
409 #define L1A_VM_AMR_RECORD_STATE 41 // l1a_mmi_vm_amr_recording_process(msg)
410 #define L1A_CPORT_STATE 42 // l1a_mmi_cport_process(msg)
411 #if (L1_GTT == 1)
412 #define L1A_GTT_STATE 43
413 #define INIT_L1 44 // l1a_init_layer1_process(msg)
414 #if (OP_L1_STANDALONE == 1)
415 #define HSW_CONF 45 // l1a_test_config_process(msg)
416 #endif
417 #else
418 #define INIT_L1 43 // l1a_init_layer1_process(msg)
419 #if (OP_L1_STANDALONE == 1)
420 #define HSW_CONF 44 // l1a_test_config_process(msg)
421 #endif
422 #endif
423 #else
424 #if (L1_GTT == 1)
425 #define L1A_GTT_STATE 25
426 #define INIT_L1 26 // l1a_init_layer1_process(msg)
427 #if (OP_L1_STANDALONE == 1)
428 #define HSW_CONF 27 // l1a_test_config_process(msg)
429 #endif
430 #else
431 #define INIT_L1 25 // l1a_init_layer1_process(msg)
432 #if (OP_L1_STANDALONE == 1)
433 #define HSW_CONF 26 // l1a_test_config_process(msg)
434 #endif
435 #endif
436 #endif
437 #endif
438
439 #if !(TESTMODE) && (AUDIO_TASK == 1)
440 #define L1A_KEYBEEP_STATE 16 // l1a_mmi_keybeep_process(msg)
441 #define L1A_TONE_STATE 17 // l1a_mmi_tone_process(msg)
442 #define L1A_MELODY0_STATE 18 // l1a_mmi_melody0_process(msg)
443 #define L1A_MELODY1_STATE 19 // l1a_mmi_melody1_process(msg)
444 #define L1A_VM_PLAY_STATE 20 // l1a_mmi_vm_playing_process(msg)
445 #define L1A_VM_RECORD_STATE 21 // l1a_mmi_vm_recording_process(msg)
446 #define L1A_SR_ENROLL_STATE 22 // l1a_mmi_sr_enroll_process(msg)
447 #define L1A_SR_UPDATE_STATE 23 // l1a_mmi_sr_update_process(msg)
448 #define L1A_SR_RECO_STATE 24 // l1a_mmi_sr_reco_process(msg)
449 #define L1A_SR_UPDATE_CHECK_STATE 25 // l1a_mmi_sr_update_check_process(msg)
450 #define L1A_AEC_STATE 26 // l1a_mmi_aec_process(msg)
451 #define L1A_FIR_STATE 27 // l1a_mmi_fir_process(msg)
452 #define L1A_AUDIO_MODE_STATE 28 // l1a_mmi_audio_mode_process(msg)
453 #define L1A_MELODY0_E2_STATE 29 // l1a_mmi_melody0_e2_process(msg)
454 #define L1A_MELODY1_E2_STATE 30 // l1a_mmi_melody1_e2_process(msg)
455 #define L1A_VM_AMR_PLAY_STATE 31 // l1a_mmi_vm_amr_playing_process(msg)
456 #define L1A_VM_AMR_RECORD_STATE 32 // l1a_mmi_vm_amr_recording_process(msg)
457 #define L1A_CPORT_STATE 33 // l1a_mmi_cport_process(msg)
458 #if (L1_GTT == 1)
459 #define L1A_GTT_STATE 34 // l1a_mmi_tty_process(msg)
460 #define INIT_L1 35 // l1a_init_layer1_process(msg)
461 #if (OP_L1_STANDALONE == 1)
462 #define HSW_CONF 36 // l1a_test_config_process(msg)
463 #endif
464 #else
465 #define INIT_L1 34 // l1a_init_layer1_process(msg)
466 #if (OP_L1_STANDALONE == 1)
467 #define HSW_CONF 35 // l1a_test_config_process(msg)
468 #endif
469 #endif
470 #elif !(TESTMODE) && !(AUDIO_TASK == 1)
471 #if (L1_GTT == 1)
472 #define L1A_GTT_STATE 16 // l1a_mmi_tty_process(msg)
473 #define INIT_L1 17 // l1a_init_layer1_process(msg)
474 #if (OP_L1_STANDALONE == 1)
475 #define HSW_CONF 18 // l1a_test_config_process(msg)
476 #endif
477 #else
478 #define INIT_L1 16 // l1a_init_layer1_process(msg)
479 #if (OP_L1_STANDALONE == 1)
480 #define HSW_CONF 17 // l1a_test_config_process(msg)
481 #endif
482 #endif
483 #endif
484
485 #if TESTMODE
486 #define TMODE_UPLINK (1<<0)
487 #define TMODE_DOWNLINK (1<<1)
488 #endif
489
490 //------------------------------------
491 // LAYER 1 DOWNLINK & UPLINK TASKS...
492 //------------------------------------
493 #define TASK_DISABLED 0
494 #define TASK_ENABLED 1
495
496 #define SEMAPHORE_RESET 0
497 #define SEMAPHORE_SET 1
498
499 #define NO_NEW_TASK -1
500
501
502 // Tasks in the order of their priority (low to high).
503
504 #if !L1_GPRS
505
506 #define NBR_DL_L1S_TASKS 32
507
508 //GSM_TASKS/
509 #define HWTEST 0 // DSP checksum reading
510 #define ADC_CSMODE0 1 // ADC task in CS_MODE0 mode
511 #define DEDIC 2 // Global Dedicated mode switch
512 #define RAACC 3 // Channel access (ul)
513 #define RAHO 4 // Handover access (ul)
514 #define NSYNC 5 // Global Neighbour cell synchro switch
515 #define FBNEW 6 // Frequency burst search (Idle mode)
516 #define SBCONF 7 // Synchro. burst confirmation
517 #define SB2 8 // Synchro. burst read (1 frame uncertainty / SB position)
518 #define FB26 9 // Frequency burst search, dedic/transfer mode MF26 or MF52
519 #define SB26 10 // Synchro burst search, dedic/transfer mode MF26 or MF52
520 #define SBCNF26 11 // Synchro burst confirmation, dedic/transfer mode MF26 or MF52
521 #define FB51 12 // Frequency burst search, dedic mode MF51
522 #define SB51 13 // Synchro burst search, dedic MF51
523 #define SBCNF51 14 // Synchro burst confirmation, dedic MF51
524 #define BCCHN 15 // BCCH Neighbor in GSM Idle
525 #define ALLC 16 // All CCCH Reading
526 #define EBCCHS 17 // Extended BCCH Serving Reading
527 #define NBCCHS 18 // Normal BCCH ServingReading
528 #define SMSCB 19 // CBCH serving Reading
529 #define NP 20 // Normal paging Reading
530 #define EP 21 // Extended pagingReading
531 #define ADL 22 // SACCH(SDCCH) DL
532 #define AUL 23 // SACCH(SDCCH) UL
533 #define DDL 24 // SDCCH DL
534 #define DUL 25 // SDCCH UL
535 #define TCHD 26 // Dummy for TCH Half rate
536 #define TCHA 27 // SACCH(TCH)
537 #define TCHTF 28 // TCH Full rate
538 #define TCHTH 29 // TCH Half rate
539 #define BCCHN_TOP 30 // BCCH Neighbour TOP priority in Idle mode
540 #define SYNCHRO 31 // synchro task: L1S reset
541 //END_GSM_TASKS/
542
543 #else
544
545 #define NBR_DL_L1S_TASKS 45
546
547 //GPRS_TASKS/
548 #define HWTEST 0 // DSP checksum reading
549 #define ADC_CSMODE0 1 // ADC task in CS_MODE0 mode
550 #define DEDIC 2 // Global Dedicated mode switch
551 #define RAACC 3 // Channel access (ul)
552 #define RAHO 4 // Handover access (ul)
553 #define NSYNC 5 // Global Neighbour cell synchro switch
554 #define POLL 6 // Packet Polling (Access)
555 #define PRACH 7 // Packet Random Access Channel
556 #define ITMEAS 8 // Interference measurements
557 #define FBNEW 9 // Frequency burst search (Idle mode)
558 #define SBCONF 10 // Synchro. burst confirmation
559 #define SB2 11 // Synchro. burst read (1 frame uncertainty / SB position)
560 #define PTCCH 12 // Packet Timing Advance control channel
561 #define FB26 13 // Frequency burst search, dedic/transfer mode MF26 or MF52
562 #define SB26 14 // Synchro burst search, dedic/transfer mode MF26 or MF52
563 #define SBCNF26 15 // Synchro burst confirmation, dedic/transfer mode MF26 or MF52
564 #define FB51 16 // Frequency burst search, dedic mode MF51
565 #define SB51 17 // Synchro burst search, dedic MF51
566 #define SBCNF51 18 // Synchro burst confirmation, dedic MF51
567 #define PDTCH 19 // Packet Data channel
568 #define BCCHN 20 // BCCH Neighbor in GSM Idle
569 #define ALLC 21 // All CCCH Reading
570 #define EBCCHS 22 // Extended BCCH Serving Reading
571 #define NBCCHS 23 // Normal BCCH Serving Reading
572 #define ADL 24 // SACCH(SDCCH) DL
573 #define AUL 25 // SACCH(SDCCH) UL
574 #define DDL 26 // SDCCH DL
575 #define DUL 27 // SDCCH UL
576 #define TCHD 28 // Dummy for TCH Half rate
577 #define TCHA 29 // SACCH(TCH)
578 #define TCHTF 30 // TCH Full rate
579 #define TCHTH 31 // TCH Half rate
580 #define PALLC 32 // All PCCCH reading
581 #define SMSCB 33 // CBCH serving Reading
582 #define PBCCHS 34 // PBCCH serving reading
583 #define PNP 35 // Packet Normal paging Reading
584 #define PEP 36 // Packet Extended paging Reading
585 #define SINGLE 37 // Single Block for GPRS
586 #define PBCCHN_TRAN 38 // Packet BCCH Neighbor in Packet Transfer mode.
587 #define PBCCHN_IDLE 39 // Packet BCCH Neighbor in Idle mode.
588 #define BCCHN_TRAN 40 // BCCH Neighbour in Packet Transfer mode
589 #define NP 41 // Normal paging Reading
590 #define EP 42 // Extended paging Reading
591 #define BCCHN_TOP 43 // BCCH Neighbour TOP priority in Idle mode
592 #define SYNCHRO 44 // synchro task: L1S reset
593 //END_GPRS_TASKS/
594
595 #endif
596
597 //------------------------------------
598 // LAYER 1 API
599 //------------------------------------
600 #define MCSI_PORT1 0
601 #define MCSI_PORT2 1
602
603
604 //---------------------------------
605 // DSP vocoder Enable/ Disable
606 //---------------------------------
607
608 #if (L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)
609 #if (FF_L1_TCH_VOCODER_CONTROL == 1)
610 #define TCH_VOCODER_DISABLE_REQ 0
611 #define TCH_VOCODER_ENABLE_REQ 1
612 #define TCH_VOCODER_ENABLED 2
613 #define TCH_VOCODER_DISABLED 3
614
615 // Number of TDMA wait frames until the DSP output is steady
616 #define DSP_VOCODER_ON_TRANSITION 165
617 #endif // FF_L1_TCH_VOCODER_CONTROL
618 #endif
619
620 //---------------------------------
621 // Handover Finished cause defines.
622 //---------------------------------
623 #define HO_COMPLETE 0
624 #define HO_TIMEOUT 1
625
626 //---------------------------------
627 // FB detection algorithm defines.
628 //---------------------------------
629 #define FB_MODE_0 0 // FB detec. mode 0.
630 #define FB_MODE_1 1 // FB detec. mode 1.
631
632 //---------------------------------
633 // AFC control defines.
634 //---------------------------------
635 #define AFC_INIT 1
636 #define AFC_OPEN_LOOP 2
637 #define AFC_CLOSED_LOOP 3
638
639 // For VCXO algo.
640 #if (VCXO_ALGO)
641 #define AFC_INIT_CENTER 4
642 #define AFC_INIT_MAX 5
643 #define AFC_INIT_MIN 6
644 #endif
645 //---------------------------------
646 // TOA control defines.
647 //---------------------------------
648 #define TOA_INIT 1
649 #define TOA_RUN 2
650
651 //---------------------------------
652 // Neighbour Synchro possible status.
653 //---------------------------------
654 #define NSYNC_FREE 0
655 #define NSYNC_PENDING 1
656 #define NSYNC_COMPLETED 2
657 #if (L1_12NEIGH ==1)
658 #define NSYNC_WAIT 3
659 #endif
660
661 /************************************/
662 /* Layer 1 constants declaration... */
663 /************************************/
664 #define MAX_FN ((UWORD32)26*51*2048)
665
666 #if L1_GPRS
667 #define MAX_BLOCK_ID ((UWORD32) (3 * (UWORD32) (MAX_FN / 13))) // Block ID corresponding to fn = FN MAX
668 #endif
669
670 //--------------------------------------------------------
671 // standard specific constants used in l1_config.std.xxx
672 //--------------------------------------------------------
673
674
675 // GSM
676 #define FIRST_ARFCN_GSM 1 // 1st arfcn is 1
677 #define NBMAX_CARRIER_GSM 124 // 124 for GSM, 174 for E_GSM, 374 for DCS1800.
678 #define MAX_TXPWR_GSM 19 // lowest power ctrl level value in GSM band
679 // GSM_E
680 #define FIRST_ARFCN_EGSM 1 // 1st arfcn is 1
681 #define NBMAX_CARRIER_EGSM 174 // 174 carriers for GSM_E.
682 #define MAX_TXPWR_EGSM 19 // lowest power ctrl level value in GSM-E band
683 // PCS1900
684 #define FIRST_ARFCN_PCS 512 // 1st arfcn is 512
685 #define NBMAX_CARRIER_PCS 299 // 299 carriers for PCS1900.
686 #define MAX_TXPWR_PCS 15 // lowest power ctrl level value in PCS band
687 #define TXPWR_TURNING_POINT_PCS 21
688 // DCS1800
689 #define FIRST_ARFCN_DCS 512 // 1st arfcn is 512
690 #define NBMAX_CARRIER_DCS 374 // 374 carriers for DCS1800.
691 #define MAX_TXPWR_DCS 15 // lowest power ctrl level value in DCS band
692 #define TXPWR_TURNING_POINT_DCS 28
693 // GSM850
694 #define FIRST_ARFCN_GSM850 128 // 1st arfcn is 128
695 #define NBMAX_CARRIER_GSM850 124 // 124 carriers for GSM850
696 #define NBMEAS_GSM850 3 // 3 measurement per frame TBD
697 #define MAX_TXPWR_GSM850 19 // lowest power ctrl level value in GSM band
698 // DUAL
699 #define FIRST_DCS_INDEX_DUAL 125 // 1st DCS index within the 498 continu list
700 #define NBMAX_CARRIER_DUAL 124+374 // 374 carriers for DCS1800 + 124 carriers for GSM900 Band
701 #define TXPWR_TURNING_POINT_DUAL 28
702 // DUALEXT
703 #define FIRST_DCS_INDEX_DUALEXT 175 // 1st DCS index within the 548 continu list
704 #define NBMAX_CARRIER_DUALEXT 174+374 // 374 carriers for DCS1800 + 174 carriers for E-GSM900 Band
705 #define TXPWR_TURNING_POINT_DUALEXT 28
706 // DUAL_US
707 #define FIRST_ARFCN_GSM850_DUAL_US 1 // 1st GSM850 index within the 423 continu list
708 #define FIRST_PCS_INDEX_DUAL_US 125 // 1st PCS index within the 423 continu list
709 #define NBMAX_CARRIER_DUAL_US 124+299 // 299 carriers for PCS1900 + 124 carriers for GSM850\ Band
710 #define NBMEAS_DUAL_US 4 // 4 measurements per frames.
711 #define TXPWR_TURNING_POINT_DUAL_US 28 // TBD
712
713
714 #define NBMAX_CARRIER NBMAX_CARRIER_DUALEXT //used in arrays for power measurement
715 //non optimized!!! (dynamic memory allocation to optimize)
716 #define BAND1 1
717 #define BAND2 2
718
719 #define NO_TXPWR 255 // sentinal value used with UWORD8 type.
720
721
722 //--------------------------------------------------------
723 // Receive level values.
724 //--------------------------------------------------------
725 #define RXLEV63 63 // max value for RXLEV.
726 #define IL_MIN 240 // minimum input level is -120 dbm.
727
728 //--------------------------------------------------------
729 // Max number of cell to report in MPHC_RXLEV_IND.
730 // Nb cells to check to see if cell of MPHC_NETWORK_SYNC_REQ has been detected
731 //--------------------------------------------------------
732 #define MAX_MEAS_RXLEV_IND_TRACE 10
733 #define NB_FQ_TO_CHK 4
734
735 /*--------------------------------------------------------*/
736 /* Max value for GSM Paging Parameters. */
737 /*--------------------------------------------------------*/
738 #define MAX_AG_BLKS_RES_NCOMB 7
739 #define MAX_AG_BLKS_RES_COMB 2
740 #define MAX_PG_BLOC_INDEX_NCOMB 8
741 #define MAX_PG_BLOC_INDEX_COMB 2
742 #define MAX_BS_PA_MFRMS 9
743
744 /*--------------------------------------------------------*/
745 /* Position of different blocs in a MF51. */
746 /*--------------------------------------------------------*/
747 #define NBCCH_POSITION 2 // Normal BCCH position in a MF51.
748 #define EBCCH_POSITION 6 // Extended BCCH position in a MF51.
749 #define CCCH_0 6
750 #define CCCH_1 12
751 #define CCCH_2 16
752 #define CCCH_3 22
753 #define CCCH_4 26
754 #define CCCH_5 32
755 #define CCCH_6 36
756 #define CCCH_7 42
757 #define CCCH_8 46
758 #define FB_0 0
759 #define FB_1 10
760 #define FB_2 20
761 #define FB_3 30
762 #define FB_4 40
763 #define SB_0 1
764 #define SB_1 11
765 #define SB_2 21
766 #define SB_3 31
767 #define SB_4 41
768
769 /*--------------------------------------------------------*/
770 /* System information position in the "si_bit_map". */
771 /*--------------------------------------------------------*/
772 #define SI_1 0x0001
773 #define SI_2 0x0002
774 #define SI_2BIS 0x0100
775 #define SI_2TER 0x0200
776 #define SI_3 0x0004
777 #define SI_4 0x0008
778 #define SI_7 0x0040
779 #define SI_8 0x0080
780 #define ALL_SI SI_1 | SI_2 | SI_2BIS | SI_2TER | SI_3 | SI_4 | SI_7 | SI_8
781
782 /*--------------------------------------------------------*/
783 /* CBCH position in the "smscb_bit_map". */
784 /*--------------------------------------------------------*/
785 #define CBCH_TB1 0x0001
786 #define CBCH_TB2 0x0002
787 #define CBCH_TB3 0x0004
788 #define CBCH_TB5 0x0008
789 #define CBCH_TB6 0x0010
790 #define CBCH_TB7 0x0020
791
792 #define CBCH_CONTINUOUS_READING 0
793 #define CBCH_SCHEDULED 1
794 #define CBCH_INACTIVE 2
795
796 /*--------------------------------------------------------*/
797 /* Channel type definitions for DEDICATED mode. */
798 /*--------------------------------------------------------*/
799
800 //TABLE/ CHAN TYPE
801 #define INVALID_CHANNEL 0
802 #define TCH_F 1
803 #define TCH_H 2
804 #define SDCCH_4 3
805 #define SDCCH_8 4
806 //END_TABLE/
807
808 /*--------------------------------------------------------*/
809 /* Channel mode definitions for DEDICATED. */
810 /*--------------------------------------------------------*/
811 #define SIG_ONLY_MODE 0 // signalling only
812 #define TCH_FS_MODE 1 // speech full rate
813 #define TCH_HS_MODE 2 // speech half rate
814 #define TCH_96_MODE 3 // data 9,6 kb/s
815 #define TCH_48F_MODE 4 // data 4,8 kb/s full rate
816 #define TCH_48H_MODE 5 // data 4,8 kb/s half rate
817 #define TCH_24F_MODE 6 // data 2,4 kb/s full rate
818 #define TCH_24H_MODE 7 // data 2,4 kb/s half rate
819 #define TCH_EFR_MODE 8 // enhanced full rate
820 #define TCH_144_MODE 9 // data 14,4 kb/s half rate
821 #if (AMR == 1)
822 #define TCH_AHS_MODE 10 // adaptative speech half rate
823 #define TCH_AFS_MODE 11 // adaptative speech full rate
824 #endif
825
826
827 /*--------------------------------------------------------*/
828 /* Layer 1 functional modes for "mode" setting pupose. */
829 /*--------------------------------------------------------*/
830 #define CS_MODE0 0 // functional mode at reset.
831 #define CS_MODE 1 // functional mode in CELL SELECTION.
832 #define I_MODE 2 // functional mode in IDLE.
833 #define CON_EST_MODE1 3 // functional mode in ACCESS (before 1st RA, for TOA convergency).
834 #define CON_EST_MODE2 4 // functional mode in ACCESS (after 1st RA).
835 #define DEDIC_MODE 5 // functional mode in DEDICATED.
836 #define DEDIC_MODE_HALF_DATA 6 // used only for TOA histogram length purpose.
837 #if L1_GPRS
838 #define PACKET_TRANSFER_MODE 7
839 #endif
840
841 /*--------------------------------------------------------*/
842 /* Error causes for MPHC_NO_BCCH message. */
843 /*--------------------------------------------------------*/
844 #define NO_FB_SB 0 // FB or SB not found.
845 #define NCC_NOT_PERMITTED 1 // Synchro OK! but PLMN not permitted.
846
847 /*--------------------------------------------------------*/
848 /* MFTAB constants and flags. */
849 /*--------------------------------------------------------*/
850 #define L1_MAX_FCT 5 /* Max number of fctions in a frame */
851 #define MFTAB_SIZE 20
852
853 /********************************/
854 /* Software register/flags */
855 /* definitions. */
856 /********************************/
857 #define NO_CTRL (TRUE_L << 0)
858 #define CTRL_MS (TRUE_L << 1)
859 #define CTRL_TX (TRUE_L << 2)
860 #define CTRL_RX (TRUE_L << 3)
861 #define CTRL_ADC (TRUE_L << 4)
862 #define CTRL_SYNC (TRUE_L << 5)
863 #define CTRL_ABORT (TRUE_L << 6)
864 #define CTRL_TEST (TRUE_L << 7)
865 #define CTRL_SYCB (TRUE_L << 8)
866 #define CTRL_FB_ABORT (TRUE_L << 9)
867 #if L1_GPRS
868 #define CTRL_PRACH (TRUE_L << 10)
869 #define CTRL_SYSINGLE (TRUE_L << 11)
870 #endif
871
872
873 /********************************/
874 /* MISC management */
875 /********************************/
876 #define GSM_CTL 0 // DSP ctrl for a GSM task
877 #define MISC_CTL 1 // DSP ctrl for a MISC task
878 #define GSM_MISC_CTL 2 // DSP ctrl for a GSM and MISC tasks
879
880 /********************************/
881 /* TOA management */
882 /********************************/
883 #define ISH_INVALID 128 // value used to disable the toa offset
884
885 /********************************/
886 /* AGC management */
887 /********************************/
888 #define DPAGC_FIFO_LEN 4
889 #define DPAGC_MAX_FLAG 1
890 #if (AMR == 1)
891 #define DPAGC_AMR_FIFO_LEN 4
892 #endif
893
894 /********************************/
895 /* ADC management */
896 /********************************/
897 #define ADC_DISABLED 0x0000
898 // Traffic part
899 #define ADC_MASK_RESET_TRAFFIC 0xFF00
900 #define ADC_NEXT_TRAFFIC_UL 0x0001
901 #define ADC_EACH_TRAFFIC_UL 0x0002
902 #define ADC_NEXT_TRAFFIC_DL 0x0004
903 #define ADC_EACH_TRAFFIC_DL 0x0008
904 #define ADC_EACH_RACH 0x0010
905
906
907 // Idle part
908 #define ADC_MASK_RESET_IDLE 0x00FF
909 #define ADC_NEXT_NORM_PAGING 0x0100
910 #define ADC_EACH_NORM_PAGING 0x0200
911 #define ADC_NEXT_MEAS_SESSION 0x0400
912 #define ADC_EACH_MEAS_SESSION 0x0800
913 #define ADC_NEXT_NORM_PAGING_REORG 0x1000
914 #define ADC_EACH_NORM_PAGING_REORG 0x2000
915
916
917 // CS_MODE0 part
918 #define ADC_NEXT_CS_MODE0 0x4000
919 #define ADC_EACH_CS_MODE0 0x8000
920
921
922 /********************************/
923 /* Neighbor BCCH priorities */
924 /********************************/
925
926 #define TOP_PRIORITY 0
927 #define HIGH_PRIORITY 1
928 #define NORMAL_PRIORITY 2
929
930 /********************************/
931 /* Driver constants definitions */
932 /********************************/
933
934 // Used to identify the 1st and last burst for offset management in Drivers.
935 #define BURST_1 0
936 #define BURST_2 1
937 #define BURST_3 2
938 #define BURST_4 3
939
940
941 // Identifier for all DSP tasks.
942 // ...RX & TX tasks identifiers.
943 #define NO_DSP_TASK 0 // No task.
944 #define NP_DSP_TASK 21 // Normal Paging reading task.
945 #define EP_DSP_TASK 22 // Extended Paging reading task.
946 #define NBS_DSP_TASK 19 // Normal BCCH serving reading task.
947 #define EBS_DSP_TASK 20 // Extended BCCH serving reading task.
948 #define NBN_DSP_TASK 17 // Normal BCCH neighbour reading task.
949 #define EBN_DSP_TASK 18 // Extended BCCH neighbour reading task.
950 #define ALLC_DSP_TASK 24 // CCCH reading task while performing FULL BCCH/CCCH reading task.
951 #define CB_DSP_TASK 25 // CBCH reading task.
952 #define DDL_DSP_TASK 26 // SDCCH/D (data) reading task.
953 #define ADL_DSP_TASK 27 // SDCCH/A (SACCH) reading task.
954 #define DUL_DSP_TASK 12 // SDCCH/D (data) transmit task.
955 #define AUL_DSP_TASK 11 // SDCCH/A (SACCH) transmit task.
956 #define RACH_DSP_TASK 10 // RACH transmit task.
957 #define TCHT_DSP_TASK 13 // TCH Traffic data DSP task id (RX or TX)
958 #define TCHA_DSP_TASK 14 // TCH SACCH data DSP task id (RX or TX)
959 #define TCHD_DSP_TASK 28 // TCH Traffic data DSP task id (RX or TX)
960
961 #define TCH_DTX_UL 15 // Replace UL task in DSP->MCU com. to say "burst not transmitted".
962
963 #if (L1_GPRS)
964 // Identifier for DSP tasks Packet dedicated.
965 // ...RX & TX tasks identifiers.
966 //------------------------------------------------------------------------
967 // WARNING ... Need to aligned following macro with MCU/DSP GPRS Interface
968 //------------------------------------------------------------------------
969 #define PNP_DSP_TASK 30
970 #define PEP_DSP_TASK 31
971 #define PALLC_DSP_TASK 32
972 #define PBS_DSP_TASK 33
973
974 #define PTCCH_DSP_TASK 33
975
976 #endif
977
978 // Identifier for measurement, FB / SB search tasks.
979 // Values 1,2,3 reserved for "number of measurements".
980 #define FB_DSP_TASK 5 // Freq. Burst reading task in Idle mode.
981 #define SB_DSP_TASK 6 // Sync. Burst reading task in Idle mode.
982 #define TCH_FB_DSP_TASK 8 // Freq. Burst reading task in Dedicated mode.
983 #define TCH_SB_DSP_TASK 9 // Sync. Burst reading task in Dedicated mode.
984 #define IDLE1 1
985
986 // Debug tasks
987 #define CHECKSUM_DSP_TASK 33
988 #define TST_NDB 35 // Checksum DSP->MCU
989 #define TST_DB 36 // DB communication check
990 #define INIT_VEGA 37
991 #define DSP_LOOP_C 38
992
993 // Identifier for measurement, FB / SB search tasks.
994 // Values 1,2,3 reserved for "number of measurements".
995 #define TCH_LOOP_A 31
996 #define TCH_LOOP_B 32
997
998 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
999 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x08DB - 0x800)))
1000 #else
1001 #define SC_CHKSUM_VER (DB_W_PAGE_0 + (2 * (0x09A0 - 0x800)))
1002 #endif
1003
1004 // bits in d_gsm_bgd_mgt - background task management
1005 #define B_DSPBGD_RECO 1 // start of reco in dsp background
1006 #define B_DSPBGD_UPD 2 // start of alignement update in dsp background
1007 #define B_DSPBGD_STOP_RECO 256 // stop of reco in dsp background
1008 #define B_DSPBGD_STOP_UPD 512 // stop of alignement update in dsp background
1009
1010 // bit in d_pll_config
1011 #define B_32KHZ_CALIB (TRUE_L << 14) // force DSP in Idle1 during 32 khz calibration
1012 // ****************************************************************
1013 // NDB AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
1014 // ****************************************************************
1015 // bits in d_tch_mode
1016 #define B_EOTD (TRUE_L << 0) // EOTD mode
1017 #define B_PLAY_UL (TRUE_L << 3) // Play UL
1018 #define B_DCO_ON (TRUE_L << 4) // DCO ON/OFF
1019 #define B_AUDIO_ASYNC (TRUE_L << 1) // WCP reserved
1020
1021 // ****************************************************************
1022 // PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
1023 // ****************************************************************
1024 #define C_POND_RED 1L
1025 // below values are defined in the file l1_time.h
1026 //#define D_NSUBB_IDLE 296L
1027 //#define D_NSUBB_DEDIC 30L
1028 #define D_FB_THR_DET_IACQ 0x3333L
1029 #define D_FB_THR_DET_TRACK 0x28f6L
1030 #define D_DC_OFF_THRES 0x7fffL
1031 #define D_DUMMY_THRES 17408L
1032 #define D_DEM_POND_GEWL 26624L
1033 #define D_DEM_POND_RED 20152L
1034 #define D_HOLE 0L
1035 #define D_TRANSFER_RATE 0x6666L
1036
1037 // Full Rate vocoder definitions.
1038 #define D_MACCTHRESH1 7872L
1039 #define D_MLDT -4L
1040 #define D_MACCTHRESH 7872L
1041 #define D_GU 5772L
1042 #define D_GO 7872L
1043 #define D_ATTMAX 53L
1044 #define D_SM -892L
1045 #define D_B 208L
1046 #define D_SD_MIN_THR_TCHFS 15L //(24L *C_POND_RED)
1047 #define D_MA_MIN_THR_TCHFS 738L //(1200L *C_POND_RED)
1048 #define D_MD_MAX_THR_TCHFS 1700L //(2000L *C_POND_RED)
1049 #define D_MD1_MAX_THR_TCHFS 99L //(160L *C_POND_RED)
1050
1051 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1052 // Frequency burst definitions
1053 #define D_FB_MARGIN_BEG 24
1054 #define D_FB_MARGIN_END 22
1055
1056 // V42bis definitions
1057 #define D_V42B_SWITCH_HYST 16L
1058 #define D_V42B_SWITCH_MIN 64L
1059 #define D_V42B_SWITCH_MAX 250L
1060 #define D_V42B_RESET_DELAY 10L
1061
1062 // Latencies definitions
1063 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1064 // C.f. BUG1404
1065 #define D_LAT_MCU_BRIDGE 0x000FL
1066 #else
1067 #define D_LAT_MCU_BRIDGE 0x0009L
1068 #endif
1069
1070 #define D_LAT_MCU_HOM2SAM 0x000CL
1071
1072 #define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L
1073 #define D_LAT_DSP_AFTER_SAM 0x0004L
1074
1075 // Background Task in GSM mode: Initialization.
1076 #define D_GSM_BGD_MGT 0L
1077
1078 #if (CHIPSET == 4)
1079 #define D_MISC_CONFIG 0L
1080 #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
1081 #define D_MISC_CONFIG 1L
1082 #else
1083 #define D_MISC_CONFIG 0L
1084 #endif
1085
1086 #endif
1087
1088 // Hall Rate vocoder and ched definitions.
1089
1090 #define D_SD_MIN_THR_TCHHS 37L
1091 #define D_MA_MIN_THR_TCHHS 344L
1092 #define D_MD_MAX_THR_TCHHS 2175L
1093 #define D_MD1_MAX_THR_TCHHS 138L
1094 #define D_SD_AV_THR_TCHHS 1845L
1095 #define D_WED_FIL_TC 0x7c00L
1096 #define D_WED_FIL_INI 4650L
1097 #define D_X_MIN 15L
1098 #define D_X_MAX 23L
1099 #define D_Y_MIN 703L
1100 #define D_Y_MAX 2460L
1101 #define D_SLOPE 135L
1102 #define D_WED_DIFF_THRESHOLD 406L
1103 #define D_MABFI_MIN_THR_TCHHS 5320L
1104 #define D_LDT_HR -5
1105 #define D_MACCTRESH_HR 6500
1106 #define D_MACCTRESH1_HR 6500
1107 #define D_GU_HR 2620
1108 #define D_GO_HR 3700
1109 #define D_B_HR 182
1110 #define D_SM_HR -1608
1111 #define D_ATTMAX_HR 53
1112
1113 // Enhanced Full Rate vocoder and ched definitions.
1114
1115 #define C_MLDT_EFR -4
1116 #define C_MACCTHRESH_EFR 8000
1117 #define C_MACCTHRESH1_EFR 8000
1118 #define C_GU_EFR 4522
1119 #define C_GO_EFR 6500
1120 #define C_B_EFR 174
1121 #define C_SM_EFR -878
1122 #define C_ATTMAX_EFR 53
1123 #define D_SD_MIN_THR_TCHEFS 15L //(24L *C_POND_RED)
1124 #define D_MA_MIN_THR_TCHEFS 738L //(1200L *C_POND_RED)
1125 #define D_MD_MAX_THR_TCHEFS 1230L //(2000L *C_POND_RED)
1126 #define D_MD1_MAX_THR_TCHEFS 99L //(160L *C_POND_RED)
1127
1128
1129 // Integrated Data Services definitions.
1130 #define D_MAX_OVSPD_UL 8
1131 // Detect frames containing 90% of 1s as synchro frames
1132 #define D_SYNC_THRES 0x3f50
1133 // IDLE frames are only frames with 100 % of 1s
1134 #define D_IDLE_THRES 0x4000
1135 #define D_M1_THRES 5
1136 #define D_MAX_OVSP_DL 8
1137
1138 // d_ra_act: bit field definition
1139 #define B_F48BLK 5
1140
1141 // Mask for b_itc information (d_ra_conf)
1142 #define CE_MASK 0x04
1143
1144 #define D_FACCH_THR 0
1145 #define D_DSP_TEST 0
1146 #define D_VERSION_NUMBER 0
1147 #define D_TI_VERSION 0
1148
1149
1150 /*------------------------------------------------------------------------------*/
1151 /* */
1152 /* DEFINITIONS FOR DSP <-> MCU COMMUNICATION. */
1153 /* ++++++++++++++++++++++++++++++++++++++++++ */
1154 /* */
1155 /*------------------------------------------------------------------------------*/
1156 // COMMUNICATION Interrupt definition
1157 //------------------------------------
1158 #define ALL_16BIT 0xffffL
1159 #define B_GSM_PAGE (TRUE_L << 0)
1160 #define B_GSM_TASK (TRUE_L << 1)
1161 #define B_MISC_PAGE (TRUE_L << 2)
1162 #define B_MISC_TASK (TRUE_L << 3)
1163
1164 #define B_GSM_PAGE_MASK (ALL_16BIT ^ B_GSM_PAGE)
1165 #define B_GSM_TASK_MASK (ALL_16BIT ^ B_GSM_TASK)
1166 #define B_MISC_PAGE_MASK (ALL_16BIT ^ B_MISC_PAGE)
1167 #define B_MISC_TASK_MASK (ALL_16BIT ^ B_MISC_TASK)
1168
1169 // Common definition
1170 //----------------------------------
1171 // Index to *_DEMOD* arrays.
1172 #define D_TOA 0 // Time Of Arrival.
1173 #define D_PM 1 // Power Measurement.
1174 #define D_ANGLE 2 // Angle (AFC correction)
1175 #define D_SNR 3 // Signal / Noise Ratio.
1176
1177 // Bit name/position definitions.
1178 #define B_FIRE0 5 // Fire result bit 0. (00 -> NO ERROR) (01 -> ERROR CORRECTED)
1179 #define B_FIRE1 6 // Fire result bit 1. (10 -> ERROR) (11 -> unused)
1180 #define B_SCH_CRC 8 // CRC result for SB decoding. (1 for ERROR).
1181 #define B_BLUD 15 // Uplink,Downlink data block Present. (1 for PRESENT).
1182 #define B_AF 14 // Activity bit: 1 if data block is valid.
1183 #define B_BFI 2 // Bad Frame Indicator
1184 #define B_UFI 0 // UNRELIABLE FRAME Indicator
1185 #define B_ECRC 9 // Enhanced full rate CRC bit
1186 #define B_EMPTY_BLOCK 10 // for voice memo purpose, this bit is used to determine
1187
1188 #if (DEBUG_DEDIC_TCH_BLOCK_STAT == 1)
1189 #define FACCH_GOOD 10
1190 #define FACCH_BAD 11
1191 #endif
1192
1193 #if (AMR == 1)
1194 // Place of the RX type in the AMR block header
1195 #define RX_TYPE_SHIFT 3
1196 #define RX_TYPE_MASK 0x0038
1197
1198 // Place of the vocoder type in the AMR block header
1199 #define VOCODER_TYPE_SHIFT 0
1200 #define VOCODER_TYPE_MASK 0x0007
1201
1202 // List of the possible RX types in a_dd block
1203 #define SPEECH_GOOD 0
1204 #define SPEECH_DEGRADED 1
1205 #define ONSET 2
1206 #define SPEECH_BAD 3
1207 #define SID_FIRST 4
1208 #define SID_UPDATE 5
1209 #define SID_BAD 6
1210 #define AMR_NO_DATA 7
1211 #define AMR_INHIBIT 8
1212
1213 // List of possible RX types in RATSCCH block
1214 #define C_RATSCCH_GOOD 5
1215
1216 // List of the possible AMR channel rate
1217 #define AMR_CHANNEL_4_75 0
1218 #define AMR_CHANNEL_5_15 1
1219 #define AMR_CHANNEL_5_9 2
1220 #define AMR_CHANNEL_6_7 3
1221 #define AMR_CHANNEL_7_4 4
1222 #define AMR_CHANNEL_7_95 5
1223 #define AMR_CHANNEL_10_2 6
1224 #define AMR_CHANNEL_12_2 7
1225
1226 // Types of RATSCCH blocks
1227 #define C_RATSCCH_UNKNOWN 0
1228 #define C_RATSCCH_CMI_PHASE_REQ 1
1229 #define C_RATSCCH_AMR_CONFIG_REQ_MAIN 2
1230 #define C_RATSCCH_AMR_CONFIG_REQ_ALT 3
1231 #define C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE 4 // Alternative AMR_CONFIG_REQ with updates coming in the next THRES_REQ block
1232 #define C_RATSCCH_THRES_REQ 5
1233
1234 // These flags define a bitmap that indicates which AMR parameters are being modified by a RATSCCH
1235 #define C_AMR_CHANGE_CMIP 0
1236 #define C_AMR_CHANGE_ACS 1
1237 #define C_AMR_CHANGE_ICM 2
1238 #define C_AMR_CHANGE_THR1 3
1239 #define C_AMR_CHANGE_THR2 4
1240 #define C_AMR_CHANGE_THR3 5
1241 #define C_AMR_CHANGE_HYST1 6
1242 #define C_AMR_CHANGE_HYST2 7
1243 #define C_AMR_CHANGE_HYST3 8
1244
1245 // CMIP default value
1246 #define C_AMR_CMIP_DEFAULT 1 // According to ETSI specification 05.09, cmip is always 1 by default (new channel, handover...)
1247
1248 #endif
1249 // "d_ctrl_tch" bits positions for TCH configuration.
1250 #define B_CHAN_MODE 0
1251 #define B_CHAN_TYPE 4
1252 #define B_RESET_SACCH 6
1253 #define B_VOCODER_ON 7
1254 #define B_SYNC_TCH_UL 8
1255 #if (AMR == 1)
1256 #define B_SYNC_AMR 9
1257 #else
1258 #define B_SYNC_TCH_DL 9
1259 #endif
1260 #define B_STOP_TCH_UL 10
1261 #define B_STOP_TCH_DL 11
1262 #define B_TCH_LOOP 12
1263 #define B_SUBCHANNEL 15
1264
1265 // "d_ctrl_abb" bits positions for conditionnal loading of abb registers.
1266 #define B_RAMP 0
1267 #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
1268 #define B_BULRAMPDEL 3 // Note: this name is changed
1269 #define B_BULRAMPDEL2 2 // Note: this name is changed
1270 #define B_BULRAMPDEL_BIS 9
1271 #define B_BULRAMPDEL2_BIS 10
1272 #endif
1273 #define B_AFC 4
1274
1275 // "d_ctrl_system" bits positions.
1276 #define B_TSQ 0
1277 #define B_BCCH_FREQ_IND 3
1278 #define B_TASK_ABORT 15 // Abort RF tasks for DSP.
1279
1280 // ****************************************************************
1281 // POLESTAR EVABOARD 3 REGISTERS & ADRESSES DEFINITIONS
1282 // ****************************************************************
1283
1284
1285 // DSP ADRESSES
1286 //--------------------
1287
1288 #define DB_SIZE (4*20L) // 4 pages of 20 words...
1289
1290 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
1291 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
1292 #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
1293 #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
1294 #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
1295 #define NDB_ADR 0xFFD001A8L // NDB start address : 268 words
1296 #define PARAM_ADR 0xFFD00862L // PARAM start address : 57 words
1297
1298 #if (DSP_DEBUG_TRACE_ENABLE == 1)
1299 #define DB2_R_PAGE_0 0xFFD00184L
1300 #define DB2_R_PAGE_1 0xFFD00188L
1301 #endif
1302 #else
1303 #define DB_W_PAGE_0 0xFFD00000L // DB page 0 write : 20 words long
1304 #define DB_W_PAGE_1 0xFFD00028L // DB page 1 write : 20 words long
1305 #define DB_R_PAGE_0 0xFFD00050L // DB page 0 read : 20 words long
1306 #define DB_R_PAGE_1 0xFFD00078L // DB page 1 read : 20 words long
1307 #define NDB_ADR 0xFFD000a0L // NDB start address : 268 words
1308 #define PARAM_ADR 0xFFD002b8L // PARAM start address : 57 words
1309 #endif
1310
1311 // ****************************************************************
1312 // ADC reading definitions
1313 // ****************************************************************
1314
1315 #define ADC_READ_PERIOD (40) //30 * 4.615 = 140ms
1316
1317
1318 // ****************************************************************
1319 // AGC: IL table identifier used by function Cust_get_agc_from_IL
1320 // ****************************************************************
1321 #define MAX_ID 1
1322 #define AV_ID 2
1323 #define PWR_ID 3
1324
1325 #if TESTMODE
1326 // ****************************************************************
1327 // Testmode: State of the continous mode
1328 // ****************************************************************
1329 #define TM_NO_CONTINUOUS 1 // continuous mode isn't active
1330 #define TM_START_RX_CONTINUOUS 2 // start the Rx continuous mode
1331 #define TM_START_TX_CONTINUOUS 3 // start the Tx continuous mode
1332 #define TM_CONTINUOUS 4 // Rx or Tx continuous mode
1333 #endif
1334 #if (AMR == 1)
1335 // ****************************************************************
1336 // AMR: Position of each AMR parameters in the AMR API buffer
1337 // ****************************************************************
1338 #define NSCB_INDEX 0
1339 #define NSCB_SHIFT 6
1340 #define ICMUL_INDEX 0
1341 #define ICMUL_SHIFT 4
1342 #define ICMDL_INDEX 0
1343 #define ICMDL_SHIFT 1
1344 #define ICMIUL_INDEX 0
1345 #define ICMIUL_SHIFT 3
1346 #define ICMIDL_INDEX 0
1347 #define ICMIDL_SHIFT 0
1348 #define ACSUL_INDEX 1
1349 #define ACSUL_SHIFT 0
1350 #define ACSDL_INDEX 1
1351 #define ACSDL_SHIFT 8
1352 #define THR1_INDEX 2
1353 #define THR1_SHIFT 0
1354 #define THR2_INDEX 2
1355 #define THR2_SHIFT 6
1356 #define THR3_INDEX 3
1357 #define THR3_SHIFT 8
1358 #define HYST1_INDEX 3
1359 #define HYST1_SHIFT 0
1360 #define HYST2_INDEX 3
1361 #define HYST2_SHIFT 4
1362 #define HYST3_INDEX 2
1363 #define HYST3_SHIFT 12
1364 #define NSYNC_INDEX 3
1365 #define NSYNC_SHIFT 14
1366 #define CMIP_INDEX 3
1367 #define CMIP_SHIFT 15
1368
1369 #define NSCB_MASK 0x0001
1370 #define ICM_MASK 0x0003
1371 #define ICMI_MASK 0x0001
1372 #define ACS_MASK 0x00FF
1373 #define THR_MASK 0x003F
1374 #define HYST_MASK 0x000F
1375 #define CMIP_MASK 0x0001
1376 #endif
1377