FreeCalypso > hg > freecalypso-sw
comparison gsm-fw/bsp/oldint.S @ 143:afceeeb2cba1
Our nuc-fw is destined to become gsm-fw, so I went ahead and did the big hg mv
| author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
|---|---|
| date | Tue, 12 Nov 2013 05:35:48 +0000 |
| parents | nuc-fw/bsp/oldint.S@8b0793c67f9f |
| children |
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| 142:15d5977390c2 | 143:afceeeb2cba1 |
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| 1 /* | |
| 2 * This module contains that part of TI's int.s (INT_Initialize) code | |
| 3 * which does some entry-point initialization of a few Calypso registers. | |
| 4 * The important part for us is getting rid of whatever PLL setup | |
| 5 * may have been done by the BootROM-based process that got us loaded | |
| 6 * and running - we need to do that before we can do our own setup. | |
| 7 */ | |
| 8 | |
| 9 .code 32 | |
| 10 .text | |
| 11 | |
| 12 #define CNTL_ARM_CLK_REG 0xFFFFFD00 // CNTL_ARM_CLK register address | |
| 13 #define DPLL_CNTRL_REG 0xFFFF9800 // DPLL control register address | |
| 14 #define EXTRA_CONTROL_REG 0xFFFFFB10 // Extra Control register CONF addr | |
| 15 #define MPU_CTL_REG 0xFFFFFF08 // MPU_CTL register address | |
| 16 | |
| 17 #define CNTL_ARM_CLK_RST 0x1081 // Init of CNTL_ARM_CLK register | |
| 18 | |
| 19 // Use DPLL, Divide by 1 | |
| 20 #define DPLL_CONTROL_RST 0x2002 // Configure DPLL in default state | |
| 21 #define DISABLE_DU_MASK 0x0800 // Mask to Disable the DU module | |
| 22 #define ENABLE_DU_MASK 0xF7FF // Mask to Enable the DU module | |
| 23 #define MPU_CTL_RST 0x0000 // Reset value of MPU_CTL register | |
| 24 // - All protections disabled | |
| 25 | |
| 26 .globl freecalypso_disable_bootrom_pll | |
| 27 freecalypso_disable_bootrom_pll: | |
| 28 @ | |
| 29 @ Configure DPLL register with reset value | |
| 30 @ | |
| 31 ldr r1,=DPLL_CNTRL_REG @ Load address of DPLL register in R1 | |
| 32 ldrh r2,=DPLL_CONTROL_RST @ Load DPLL reset value in R2 | |
| 33 strh r2,[r1] @ Store DPLL reset value in DPLL register | |
| 34 | |
| 35 @ | |
| 36 @ Wait that DPLL goes in BYPASS mode | |
| 37 @ | |
| 38 Wait_DPLL_Bypass: | |
| 39 ldr r2,[r1] @ Load DPLL register | |
| 40 and r2,r2,#1 @ Perform a mask on bit 0 | |
| 41 cmp r2,#1 @ Compare DPLL lock bit | |
| 42 beq Wait_DPLL_Bypass @ Wait Bypass mode (i.e. bit[0]='0') | |
| 43 | |
| 44 @ | |
| 45 @ Configure CNTL_ARM_CLK register with reset value: DPLL is used to | |
| 46 @ generate ARM clock with division factor of 1. | |
| 47 @ | |
| 48 ldr r1,=CNTL_ARM_CLK_REG @ Load address of CNTL_ARM_CLK register in R1 | |
| 49 ldrh r2,=CNTL_ARM_CLK_RST @ Load CNTL_ARM_CLK reset value in R2 | |
| 50 strh r2,[r1] @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register | |
| 51 | |
| 52 @ | |
| 53 @ Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0' | |
| 54 @ | |
| 55 ldr r1,=EXTRA_CONTROL_REG @ Load address of Extra Control register CONF | |
| 56 @ ldrh r2,=DISABLE_DU_MASK @ Load mask to write in Extra Control register CONF | |
| 57 ldrh r2,=ENABLE_DU_MASK @ Load mask to write in Extra Control register CONF | |
| 58 ldrh r0,[r1] @ Load Extra Control register CONF in r0 | |
| 59 @ orr r0,r0,r2 @ Disable DU module | |
| 60 and r0,r0,r2 @ Enable DU module | |
| 61 strh r0,[r1] @ Store configuration in Extra Control register CONF | |
| 62 | |
| 63 @ | |
| 64 @ Disable all MPU protections | |
| 65 @ | |
| 66 ldr r1,=MPU_CTL_REG @ Load address of MPU_CTL register | |
| 67 ldrh r2,=MPU_CTL_RST @ Load reset value of MPU_CTL register | |
| 68 strh r2,[r1] @ Store reset value of MPU_CTL register | |
| 69 | |
| 70 bx lr |