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comparison gsm-fw/L1/audio_cfile/l1audio_init.c @ 606:c5286d24539e

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gsm-fw/L1/audio_cfile: initial import from LoCosto source
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 29 Aug 2014 03:25:51 +0000
parents
children 3121e35f422c
comparison
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605:527956ce73c7 606:c5286d24539e
1 /************* Revision Controle System Header *************
2 * GSM Layer 1 software
3 * L1AUDIO_INIT.C
4 *
5 * Filename l1audio_init.c
6 * Copyright 2003 (C) Texas Instruments
7 *
8 ************* Revision Controle System Header *************/
9
10 /************************************/
11 /* Include files... */
12 /************************************/
13
14 #include "l1_macro.h"
15 #include "l1_confg.h"
16
17
18 #include "l1_types.h"
19 #include "sys_types.h"
20
21 #if (CODE_VERSION == SIMULATION) && (AUDIO_SIMULATION)
22
23
24 #include <stdlib.h>
25 #include <string.h>
26
27 #include "iq.h" // Debug / Init hardware ("eva3.lib")
28 #include "l1_ver.h"
29 #include "l1_const.h"
30 #include "l1_signa.h"
31
32 #if TESTMODE
33 #include "l1tm_defty.h"
34 #endif
35
36 #include "l1audio_const.h"
37 #include "l1audio_cust.h"
38 #include "l1audio_defty.h"
39 #include "l1audio_msgty.h"
40 #include "l1audio_varex.h"
41
42 #if (L1_GTT == 1)
43 #include "l1gtt_const.h"
44 #include "l1gtt_defty.h"
45 #endif
46 //added here from e-sample for AAC
47 #if (L1_DYN_DSP_DWNLD == 1)
48 #include "l1_dyn_dwl_const.h"
49 #include "l1_dyn_dwl_defty.h"
50 #endif
51 #if (L1_MP3 == 1)
52 #include "l1mp3_defty.h"
53 #endif
54
55 #if (L1_MIDI == 1)
56 #include "l1midi_defty.h"
57 #endif
58 //added here from e-sample for AAC
59 #if (L1_AAC == 1)
60 #include "l1aac_defty.h"
61 #endif
62 #include "l1_defty.h"
63 #include "cust_os.h"
64 #include "l1_msgty.h"
65 #include "l1_varex.h"
66 #include "l1_mftab.h"
67 #include "l1_tabs.h"
68 #include "l1_ctl.h"
69
70 #include "l1_time.h"
71 #include "l1_scen.h"
72 #else // NOT SIMULATION
73
74 // Layer1 and debug include files.
75 #include <ctype.h>
76 #include <math.h>
77 #include "l1_ver.h"
78 #include "l1_const.h"
79 #include "l1_signa.h"
80
81 #if TESTMODE
82 #include "l1tm_defty.h"
83 #endif
84
85 #include "l1audio_const.h"
86 #include "l1audio_cust.h"
87 #include "l1audio_defty.h"
88 #include "l1audio_msgty.h"
89 #include "l1audio_varex.h"
90
91 #if (L1_GTT == 1)
92 #include "l1gtt_const.h"
93 #include "l1gtt_defty.h"
94 #endif
95 //added here from e-sample for AAC
96 #if (L1_DYN_DSP_DWNLD == 1)
97 #include "l1_dyn_dwl_const.h"
98 #include "l1_dyn_dwl_defty.h"
99 #endif
100 #if (L1_MP3 == 1)
101 #include "l1mp3_defty.h"
102 #endif
103
104 #if (L1_MIDI == 1)
105 #include "l1midi_defty.h"
106 #endif
107 //added here from e-sample for AAC
108 #if (L1_AAC == 1)
109 #include "l1aac_defty.h"
110 #endif
111
112 #include "l1_defty.h"
113 #include "cust_os.h"
114 #include "l1_msgty.h"
115 #include "tpudrv.h" // TPU drivers. ("eva3.lib")
116 #include "l1_varex.h"
117 #include "l1_proto.h"
118 #include "l1_mftab.h"
119 #include "l1_tabs.h"
120 #include "mem.h"
121 #include "armio.h"
122 #include "timer.h"
123 #include "timer1.h"
124 #include "dma.h"
125 #include "inth.h"
126 #include "ulpd.h"
127 #include "rhea_arm.h"
128 #include "clkm.h" // Clockm ("eva3.lib")
129 #include "l1_ctl.h"
130 #include "l1_time.h"
131
132 #if L2_L3_SIMUL
133 #include "l1_scen.h"
134 #endif
135 #endif // NOT_SIMULATION
136
137 #if (L1_DRC == 1)
138 extern T_DRC_MCU_DSP *drc_ndb;
139 #if (CODE_VERSION == SIMULATION)
140 extern T_DRC_MCU_DSP drc_ndb_sim;
141 #endif
142 #endif
143 #if(L1_BT_AUDIO ==1)
144 extern T_L1_BT_AUDIO bt_audio;
145 #endif
146 /**************************************/
147 /* Prototypes for L1 initialization */
148 /**************************************/
149 void l1audio_dsp_init (void);
150 void l1audio_initialize_var (void);
151
152 /**************************************/
153 /* External prototypes */
154 /**************************************/
155
156 /*-------------------------------------------------------*/
157 /* l1audio_dsp_init() */
158 /*-------------------------------------------------------*/
159 /* */
160 /* Parameters : */
161 /* */
162 /* Return : */
163 /* */
164 /* Description : Initialize the part of the API */
165 /* dedicated to the audio task. */
166 /* */
167 /*-------------------------------------------------------*/
168 void l1audio_dsp_init(void)
169 {
170 UWORD8 i, j;
171
172 #if (KEYBEEP)
173 l1s_dsp_com.dsp_ndb_ptr->d_k_x1_kt0 = 0; // keybeep variable
174 l1s_dsp_com.dsp_ndb_ptr->d_k_x1_kt1 = 0; // keybeep variable
175 l1s_dsp_com.dsp_ndb_ptr->d_dur_kb = 0; // keybeep variable
176 #endif
177
178 #if ((TONE) || (VOICE_MEMO))
179 l1s_dsp_com.dsp_ndb_ptr->d_k_x1_t0 = 0; // tone variable
180 l1s_dsp_com.dsp_ndb_ptr->d_k_x1_t1 = 0; // tone variable
181 l1s_dsp_com.dsp_ndb_ptr->d_k_x1_t2 = 0; // tone variable
182 l1s_dsp_com.dsp_ndb_ptr->d_pe_rep = 0; // tone variable
183 l1s_dsp_com.dsp_ndb_ptr->d_pe_off = 0; // tone variable
184 l1s_dsp_com.dsp_ndb_ptr->d_se_off = 0; // tone variable
185 l1s_dsp_com.dsp_ndb_ptr->d_bu_off = 0; // tone variable
186 l1s_dsp_com.dsp_ndb_ptr->d_t0_on = 0; // tone variable
187 l1s_dsp_com.dsp_ndb_ptr->d_t0_off = 0; // tone variable
188 l1s_dsp_com.dsp_ndb_ptr->d_t1_on = 0; // tone variable
189 l1s_dsp_com.dsp_ndb_ptr->d_t1_off = 0; // tone variable
190 l1s_dsp_com.dsp_ndb_ptr->d_t2_on = 0; // tone variable
191 l1s_dsp_com.dsp_ndb_ptr->d_t2_off = 0; // tone variable
192
193 l1s_dsp_com.dsp_ndb_ptr->d_shiftul = 0x100;
194 l1s_dsp_com.dsp_ndb_ptr->d_shiftdl = 0x100;
195 #endif // (TONE) || (VOICE_MEMO)
196 #if (L1_PCM_EXTRACTION)
197 l1s_dsp_com.dsp_ndb_ptr->d_pcm_api_upload = 0;
198 l1s_dsp_com.dsp_ndb_ptr->d_pcm_api_download = 0;
199 l1s_dsp_com.dsp_ndb_ptr->d_pcm_api_error = 0;
200 #endif
201
202 // Correction of PR G23M/L1_MCU-SPR-15494
203 #if ((CHIPSET == 12) || (CHIPSET == 15))
204 #if (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
205 l1s_dsp_com.dsp_ndb_ptr->d_cport_init = 0;
206 l1s_dsp_com.dsp_ndb_ptr->d_cport_ctrl = 0;
207 l1s_dsp_com.dsp_ndb_ptr->a_cport_cfr[0] = 0;
208 l1s_dsp_com.dsp_ndb_ptr->a_cport_cfr[1] = 0;
209 l1s_dsp_com.dsp_ndb_ptr->d_cport_tcl_tadt = 0;
210 l1s_dsp_com.dsp_ndb_ptr->d_cport_tdat = 0;
211 l1s_dsp_com.dsp_ndb_ptr->d_cport_tvs = 0;
212 #endif
213 #endif
214
215 #if (L1_VOICE_MEMO_AMR)
216 l1s_dsp_com.dsp_ndb_ptr->d_shiftul = 0x100;
217 #endif // L1_VOICE_MEMO_AMR
218
219 #if (MELODY_E1)
220 l1s_dsp_com.dsp_ndb_ptr->d_melo_osc_used = 0;
221 l1s_dsp_com.dsp_ndb_ptr->d_melo_osc_active = 0;
222
223 l1s_dsp_com.dsp_ndb_ptr->a_melo_note0[0] = SC_END_OSCILLATOR_MASK;
224 l1s_dsp_com.dsp_ndb_ptr->a_melo_note1[0] = SC_END_OSCILLATOR_MASK;
225 l1s_dsp_com.dsp_ndb_ptr->a_melo_note2[0] = SC_END_OSCILLATOR_MASK;
226 l1s_dsp_com.dsp_ndb_ptr->a_melo_note3[0] = SC_END_OSCILLATOR_MASK;
227 l1s_dsp_com.dsp_ndb_ptr->a_melo_note4[0] = SC_END_OSCILLATOR_MASK;
228 l1s_dsp_com.dsp_ndb_ptr->a_melo_note5[0] = SC_END_OSCILLATOR_MASK;
229 l1s_dsp_com.dsp_ndb_ptr->a_melo_note6[0] = SC_END_OSCILLATOR_MASK;
230 l1s_dsp_com.dsp_ndb_ptr->a_melo_note7[0] = SC_END_OSCILLATOR_MASK;
231 #endif // MELODY_E1
232
233 // Initialize the FIR as an all band pass
234 // IMPORTANT NOTE: FIR/DL parameters are also initialized for DSP 36 when L1_IIR == 1 because
235 // in FIR loop mode, the old FIR API is still used
236 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)// The FIR coefficents are in param memory
237 l1s_dsp_com.dsp_param_ptr->a_fir31_downlink[0] = 0x4000;
238 l1s_dsp_com.dsp_param_ptr->a_fir31_uplink[0] = 0x4000;
239 #else
240 l1s_dsp_com.dsp_ndb_ptr->a_fir31_downlink[0] = 0x4000;
241 l1s_dsp_com.dsp_ndb_ptr->a_fir31_uplink[0] = 0x4000;
242 #endif
243
244 for (i=1; i<MAX_FIR_COEF; i++)
245 {
246 #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)// The FIR coefficents are in param memory
247 l1s_dsp_com.dsp_param_ptr->a_fir31_downlink[i] = 0;
248 l1s_dsp_com.dsp_param_ptr->a_fir31_uplink[i] = 0;
249 #else
250 l1s_dsp_com.dsp_ndb_ptr->a_fir31_downlink[i] = 0;
251 l1s_dsp_com.dsp_ndb_ptr->a_fir31_uplink[i] = 0;
252 #endif
253 }
254 #if (DSP == 17) || (DSP == 32)
255 // start the FIR task
256 l1s_dsp_com.dsp_ndb_ptr->d_audio_init |= B_FIR_START;
257 #endif
258
259 #if (L1_IIR == 1)
260 // IIR enabled by default
261 // Set the default configuration (all band pass - FIR only mode)
262 l1s_dsp_com.dsp_ndb_ptr->d_iir_nb_iir_blocks = 0;
263 l1s_dsp_com.dsp_ndb_ptr->d_iir_nb_fir_coefs = 0x1f;
264
265 l1s_dsp_com.dsp_ndb_ptr->a_iir_fir_coefs[0] = 0x4000;
266 for (i=1; i < (l1s_dsp_com.dsp_ndb_ptr->d_iir_nb_fir_coefs - 1); i++)
267 l1s_dsp_com.dsp_ndb_ptr->a_iir_fir_coefs[i] = 0;
268
269 l1s_dsp_com.dsp_ndb_ptr->d_iir_input_scaling = 0;
270 l1s_dsp_com.dsp_ndb_ptr->d_iir_fir_scaling = 0;
271 l1s_dsp_com.dsp_ndb_ptr->d_iir_input_gain_scaling = 0;
272 l1s_dsp_com.dsp_ndb_ptr->d_iir_output_gain_scaling = 0;
273 l1s_dsp_com.dsp_ndb_ptr->d_iir_output_gain = 0xffff;
274 l1s_dsp_com.dsp_ndb_ptr->d_iir_feedback = 0;
275 #endif
276
277 #if (AUDIO_MODE)
278 // Reset the FIR loopback and the audio mode
279 l1s_dsp_com.dsp_ndb_ptr->d_audio_init &= ~(B_FIR_LOOP | B_GSM_ONLY | B_BT_HEADSET | B_BT_CORDLESS);
280 // Set the GSM mode
281 l1s_dsp_com.dsp_ndb_ptr->d_audio_init |= B_GSM_ONLY;
282 #else
283 // Reset the loopback
284 l1s_dsp_com.dsp_ndb_ptr->d_audio_init &= ~(B_FIR_LOOP);
285 #endif
286
287 #if (W_A_DSP_SR_BGD)
288 // Initialize the DSP speech reco background task
289
290 // DSP background enabled for SR.
291 l1s_dsp_com.dsp_param_ptr->d_gsm_bgd_mgt = (B_DSPBGD_RECO | B_DSPBGD_UPD);
292 l1s_dsp_com.dsp_ndb_ptr->d_max_background = 7;
293
294 // TEMPORARY: Init DSP background interface for RECO.
295 if (l1s_dsp_com.dsp_param_ptr->d_gsm_bgd_mgt & B_DSPBGD_RECO)
296 {
297 l1s_dsp_com.dsp_ndb_ptr->d_background_enable &= ~(1 << C_BGD_RECOGN);
298 l1s_dsp_com.dsp_ndb_ptr->d_background_abort &= ~(1 << C_BGD_RECOGN);
299 l1s_dsp_com.dsp_ndb_ptr->a_background_tasks[C_BGD_RECOGN] = (C_BGD_RECOGN<<11) | 1;
300 l1s_dsp_com.dsp_ndb_ptr->a_back_task_io[C_BGD_RECOGN] = (API)(0x0000); // Not used by Recognition task.
301 }
302 if (l1s_dsp_com.dsp_param_ptr->d_gsm_bgd_mgt & B_DSPBGD_UPD)
303 {
304 l1s_dsp_com.dsp_ndb_ptr->d_background_enable &= ~(1 << C_BGD_ALIGN);
305 l1s_dsp_com.dsp_ndb_ptr->d_background_abort &= ~(1 << C_BGD_ALIGN);
306 l1s_dsp_com.dsp_ndb_ptr->a_background_tasks[C_BGD_ALIGN] = (C_BGD_ALIGN<<11) | 1;
307 l1s_dsp_com.dsp_ndb_ptr->a_back_task_io[C_BGD_ALIGN] = (API)(0x0000); // Not used by Alignement task.
308 }
309 #elif (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39)
310 // DSP background task through pending task queue
311 l1s_dsp_com.dsp_param_ptr->d_gsm_bgd_mgt = 0;
312 #endif
313
314 #if (MELODY_E2)
315 // Initalize the Audio compressor used for E2
316 l1s_dsp_com.dsp_ndb_ptr->d_audio_compressor_ctrl = 0x0401;
317
318 // Initialize the melody E2 variables
319 l1s_dsp_com.dsp_ndb_ptr->d_melody_e2_osc_stop = 0x0000;
320 l1s_dsp_com.dsp_ndb_ptr->d_melody_e2_osc_active = 0x0000;
321 l1s_dsp_com.dsp_ndb_ptr->d_melody_e2_semaphore = 0x0000;
322 for(i=0; i<SC_MELODY_E2_NUMBER_OF_OSCILLATOR; i++)
323 {
324 l1s_dsp_com.dsp_ndb_ptr->a_melody_e2_osc[i][0] = 0x0000;
325 }
326 l1s_dsp_com.dsp_ndb_ptr->d_melody_e2_globaltimefactor = 0x0000;
327
328 for (i=0; i<(SC_AUDIO_MELODY_E2_MAX_NUMBER_OF_INSTRUMENT); i++)
329 {
330 l1s_dsp_com.dsp_ndb_ptr->a_melody_e2_instrument_ptr[i] = 0x0000;
331 }
332
333 // Reset the flag to know if the DSP melody E2 task runs
334 l1s.melody_e2.dsp_task = FALSE;
335 #endif // MELODY_E2
336
337 #if ((DSP==33) || (DSP == 34) || (DSP==35) || (DSP==36) || (DSP == 37) || (DSP == 38) || (DSP == 39))
338 // Linked to E2 melody
339 // In case of WCP, there is a WCP variable at this address
340 l1s_dsp_com.dsp_ndb_ptr->d_melody_selection = NO_MELODY_SELECTED;
341 #endif
342
343 //-----------------------------------
344 // AUDIO control words initialization
345 //-----------------------------------
346 l1s_dsp_com.dsp_ndb_ptr->d_toneskb_init = 0; // MCU/DSP audio task com. register
347 l1s_dsp_com.dsp_ndb_ptr->d_toneskb_status = 0; // MCU/DSP audio task com. register
348
349
350 #if ((CHIPSET == 4) || (CHIPSET == 12) || (CHIPSET == 15) || ((CHIPSET==10) && (OP_WCP==1))) && ((DSP == 36) || (DSP == 37) || (DSP == 38) || (DSP == 39))
351 l1s_dsp_com.dsp_ndb_ptr->d_es_ctrl = 0; // ES control
352 l1s_dsp_com.dsp_ndb_ptr->d_anr_ul_ctrl = 0; // ANR control
353 #if (L1_IIR == 1)
354 l1s_dsp_com.dsp_ndb_ptr->d_iir_dl_ctrl = B_IIR_ENABLE; // IIR control: enabled by default
355 #else
356 l1s_dsp_com.dsp_ndb_ptr->d_iir_dl_ctrl = 0;
357 #endif
358 l1s_dsp_com.dsp_ndb_ptr->d_lim_dl_ctrl = 0; // Limiter control
359
360 #endif
361
362
363
364 #if (DSP == 38) || (DSP == 39)
365
366 //-----------------------------------
367 // AUDIO control words initialization
368 //-----------------------------------
369
370 l1s_dsp_com.dsp_ndb_ptr->d_es_ctrl = 0; // ES control
371 l1s_dsp_com.dsp_ndb_ptr->d_anr_ul_ctrl = 0; // ANR control
372 l1s_dsp_com.dsp_ndb_ptr->d_aec_ul_ctrl = 0; // AEC control
373 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_ctrl = 0; // AGC control
374
375 #if (L1_IIR == 1)
376 l1s_dsp_com.dsp_ndb_ptr->d_iir_dl_ctrl = B_IIR_ENABLE; // IIR control: enabled by default
377 #else
378 l1s_dsp_com.dsp_ndb_ptr->d_iir_dl_ctrl = 0;
379 #endif
380 l1s_dsp_com.dsp_ndb_ptr->d_lim_dl_ctrl = 0; // Limiter control
381 l1s_dsp_com.dsp_ndb_ptr->d_drc_dl_ctrl = 0; // DRC control
382 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_ctrl = 0; // AGC control
383 l1s_dsp_com.dsp_ndb_ptr->d_audio_apps_ctrl = 0; // WCM control
384 l1s_dsp_com.dsp_ndb_ptr->d_audio_apps_status = 0; // WCM status
385 l1s_dsp_com.dsp_ndb_ptr->d_aqi_status = 0; // Initialise the status word
386
387 #if(L1_ANR == 2)
388 l1s_dsp_com.dsp_ndb_ptr->d_anr_control = (API) 0;
389 l1s_dsp_com.dsp_ndb_ptr->d_anr_ns_level = (API) 0;
390 l1s_dsp_com.dsp_ndb_ptr->d_anr_tone_ene_th = (API) 0;
391 l1s_dsp_com.dsp_ndb_ptr->d_anr_tone_cnt_th = (API) 0;
392 #endif
393
394
395 #if(L1_IIR == 2)
396 // Set IIR parameters
397 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_control = (API) 0;
398 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_frame_size = (API) 0;
399 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_swap = (API) 0;
400
401 // Set parameter os FIR part
402 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_enable = (API) 0;
403 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_length = (API) 0;
404 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_fir_shift = (API) 0;
405
406 for (i=0; i < IIR_4X_FIR_MAX_LENGTH; i++)
407 {
408 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_fir_taps[i] = (API) 0;
409 }
410
411 // Set parameters for IIR part
412 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_enable = (API) 0;
413 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_number = (API) 0;
414
415 // Set parameters for IIR part - SOS 1
416 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_1 = (API) 0;
417 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_1 = (API) 0;
418
419 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
420 {
421 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_1[j] = (API) 0;
422 }
423 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
424 {
425 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_1[j] = (API) 0;
426 }
427 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_1 = (API) 0;
428
429
430 // Set parameters for IIR part - SOS 2
431 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_2 = (API) 0;
432 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_2 = (API) 0;
433
434 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
435 {
436 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_2[j] = (API) 0;
437 }
438 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
439 {
440 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_2[j] = (API) 0;
441 }
442 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_2 = (API) 0;
443
444
445 // Set parameters for IIR part - SOS 3
446 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_3 = (API) 0;
447 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_3 = (API) 0;
448
449 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
450 {
451 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_3[j] = (API) 0;
452 }
453 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
454 {
455 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_3[j] = (API) 0;
456 }
457 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_3 = (API) 0;
458
459
460 // Set parameters for IIR part - SOS 4
461 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_4 = (API) 0;
462 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_4 = (API) 0;
463
464 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
465 {
466 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_4[j] = (API) 0;
467 }
468 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
469 {
470 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_4[j] = (API) 0;
471 }
472 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_4 = (API) 0;
473
474
475 // Set parameters for IIR part - SOS 5
476 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_5 = (API) 0;
477 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_5 = (API) 0;
478
479 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
480 {
481 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_5[j] = (API) 0;
482 }
483 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
484 {
485 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_5[j] = (API) 0;
486 }
487 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_5 = (API) 0;
488
489
490 // Set parameters for IIR part - SOS 6
491 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_6 = (API) 0;
492 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_fact_form_6 = (API) 0;
493
494 for (j=0; j < IIR_4X_ORDER_OF_SECTION; j++)
495 {
496 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_den_6[j] = (API) 0;
497 }
498 for (j=0; j < (IIR_4X_ORDER_OF_SECTION + 1); j++)
499 {
500 l1s_dsp_com.dsp_ndb_ptr->a_iir4x_sos_num_6[j] = (API) 0;
501 }
502 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_sos_num_form_6 = (API) 0;
503
504
505
506 l1s_dsp_com.dsp_ndb_ptr->d_iir4x_gain = (API) 0;
507
508 #endif
509
510 #if(L1_AGC_UL == 1)
511 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_control = (API) 0;
512 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_frame_size = (API) 0;
513 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_targeted_level = (API) 0;
514 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_signal_up = (API) 0;
515 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_signal_down = (API) 0;
516 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_max_scale = (API) 0;
517 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_gain_smooth_alpha = (API) 0;
518 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_gain_smooth_alpha_fast = (API) 0;
519 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_gain_smooth_beta = (API) 0;
520 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_gain_smooth_beta_fast = (API) 0;
521 l1s_dsp_com.dsp_ndb_ptr->d_agc_ul_gain_intp_flag = (API) 0;
522 #endif
523
524 #if(L1_AGC_DL == 1)
525 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_control = (API) 0;
526 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_frame_size = (API) 0;
527 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_targeted_level = (API) 0;
528 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_signal_up = (API) 0;
529 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_signal_down = (API) 0;
530 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_max_scale = (API) 0;
531 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_gain_smooth_alpha = (API) 0;
532 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_gain_smooth_alpha_fast = (API) 0;
533 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_gain_smooth_beta = (API) 0;
534 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_gain_smooth_beta_fast = (API) 0;
535 l1s_dsp_com.dsp_ndb_ptr->d_agc_dl_gain_intp_flag = (API) 0;
536 #endif
537
538 #if(L1_WCM == 1)
539
540 l1s_dsp_com.dsp_ndb_ptr->d_wcm_mode = (API) 0;
541 l1s_dsp_com.dsp_ndb_ptr->d_wcm_frame_size = (API) 0;
542 l1s_dsp_com.dsp_ndb_ptr->d_wcm_num_sub_frames = (API) 0;
543 l1s_dsp_com.dsp_ndb_ptr->d_wcm_ratio = (API) 0;
544 l1s_dsp_com.dsp_ndb_ptr->d_wcm_threshold = (API) 0;
545 #endif
546
547 #endif // DSP 38
548
549 }
550
551
552 #if (AUDIO_TASK == 1)
553
554 /*-------------------------------------------------------*/
555 /* l1audio_initialize_var() */
556 /*-------------------------------------------------------*/
557 /* */
558 /* Parameters : */
559 /* */
560 /* Return : */
561 /* */
562 /* Description : Initialize the part of l1a, l1s and */
563 /* l1a_l1s_com dedicated to the audio task.*/
564 /* */
565 /*-------------------------------------------------------*/
566 void l1audio_initialize_var(void)
567 {
568 UWORD8 i, j;
569
570 // Initialize the state of the L1S maanger...
571 //--------------------------------------------
572 for(i=0; i<NBR_AUDIO_MANAGER; i++)
573 {
574 l1s.audio_state[i] = 0;
575 }
576
577 #if (L1_EXTERNAL_AUDIO_VOICE_ONOFF == 1)
578 l1a_l1s_com.audio_onoff_task.parameters.onoff_value = FALSE;
579 #endif
580 l1a_l1s_com.audio_forced_by_l1s = FALSE;
581
582 #if (MELODY_E1)
583 l1s.melody0.oscillator[0] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note0[0]);
584 l1s.melody0.oscillator[1] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note1[0]);
585 l1s.melody0.oscillator[2] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note2[0]);
586 l1s.melody0.oscillator[3] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note3[0]);
587 l1s.melody0.oscillator[4] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note4[0]);
588 l1s.melody0.oscillator[5] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note5[0]);
589 l1s.melody0.oscillator[6] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note6[0]);
590 l1s.melody0.oscillator[7] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note7[0]);
591
592 l1s.melody1.oscillator[0] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note0[0]);
593 l1s.melody1.oscillator[1] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note1[0]);
594 l1s.melody1.oscillator[2] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note2[0]);
595 l1s.melody1.oscillator[3] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note3[0]);
596 l1s.melody1.oscillator[4] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note4[0]);
597 l1s.melody1.oscillator[5] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note5[0]);
598 l1s.melody1.oscillator[6] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note6[0]);
599 l1s.melody1.oscillator[7] = &(l1s_dsp_com.dsp_ndb_ptr->a_melo_note7[0]);
600 #endif // MELODY_E1
601
602 #if (MELODY_E2)
603 // Initialization ofthe audio background melody E2 load insturment variable
604 audioback_melody_e2.allowed_size =
605 SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT;
606 audioback_melody_e2.API_address =
607 l1s_dsp_com.dsp_ndb_ptr->a_melody_e2_instrument_wave;
608
609 for (i=0; i < SC_AUDIO_MELODY_E2_MAX_NUMBER_OF_INSTRUMENT; i++)
610 {
611 audioback_melody_e2.number_of_user[i] = 0;
612 }
613 #endif // MELODY_E2
614
615 #if (L1_STEREOPATH == 1)
616 // Reset the stereopath L1S commands
617 l1a_l1s_com.stereopath_drv_task.command.start = FALSE;
618 l1a_l1s_com.stereopath_drv_task.command.stop = FALSE;
619 #endif
620
621 // Triton Audio ON/OFF Changes
622 #if (L1_AUDIO_MCU_ONOFF == 1)
623 l1s.audio_on_off_ctl.l1_audio_switch_on_ul_request = 0;
624 l1s.audio_on_off_ctl.l1_audio_switch_on_dl_request = 0;
625
626 l1s.audio_on_off_ctl.l1_audio_ul_on2off_hold_time =
627 L1_AUDIO_ON2OFF_UL_HOLD_TIME;
628 l1s.audio_on_off_ctl.l1_audio_dl_on2off_hold_time =
629 L1_AUDIO_ON2OFF_DL_HOLD_TIME;
630
631 l1s.audio_on_off_ctl.l1_audio_ul_action = L1_AUDIO_NO_ACTION;
632 l1s.audio_on_off_ctl.l1_audio_dl_action = L1_AUDIO_NO_ACTION;
633
634 l1s.audio_on_off_ctl.l1_audio_ul_switched_on = FALSE;
635 l1s.audio_on_off_ctl.l1_audio_dl_switched_on = FALSE;
636
637 l1s.audio_on_off_ctl.l1_audio_ul_switched_off = TRUE;
638 l1s.audio_on_off_ctl.l1_audio_dl_switched_off = TRUE;
639 #endif // L1_AUDIO_MCU_ONOFF
640
641
642 #if (L1_DRC == 1)
643
644 // init DRC NDB
645 drc_ndb = (T_DRC_MCU_DSP *)API_address_dsp2mcu(C_DRC_API_BASE_ADDRESS);
646 #if (CODE_VERSION == SIMULATION)
647 {
648 drc_ndb = &drc_ndb_sim;
649 }
650 #endif
651
652 drc_ndb->d_drc_speech_mode_samp_f =(API)0;
653 drc_ndb->d_drc_num_subbands =(API)0;
654 drc_ndb->d_drc_frame_len =(API)0;
655 drc_ndb->d_drc_expansion_knee_fb_bs =(API)0;
656 drc_ndb->d_drc_expansion_knee_md_hg =(API)0;
657 drc_ndb->d_drc_expansion_ratio_fb_bs =(API)0;
658 drc_ndb->d_drc_expansion_ratio_md_hg =(API)0;
659 drc_ndb->d_drc_max_amplification_fb_bs =(API)0;
660 drc_ndb->d_drc_max_amplification_md_hg =(API)0;
661 drc_ndb->d_drc_compression_knee_fb_bs =(API)0;
662 drc_ndb->d_drc_compression_knee_md_hg =(API)0;
663 drc_ndb->d_drc_compression_ratio_fb_bs =(API)0;
664 drc_ndb->d_drc_compression_ratio_md_hg =(API)0;
665 drc_ndb->d_drc_energy_limiting_th_fb_bs =(API)0;
666 drc_ndb->d_drc_energy_limiting_th_md_hg =(API)0;
667 drc_ndb->d_drc_limiter_threshold_fb =(API)0;
668 drc_ndb->d_drc_limiter_threshold_bs =(API)0;
669 drc_ndb->d_drc_limiter_threshold_md =(API)0;
670 drc_ndb->d_drc_limiter_threshold_hg =(API)0;
671 drc_ndb->d_drc_limiter_hangover_spect_preserve =(API)0;
672 drc_ndb->d_drc_limiter_release_fb_bs =(API)0;
673 drc_ndb->d_drc_limiter_release_md_hg =(API)0;
674 drc_ndb->d_drc_gain_track_fb_bs =(API)0;
675 drc_ndb->d_drc_gain_track_md_hg =(API)0;
676 for (j=0; j < DRC_LPF_LENGTH; j++)
677 {
678 drc_ndb->a_drc_low_pass_filter[j] = (API)0;
679 }
680 for (j=0; j < DRC_BPF_LENGTH; j++)
681 {
682 drc_ndb->a_drc_mid_band_filter[j] = (API)0;
683 }
684 #endif
685
686 l1a_l1s_com.outen_cfg_task.outen1 =
687 l1a_l1s_com.outen_cfg_task.outen2 =
688 l1a_l1s_com.outen_cfg_task.outen3 =
689 l1a_l1s_com.outen_cfg_task.command_requested =
690 l1a_l1s_com.outen_cfg_task.command_commited = 0;
691 //voice and stereo path configuration for L1 standalone mode CQ- OMAPS00088143
692 #if (OP_L1_STANDALONE == 1)
693 // Voice path and Stereo path
694 l1a_l1s_com.outen_cfg_task.outen3 = 0;
695 l1a_l1s_com.outen_cfg_task.outen2 = 0x03;
696 l1a_l1s_com.outen_cfg_task.outen1 = 0;
697 #endif
698 #if(L1_BT_AUDIO ==1)
699 bt_audio.pcm_data_pending = 0;
700 bt_audio.pcm_data_end = 0;
701 bt_audio.pcm_data_ready = 0;
702 bt_audio.pcm_data_failed = 0;
703 bt_audio.connected_status = FALSE;
704 #endif
705 }
706
707 #endif // AUDIO_TASK