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comparison target-utils/c139explore/uwire.c @ 950:cd34e0d534b9

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c139explore: LCD output implemented, does not work
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Wed, 04 Nov 2015 01:43:44 +0000
parents
children 15b1b396ad23
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949:df1dccc0ef9c 950:cd34e0d534b9
1 /* Driver for uWire Master Controller inside TI Calypso */
2 /* lifted from OsmocomBB and ported to FreeCalypso target-utils environment */
3
4 /* (C) 2010 by Sylvain Munaut <tnt@246tNt.com>
5 *
6 * All Rights Reserved
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License along
19 * with this program; if not, write to the Free Software Foundation, Inc.,
20 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
21 *
22 */
23
24 #include "types.h"
25
26 struct uwire_regs {
27 u16 reg_data;
28 u16 reg_csr;
29 u16 reg_sr1;
30 u16 reg_sr2;
31 u16 reg_sr3;
32 };
33
34 #define UWIRE_REGS (*(volatile struct uwire_regs *) 0xFFFE4000)
35
36 #define UWIRE_CSR_BITS_RD(n) (((n) & 0x1f) << 0)
37 #define UWIRE_CSR_BITS_WR(n) (((n) & 0x1f) << 5)
38 #define UWIRE_CSR_IDX(n) (((n) & 3) << 10)
39 #define UWIRE_CSR_CS_CMD (1 << 12)
40 #define UWIRE_CSR_START (1 << 13)
41 #define UWIRE_CSR_CSRB (1 << 14)
42 #define UWIRE_CSR_RDRB (1 << 15)
43
44 #define UWIRE_CSn_EDGE_RD (1 << 0) /* 1=falling 0=rising */
45 #define UWIRE_CSn_EDGE_WR (1 << 1) /* 1=falling 0=rising */
46 #define UWIRE_CSn_CS_LVL (1 << 2)
47 #define UWIRE_CSn_FRQ_DIV2 (0 << 3)
48 #define UWIRE_CSn_FRQ_DIV4 (1 << 3)
49 #define UWIRE_CSn_FRQ_DIV8 (2 << 3)
50 #define UWIRE_CSn_CKH
51
52 #define UWIRE_CSn_SHIFT(n) (((n) & 1) ? 6 : 0)
53 #define UWIRE_CSn_REG(n) (((n) & 2) ? REG_SR2 : REG_SR1)
54
55 #define UWIRE_SR3_CLK_EN (1 << 0)
56 #define UWIRE_SR3_CLK_DIV2 (0 << 1)
57 #define UWIRE_SR3_CLK_DIV4 (1 << 1)
58 #define UWIRE_SR3_CLK_DIV7 (2 << 1)
59 #define UWIRE_SR3_CLK_DIV10 (3 << 1)
60
61 static inline void _uwire_wait(int mask, int val)
62 {
63 while ((UWIRE_REGS.reg_csr & mask) != val);
64 }
65
66 void uwire_init(void)
67 {
68 UWIRE_REGS.reg_sr3 = UWIRE_SR3_CLK_EN | UWIRE_SR3_CLK_DIV2;
69 UWIRE_REGS.reg_sr1 = UWIRE_CSn_CS_LVL | UWIRE_CSn_FRQ_DIV2;
70 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD;
71 _uwire_wait(UWIRE_CSR_CSRB, 0);
72 }
73
74 send_via_uwire(word)
75 unsigned word;
76 {
77 u16 tmp = 0;
78
79 /* select the chip */
80 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | UWIRE_CSR_CS_CMD;
81 _uwire_wait(UWIRE_CSR_CSRB, 0);
82
83 UWIRE_REGS.reg_data = word << 7;
84 UWIRE_REGS.reg_csr = UWIRE_CSR_BITS_WR(9) | UWIRE_CSR_START;
85 _uwire_wait(UWIRE_CSR_CSRB, 0);
86
87 /* unselect the chip */
88 UWIRE_REGS.reg_csr = UWIRE_CSR_IDX(0) | 0;
89 _uwire_wait(UWIRE_CSR_CSRB, 0);
90
91 return 0;
92 }