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comparison gsm-fw/L1/include/l1_confg.h @ 531:de635895e0be

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gsm-fw/L1/include/*.h: s/ANLG_FAM/ANALOG/ in LoCosto-based version
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 01 Aug 2014 16:46:33 +0000
parents 25a7fe25864c
children d9fd344d7570
comparison
equal deleted inserted replaced
530:25a7fe25864c 531:de635895e0be
612 // bit0 - Work-around to support CRTG. 612 // bit0 - Work-around to support CRTG.
613 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 613 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
614 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 614 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
615 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. 615 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
616 616
617 #if (ANLG_FAM == 1) // OMEGA / NAUSICA 617 #if (ANALOG == 1) // OMEGA / NAUSICA
618 #define C_DSP_SW_WORK_AROUND 0x0006 618 #define C_DSP_SW_WORK_AROUND 0x0006
619 619
620 #elif (ANLG_FAM == 2) // IOTA 620 #elif (ANALOG == 2) // IOTA
621 #define C_DSP_SW_WORK_AROUND 0x000E 621 #define C_DSP_SW_WORK_AROUND 0x000E
622 622
623 #elif (ANLG_FAM == 3) // SYREN 623 #elif (ANALOG == 3) // SYREN
624 #define C_DSP_SW_WORK_AROUND 0x000E 624 #define C_DSP_SW_WORK_AROUND 0x000E
625 625
626 #endif 626 #endif
627 627
628 /* DSP debug trace configuration */ 628 /* DSP debug trace configuration */
710 // DSP software work-around config 710 // DSP software work-around config
711 // bit0 - Work-around to support CRTG. 711 // bit0 - Work-around to support CRTG.
712 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 712 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
713 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 713 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
714 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. 714 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
715 #if (ANLG_FAM == 1) // OMEGA / NAUSICA 715 #if (ANALOG == 1) // OMEGA / NAUSICA
716 #define C_DSP_SW_WORK_AROUND 0x0006 716 #define C_DSP_SW_WORK_AROUND 0x0006
717 717
718 #elif (ANLG_FAM == 2) // IOTA 718 #elif (ANALOG == 2) // IOTA
719 #define C_DSP_SW_WORK_AROUND 0x000E 719 #define C_DSP_SW_WORK_AROUND 0x000E
720 720
721 #elif (ANLG_FAM == 3) // SYREN 721 #elif (ANALOG == 3) // SYREN
722 #define C_DSP_SW_WORK_AROUND 0x000E 722 #define C_DSP_SW_WORK_AROUND 0x000E
723 723
724 #endif 724 #endif
725 725
726 /* DSP debug trace configuration */ 726 /* DSP debug trace configuration */
818 // DSP software work-around config 818 // DSP software work-around config
819 // bit0 - Work-around to support CRTG. 819 // bit0 - Work-around to support CRTG.
820 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 820 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
821 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 821 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
822 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. 822 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
823 #if (ANLG_FAM == 1) // OMEGA / NAUSICA 823 #if (ANALOG == 1) // OMEGA / NAUSICA
824 #define C_DSP_SW_WORK_AROUND 0x0006 824 #define C_DSP_SW_WORK_AROUND 0x0006
825 825
826 #elif (ANLG_FAM == 2) // IOTA 826 #elif (ANALOG == 2) // IOTA
827 #define C_DSP_SW_WORK_AROUND 0x000E 827 #define C_DSP_SW_WORK_AROUND 0x000E
828 828
829 #elif (ANLG_FAM == 3) // SYREN 829 #elif (ANALOG == 3) // SYREN
830 #define C_DSP_SW_WORK_AROUND 0x000E 830 #define C_DSP_SW_WORK_AROUND 0x000E
831 831
832 #endif 832 #endif
833 833
834 /* DSP debug trace configuration */ 834 /* DSP debug trace configuration */
931 // DSP software work-around config 931 // DSP software work-around config
932 // bit0 - Work-around to support CRTG. 932 // bit0 - Work-around to support CRTG.
933 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260. 933 // bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
934 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650. 934 // bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
935 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911. 935 // bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
936 #if (ANLG_FAM == 1) // OMEGA / NAUSICA 936 #if (ANALOG == 1) // OMEGA / NAUSICA
937 #define C_DSP_SW_WORK_AROUND 0x0006 937 #define C_DSP_SW_WORK_AROUND 0x0006
938 938
939 #elif (ANLG_FAM == 2) // IOTA 939 #elif (ANALOG == 2) // IOTA
940 #define C_DSP_SW_WORK_AROUND 0x000E 940 #define C_DSP_SW_WORK_AROUND 0x000E
941 941
942 #elif (ANLG_FAM == 3) // SYREN 942 #elif (ANALOG == 3) // SYREN
943 #define C_DSP_SW_WORK_AROUND 0x000E 943 #define C_DSP_SW_WORK_AROUND 0x000E
944 944
945 #elif (ANLG_FAM == 11) // TRITON 945 #elif (ANALOG == 11) // TRITON
946 #define C_DSP_SW_WORK_AROUND 0x000E 946 #define C_DSP_SW_WORK_AROUND 0x000E
947 947
948 #endif 948 #endif
949 949
950 /* DSP debug trace configuration */ 950 /* DSP debug trace configuration */