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comparison nuc-fw/finlink/ld-script.src @ 92:f459043fae0c

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nuc-fw config: ld script generation implemented
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 25 Aug 2013 21:20:20 +0000
parents
children 2c5160a9d652
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91:3641e44f044e 92:f459043fae0c
1 dnl This ld script source is fed through m4 in order to fill in
2 dnl those settings which depend on the configuration.
3 dnl Memory region sizes are set in ../include/config.m4, generated
4 dnl by the configuration mechanism based on the selected target,
5 dnl and the Makefile prepends flash.m4 or xram.m4 to select the
6 dnl type of image we are linking: either the regular flashable image,
7 dnl or a RAM-only test image (to be loaded via fc-xram) that does not
8 dnl touch the flash and pretends as if the flash doesn't even exist.
9
10 /*
11 * FreeCalypso ld script for the Buildmem build
12 */
13
14 ENTRY(ifelse(Buildmem,XRAM,_FlashorXram_entry,0))
15
16 include(`../include/config.m4')dnl
17 MEMORY {
18 ifelse(Buildmem,FLASH,
19 ` FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000
20 FLASH : ORIGIN = 0x2000, LENGTH = CONFIG_FWFLASH_SIZE - 0x2000')
21 IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE
22 XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE
23 }
24
25 SECTIONS {
26 /* XIP code, going into flash or XRAM emulating flash */
27 xip.text : {
28 *(xip.text*)
29 xipcode.o(.text*)
30 *libplus.xip.a:(.text*)
31 *libsprintf.a:(.text*)
32 /* let's put the ARM->Thumb veneers in the XIP section */
33 *(.glue_7)
34 } > Buildmem
35
36 /* copy-to-IRAM code */
37 iram.text 0x80001C : {
38 /* the 7 exception and interrupt vectors @ 0x80001C */
39 *(iram.vectors)
40 *(iram.text*)
41 iramcode.o(.text*)
42 *libplus.iram.a:(.text*)
43 *libc.a:(.text*)
44 *libgcc.a:(.text*)
45 } > IRAM AT> Buildmem
46 __iramtext_ram_addr = ADDR(iram.text);
47 __iramtext_flash_addr = LOADADDR(iram.text);
48 __iramtext_size = SIZEOF(iram.text);
49
50 /* all .rodata will stay in flash */
51 .rodata : {
52 *(.rodata*)
53 } > Buildmem
54
55 /*
56 * All .data will go into XRAM.
57 * For the flash build we'll have a step that copies
58 * the .data section from flash to XRAM; for the RAM-only
59 * build it goes directly into XRAM and stays there.
60 */
61 .data : {
62 *(.data*)
63 } > XRAM AT> Buildmem
64 ifelse(Buildmem,FLASH,
65 ` __initdata_ram_addr = ADDR(.data);
66 __initdata_flash_addr = LOADADDR(.data);
67 __initdata_size = SIZEOF(.data);
68 ')dnl
69
70 /* we have two kinds of BSS: internal and external */
71 int.bss (NOLOAD) : {
72 *(int.bss*)
73 iramcode.o(.bss* COMMON)
74 *libplus.iram.a:(.bss* COMMON)
75 *libc.a:(.bss* COMMON)
76 *libgcc.a:(.bss* COMMON)
77 . = ALIGN(4);
78 } > IRAM
79 __intbss_start = ADDR(int.bss);
80 __intbss_size = SIZEOF(int.bss);
81
82 ext.bss (NOLOAD) : {
83 *(ext.bss*)
84 xipcode.o(.bss* COMMON)
85 *libplus.xip.a:(.bss* COMMON)
86 *libsprintf.a:(.bss* COMMON)
87 . = ALIGN(4);
88 } > XRAM
89 __extbss_start = ADDR(ext.bss);
90 __extbss_size = SIZEOF(ext.bss);
91
92 /* finally, we have "raw RAM": like BSS, but we don't zero it out */
93 int.ram (NOLOAD) : {
94 *(int.ram*)
95 *(system_stack)
96 *(irq_stack)
97 *(fiq_stack)
98 *(timer_hisr_stack)
99 . = ALIGN(4);
100 _iram_end = .;
101 } > IRAM
102
103 ext.ram (NOLOAD) : {
104 *(ext.ram*)
105 . = ALIGN(4);
106 _xram_end = .;
107 } > XRAM
108 }