FreeCalypso > hg > freecalypso-sw
comparison gsm-fw/serial/uartfax.c @ 852:fc713944bd1c
gsm-fw: uartfax.c included in the build with feature at-modem
author | Space Falcon <falcon@ivan.Harhan.ORG> |
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date | Sun, 26 Apr 2015 03:06:32 +0000 |
parents | 9e54d153eb8c |
children | ae254ffeaec3 |
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851:9e54d153eb8c | 852:fc713944bd1c |
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74 * 8 CTS RTS 8 | 74 * 8 CTS RTS 8 |
75 * 9 NC 9 NC | 75 * 9 NC 9 NC |
76 * | 76 * |
77 */ | 77 */ |
78 | 78 |
79 #include "swconfig.cfg" | 79 #include "../include/config.h" |
80 | |
81 #include "l1sw.cfg" | |
82 | |
83 #if (OP_L1_STANDALONE == 0) | |
84 #include "rv.cfg" | |
85 #endif | |
86 #include "board.cfg" | |
87 #include "chipset.cfg" | |
88 #ifdef BLUETOOTH_INCLUDED | |
89 #include "btemobile.cfg" | |
90 #endif | |
91 | |
92 | 80 |
93 #include <string.h> | 81 #include <string.h> |
94 #include "nucleus.h" | 82 |
95 | 83 /* |
96 #include "main/sys_types.h" | 84 * rv_general.h is needed for macros Min & Min3. |
85 */ | |
86 #include "../riviera/rv/rv_general.h" | |
87 #include "../nucleus/nucleus.h" | |
88 | |
89 #include "../include/sys_types.h" | |
97 #include "faxdata.h" | 90 #include "faxdata.h" |
98 #include "uartfax.h" | 91 #include "uartfax.h" |
99 | 92 |
100 /* | 93 /* |
101 * Needed to reset and restart the sleep timer in case of incoming characters. | 94 * Needed to reset and restart the sleep timer in case of incoming characters. |
102 */ | 95 */ |
103 | 96 |
104 #include "serialswitch.h" | 97 #include "serialswitch.h" |
105 extern SYS_BOOL uart_sleep_timer_enabled; | 98 extern SYS_BOOL uart_sleep_timer_enabled; |
106 | 99 |
107 /* | 100 #include "../bsp/mem.h" |
108 * rv_general.h is needed for macros Min & Min3. | 101 #include "../bsp/armio.h" |
109 */ | 102 |
110 | 103 #if CONFIG_TARGET_GTAMODEM |
111 #include "rv/rv_general.h" | 104 #define EXTHOST_WAKEUP_GPIO 1 |
112 | 105 #else |
113 #include "memif/mem.h" | 106 #undef EXTHOST_WAKEUP_GPIO |
114 | |
115 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) | |
116 #include "armio/armio.h" | |
117 #endif | 107 #endif |
118 | 108 |
119 /* | 109 /* |
120 * Maximal value for an unsigned 32 bits. | 110 * Maximal value for an unsigned 32 bits. |
121 */ | 111 */ |
122 | 112 |
123 #define MAX_UNSIGNED_32 (4294967295) | 113 #define MAX_UNSIGNED_32 (0xFFFFFFFFU) |
124 | 114 |
125 #define FIFO_SIZE (64) /* In bytes. */ | 115 #define FIFO_SIZE (64) /* In bytes. */ |
126 | 116 |
127 | 117 |
128 /* | 118 /* |
303 * 3 HISR are used to avoid to execute operations from the LISR. | 293 * 3 HISR are used to avoid to execute operations from the LISR. |
304 */ | 294 */ |
305 | 295 |
306 #define RX_HISR_PRIORITY (2) | 296 #define RX_HISR_PRIORITY (2) |
307 | 297 |
308 | |
309 | |
310 | |
311 // NGENGE increase hisr stack otherwise overflows with multiple callbacks | 298 // NGENGE increase hisr stack otherwise overflows with multiple callbacks |
312 //#define RX_HISR_STACK_SIZE (512) /* Bytes. */ | 299 //#define RX_HISR_STACK_SIZE (512) /* Bytes. */ |
313 #define RX_HISR_STACK_SIZE (768) /* Bytes. */ | 300 #define RX_HISR_STACK_SIZE (768) /* Bytes. */ |
314 | 301 |
315 | |
316 | |
317 | |
318 #define TX_HISR_PRIORITY (2) | 302 #define TX_HISR_PRIORITY (2) |
319 | |
320 | |
321 | 303 |
322 // NGENGE increase hisr stack otherwise overflows with multiple callbacks | 304 // NGENGE increase hisr stack otherwise overflows with multiple callbacks |
323 //#define TX_HISR_STACK_SIZE (512) /* Bytes. */ | 305 //#define TX_HISR_STACK_SIZE (512) /* Bytes. */ |
324 #define TX_HISR_STACK_SIZE (768) /* Bytes. */ | 306 #define TX_HISR_STACK_SIZE (768) /* Bytes. */ |
325 | |
326 | |
327 | |
328 | 307 |
329 #define V24_HISR_PRIORITY (2) | 308 #define V24_HISR_PRIORITY (2) |
330 #define V24_HISR_STACK_SIZE (512) /* Bytes. */ | 309 #define V24_HISR_STACK_SIZE (512) /* Bytes. */ |
331 | 310 |
332 /* | 311 /* |
354 | 333 |
355 #define WRITE_UART_REGISTER(UART,REG,VALUE) \ | 334 #define WRITE_UART_REGISTER(UART,REG,VALUE) \ |
356 *((volatile SYS_UWORD8 *) ((UART)->base_address + (REG))) = (VALUE) | 335 *((volatile SYS_UWORD8 *) ((UART)->base_address + (REG))) = (VALUE) |
357 | 336 |
358 #define RESET_BIT(UART,REG,BIT) \ | 337 #define RESET_BIT(UART,REG,BIT) \ |
359 (WRITE_UART_REGISTER ( \ | 338 (WRITE_UART_REGISTER ( \ |
360 UART, REG, READ_UART_REGISTER (UART, REG) & ~(1 << (BIT)))) | 339 UART, REG, READ_UART_REGISTER (UART, REG) & ~(1 << (BIT)))) |
361 | 340 |
362 #define SET_BIT(UART,REG,BIT) \ | 341 #define SET_BIT(UART,REG,BIT) \ |
363 (WRITE_UART_REGISTER ( \ | 342 (WRITE_UART_REGISTER ( \ |
364 UART, REG, READ_UART_REGISTER (UART, REG) | (1 << (BIT)))) | 343 UART, REG, READ_UART_REGISTER (UART, REG) | (1 << (BIT)))) |
365 | 344 |
366 | 345 |
367 /* | 346 /* |
368 * These macros allow to enable or disable the wake-up interrupt. | 347 * These macros allow to enable or disable the wake-up interrupt. |
369 */ | 348 */ |
551 | 530 |
552 SYS_BOOL esc_seq_received; | 531 SYS_BOOL esc_seq_received; |
553 SYS_UWORD8 rts_level; /* RTS on RS232 side, CTS on chipset side. | 532 SYS_UWORD8 rts_level; /* RTS on RS232 side, CTS on chipset side. |
554 1: The RS232 line is deactivated (low). */ | 533 1: The RS232 line is deactivated (low). */ |
555 | 534 |
556 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 535 #if TARGET_HAS_DTR_INPUT |
557 SYS_UWORD8 dtr_level; /* Controlled with an I/O on C & D-Sample and | 536 SYS_UWORD8 dtr_level; /* Controlled with an I/O on C & D-Sample and |
558 handled by Calypso+ on E-Sample. | 537 handled by Calypso+ on E-Sample. |
559 1: The RS232 line is deactivated (low). */ | 538 1: The RS232 line is deactivated (low). */ |
560 /* | 539 /* |
561 * When the DTR interrupt is detected the user's Rx callback function must | 540 * When the DTR interrupt is detected the user's Rx callback function must |
655 * DLL (LSB) and DLH (MSB) registers values using the 13 MHz clock. | 634 * DLL (LSB) and DLH (MSB) registers values using the 13 MHz clock. |
656 */ | 635 */ |
657 | 636 |
658 static const SYS_UWORD8 dll[] = | 637 static const SYS_UWORD8 dll[] = |
659 { | 638 { |
660 0, /* Auto baud: */ | 639 0, /* Auto baud: */ |
661 81, /* 75 baud. */ | 640 81, /* 75 baud. */ |
662 40, /* 150 baud. */ | 641 40, /* 150 baud. */ |
663 148, /* 300 baud. */ | 642 148, /* 300 baud. */ |
664 74, /* 600 baud. */ | 643 74, /* 600 baud. */ |
665 165, /* 1200 baud. */ | 644 165, /* 1200 baud. */ |
913 * Build the state parameter defined in UAF_GetLineState. | 892 * Build the state parameter defined in UAF_GetLineState. |
914 * The field state_2 is used when state_1 is set to 0 to avoid to | 893 * The field state_2 is used when state_1 is set to 0 to avoid to |
915 * lose events detected in the RX interrupt handler. | 894 * lose events detected in the RX interrupt handler. |
916 */ | 895 */ |
917 | 896 |
918 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 897 #if TARGET_HAS_DTR_INPUT |
919 if (call_source == 3) /* Call from Rx HISR */ | 898 if (call_source == 3) /* Call from Rx HISR */ |
920 dtr_level = uart->dtr_level_saved[uart->index_hisr]; | 899 dtr_level = uart->dtr_level_saved[uart->index_hisr]; |
921 else | 900 else |
922 dtr_level = uart->dtr_level; | 901 dtr_level = uart->dtr_level; |
923 #endif | 902 #endif |
930 uart->state_1 = 0; | 909 uart->state_1 = 0; |
931 uart->state = &(uart->state_1); | 910 uart->state = &(uart->state_1); |
932 | 911 |
933 state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | | 912 state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | |
934 | 913 |
935 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 914 #if TARGET_HAS_DTR_INPUT |
936 (((SYS_UWORD32) dtr_level) << DTR) | | 915 (((SYS_UWORD32) dtr_level) << DTR) | |
937 #endif | 916 #endif |
938 | 917 |
939 (((SYS_UWORD32) (uart->tx_stopped_by_application | | 918 (((SYS_UWORD32) (uart->tx_stopped_by_application | |
940 uart->tx_stopped_by_driver)) << TXSTP) | | 919 uart->tx_stopped_by_driver)) << TXSTP) | |
953 * X 0 RTS XON:0 XOFF:1 (transmitter) | 932 * X 0 RTS XON:0 XOFF:1 (transmitter) |
954 * | 933 * |
955 * DTR is supported on C, D & E-Sample. | 934 * DTR is supported on C, D & E-Sample. |
956 */ | 935 */ |
957 | 936 |
958 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 937 #if TARGET_HAS_DTR_INPUT |
959 state |= (((SYS_UWORD32) uart->dtr_level) << SA); | 938 state |= (((SYS_UWORD32) uart->dtr_level) << SA); |
960 #endif | 939 #endif |
961 | 940 |
962 if (uart->flow_control_mode != fc_rts) | 941 if (uart->flow_control_mode != fc_rts) |
963 state |= (((SYS_UWORD32) uart->rts_level) << SB); | 942 state |= (((SYS_UWORD32) uart->rts_level) << SB); |
1798 } | 1777 } |
1799 | 1778 |
1800 current_byte = first_byte; | 1779 current_byte = first_byte; |
1801 | 1780 |
1802 if (*bytes_in_rx_buffer) { | 1781 if (*bytes_in_rx_buffer) { |
1803 | 1782 |
1804 | 1783 /* The Rx buffer is not empty and is being used by HISR ! */ |
1805 /* The Rx buffer is not empty and is being used by HISR ! */ | 1784 /* Hence stop the flow control */ |
1806 /* Hence stop the flow control */ | |
1807 stop_receiver (uart); | 1785 stop_receiver (uart); |
1808 | 1786 |
1809 /* | 1787 /* |
1810 * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers. | 1788 * Reset LCR[7] (DLAB) to have access to the RBR, THR and IER registers. |
1811 */ | 1789 */ |
1812 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); | 1790 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); |
1813 | 1791 |
1814 /* Mask The Rx and interrupt */ | 1792 /* Mask The Rx and interrupt */ |
1815 | 1793 |
1816 WRITE_UART_REGISTER ( | 1794 WRITE_UART_REGISTER ( |
1817 uart, IER, READ_UART_REGISTER (uart, IER) & | 1795 uart, IER, READ_UART_REGISTER (uart, IER) & |
1818 ~(ERBI | EDSSI)); | 1796 ~(ERBI | EDSSI)); |
1819 | 1797 |
1820 uart->rx_stopped_by_lisr = 1; | 1798 uart->rx_stopped_by_lisr = 1; |
1821 return (bytes_received); | 1799 return (bytes_received); |
1822 | 1800 |
1823 } | 1801 } |
1824 | 1802 |
1825 uart->rx_buffer_used_by_rx_lisr = first_byte; | 1803 uart->rx_buffer_used_by_rx_lisr = first_byte; |
1826 | 1804 |
1827 status = READ_UART_REGISTER (uart, LSR); | 1805 status = READ_UART_REGISTER (uart, LSR); |
1828 | 1806 |
1963 */ | 1941 */ |
1964 | 1942 |
1965 SER_restart_uart_sleep_timer (); | 1943 SER_restart_uart_sleep_timer (); |
1966 uart_sleep_timer_enabled = 1; | 1944 uart_sleep_timer_enabled = 1; |
1967 | 1945 |
1968 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 1946 #if TARGET_HAS_DTR_INPUT |
1969 uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */ | 1947 uart->index_hisr = (uart->index_hisr + 1) & 0x01; /* 0 or 1 */ |
1970 #endif | 1948 #endif |
1971 | 1949 |
1972 xon_xoff_detected = 0; | 1950 xon_xoff_detected = 0; |
1973 | 1951 |
2088 bytes_free_in_rx_buffer -= bytes_to_copy; | 2066 bytes_free_in_rx_buffer -= bytes_to_copy; |
2089 bytes_read -= bytes_to_copy; | 2067 bytes_read -= bytes_to_copy; |
2090 | 2068 |
2091 wrap_around_counter -= bytes_to_copy; | 2069 wrap_around_counter -= bytes_to_copy; |
2092 if (!wrap_around_counter) | 2070 if (!wrap_around_counter) |
2093 uart->rx_in = &(uart->rx_buffer[0]); | 2071 uart->rx_in = &(uart->rx_buffer[0]); |
2094 else | 2072 else |
2095 uart->rx_in += bytes_to_copy; | 2073 uart->rx_in += bytes_to_copy; |
2096 | 2074 |
2097 /* | 2075 /* |
2098 * Check if there are still some characters to copy. | 2076 * Check if there are still some characters to copy. |
2121 uart->rx_in += bytes_to_copy; | 2099 uart->rx_in += bytes_to_copy; |
2122 | 2100 |
2123 /* | 2101 /* |
2124 * bytes_free_in_rx_buffer not updated since not used anymore. | 2102 * bytes_free_in_rx_buffer not updated since not used anymore. |
2125 */ | 2103 */ |
2126 bytes_read -= bytes_to_copy; | 2104 bytes_read -= bytes_to_copy; |
2127 | 2105 |
2128 } | 2106 } |
2129 else { | 2107 else { |
2130 bytes_read = 0; | 2108 bytes_read = 0; |
2131 } | 2109 } |
2132 } /* end if (uart->flow_control_mode == fc_xoff) */ | 2110 } /* end if (uart->flow_control_mode == fc_xoff) */ |
2164 if ((!uart->rd_call_from_hisr_in_progress) && | 2142 if ((!uart->rd_call_from_hisr_in_progress) && |
2165 (uart->reading_suspended || | 2143 (uart->reading_suspended || |
2166 (uart->rd_call_setup == rm_reInstall))) { | 2144 (uart->rd_call_setup == rm_reInstall))) { |
2167 | 2145 |
2168 if ((bytes_in_rx_buffer >= uart->rx_threshold_level) || | 2146 if ((bytes_in_rx_buffer >= uart->rx_threshold_level) || |
2169 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 2147 #if TARGET_HAS_DTR_INPUT |
2170 uart->dtr_change_detected[uart->index_hisr] || | 2148 uart->dtr_change_detected[uart->index_hisr] || |
2171 #endif | 2149 #endif |
2172 uart->break_received || | 2150 uart->break_received || |
2173 xon_xoff_detected) { | 2151 xon_xoff_detected) { |
2174 | 2152 |
2177 update_reading_callback (uart, 3); /* 3: call from Rx HISR. */ | 2155 update_reading_callback (uart, 3); /* 3: call from Rx HISR. */ |
2178 | 2156 |
2179 uart->reading_suspended = 0; | 2157 uart->reading_suspended = 0; |
2180 uart->break_received = 0; | 2158 uart->break_received = 0; |
2181 uart->esc_seq_received = 0; | 2159 uart->esc_seq_received = 0; |
2182 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 2160 #if TARGET_HAS_DTR_INPUT |
2183 uart->dtr_change_detected[uart->index_hisr] = 0; | 2161 uart->dtr_change_detected[uart->index_hisr] = 0; |
2184 #endif | 2162 #endif |
2185 } | 2163 } |
2186 } | 2164 } |
2187 | 2165 |
2188 } | 2166 } |
2189 | |
2190 | 2167 |
2191 | 2168 |
2192 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); | 2169 WRITE_UART_REGISTER (uart, LCR, READ_UART_REGISTER (uart, LCR) & ~DLAB); |
2193 | 2170 |
2194 /* Mask The Rx and Modem status interrupt */ | 2171 /* Mask The Rx and Modem status interrupt */ |
2497 */ | 2474 */ |
2498 | 2475 |
2499 if (DRIVER_DISABLED (uart)) | 2476 if (DRIVER_DISABLED (uart)) |
2500 empty_rx_fifo (uart); | 2477 empty_rx_fifo (uart); |
2501 | 2478 |
2502 else if (build_rx_fifo_array (uart)){ | 2479 else if (build_rx_fifo_array (uart)) { |
2503 (void) NU_Activate_HISR (&(uart->rx_hisr_ctrl_block)); | 2480 (void) NU_Activate_HISR (&(uart->rx_hisr_ctrl_block)); |
2504 | 2481 } |
2505 } | |
2506 | |
2507 | 2482 |
2508 } | 2483 } |
2509 | 2484 |
2510 /******************************************************************************* | 2485 /******************************************************************************* |
2511 * | 2486 * |
2590 } | 2565 } |
2591 | 2566 |
2592 else { | 2567 else { |
2593 | 2568 |
2594 uart->tx_stopped_by_driver = 0; | 2569 uart->tx_stopped_by_driver = 0; |
2595 LowGPIO(1); | 2570 #ifdef EXTHOST_WAKEUP_GPIO |
2571 AI_ResetBit(EXTHOST_WAKEUP_GPIO); | |
2572 #endif | |
2596 | 2573 |
2597 #if ((CHIPSET != 5) && (CHIPSET != 6)) | 2574 #if ((CHIPSET != 5) && (CHIPSET != 6)) |
2598 /* | 2575 /* |
2599 * Disable sleep mode. | 2576 * Disable sleep mode. |
2600 */ | 2577 */ |
2997 if (status & MCTS) | 2974 if (status & MCTS) |
2998 uart->rts_level = 0; | 2975 uart->rts_level = 0; |
2999 else | 2976 else |
3000 uart->rts_level = 1; | 2977 uart->rts_level = 1; |
3001 | 2978 |
3002 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) | 2979 #if TARGET_HAS_DTR_INPUT |
3003 /* | 2980 /* |
3004 * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem. | 2981 * On C & D-Sample, 2 I/O are used to control DCD and DTR on UART Modem. |
3005 * DCD: I/O 2 (output) | 2982 * DCD: I/O 2 (output) |
3006 * DTR: I/O 3 (input) | 2983 * DTR: I/O 3 (input) |
3007 */ | 2984 */ |
3217 * Mask all interrupts causes and disable sleep mode and low power mode. | 3194 * Mask all interrupts causes and disable sleep mode and low power mode. |
3218 */ | 3195 */ |
3219 | 3196 |
3220 WRITE_UART_REGISTER (uart, IER, 0x00); | 3197 WRITE_UART_REGISTER (uart, IER, 0x00); |
3221 | 3198 |
3222 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) | 3199 #if TARGET_HAS_DTR_INPUT |
3223 AI_MaskIT (ARMIO_MASKIT_GPIO); | 3200 AI_MaskIT (ARMIO_MASKIT_GPIO); |
3224 #elif (CHIPSET == 12) | 3201 #elif (CHIPSET == 12) |
3225 DISABLE_DSR_INTERRUPT (uart); | 3202 DISABLE_DSR_INTERRUPT (uart); |
3226 #endif | 3203 #endif |
3227 | 3204 |
3358 if (status & MCTS) | 3335 if (status & MCTS) |
3359 uart->rts_level = 0; | 3336 uart->rts_level = 0; |
3360 else | 3337 else |
3361 uart->rts_level = 1; | 3338 uart->rts_level = 1; |
3362 | 3339 |
3363 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) | 3340 #if TARGET_HAS_DTR_INPUT |
3364 /* | 3341 /* |
3365 * Read the state of DTR and select the edge. | 3342 * Read the state of DTR and select the edge. |
3366 */ | 3343 */ |
3367 | 3344 |
3368 uart->dtr_level = AI_ReadBit (ARMIO_DTR); | 3345 uart->dtr_level = AI_ReadBit (ARMIO_DTR); |
3942 | 3919 |
3943 uart = &uart_parameters; | 3920 uart = &uart_parameters; |
3944 deep_sleep = 0; | 3921 deep_sleep = 0; |
3945 | 3922 |
3946 /* | 3923 /* |
3947 * Check if RX & TX FIFOs are both empty | 3924 * Check if RX & TX FIFOs are both empty |
3948 */ | 3925 */ |
3949 | 3926 |
3950 status = READ_UART_REGISTER (uart, LSR); | 3927 status = READ_UART_REGISTER (uart, LSR); |
3951 | 3928 |
3952 if (!(status & DR) && | 3929 if (!(status & DR) && |
3953 (status & TEMT)) { | 3930 (status & TEMT)) { |
4320 if (uart->tx_in >= &(uart->tx_buffer[0]) + uart->buffer_size + 1) | 4297 if (uart->tx_in >= &(uart->tx_buffer[0]) + uart->buffer_size + 1) |
4321 uart->tx_in = uart->tx_in - uart->buffer_size - 1; | 4298 uart->tx_in = uart->tx_in - uart->buffer_size - 1; |
4322 | 4299 |
4323 /* If we have been stopped due to high RTS, we have to | 4300 /* If we have been stopped due to high RTS, we have to |
4324 * wake up application processor by IRQ via IO1 -HW */ | 4301 * wake up application processor by IRQ via IO1 -HW */ |
4302 #ifdef EXTHOST_WAKEUP_GPIO | |
4325 if (uart->tx_stopped_by_driver) | 4303 if (uart->tx_stopped_by_driver) |
4326 HighGPIO(1); | 4304 AI_SetBit(EXTHOST_WAKEUP_GPIO); |
4305 #endif | |
4327 | 4306 |
4328 /* | 4307 /* |
4329 * If: | 4308 * If: |
4330 * - there is no break to send, | 4309 * - there is no break to send, |
4331 * - the flow control is not activated, | 4310 * - the flow control is not activated, |
4542 uart->state_1 = 0; | 4521 uart->state_1 = 0; |
4543 uart->state = &(uart->state_1); | 4522 uart->state = &(uart->state_1); |
4544 | 4523 |
4545 *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | | 4524 *state |= ((((SYS_UWORD32) uart->rts_level) << RTS) | |
4546 | 4525 |
4547 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 4526 #if TARGET_HAS_DTR_INPUT |
4548 (((SYS_UWORD32) uart->dtr_level) << DTR) | | 4527 (((SYS_UWORD32) uart->dtr_level) << DTR) | |
4549 #endif | 4528 #endif |
4550 | 4529 |
4551 (((SYS_UWORD32) (uart->tx_stopped_by_application | | 4530 (((SYS_UWORD32) (uart->tx_stopped_by_application | |
4552 uart->tx_stopped_by_driver)) << TXSTP) | | 4531 uart->tx_stopped_by_driver)) << TXSTP) | |
4566 * X 0 RTS XON:0 XOFF:1 (transmitter) | 4545 * X 0 RTS XON:0 XOFF:1 (transmitter) |
4567 * | 4546 * |
4568 * DTR is supported on C, D & E-Sample. | 4547 * DTR is supported on C, D & E-Sample. |
4569 */ | 4548 */ |
4570 | 4549 |
4571 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 4550 #if TARGET_HAS_DTR_INPUT |
4572 *state |= (((SYS_UWORD32) uart->dtr_level) << SA); | 4551 *state |= (((SYS_UWORD32) uart->dtr_level) << SA); |
4573 #endif | 4552 #endif |
4574 | 4553 |
4575 if (uart->flow_control_mode != fc_rts) | 4554 if (uart->flow_control_mode != fc_rts) |
4576 *state |= (((SYS_UWORD32) uart->rts_level) << SB); | 4555 *state |= (((SYS_UWORD32) uart->rts_level) << SB); |
4881 | 4860 |
4882 switch (interrupt_status) { | 4861 switch (interrupt_status) { |
4883 | 4862 |
4884 case RX_DATA: | 4863 case RX_DATA: |
4885 | 4864 |
4886 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (CHIPSET == 12)) | 4865 #if TARGET_HAS_DTR_INPUT |
4887 uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */ | 4866 uart->index_it = (uart->index_it + 1) & 0x01; /* 0 or 1 */ |
4888 uart->dtr_change_detected[uart->index_it] = 0; | 4867 uart->dtr_change_detected[uart->index_it] = 0; |
4889 uart->dtr_level_saved[uart->index_it] = uart->dtr_level; | 4868 uart->dtr_level_saved[uart->index_it] = uart->dtr_level; |
4890 #endif | 4869 #endif |
4891 read_rx_fifo (uart); | 4870 read_rx_fifo (uart); |
4992 if (uartNo != UAF_UART_1) | 4971 if (uartNo != UAF_UART_1) |
4993 return (FD_NOT_SUPPORTED); | 4972 return (FD_NOT_SUPPORTED); |
4994 | 4973 |
4995 /* | 4974 /* |
4996 * There is no case where FD_INTERNAL_ERR may be returned. | 4975 * There is no case where FD_INTERNAL_ERR may be returned. |
4997 */ | 4976 */ |
4998 | 4977 |
4999 result = FD_OK; | 4978 result = FD_OK; |
5000 | 4979 |
5001 uart = &uart_parameters; | 4980 uart = &uart_parameters; |
5002 status = READ_UART_REGISTER (uart, LSR); | 4981 status = READ_UART_REGISTER (uart, LSR); |
5015 result = FD_NOT_READY; | 4994 result = FD_NOT_READY; |
5016 | 4995 |
5017 return (result); | 4996 return (result); |
5018 } | 4997 } |
5019 | 4998 |
5020 #if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41)) | 4999 #if TARGET_HAS_DTR_INPUT |
5021 /******************************************************************************* | 5000 /******************************************************************************* |
5022 * | 5001 * |
5023 * UAF_DTRInterruptHandler | 5002 * UAF_DTRInterruptHandler |
5024 * | 5003 * |
5025 * Purpose : This function is only used on C & D-Sample. On this platform, the | 5004 * Purpose : This function is only used on C & D-Sample. On this platform, the |
5165 */ | 5144 */ |
5166 | 5145 |
5167 return (FD_OK); | 5146 return (FD_OK); |
5168 } | 5147 } |
5169 #endif /* (defined BTEMOBILE && (CHIPSET != 12)) */ | 5148 #endif /* (defined BTEMOBILE && (CHIPSET != 12)) */ |
5170 | |
5171 |