FreeCalypso > hg > freecalypso-sw
comparison target-utils/pirexplore/lcd.c @ 77:fcbe1332b197
pirexplore: LCD init and BL control work now
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
---|---|
date | Thu, 01 Aug 2013 00:57:49 +0000 |
parents | 07b686248ab7 |
children | 2c266d4339ff |
comparison
equal
deleted
inserted
replaced
76:07b686248ab7 | 77:fcbe1332b197 |
---|---|
55 fb_spca_write(0x06, 0xff); | 55 fb_spca_write(0x06, 0xff); |
56 fb_spca_write(0x7f, 0x09); | 56 fb_spca_write(0x7f, 0x09); |
57 fb_spca_write(0x19, 0x08); /* backlight: 0x08 is on, 0x0c is off */ | 57 fb_spca_write(0x19, 0x08); /* backlight: 0x08 is on, 0x0c is off */ |
58 fb_spca_write(0x23, 0x18); | 58 fb_spca_write(0x23, 0x18); |
59 } | 59 } |
60 | |
61 enum s6b33b1x_cmdflag { CMD, DATA, END }; | |
62 | |
63 struct s6b33b1x_cmdlist { | |
64 enum s6b33b1x_cmdflag is_cmd:8; /* 1: is a command, 0: is data, 2: end marker! */ | |
65 u_char data; /* 8 bit to send to LC display */ | |
66 }; | |
67 | |
68 static const struct s6b33b1x_cmdlist | |
69 s6b33b1x_initdata[] = { | |
70 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */ | |
71 { DATA, 0x00 }, /* DATA: everything off */ | |
72 { CMD, 0x02 }, /* CMD Oscillation Mode Set */ | |
73 { DATA, 0x00 }, /* DATA: oscillator off */ | |
74 { CMD, 0x2c }, /* CMD Standby Mode off */ | |
75 { CMD, 0x50 }, /* CMD Display off */ | |
76 { CMD, 0x02 }, /* CMD Oscillation Mode Set */ | |
77 { DATA, 0x01 }, /* DATA: oscillator on */ | |
78 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */ | |
79 { DATA, 0x01 }, /* DATA: Booster 1 on */ | |
80 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */ | |
81 { DATA, 0x09 }, /* DATA: Booster 1 on, OP-AMP on */ | |
82 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */ | |
83 { DATA, 0x0b }, /* DATA: Booster 1 + 2 on, OP-AMP on */ | |
84 { CMD, 0x26 }, /* CMD DCDC and AMP ON/OFF set */ | |
85 { DATA, 0x0f }, /* DATA: Booster 1 + 2 + 3 on, OP-AMP on */ | |
86 { CMD, 0x20 }, /* CMD DC-DC Select */ | |
87 { DATA, 0x01 }, /* DATA: step up x1.5 */ | |
88 { CMD, 0x24 }, /* CMD DCDC Clock Division Set */ | |
89 { DATA, 0x0a }, /* DATA: fPCK = fOSC/6 */ | |
90 { CMD, 0x2a }, /* CMD Contrast Control */ | |
91 { DATA, 0x2d }, /* DATA: default contrast */ | |
92 { CMD, 0x30 }, /* CMD Adressing mode set */ | |
93 { DATA, 0x0b }, /* DATA: 65536 color mode */ | |
94 { CMD, 0x10 }, /* CMD Driver output mode set */ | |
95 { DATA, 0x03 }, /* DATA: Display duty: 1/132 */ | |
96 { CMD, 0x34 }, /* CMD N-line inversion set */ | |
97 { DATA, 0x88 }, /* DATA: inversion on, one frame, every 8 blocks */ | |
98 { CMD, 0x40 }, /* CMD Entry mode set */ | |
99 { DATA, 0x00 }, /* DATA: Y address counter mode */ | |
100 { CMD, 0x28 }, /* CMD Temperature Compensation set */ | |
101 { DATA, 0x01 }, /* DATA: slope -0.05%/degC */ | |
102 { CMD, 0x32 }, /* CMD ROW vector mode set */ | |
103 { DATA, 0x01 }, /* DATA: every 2 subgroup */ | |
104 { CMD, 0x51 }, /* CMD Display on */ | |
105 { END, 0x00 }, /* MARKER: end of list */ | |
106 }; | |
107 | |
108 static void | |
109 fb_s6b33b1x_send_cmdlist(p) | |
110 struct s6b33b1x_cmdlist *p; | |
111 { | |
112 while(p->is_cmd != END) { | |
113 nCS4_ADDR0 = p->data; | |
114 p++; | |
115 } | |
116 } | |
117 | |
118 void | |
119 cmd_lcdinit() | |
120 { | |
121 GPIO_OUT_REG |= 0x0080; | |
122 fb_s6b33b1x_send_cmdlist(s6b33b1x_initdata); | |
123 } |