FreeCalypso > hg > freecalypso-sw
diff nuc-fw/nucleus/tct.S @ 132:2c5160a9d652
nuc-fw: switched from nucdemo to Riviera, got some serial output
author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
---|---|
date | Sat, 02 Nov 2013 01:48:11 +0000 |
parents | 947b1f473960 |
children |
line wrap: on
line diff
--- a/nuc-fw/nucleus/tct.S Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/nucleus/tct.S Sat Nov 02 01:48:11 2013 +0000 @@ -2291,8 +2291,11 @@ @ Nested interrupt. Save complete context on the current stack. TCT_Nested_Save: +/* No longer needed in the FreeCalypso version, as we can use r0 instead. */ +#if 0 @ 1. Save another register on the exception stack so we have enough to work with STMDB r13!,{r5} +#endif @ 2. Save the necessary exception registers into r1-r3 MOV r1,r13 @ Put the exception r13 into r1 @@ -2301,49 +2304,59 @@ MRS r3,spsr @ Put the exception spsr into r3 @ 3. Adjust the exception stack pointer for future exceptions - ADD r13,r13,#24 @ r13 will point to enable reg value when done + ADD r13,r13,#20 @ r13 reset to pre-interrupt value @ 4. Switch CPU modes to save context on system stack - MRS r5,CPSR @ Pickup the current CPSR - BIC r5,r5,#MODE_MASK @ Clear the mode bits + MRS r0,CPSR @ Pickup the current CPSR + BIC r0,r0,#MODE_MASK @ Clear the mode bits - ORR r5,r5,#SUP_MODE @ Change to supervisor mode (SVD) + ORR r0,r0,#SUP_MODE @ Change to supervisor mode (SVD) - MSR CPSR,r5 @ Switch modes (IRQ->SVC) + MSR CPSR,r0 @ Switch modes (IRQ->SVC) @ 5. Store the SVC r13 into r5 so the r13 can be saved as is. - MOV r5,r13 +@ FreeCalyspo: using r0 instead + MOV r0,r13 @ 6. Save the exception return address on the stack (r15). - STMDB r5!,{r4} - -@ 7. Save r6-r14 on stack - STMDB r5!,{r6-r14} + STMDB r0!,{r4} + +@ 7. Save r5-r14 on stack (used to be r6-r14) + STMDB r0!,{r5-r14} @ 8. Switch back to using r13 now that the original r13 has been saved. - MOV r13,r5 - + MOV r13,r0 + +/* no longer relevant */ +#if 0 @ 9. Get r5 and exception enable registers off of exception stack and @ save r5 (stored in r4) back to the system stack. LDMIA r1!,{r4-r5} STMDB r13!,{r4} MOV r4,r5 @ Put exception enable value into r4 +#endif @ 10. Get the rest of the registers off the exception stack and @ save them onto the system stack. LDMIA r1!,{r5-r8,r11} @ Get r0-r4 off exception stack STMDB r13!,{r5-r8,r11} @ Put r0-r4 on system stack +/* no longer relevant */ +#if 0 @ 11. Store the exception enable value back on the exception stack. STMDB r1,{r4} +#endif @ 12. Save the SPSR on the system stack (CPSR) STMDB r13!,{r3} +/* TI's approach to interrupt handling does not support re-enabling here */ +#if 0 @ 13. Re-enable interrupts MRS r1,CPSR BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) MSR CPSR,r1 +#endif BX r2 @ Return to calling ISR @ } @@ -2364,8 +2377,11 @@ @ Yes, a thread was interrupted. Save complete context on the @ thread's stack. +/* No longer needed in the FreeCalypso version, as we can use r0 instead. */ +#if 0 @ 1. Save another register on the exception stack so we have enough to work with STMDB r13!,{r5} +#endif @ 2. Save the necessary exception registers into r1-r3 MOV r1,r13 @ Put the exception r13 into r1 @@ -2374,41 +2390,48 @@ MRS r3,spsr @ Put the exception spsr into r3 @ 3. Adjust the exception stack pointer for future exceptions - ADD r13,r13,#24 @ r13 will point to enable reg value when done + ADD r13,r13,#20 @ r13 reset to pre-interrupt value @ 4. Switch CPU modes to save context on system stack - MRS r5,CPSR @ Pickup the current CPSR - BIC r5,r5,#MODE_MASK @ Clear the mode bits + MRS r0,CPSR @ Pickup the current CPSR + BIC r0,r0,#MODE_MASK @ Clear the mode bits - ORR r5,r5,#SUP_MODE @ Change to supervisor mode (SVD) + ORR r0,r0,#SUP_MODE @ Change to supervisor mode (SVD) - MSR CPSR,r5 @ Switch modes (IRQ->SVC) + MSR CPSR,r0 @ Switch modes (IRQ->SVC) @ 5. Store the SVC r13 into r5 so the r13 can be saved as is. - MOV r5,r13 +@ FreeCalyspo: using r0 instead + MOV r0,r13 @ 6. Save the exception return address on the stack (r15). - STMDB r5!,{r4} - -@ 7. Save r6-r14 on stack - STMDB r5!,{r6-r14} + STMDB r0!,{r4} + +@ 7. Save r5-r14 on stack (used to be r6-r14) + STMDB r0!,{r5-r14} @ 8. Switch back to using r13 now that the original r13 has been saved. - MOV r13,r5 - + MOV r13,r0 + +/* no longer relevant */ +#if 0 @ 9. Get r5 and exception enable registers off of exception stack and @ save r5 (stored in r4) back to the system stack. LDMIA r1!,{r4-r5} STMDB r13!,{r4} MOV r4,r5 @ Put exception enable value into r4 +#endif @ 10. Get the rest of the registers off the exception stack and @ save them onto the system stack. LDMIA r1!,{r5-r8,r11} @ Get r0-r4 off exception stack STMDB r13!,{r5-r8,r11} @ Put r0-r4 on system stack +/* no longer relevant */ +#if 0 @ 11. Store the exception enable value back on the exception stack. STMDB r1,{r4} +#endif @ 12. Save the SPSR on the system stack (CPSR) STMDB r13!,{r3} @@ -2433,10 +2456,13 @@ LDR r13,[r1, #0] @ Switch to system stack LDR r10,[r3, #0] @ Setup system stack limit +/* TI's approach to interrupt handling does not support re-enabling here */ +#if 0 @ Re-enable interrupts MRS r1,CPSR BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) MSR CPSR,r1 +#endif @ Return to caller ISR. @@ -2447,13 +2473,13 @@ TCT_Idle_Context_Save: MOV r2,r14 @ Save r14 in r2 - LDR r3,[r13] @ Get exception enable value from stack +@ LDR r3,[r13] @ Get exception enable value from stack ADD r13,r13,#20 @ Adjust exception r13 for future interrupts - STR r3,[r13] @ Put exception enable value back on stack +@ STR r3,[r13] @ Put exception enable value back on stack MRS r1,CPSR @ Pickup current CPSR BIC r1,r1,#MODE_MASK @ Clear the current mode - BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) @ Re-enable interrupts +@ BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) @ Re-enable interrupts ORR r1,r1,#SUP_MODE @ Prepare to switch to supervisor @ mode (SVC) @@ -2963,3 +2989,10 @@ B TCT_Schedule @ Return to main scheduling loop @} + +/* FreeCalypso addition, used by riviera/rvf/rvf_task.c: */ + .globl INT_Check_IRQ_Mask +INT_Check_IRQ_Mask: + MRS r0,CPSR + BX lr +