view gsm-fw/finlink/ld-script.src @ 586:25a3095e8a98

L1: dsp subdir added to the build
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Fri, 15 Aug 2014 22:29:30 +0000
parents 2a26785fb5a2
children aa93994e9f63
line wrap: on
line source

dnl This ld script source is fed through m4 in order to fill in
dnl those settings which depend on the configuration.
dnl Memory region sizes are set in ../include/config.m4, generated
dnl by the configuration mechanism based on the selected target,
dnl and the Makefile prepends flash.m4 or xram.m4 to select the
dnl type of image we are linking: either the regular flashable image,
dnl or a RAM-only test image (to be loaded via fc-xram) that does not
dnl touch the flash and pretends as if the flash doesn't even exist.

/*
 * FreeCalypso ld script for the Buildmem build
 */

ENTRY(ifelse(Buildmem,XRAM,_FlashorXram_entry,0))

include(`../include/config.m4')dnl
MEMORY {
ifelse(Buildmem,FLASH,
`	FLASH_OVERLAY : ORIGIN = 0, LENGTH = 0x2000
	FLASH : ORIGIN = 0x2000,    LENGTH = CONFIG_FWFLASH_SIZE - 0x2000')
	IRAM : ORIGIN = 0x00800000, LENGTH = CONFIG_IRAM_SIZE
	XRAM : ORIGIN = 0x01000000, LENGTH = CONFIG_XRAM_SIZE
}
ifelse(FFS_IN_RAM,1,`
RAMFFS_BLKSIZE_BYTES = 1 << RAMFFS_BLKSIZE_LOG2;
RAMFFS_TOTAL_SIZE = RAMFFS_BLKSIZE_BYTES * RAMFFS_NBLOCKS;
')dnl

SECTIONS {
	/* XIP code, going into flash or XRAM emulating flash */
	xip.text : {
		*(xip.text*)
		xipcode.o(.text*)
		*libplus.xip.a:(.text*)
		*libgpf.xip.a:(.text*)
		*librv.a:(.text*)
		*libsprintf.a:(.text*)
		/* let's put the ARM->Thumb veneers in the XIP section */
		*(.glue_7)
	} > Buildmem

	/* copy-to-IRAM code */
	iram.text 0x80001C : {
		/* the 7 exception and interrupt vectors @ 0x80001C */
		*(iram.vectors)
		*(iram.text*)
		iramcode.o(.text*)
		*libplus.iram.a:(.text*)
		*libgpf.iram.a:(.text*)
		*libc.a:(.text*)
		*libgcc.a:(.text*)
	} > IRAM AT> Buildmem
	__iramtext_ram_addr = ADDR(iram.text);
	__iramtext_flash_addr = LOADADDR(iram.text);
	__iramtext_size = SIZEOF(iram.text);

	/* all .rodata will stay in flash */
	.rodata : {
		*(.rodata*)
	} > Buildmem

	/*
	 * All .data will go into XRAM.
	 * For the flash build we'll have a step that copies
	 * the .data section from flash to XRAM; for the RAM-only
	 * build it goes directly into XRAM and stays there.
	 */
	.data : {
		*(.data*)
	} > XRAM AT> Buildmem
ifelse(Buildmem,FLASH,
`	__initdata_ram_addr = ADDR(.data);
	__initdata_flash_addr = LOADADDR(.data);
	__initdata_size = SIZEOF(.data);
')dnl

	/* we have two kinds of BSS: internal and external */
	int.bss (NOLOAD) : {
		*(int.bss*)
		iramcode.o(.bss* COMMON)
		*libplus.iram.a:(.bss* COMMON)
		*libgpf.iram.a:(.bss* COMMON)
		*libc.a:(.bss* COMMON)
		*libgcc.a:(.bss* COMMON)
		. = ALIGN(4);
	} > IRAM
	__intbss_start = ADDR(int.bss);
	__intbss_size = SIZEOF(int.bss);

	ext.bss (NOLOAD) : {
		*(ext.bss*)
		xipcode.o(.bss* COMMON)
		*libplus.xip.a:(.bss* COMMON)
		*libgpf.xip.a:(.bss* COMMON)
		*librv.a:(.bss* COMMON)
		*libsprintf.a:(.bss* COMMON)
		. = ALIGN(4);
	} > XRAM
	__extbss_start = ADDR(ext.bss);
	__extbss_size = SIZEOF(ext.bss);

	/* finally, we have "raw RAM": like BSS, but we don't zero it out */
	int.ram (NOLOAD) : {
		*(int.ram*)
		*(system_stack)
		*(irq_stack)
		*(fiq_stack)
		*(timer_hisr_stack)
		. = ALIGN(4);
		_iram_end = .;
	} > IRAM

	ext.ram (NOLOAD) : {
		*(ext.ram*)
		*(except_stack)
		. = ALIGN(4);
ifelse(FFS_IN_RAM,1,
`		_RAMFFS_area = .;
		. += RAMFFS_TOTAL_SIZE;
')dnl
		_xram_end = .;
	} > XRAM
}