FreeCalypso > hg > freecalypso-sw
view gsm-fw/sysglue/flashboot.S @ 838:a963ff26848a
gdi/ffs_coat.c: added boilerplate includes just in case
author | Space Falcon <falcon@ivan.Harhan.ORG> |
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date | Sat, 25 Apr 2015 19:27:04 +0000 |
parents | 06ecb305f650 |
children | a8fc7526935e |
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/* * This assembly module contains those bits which are specific to flashable * image builds only. It puts bits of code into several different sections. */ #include "../include/config.h" #if FLASH_BOOT_VIA_BOOTROM /* * Put something sensible in the boot ROM overlay area, just for the * heck of it, or for extra robustness. */ .section bootrom.overlay,"ax",%progbits .code 32 .org 0 b BootROM_disabled_entry #include "vectors.S" BootROM_disabled_entry: /* copy the boot ROM switch code to IRAM and jump to it */ ldr r4, =__romswitch_flash_addr ldr r5, =__romswitch_ram_addr ldr r2, =__romswitch_size 1: ldr r0, [r4], #4 str r0, [r5], #4 subs r2, r2, #4 bhi 1b ldr pc, =__romswitch_ram_addr .section bootrom.switch,"ax",%progbits .code 32 .org 0 @ enable the Calypso boot ROM ldr r1, =0xFFFFFB10 mov r2, #0x0100 strh r2, [r1] @ jump to it! mov pc, #0 #endif .section flashboot.text,"ax",%progbits .code 32 .org 0 #if FLASH_BOOT_VIA_BOOTROM /* sane targets with Calypso boot ROM enabled by the PCB wiring */ /* provide the necessary magic words for the boot ROM */ .word 0 .word _Flash_boot_entry #elif CONFIG_TARGET_C139 /* * On this target we are going to put a special flash boot stage at 0x2000, * and then the actual gsm-fw image at the flash erase block boundary * at 0x10000. The following bits will be read by our intermediate * flash boot stage. */ .asciz "FreeCalypso" .word _Flash_boot_entry #elif CONFIG_TARGET_C155 /* * On this target the hand-off point between the bootloader and the main * fw image coincides with a flash erase block boundary, thus no need * for an intermediate flash boot stage. The following bits will appear * at 0x20000. */ .asciz "FreeCalypso firmware for C155/156 target" .org 0xE0 /* C155/156 bootloader jumps here */ b _Flash_boot_entry #include "vectors.S" #else #error "Unsupported flash boot configuration" #endif .globl _Flash_boot_entry _Flash_boot_entry: /* first order of business: configure flash and XRAM access */ ldr r2, =0xFFFFFB00 #if CONFIG_TARGET_PIRELLI mov r0, #0x00A4 strh r0, [r2, #0] strh r0, [r2, #2] strh r0, [r2, #6] #else mov r0, #0x00A3 strh r0, [r2, #0] strh r0, [r2, #2] #endif /* * On targets with 8 MiB flash (or XRAM) banks we need to switch the * CS4/ADD22 pin to the ADD22 function. We could do it for all targets * (not aware of any that need the pin to be CS4), but we strongly * prefer to have a consistent execution environment between flashImage * and ramImage, so let's only do this setting on those targets * on which we do it in ../../loadtools/scripts/*.init (for fc-xram). */ #if CONFIG_TARGET_PIRELLI || CONFIG_TARGET_C155 ldr r1, =0xFFFEF006 mov r2, #0x0008 strh r2, [r1] #endif /* we now have full access to all flash and RAM on the device */ /* copy iram.text to where it's supposed to be */ ldr r8, =__iramtext_flash_addr ldr r9, =__iramtext_ram_addr ldr r10, =__iramtext_size 1: ldmia r8!, {r0-r7} stmia r9!, {r0-r7} subs r10, r10, #0x20 bhi 1b /* likewise copy .data from flash to XRAM */ ldr r8, =__initdata_flash_addr ldr r9, =__initdata_ram_addr ldr r10, =__initdata_size 1: ldmia r8!, {r0-r7} stmia r9!, {r0-r7} subs r10, r10, #0x20 bhi 1b /* boot path joins with fc-xram loadable builds */ b _FlashorXram_entry