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rvinterf/asyncshell/rxctl.c: buglet in the implementation of dis/enable commands
author Space Falcon <falcon@ivan.Harhan.ORG>
date Sat, 30 May 2015 07:50:05 +0000
parents 7cf154cd3891
children
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/*
 * These 7 branch instructions, corresponding to ARM exception and interrupt
 * vectors, will be placed in different sections depending on the flashImage
 * vs. ramImage configuration and which target we build for; this little
 * snippet file will be #included where it is needed.
 */

	b	_arm_undefined
	b	_arm_swi
	b	_arm_abort_prefetch
	b	_arm_abort_data
	b	_arm_reserved
	b	_INT_IRQ
	b	_INT_FIQ