# HG changeset patch
# User Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
# Date 1382848984 0
# Node ID 1e41550feec5a904c29ebad24beefc5bcc7fbe67
# Parent  17b0511b243c4635202a6d1901fc5db6d5aebd0a
nuc-fw: Init_Target() reconstructed

diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_api_hisr.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_api_hisr.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,20 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_API_HISR.H
+ *
+ *        Filename l1_api_hisr.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+#ifndef _L1_API_HISR_H_
+#define _L1_API_HISR_H_
+
+/* Constants */
+#define ID_API_INT		0x4
+
+/* Prototypes */
+void l1_trigger_api_interrupt();
+void l1_api_handler();
+
+#endif
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_confg.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_confg.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,983 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software
+ * L1_CONFG.H
+ *
+ *        Filename l1_confg.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+#ifndef __L1_CONFG_H__
+#define __L1_CONFG_H__
+
+// Traces...
+// TRACE_TYPE == 1,2,3 are used in standalone mode (L2-L3 Simul) with USART
+// TRACE_TYPE == 4 is used on A-sample only (with UART): L1 + protocol stack
+// TRACE_TYPE == 1 -> L1/L3 interface trace
+// TRACE_TYPE == 2 -> Trace mode: ~33~~1~011...
+// TRACE_TYPE == 3 -> same as above (2) plus FER or stats trace
+// TRACE_TYPE == 4 -> L1/L3 interface trace on A-sample with protocol stack
+// TRACE_TYPE == 5 -> trace for full simulation
+// TRACE_TYPE == 6 -> CPU load trace for hisr
+// TRACE_TYPE == 7 -> CPU LOAD trace for layer 1 hisr for all TDMA. Output on
+//                    UART at 38400 bps =>
+//                    format : <hisr cpu value in microseconds> <frame number>
+
+// Code PB reported workaround
+//------------------------------
+
+
+// Code Version possible choices
+//------------------------------
+#define SIMULATION     1
+#define NOT_SIMULATION 2
+
+// RCL functions Version possible choices
+//------------------------------
+#define       POLL_FORCED     0
+#define       RLC_SCENARIO    1
+#define       MODEM_FLOW      2
+
+// possible choices for UART trace output
+//------------------------------
+#define       MODEM_UART     0
+#define       IRDA_UART      1
+#if (CHIPSET == 12)
+  #define     MODEM2_UART    2
+#endif
+
+//============
+// CODE CHOICE
+//============
+#if 0
+#if (OP_L1_STANDALONE==0)
+#define CODE_VERSION NOT_SIMULATION
+#else // OP_L1_STANDALONE
+#ifdef WIN32
+#define CODE_VERSION  SIMULATION
+#else // WIN32
+#define CODE_VERSION  NOT_SIMULATION
+#endif // WIN32
+#endif // OP_L1_STANDALONE
+#endif // #if 0
+
+/* FreeCalypso */
+#define	CODE_VERSION	NOT_SIMULATION
+#define	AMR		1
+#define	L1_12NEIGH	1
+#define	L1_EOTD		0
+#define	L1_GTT		0
+#define	MELODY_E2	1
+#define	TESTMODE	1
+
+#if CONFIG_GPRS
+#  define L1_GPRS	1
+#else
+#  define L1_GPRS	0
+#endif
+
+//---------------------------------------------------------------------------------
+// Test with full simulation.
+//---------------------------------------------------------------------------------
+#if (CODE_VERSION == SIMULATION)
+
+  // Test Scenari...
+  #define SCENARIO_FILE          1  // Test Scenario comes from input files.
+  #define SCENARIO_MEM           0  // Test Scenario comes from RAM.
+
+  // Traces...
+  #undef TRACE_TYPE
+  #define TRACE_TYPE             5
+  #define LOGFILE_TRACE          1  // trace in an output logfile
+  #define FLOWCHART              0  // Message sequence/flow chart trace.
+  #define NUCLEUS_TRACE          0  // Nucleus error trace
+  #define EOTD_TRACE             1  // EOTD log trace
+  #define TRACE_FULL_NAME        0  // display full fct names after a PM/COM error
+
+  #define L2_L3_SIMUL            1  // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
+
+  // Control algorithms...
+  #define AFC_ALGO               1  // AFC algorithm.
+  #define TOA_ALGO               1  // TOA algorithm.
+  #define AGC_ALGO               1  // AGC algorithm.
+  #define TA_ALGO                0  // TA (Timing Advance) algorithm.
+  #undef VCXO_ALGO
+  #define VCXO_ALGO              0  // VCXO algo
+  #undef DCO_ALGO
+  #define DCO_ALGO               0  // DCO algo (TIDE)
+  #undef ORDER2_TX_TEMP_CAL
+  #define ORDER2_TX_TEMP_CAL     0  // TX Temperature Compensation Algorithm selection
+
+
+  #define FACCH_TEST             0  // FACCH test enabled.
+
+  #define ADC_TIMER_ON           0  // Timer for ADC measurements
+  #define AFC_ON                 1  // Enable of the Omega AFC module
+
+  #define AUDIO_TASK             1  // Enable the L1 audio features
+  #define AUDIO_SIMULATION       1  // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
+  #define AUDIO_L1_STANDALONE    0  // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
+
+  #define GTT_SIMULATION         1  // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
+  #define TTY_SYNC_MCU           1  // TTY WORKAROUND BUG03401
+  #define TTY_SYNC_MCU_2         1  // 
+  #define L1_GTT_FIFO_TEST_ATOMIC 0 //
+  #define NEW_WKA_PATCH          0
+  #define OPTIMISED              1
+
+  #define L1_RECOVERY            0  // L1 recovery
+
+  #undef L1_GPRS
+  #define L1_GPRS                1  // GPRS L1: MS supporting both Circuit Switched and Packet (GPRS) capabilities
+
+  #undef AMR
+  #define AMR                    1  // AMR version 1.0 supported
+
+  #undef L1_12NEIGH
+  #define L1_12NEIGH             1  // new L1-RR interface for 12 neighbour cells
+
+  #undef L1_GTT
+  #define L1_GTT                 1  // Enable Global Text Telephony feature for simulation
+
+  #undef  OP_L1_STANDALONE
+  #define OP_L1_STANDALONE       1  // Selection of code for L1 stand alone
+
+  #undef  OP_RIV_AUDIO
+  #define OP_RIV_AUDIO           0  // Selection of code for Riviera audio
+
+  #undef OP_WCP
+  #define OP_WCP                 0  // No WCP integration
+//---------------------------------------------------------------------------------
+// Test with H/W platform.
+//---------------------------------------------------------------------------------
+#elif (CODE_VERSION == NOT_SIMULATION)
+
+  #define WA_PCTM_AGC_PARAMS 0 // to work by default with 4 parameters to calibration (compatible with PCTM if 1) 
+  // Work around about Calypso RevA: the bus is floating (Cf PB01435)
+  // (corrected with Calypso ReV B and Calypso C035)
+  #if (CHIPSET == 7)
+    #define W_A_CALYPSO_BUG_01435 1
+  #else
+    #define W_A_CALYPSO_BUG_01435 0
+  #endif
+
+
+  // for AMR thresolds definition CQ22226
+  #define AMR_THRESHOLDS_WORKAROUND 1
+
+  #if (L1_GTT==1)
+    #define TTY_SYNC_MCU 1
+    #define TTY_SYNC_MCU_2 1
+    #define L1_GTT_FIFO_TEST_ATOMIC 0
+    #define NEW_WKA_PATCH          0
+    #define OPTIMISED              1
+  #else
+    #define TTY_SYNC_MCU_2 0
+    #define L1_GTT_FIFO_TEST_ATOMIC 0
+    #define TTY_SYNC_MCU 0
+    #define NEW_WKA_PATCH          0
+    #define OPTIMISED              0
+
+  #endif
+ 
+  // Traces...
+  #define NUCLEUS_TRACE        0  // Nucleus error trace
+  #define FLOWCHART            0  // Message sequence/flow chart trace.
+  #define LOGFILE_TRACE        0  // trace in an output logfile
+  #define TRACE_FULL_NAME      0  // display full fct names after a PM/COM error
+
+  // Test Scenari...
+  #define SCENARIO_FILE          0  // Test Scenario comes from input files.
+  #define SCENARIO_MEM           1  //  // Test Scenario comes from RAM.
+
+  #if (OP_L1_STANDALONE == 1)
+    #define L2_L3_SIMUL            1  // Layer 2 & Layer 3 simulated, main within NU_MAIN.C, trace possible.
+  #else
+    #define L2_L3_SIMUL            0
+  #endif
+
+  // Control algorithms...
+  #define AFC_ALGO               1  // AFC algorithm.
+  //TOA Algorithm needs to be on for TestMode, otherwise no dedic test will be succesful!!!
+  #define TOA_ALGO               1  // TOA algorithm.
+  #define AGC_ALGO               1  // AGC algorithm.
+  #define TA_ALGO                1  // TA (Timing Advance) algorithm.
+
+  #define FACCH_TEST             0  // FACCH test enabled.
+
+  #define ADC_TIMER_ON           0  // Timer for ADC measurements
+  #define AFC_ON                 1  // Enable of the Omega AFC module
+
+  #define AUDIO_TASK             1  // Enable the L1 audio features
+  #define AUDIO_SIMULATION       0  // Audio simulator for the audio tasks (works only with the new audio design i.e. AUDIO_TASK=1)
+  #if (OP_L1_STANDALONE == 1)
+    #define AUDIO_L1_STANDALONE    1  // Flag to enable the audio simulator used with the L1 stand-alone (works only with the new audio design i.e. AUDIO_TASK=1)
+  #else
+    #define AUDIO_L1_STANDALONE    0
+  #endif
+
+  #define GTT_SIMULATION         0  // Gtt simulator for the gtt tasks (works only with if L1_GTT=1)
+
+  #define OP_BT                  0  // Simulation of ISLAND (BLUETOOTH) sleep management 
+
+  #define L1_RECOVERY            1  // L1 recovery
+
+
+  #if (L1_GPRS == 1)
+    #define RLC_VERSION            RLC_SCENARIO
+    #if (RLC_VERSION == RLC_SCENARIO)
+      #define RLC_DL_BLOCK_STAT    0  // Works with RLC_VERSION = RLC_SCENARIO
+                                      // output stat on CRC error blocks
+                                      // The user must enter the cs type and
+                                      // the number of frames desired.
+    #else
+      #define RLC_DL_BLOCK_STAT    0  // Default value; Never change it
+    #endif
+
+    #if (OP_L1_STANDALONE == 1)
+      #define DSP_BACKGROUND_TASKS     1 // Enable the TEST of DSP background.tasks
+                                         // activated by a layer 3 message (BG_TASK_START (<task number>))
+                                         // deactivated by a layer 3 message (BG_TASK_STOP (<task number>))
+                                         // Warning : Works only with DSP>=31
+    #else
+      #define DSP_BACKGROUND_TASKS   0
+    #endif
+
+  #else
+    #define DSP_BACKGROUND_TASKS     0
+    #define RLC_DL_BLOCK_STAT        0  // Default value; Never change it
+  #endif
+#endif
+
+// Audio tasks selection
+//-----------------------
+
+#if (AUDIO_TASK == 1)
+  #define KEYBEEP          1  // Enable keybeep feature
+  #define TONE             1  // Enable tone feature
+  // Temporary modification for protocol stack compatibility - GSMLITE will be removed
+  #if (OP_L1_STANDALONE == 1)
+    #define GSMLITE 1
+  #endif
+  #if ((OP_L1_STANDALONE == 1) || (!GSMLITE))
+    #define MELODY_E1        1  // Enable melody format E1 feature
+    #define VOICE_MEMO       1  // Enable voice memorization feature
+
+    #define FIR              1  // Enable FIR feature
+    #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+      #define AUDIO_MODE       1  // Enable Audio mode feature
+    #else
+      #define AUDIO_MODE        0  // Disable Audio mode feature
+    #endif
+  #else
+    #define MELODY_E1        0  // Disable melody format E1 feature
+    #define VOICE_MEMO       0  // Disable voice memorization feature
+    #if (MELODY_E2)
+	    #define FIR              1  // Enable FIR feature  
+	  #else
+      #define FIR              0  // Disable FIR feature  
+    #endif
+
+    #define AUDIO_MODE       0  // Disable Audio mode feature
+  #endif
+  // Define CPORT for ESample only
+  #if ((CHIPSET == 12) && ((DSP == 35) || (DSP == 36))) 
+    #define L1_CPORT         1  // Enable cport feature
+  #else
+    #define L1_CPORT         0  // Disable cport feature
+  #endif
+
+#else
+  #define KEYBEEP           0  // Enable keybeep feature
+  #define TONE              0  // Enable tone feature
+  #define MELODY_E1         0  // Enable melody format E1 feature
+  #define VOICE_MEMO        0  // Enable voice memorization feature
+
+  #define FIR               0  // Enable FIR feature
+  #define AUDIO_MODE        0  // Enable Audio mode feature
+  #define L1_CPORT          0  // Enable cport feature
+#endif
+
+#define L1_AUDIO_BACKGROUND_TASK (SPEECH_RECO | MELODY_E2) // audio background task is used by speech reco and melody_e2
+#if (OP_RIV_AUDIO == 1)
+  #define L1_AUDIO_DRIVER L1_VOICE_MEMO_AMR // Riviera audio driver (only Voice Memo AMR is available)
+#endif
+
+
+// Vocoder selections
+//-------------------
+
+#define FR        1            // Full Rate
+#define FR_HR     2            // Full Rate + Half Rate
+#define FR_EFR    3            // Full Rate + Enhanced Full Rate
+#define FR_HR_EFR 4            // Full Rate + Half Rate + Enhanced Full Rate
+
+// Standard (frequency plan) selections
+//-------------------------------------
+
+#define GSM             1            // GSM900.
+#define GSM_E           2            // GSM900 Extended.
+#define PCS1900         3            // PCS1900.
+#define DCS1800         4            // DCS1800.
+#define DUAL            5            // Dual Band (GSM900 + DCS 1800 bands)
+#define DUALEXT         6            // Dual Band (E-GSM900 + DCS 1800 bands)
+#define GSM850          7            // GSM850 Band
+#define DUAL_US         8            // PCS1900 + GSM850
+
+/*------------------------------------*/
+/* Power Management                   */
+/*------------------------------------*/
+#define PWR_MNGT  1            // POWER management active if l1_config.pwr_mngt=1
+
+
+/*---------------------------------------------------------------------------*/
+/* DSP configurations                                                        */
+/* ------------------                                                        */
+/*  DSP      | FR| HR|EFR|14.4| SPEED   |12LA68|12LA68 |4L32|AEC| MCU/DSP    */
+/* (version) |   |   |   |    |         |POLE80|POLE112|    |/NS| interface  */
+/* ----------+---+---+---+----+---------+------+-------+----+---+----------  */
+/*  0 (821)  | x |   |   |    | 39Mhz   |  x   |       |    |   | 1          */
+/* ----------+---+---+---+----+---------+------+-------+----+---+----------  */
+/*  1 (830)  | x |   |   |    | 39Mhz   | (1)  |       | x  |   | 1          */
+/* ----------+---+---+---+----+---------+------+-------+----+---+----------  */
+/*  2 (912)  | x | x |   |    | 58.5Mhz |  x   |       |    |   | 2          */
+/* ----------+---+---+---+----+---------+------+-------+----+---+----------  */
+/*  3 (10xx) | x |   | x | x  | 65Mhz   |  x   |       |    | x | 3          */
+/* ----------+---+---+---+----+---------+------+-------+----|---+----------  */
+/*  4 (11xx) | x | x | x | x  | 65Mhz   |  x   |  x (3)|    | x | 3          */
+/* ----------+---+---+---+----+---------+------+-------+----+---+----------  */
+/*  5 (830)  | x |   |   |    | 39Mhz   |  x   |       |    |   | 1          */
+/* ----------+---+---+---+----+---------+------+-------+----+---+----------  */
+/*  6 (11xx) | x | x | x | x  | 65Mhz   |  x   |  x (3)|    |(2)| 3          */
+/* ----------+---+---+---+----+---------+------+-------+----+---+----------  */
+/*                                                                           */
+/*(1) this version can be loaded on a 12LA68/POLE80 but the RIF/DL problem is*/
+/*    not corrected.                                                         */
+/*                                                                           */
+/*(2) AEC is disabled at DSP level but L1 must be compiled with MCU/DSP      */
+/*    interface which support AEC, therefore AEC is defined as 1.            */
+/*                                                                           */
+/*(3) Pole112 include RIF DL correction. No patch is needed if this one only */
+/*    include RIF/DL problem.                                                */
+/*                                                                           */
+/*---------------------------------------------------------------------------*/
+#if   (DSP == 16 || DSP == 17)
+
+/*  #define CLKMOD1    0x414e  // ...
+  #define CLKMOD2    0x414e  // ...65 Mips
+  #define CLKSTART   0x29    // ...65 Mips */
+
+  #define CLKMOD1    0x4006  // ...
+  #define CLKMOD2    0x4116  // ...65 Mips pll free
+  #define CLKSTART   0x29    // ...65 Mips
+
+/*  #define CLKMOD1     0x2116  //This settings force the DSP to never enteridle
+  #define CLKMOD2     0x2116  //In this case the PLL will be always on. 39 Mips
+  #define CLKSTART    0x25    // ...39 Mips */
+
+  #define VOC        FR_HR_EFR // FR + HR + EFR.
+  #define DATA14_4   1         // No 14.4 data allowed.
+  #define AEC        1         // AEC/NS supported.
+  #define MAP        3
+  #define DSP_START  0x2000
+  #define W_A_DSP1   0         // Work Around correcting pb in DSP: SACCH
+
+  #define W_A_DSP_SR_BGD 0    // Work around about the DSP speech reco background task.
+
+  /* DSP debug trace configuration */
+  /*-------------------------------*/
+  #if (MELODY_E2)
+    // In case of the melody E2 the DSP trace must be disable because the
+    // melody instrument waves are overlayed with DSP trace buffer
+
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
+  #else
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
+  #endif
+
+#elif   (DSP == 30)    // First GPRS.
+  #define CLKMOD1    0x4006  // ...
+  #define CLKMOD2    0x4116  // ...65 Mips pll free
+  #define CLKSTART   0x29    // ...65 Mips
+
+  #define VOC        FR_HR_EFR // FR + HR + EFR.
+  #define DATA14_4   1         // No 14.4 data allowed.
+  #define AEC        1         // AEC/NS not supported.
+  #define MAP        3
+  #define DSP_START  0x1F81
+  #define W_A_DSP1   0         // Work Around correcting pb in DSP: SACCH
+  #define ULYSSE      0
+
+  #define W_A_DSP_SR_BGD 0    // Work around about the DSP speech reco background task.
+#elif   (DSP == 31)    // ROM Code GPRS G0.
+  #define CLKMOD1    0x4006  // ...
+  #define CLKMOD2    0x4116  // ...65 Mips pll free
+  #define CLKSTART   0x29    // ...65 Mips
+
+  #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
+  #define DATA14_4   1         // 14.4 data allowed.
+  #define AEC        1         // AEC/NS not supported.
+  #define MAP        3
+
+  #define DSP_START  0x8763
+
+  #define INSTALL_ADD            0x87c9 // Used to set gprs_install_address pointer
+  #define INSTALL_ADD_WITH_PATCH 0x1352 // Used to set gprs_install_address pointer
+
+  #define W_A_DSP1   0         // Work Around correcting pb in DSP: SACCH
+  #define ULYSSE      0
+
+  #define W_A_DSP_SR_BGD 0    // Work around about the DSP speech reco background task.
+#elif   (DSP == 32)    // ROM Code GPRS G1.
+  #define CLKMOD1    0x4006  // ...
+  #define CLKMOD2    0x4116  // ...65 Mips pll free
+  #define CLKSTART   0x29    // ...65 Mips
+
+  #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
+  #define DATA14_4   1         // 14.4 data allowed.
+  #define AEC        1         // AEC/NS not supported.
+  #define MAP        3
+
+  #define DSP_START  0x8763
+
+  #define INSTALL_ADD 0x87c9   // Used to set gprs_install_address pointer
+
+  #define W_A_DSP1   0         // Work Around correcting pb in DSP: SACCH
+  #define ULYSSE      0
+
+  #define W_A_DSP_SR_BGD 0    // Work around about the DSP speech reco background task.
+#elif   (DSP == 33)    // ROM Code GPRS.
+  #define CLKMOD1    0x4006  // ...
+  #define CLKMOD2    0x4116  // ...65 Mips pll free
+  #define CLKSTART   0x29    // ...65 Mips
+  #define C_PLL_CONFIG 0x154   // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
+  #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
+  #define AEC        1         // AEC/NS not supported.
+  #if (OP_RIV_AUDIO == 0)
+    #define L1_NEW_AEC 1
+  #else
+  // Available but not yet tuned with Riviera AUDIO    
+  #define L1_NEW_AEC 0
+  #endif
+  #if ((L1_NEW_AEC) && (!AEC))
+    // First undef the flag to avoid warnings at compilation time
+    #undef AEC
+    #define AEC 1
+  #endif
+
+  #define MAP        3
+
+  #define DSP_START  0x7000
+
+  #define INSTALL_ADD   0x7002 // Used to set gprs_install_address pointer
+
+  #define W_A_DSP1   0         // Work Around correcting pb in DSP: SACCH
+  #define ULYSSE      0
+
+  #define W_A_DSP_SR_BGD 1    // Work around about the DSP speech reco background task.
+
+  #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
+
+    #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
+
+                                // management.
+
+								// DSP_IDLE3 is not supported in simulation
+
+  #else
+    #define W_A_DSP_IDLE3 0
+  #endif
+
+  // DSP software work-around config
+  //  bit0 - Work-around to support CRTG.
+  //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
+  //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
+  //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
+
+  #if    (ANALOG == 1)  // OMEGA / NAUSICA
+    #define C_DSP_SW_WORK_AROUND 0x0006
+
+  #elif  (ANALOG == 2)  // IOTA
+    #define C_DSP_SW_WORK_AROUND 0x000E
+
+  #elif  (ANALOG == 3)  // SYREN
+    #define C_DSP_SW_WORK_AROUND 0x000E
+
+  #endif
+
+  /* DSP debug trace configuration */
+  /*-------------------------------*/
+  #if (MELODY_E2)
+    // In case of the melody E2 the DSP trace must be disable because the
+    // melody instrument waves are overlayed with DSP trace buffer
+
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
+
+    // DSP debug trace type config
+    //             |<-------------- Features -------------->|<---------- Levels ----------->|
+    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
+    #define C_DEBUG_TRACE_TYPE  0x0000  // Level = BASIC; Features = Timer + Buffer Header + Burst.
+
+    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+      #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability
+                                                // Currently not supported !
+    #endif
+  #else
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
+
+    // DSP debug trace type config
+    //             |<-------------- Features -------------->|<---------- Levels ----------->|
+    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
+    #define C_DEBUG_TRACE_TYPE  0x0012  // Level = BASIC; Features = Buffer Header.
+
+    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+    #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
+    #endif
+  #endif
+  /* d_error_status                */
+  /*-------------------------------*/
+
+  #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+    #define D_ERROR_STATUS_TRACE_ENABLE  1    // Enable d_error_status checking capability (supported since patch 2090)
+
+    // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
+    #define DSP_DEBUG_GSM_MASK     0x0000
+    #define DSP_DEBUG_GPRS_MASK    0x0f3d
+  #endif
+
+  #if DCO_ALGO
+    // DCO type of scheduling
+    #define C_CN_DCO_PARAM 0xA248
+  #endif
+
+#elif (DSP == 34)            // ROM Code GPRS AMR.
+  #define CLKMOD1    0x4006  // ...
+  #define CLKMOD2    0x4116  // ...65 Mips pll free
+  #define CLKSTART   0x29    // ...65 Mips
+  #define C_PLL_CONFIG 0x154   // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
+  #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
+  #define AEC        1         // AEC/NS not supported.
+  #if (OP_RIV_AUDIO == 0)
+    #define L1_NEW_AEC 1
+  #else
+  // Available but not yet tuned with Riviera AUDIO    
+    #define L1_NEW_AEC 0
+   #endif
+  #if ((L1_NEW_AEC) && (!AEC))
+    // First undef the flag to avoid warnings at compilation time
+    #undef AEC
+    #define AEC 1
+  #endif
+  #define MAP        3
+
+  #define DSP_START  0x7000
+
+  #define INSTALL_ADD   0x7002 // Used to set gprs_install_address pointer
+
+  #define W_A_DSP1   0         // Work Around correcting pb in DSP: SACCH
+  #define ULYSSE      0
+
+  #define W_A_DSP_SR_BGD 1    // Work around about the DSP speech reco background task.
+
+  #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
+
+    #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
+
+                                // management.
+
+								// DSP_IDLE3 is not supported in simulation
+
+  #else
+    #define W_A_DSP_IDLE3 0
+  #endif
+
+  // DSP software work-around config
+  //  bit0 - Work-around to support CRTG.
+  //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
+  //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
+  //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
+  #if    (ANALOG == 1)  // OMEGA / NAUSICA
+    #define C_DSP_SW_WORK_AROUND 0x0006
+
+  #elif  (ANALOG == 2)  // IOTA
+    #define C_DSP_SW_WORK_AROUND 0x000E
+
+  #elif  (ANALOG == 3)  // SYREN
+    #define C_DSP_SW_WORK_AROUND 0x000E
+
+  #endif
+
+  /* DSP debug trace configuration */
+  /*-------------------------------*/
+  #if (MELODY_E2)
+    // In case of the melody E2 the DSP trace must be disable because the
+    // melody instrument waves are overlayed with DSP trace buffer
+
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
+
+    // DSP debug trace type config
+    //             |<-------------- Features -------------->|<---------- Levels ----------->|
+    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
+    #define C_DEBUG_TRACE_TYPE  0x0000  // Level = BASIC; Features = Timer + Buffer Header + Burst.
+
+    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+      #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability
+                                                // Currently not supported !
+    #endif
+  #else
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
+
+    // DSP debug trace type config
+    //             |<-------------- Features -------------->|<---------- Levels ----------->|
+    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
+    #define C_DEBUG_TRACE_TYPE  0x0012  // Level = BASIC; Features = Buffer Header.
+
+    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+    #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
+    #endif
+
+    // AMR trace
+    #define C_AMR_TRACE_ID 55
+
+  #endif
+  /* d_error_status                */
+  /*-------------------------------*/
+
+  #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+    #define D_ERROR_STATUS_TRACE_ENABLE  1    // Enable d_error_status checking capability (supported since patch 2090)
+
+    // masks to apply on d_error_status bit field
+    #define DSP_DEBUG_GSM_MASK     0x0000
+    #define DSP_DEBUG_GPRS_MASK    0x0f3d
+  #endif
+
+#elif (DSP == 35)            // ROM Code GPRS AMR.
+  #define CLKMOD1    0x4006  // ...
+  #define CLKMOD2    0x4116  // ...65 Mips pll free
+  #define CLKSTART   0x29    // ...65 Mips
+  #define C_PLL_CONFIG 0x154   // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
+  #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
+  #define AEC        1         // AEC/NS not supported.
+  #if (OP_RIV_AUDIO == 0)
+    #define L1_NEW_AEC 1
+  #else
+  // Available but not yet tuned with Riviera AUDIO    
+    #define L1_NEW_AEC 0
+  #endif
+  #if ((L1_NEW_AEC) && (!AEC))
+    // First undef the flag to avoid warnings at compilation time
+    #undef AEC
+    #define AEC 1
+  #endif
+  #define MAP        3
+
+  #define FF_L1_TCH_VOCODER_CONTROL 1
+  #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
+
+  #define DSP_START  0x7000
+
+  #define INSTALL_ADD   0x7002 // Used to set gprs_install_address pointer
+
+  #define W_A_DSP1   0         // Work Around correcting pb in DSP: SACCH
+  #define ULYSSE      0
+
+  #define W_A_DSP_SR_BGD 1    // Work around about the DSP speech reco background task.
+
+  #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
+
+    #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
+
+                                // management.
+
+								// DSP_IDLE3 is not supported in simulation
+
+  #else
+    #define W_A_DSP_IDLE3 0
+  #endif
+
+  // DSP software work-around config
+  //  bit0 - Work-around to support CRTG.
+  //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
+  //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
+  //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
+  #if    (ANALOG == 1)  // OMEGA / NAUSICA
+    #define C_DSP_SW_WORK_AROUND 0x0006
+
+  #elif  (ANALOG == 2)  // IOTA
+    #define C_DSP_SW_WORK_AROUND 0x000E
+
+  #elif  (ANALOG == 3)  // SYREN
+    #define C_DSP_SW_WORK_AROUND 0x000E
+
+  #endif
+
+  /* DSP debug trace configuration */
+  /*-------------------------------*/
+  #if (MELODY_E2)
+    // In case of the melody E2 the DSP trace must be disable because the
+    // melody instrument waves are overlayed with DSP trace buffer
+
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
+
+    // DSP debug trace type config
+    //             |<-------------- Features -------------->|<---------- Levels ----------->|
+    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
+    #define C_DEBUG_TRACE_TYPE  0x0000  // Level = BASIC; Features = Timer + Buffer Header + Burst.
+
+    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+      #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability
+                                                // Currently not supported !
+    #endif
+  #else
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
+
+    // DSP debug trace type config
+    //             |<-------------- Features -------------->|<---------- Levels ----------->|
+    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
+    #define C_DEBUG_TRACE_TYPE  0x0012  // Level = BASIC; Features = Timer + Buffer Header + Burst.
+
+    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+    #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
+    #endif
+
+    // AMR trace
+    #define C_AMR_TRACE_ID 55
+
+  #endif
+  /* d_error_status                */
+  /*-------------------------------*/
+
+  #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+    #define D_ERROR_STATUS_TRACE_ENABLE  1    // Enable d_error_status checking capability (supported since patch 2090)
+
+    // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
+    #define DSP_DEBUG_GSM_MASK     0x08BD
+    #define DSP_DEBUG_GPRS_MASK    0x0f3d
+  #endif
+#elif (DSP == 36)            // ROM Code GPRS AMR.
+  #define CLKMOD1    0x4006  // ...
+  #define CLKMOD2    0x4116  // ...65 Mips pll free
+  #define CLKSTART   0x29    // ...65 Mips
+  #define C_PLL_CONFIG 0x154   // For VTCXO = 13 MHz and max DSP speed = 84.5 Mips
+  #define VOC        FR_HR_EFR // FR + HR + EFR (normaly FR_EFR : PBs).
+  #define AEC        1         // AEC/NS not supported.
+  #if (OP_RIV_AUDIO == 0)
+    #define L1_NEW_AEC 1
+  #else
+  // Available but not yet tuned with Riviera AUDIO    
+    #define L1_NEW_AEC 0
+  #endif
+  #if ((L1_NEW_AEC) && (!AEC))
+    // First undef the flag to avoid warnings at compilation time
+    #undef AEC
+    #define AEC 1
+  #endif
+  #define MAP        3
+  #undef  L1_AMR_NSYNC
+  #define L1_AMR_NSYNC 1
+  #define FF_L1_TCH_VOCODER_CONTROL 1
+  #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 1
+
+  #define DSP_START  0x7000
+
+  #define INSTALL_ADD   0x7002 // Used to set gprs_install_address pointer
+
+  #define W_A_DSP1   0         // Work Around correcting pb in DSP: SACCH
+  #define ULYSSE      0
+
+  #define W_A_DSP_SR_BGD 1    // Work around about the DSP speech reco background task.
+
+  #if ( (CHIPSET != 12) && (CODE_VERSION == NOT_SIMULATION))
+
+    #define W_A_DSP_IDLE3 1     // Work around to report DSP state to the ARM for Deep Sleep
+
+                                // management.
+
+								// DSP_IDLE3 is not supported in simulation
+
+  #else
+    #define W_A_DSP_IDLE3 0
+  #endif
+
+  // DSP software work-around config
+  //  bit0 - Work-around to support CRTG.
+  //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
+  //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
+  //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
+  #if    (ANALOG == 1)  // OMEGA / NAUSICA
+    #define C_DSP_SW_WORK_AROUND 0x0006
+
+  #elif  (ANALOG == 2)  // IOTA
+    #define C_DSP_SW_WORK_AROUND 0x000E
+
+  #elif  (ANALOG == 3)  // SYREN
+    #define C_DSP_SW_WORK_AROUND 0x000E
+  #endif
+
+  // This workaround should be enabled only for H2-sample on full build config
+  #if (OP_L1_STANDALONE==1)
+    #define RAZ_VULSWITCH_REGAUDIO 0
+  #endif
+
+  /* DSP debug trace configuration */
+  /*-------------------------------*/
+  #if (MELODY_E2)
+    // In case of the melody E2 the DSP trace must be disable because the
+    // melody instrument waves are overlayed with DSP trace buffer
+
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 7       // Real size is incremented by 1 for DSP write pointer.
+
+    // DSP debug trace type config
+    //             |<-------------- Features -------------->|<---------- Levels ----------->|
+    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
+    #define C_DEBUG_TRACE_TYPE  0x0000  // Level = BASIC; Features = Timer + Buffer Header + Burst.
+
+    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+      #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability
+                                                // Currently not supported !
+    #endif
+  #else
+    // DSP debug trace API buufer config
+    #define C_DEBUG_BUFFER_ADD  0x17ff  // Address of DSP write pointer... data are just after.
+    #define C_DEBUG_BUFFER_SIZE 2047    // Real size is incremented by 1 for DSP write pointer.
+
+    // DSP debug trace type config
+    //             |<-------------- Features -------------->|<---------- Levels ----------->|
+    // [15-8:UNUSED|7:TIMER|6:BURST|5:BUFFER|4:BUFFER HEADER|3:UNUSED|2:KERNEL|1:BASIC|0:ISR]
+    #define C_DEBUG_TRACE_TYPE  0x0012  // Level = BASIC; Features = Buffer Header.
+
+    #if (C_DEBUG_TRACE_TYPE != 0) && ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+    #define DSP_DEBUG_TRACE_ENABLE       1    // Enable DSP debug trace dumping capability (supported since patch 2090)
+    #endif
+
+    // AMR trace
+    #define C_AMR_TRACE_ID 55
+
+  #endif
+  /* d_error_status                */
+  /*-------------------------------*/
+
+  #if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4))
+    #define D_ERROR_STATUS_TRACE_ENABLE  1    // Enable d_error_status checking capability (supported since patch 2090)
+
+    // masks to apply on d_error_status bit field for DSP patch 0x2061 or 0x2062
+    #define DSP_DEBUG_GSM_MASK     0x08BD
+    #define DSP_DEBUG_GPRS_MASK    0x0f3d
+  #endif
+#endif // DSP
+
+/*------------------------------------*/
+/* Default value                      */
+/*------------------------------------*/
+#ifndef W_A_DSP1
+  #define W_A_DSP1   0
+#endif
+
+#ifndef DATA14_4
+  #define DATA14_4   0
+#endif
+
+#ifndef W_A_ITFORCE
+  #define W_A_ITFORCE   0
+#endif
+
+#ifndef W_A_DSP_IDLE3
+  #define W_A_DSP_IDLE3 0
+#endif
+
+#ifndef L1_NEW_AEC
+  #define L1_NEW_AEC 0
+#endif
+
+#ifndef DSP_DEBUG_TRACE_ENABLE
+  #define DSP_DEBUG_TRACE_ENABLE 0
+#endif
+
+#ifndef DEBUG_DEDIC_TCH_BLOCK_STAT
+  #define DEBUG_DEDIC_TCH_BLOCK_STAT 0
+#endif
+
+#ifndef D_ERROR_STATUS_TRACE_ENABLE
+  #define D_ERROR_STATUS_TRACE_ENABLE  0
+#endif
+
+#ifndef L1_GTT
+  #define L1_GTT 0
+  #define TTY_SYNC_MCU 0
+  #define TTY_SYNC_MCU_2 0
+  #define L1_GTT_FIFO_TEST_ATOMIC 0
+  #define NEW_WKA_PATCH          0
+  #define OPTIMISED              0
+#endif
+
+#ifndef L1_AMR_NSYNC
+  #define L1_AMR_NSYNC 0
+#endif
+
+#ifndef FF_L1_TCH_VOCODER_CONTROL
+  #define FF_L1_TCH_VOCODER_CONTROL 0
+  #define L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE 0 
+#endif
+
+/*------------------------------------*/
+/* Download                           */
+/*------------------------------------*/
+
+
+/* Possible values for the download status */
+
+#define LEAD_READY      1
+#define BLOCK_READY     2
+#define PROGRAM_DONE    3
+#define PAGE_SELECTION  4
+
+
+/************************************/
+/* Options of compilation...        */
+/************************************/
+
+// Possible choice of hardware plateform.
+#define GEMINI       1   // GEMINI chip (rom dsp code)
+#define POLESTAR     2   // POLESTAR chip (no rom)
+
+// Possible choice for DSP software setup.
+#define NO_DWNLD         0
+#define PATCH_DWNLD      1
+#define DSP_DWNLD        2
+#define PATCH_DSP_DWNLD  3
+
+// MAC-S status reporting to Layer 1
+#define MACS_STATUS     0   // MAC-S STATUS activated if set to 1
+
+
+// Possible choice for dll_dcch_downlink interface (with FN or without FN)
+#define SEND_FN_TO_L2_IN_DCCH 1 /* 0=without, 1=with FN parameter */
+
+//---------------------------------------------------------------------------------
+
+// Neighbor Cell RXLEV indication
+#if ((OP_L1_STANDALONE==1) && (CODE_VERSION == NOT_SIMULATION))
+ #define  L1_MPHC_RXLEV_IND_REPORT_SORT 1
+#else
+ #define  L1_MPHC_RXLEV_IND_REPORT_SORT 0
+#endif
+
+#endif /* __L1_CONFG_H__ */
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_const.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_const.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,1377 @@
+ /************* Revision Controle System Header *************
+ *                  GSM Layer 1 software
+ * L1_CONST.H
+ *
+ *        Filename l1_const.h
+ *  Copyright 2003 (C) Texas Instruments
+ *
+ ************* Revision Controle System Header *************/
+
+#ifdef __MSDOS__              // Running BORLANDC compiler.
+  #ifdef MVC
+    #define EXIT exit(0)
+    #define FAR
+  #else
+    #define EXIT DOS_Exit(0)
+    #define FAR far
+  #endif
+#else                         // Running ARM compiler.
+  #define FAR
+  #define EXIT exit(0)
+  #define stricmp strcmp
+#endif
+
+
+#if (CODE_VERSION != SIMULATION)
+  #define NULL                0
+#endif
+
+#define NO_PAR                0
+
+#define NO_TASK               0
+#define ALL_TASK              0xffffffff
+#define ALL_PARAM             0xffffffff
+
+#define TRUE                  1
+#define TRUE_L                1L
+#define FALSE                 0
+
+#define NOT_PENDING           0
+#define PENDING               1
+
+#define INACTIVE              2
+#define ACTIVE                3
+#define RE_ENTERED            4
+#define WAIT_IQ               5
+
+//---------------------------------------------
+// MCU-DSP bit-field bit position definitions
+//---------------------------------------------
+#if L1_GPRS
+  #define GPRS_SCHEDULER     1  // Select GPRS scheduler
+#endif
+#define GSM_SCHEDULER        2  // Select GSM  scheduler
+
+//-----------------------------
+// POWER MANAGEMENT............
+//-----------------------------
+#define MIN_SLEEP_TIME  (SETUP_FRAME+2+l1_config.params.setup_afc_and_rf) //HW WAKE-UP+MIN_SLEEP(2)+AFC RESTORE(2)
+#define TPU_LOAD              01
+#define TPU_FREEZE            02
+
+// SLEEP ALGO SWITCH
+#define NO_SLEEP              00   // ------ + ------ + ------
+#define SMALL_SLEEP           01   // SMALL  + ------ + ------
+#define BIG_SLEEP             02   // ------ +   BIG  + ------
+#define DEEP_SLEEP            03   // ------ +   BIG  +  DEEP
+#define ALL_SLEEP             04   // SMALL  +   BIG  +  DEEP
+
+// GAUGING SAMPLES
+#define SIZE_HIST             10
+#define MAX_BAD_GAUGING        3
+
+// GAUG_IN_32T =  (HF in clock of 13Mhz*dpll) * ( LF in Khz)
+#define GAUG_IN_32T           1348   // gauging duration is 1348*T32 measured on eva4
+
+// DSP state need to be used to enter Deep Sleep mode
+#if (W_A_DSP_IDLE3 == 1)
+  #define C_DSP_IDLE3           3
+#endif
+
+//-------------------------------------------------
+// INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
+//       to face temperature variation
+//
+// ACQUIS: variations allowed 32.768Khz +- 50 ppm
+  // 9 frames gauging is 1348*T32 (measured on eva4)
+// UPDATE: variation allowed is +- 6 ppm jitter
+//-------------------------------------------------
+
+#define MCUCLK                13000       // 13 Mhz
+#define LF                    32.768
+#define LF_100PPM             32.7712768  // 32.768*(1+100*10E-6)
+#define LF_500PPM             32.751616   // 32.768*(1-500*10E-6)
+#define LF_50PPM              32.7696384  // 32.768*(1+50*10E-6)
+#define LF_6PPM               32.76819661 // 32.768*(1+6*10E-6)
+
+#define NB_INIT               5           // nbr of gauging to pass to ACQUIS
+#define NB_ACQU               10          // nbr of gauging to pass to UPDATE
+
+#if (CHIPSET ==2 || CHIPSET ==3 || CHIPSET == 5 || CHIPSET == 6 || CHIPSET == 9) // PLL is at 65 Mhz !!!!!!
+  #define PLL                5           // 5*13Mhz = 65 Mhz
+  //-------------------------------------------------
+  // INIT: value is 32.768Khz at [-500 ppm, +100 ppm]
+  //
+  // ACQUIS: variations allowed 32.768Khz +- 50 ppm
+  // 9 frames gauging is 1348*T32 (measured on eva4)
+  // UPDATE: variation allowed is +- 6 ppm jitter
+  //-------------------------------------------------
+  #define C_CLK_MIN             1983     // 65000/32.7712768 = 1983.444234
+  #define C_CLK_INIT_MIN        29113    // 0.444234*2^16
+  #define C_CLK_MAX             1984     // 65000 / 32.751616 = 1984.634896
+  #define C_CLK_INIT_MAX        41608    // 0.634896*2^16
+  #define C_DELTA_HF_ACQUIS     130      // 1348/32.768-1348/32.7696384 = 0.002056632ms
+                                         // 0.002056632/0.0001538 = 130 T65Mhz
+  #define C_DELTA_HF_UPDATE     15       // 1348/32.768-1348/32.76819661 =0.00024691ms
+                                         // 0.00024691/0.0001538 = 15 T65Mhz
+#endif
+
+#define ARMIO_CLK_CUT       0x0001
+#define UWIRE_CLK_CUT       0x0002
+
+//-----------------------------
+// Neighbour cell sync. reading
+//-----------------------------
+#if (L1_12NEIGH)
+ #define NBR_NEIGHBOURS      12
+#else
+ #define NBR_NEIGHBOURS       6
+#endif
+
+//-----------------------------
+// LAYER 1 MEASUREMENT TASKS...
+//-----------------------------
+#define NBR_L1S_MEAS_TASKS    4
+
+#define FSMS                  0
+#define I_BAMS                1
+#define D_BAMS                2
+#define SERVMS                3
+
+#define FSMS_MEAS             (TRUE_L << FSMS)              // Measurement task on FULL list (Cell Selection/Idle).
+#define I_BAMS_MEAS           (TRUE_L << I_BAMS)            // Measurement task on BA list in Idle.
+#define D_BAMS_MEAS           (TRUE_L << D_BAMS)            // Measurement task on BA list in Dedicated.
+#define SERVMS_MEAS           (TRUE_L << SERVMS)            // Measurement task for Serving.
+
+#define FSMS_MEAS_MASK        ALL_TASK ^ FSMS_MEAS
+#define I_BAMS_MEAS_MASK      ALL_TASK ^ I_BAMS_MEAS
+#define D_BAMS_MEAS_MASK      ALL_TASK ^ D_BAMS_MEAS
+#define SERVMS_MEAS_MASK      ALL_TASK ^ SERVMS_MEAS
+
+#define A_D_BLEN              456                           // SACCH/SDCCH data block length (GSM 5.01 $7)
+#define TCH_FS_BLEN           378                           // TCH FULL SPEECH block length
+#define TCH_HS_BLEN           211                           // TCH HALF SPEECH block length
+#define TCH_F_D_BLEN          456                           // FACCH, TCH_DATA block length
+
+// Define max PM/TDMA according to DSP code and TPU RAM size
+//----------------------------------------------------------
+
+// NOTE: we should use a global variable initialized at L1 start and function of rx synth setup time.
+
+#if ((CHIPSET == 2) || (CHIPSET == 3) || (CHIPSET == 4))
+
+  // TPU RAM size limitation
+
+  #define NB_MEAS_MAX       4
+  #define NB_MEAS_MAX_GPRS  4
+
+#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7)  || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+
+  #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+
+    // DSP code 33: upto 8 PMs with GSM and GPRS scheduler
+
+    #define NB_MEAS_MAX       8
+    #define NB_MEAS_MAX_GPRS  8
+
+  #elif (DSP == 32)
+
+    // DSP code prior to code 33 support upto 4 PMs with GSM scheduler
+    // and 8 PMs with GPRS scheduler, 6 for DSP 32 because of CPU load
+
+    #define NB_MEAS_MAX       4
+    #define NB_MEAS_MAX_GPRS  6
+
+  #else
+
+
+    // DSP code prior to code 33 support upto 4 PMs with GSM scheduler
+    // and 8 PMs with GPRS scheduler
+
+    #define NB_MEAS_MAX       4
+    #define NB_MEAS_MAX_GPRS  8
+
+  #endif
+#endif
+#if (AMR == 1)
+  #define SID_UPDATE_BLEN       212                           // SID UPDATE block length
+  #define RATSCCH_BLEN          212                           // RATSCCH block length
+  #define TCH_AFS_BLEN          448                           // TCH Adaptative Full rate Speech block length
+  // Note: the d_nerr value is calculated thanks to the bit class 1 of the block.
+  // But the number AHS bit class 1 depends on the type of vocoder currently used (c.f. 5.03 &3.10.7.2)
+  #define TCH_AHS_7_95_BLEN     188                           // TCH AHS 7.95 Speech block length
+  #define TCH_AHS_7_4_BLEN      196                           // TCH AHS 7.4 Speech block length
+  #define TCH_AHS_6_7_BLEN      200                           // TCH AHS 6.7 Speech block length
+  #define TCH_AHS_5_9_BLEN      208                           // TCH AHS 5.9 Speech block length
+  #define TCH_AHS_5_15_BLEN     212                           // TCH AHS 5.15 Speech block length
+  #define TCH_AHS_4_75_BLEN     212                           // TCH AHS 4.75 Speech block length
+#endif
+//----------------------------------------
+// LAYER 1 Asynchronous processes names...
+//----------------------------------------
+#if (TESTMODE) && !(L1_GPRS)
+  #if (AUDIO_TASK == 1)
+    #if (L1_GTT)
+      #if (OP_L1_STANDALONE == 1)
+        #define NBR_L1A_PROCESSES       45
+      #else    
+        #define NBR_L1A_PROCESSES       44
+      #endif
+    #else
+      #if (OP_L1_STANDALONE == 1)
+        #define NBR_L1A_PROCESSES       44
+      #else    
+        #define NBR_L1A_PROCESSES       43
+      #endif
+    #endif
+  #else
+    #if (L1_GTT)
+      #if (OP_L1_STANDALONE == 1)
+        #define NBR_L1A_PROCESSES       27
+      #else
+        #define NBR_L1A_PROCESSES       26
+      #endif
+  #else
+      #if (OP_L1_STANDALONE == 1)
+        #define NBR_L1A_PROCESSES       26
+      #else  
+        #define NBR_L1A_PROCESSES       25
+      #endif
+  #endif
+#endif
+#endif
+
+#if (TESTMODE) && (L1_GPRS)
+  #if (AUDIO_TASK == 1)
+    #if (L1_GTT)
+      #if (OP_L1_STANDALONE == 1)
+        #define NBR_L1A_PROCESSES       46
+      #else
+        #define NBR_L1A_PROCESSES       45
+      #endif
+    #else
+      #if (OP_L1_STANDALONE == 1)
+        #define NBR_L1A_PROCESSES       45
+      #else
+        #define NBR_L1A_PROCESSES       44
+      #endif
+    #endif
+  #else
+    #if (L1_GTT)
+      #if (OP_L1_STANDALONE == 1)
+        #define NBR_L1A_PROCESSES       28
+      #else
+        #define NBR_L1A_PROCESSES       27
+      #endif
+  #else
+      #if (OP_L1_STANDALONE == 1)
+        #define NBR_L1A_PROCESSES       27
+      #else
+        #define NBR_L1A_PROCESSES       26
+      #endif    
+  #endif
+#endif
+#endif
+
+#if !(TESTMODE)
+  #if (AUDIO_TASK == 1)
+    #if (L1_GTT)
+       #if (OP_L1_STANDALONE == 1)
+          #define NBR_L1A_PROCESSES       37
+       #else
+          #define NBR_L1A_PROCESSES       36
+       #endif
+    #else
+      #if (OP_L1_STANDALONE == 1)
+         #define NBR_L1A_PROCESSES       36
+      #else
+         #define NBR_L1A_PROCESSES       35
+      #endif
+    #endif
+  #else
+    #if (L1_GTT)
+      #if (OP_L1_STANDALONE == 1)
+          #define NBR_L1A_PROCESSES       19
+      #else
+          #define NBR_L1A_PROCESSES       18
+      #endif
+  #else
+      #if (OP_L1_STANDALONE == 1)
+          #define NBR_L1A_PROCESSES       18
+      #else
+          #define NBR_L1A_PROCESSES       17
+      #endif
+  #endif
+#endif
+#endif
+
+
+#define FULL_MEAS                0   // l1a_full_list_meas_process(msg)
+#define CS_NORM                  1   // l1a_cs_bcch_process(msg)
+#define I_6MP                    2   // l1a_idle_6strongest_monitoring_process(msg)
+#define I_SCP                    3   // l1a_idle_serving_cell_paging_process(msg)
+#define I_SCB                    4   // l1a_idle_serving_cell_bcch_reading_process(msg)
+#define I_SMSCB                  5   // l1a_idle_smscb_process(msg)
+#define CR_B                     6   // l1a_cres_process(msg)
+#define ACCESS                   7   // l1a_access_process(msg)
+#define DEDICATED                8   // l1a_dedicated_process(msg)
+#define I_FULL_MEAS              9   // l1a_dedicated_process(msg)
+#define I_NMEAS                 10   // l1a_idle_ba_meas_process(msg)
+#define DEDIC_6                 11   // l1a_dedic6_process(msg)
+#define D_NMEAS                 12   // l1a_dedic_ba_list_meas_process(msg)
+#define HW_TEST                 13   // l1a_test_process(msg)
+#define I_BCCHN                 14   // l1a_idle_neighbour_cell_bcch_reading_process(msg)
+#define I_ADC                   15   // l1a_mmi_adc_req(msg)
+
+#if (TESTMODE) && !(L1_GPRS)
+  #define TMODE_FB0                     16   // l1a_tmode_fb0_process(msg)
+  #define TMODE_FB1                     17   // l1a_tmode_fb1_process(msg)
+  #define TMODE_SB                      18   // l1a_tmode_sb_process(msg)
+  #define TMODE_BCCH                    19   // l1a_tmode_bcch_reading_process(msg)
+  #define TMODE_RA                      20   // l1a_tmode_access_process(msg)
+  #define TMODE_DEDICATED               21   // l1a_tmode_dedicated_process(msg)
+  #define TMODE_FULL_MEAS               22   // l1a_tmode_full_list_meas_process(msg)
+  #define TMODE_PM                      23   // l1a_tmode_meas_process(msg)
+  #if (AUDIO_TASK == 1)
+    #define L1A_KEYBEEP_STATE           24   // l1a_mmi_keybeep_process(msg)
+    #define L1A_TONE_STATE              25   // l1a_mmi_tone_process(msg)
+    #define L1A_MELODY0_STATE           26   // l1a_mmi_melody0_process(msg)
+    #define L1A_MELODY1_STATE           27   // l1a_mmi_melody1_process(msg)
+    #define L1A_VM_PLAY_STATE           28   // l1a_mmi_vm_playing_process(msg)
+    #define L1A_VM_RECORD_STATE         29   // l1a_mmi_vm_recording_process(msg)
+    #define L1A_SR_ENROLL_STATE         30   // l1a_mmi_sr_enroll_process(msg)
+    #define L1A_SR_UPDATE_STATE         31   // l1a_mmi_sr_update_process(msg)
+    #define L1A_SR_RECO_STATE           32   // l1a_mmi_sr_reco_process(msg)
+    #define L1A_SR_UPDATE_CHECK_STATE   33   // l1a_mmi_sr_update_check_process(msg)
+    #define L1A_AEC_STATE               34   // l1a_mmi_aec_process(msg)
+    #define L1A_FIR_STATE               35   // l1a_mmi_fir_process(msg)
+    #define L1A_AUDIO_MODE_STATE        36   // l1a_mmi_audio_mode_process(msg)
+    #define L1A_MELODY0_E2_STATE        37   // l1a_mmi_melody0_e2_process(msg)
+    #define L1A_MELODY1_E2_STATE        38   // l1a_mmi_melody1_e2_process(msg)
+    #define L1A_VM_AMR_PLAY_STATE       39   // l1a_mmi_vm_amr_playing_process(msg)
+    #define L1A_VM_AMR_RECORD_STATE     40   // l1a_mmi_vm_amr_recording_process(msg)
+    #define L1A_CPORT_STATE             41   // l1a_mmi_cport_process(msg)
+    #if (L1_GTT == 1)
+      #define L1A_GTT_STATE               42   // l1a_mmi_gtt_process(msg)
+      #define INIT_L1                     43   // l1a_init_layer1_process(msg)
+      #if (OP_L1_STANDALONE == 1)
+        #define HSW_CONF                  44   // l1a_test_config_process(msg)
+      #endif
+    #else
+      #define INIT_L1                     42   // l1a_init_layer1_process(msg)
+      #if (OP_L1_STANDALONE == 1)
+        #define HSW_CONF                  43  // l1a_test_config_process(msg)
+      #endif
+    #endif
+  #else
+    #if (L1_GTT == 1)
+      #define L1A_GTT_STATE               24   // l1a_mmi_gtt_process(msg)
+      #define INIT_L1                     25   // l1a_init_layer1_process(msg)
+      #if (OP_L1_STANDALONE == 1)
+        #define HSW_CONF                  26  // l1a_test_config_process(msg)
+      #endif
+    #else
+      #define INIT_L1                     24   // l1a_init_layer1_process(msg)
+      #if (OP_L1_STANDALONE == 1)
+        #define HSW_CONF                  25  // l1a_test_config_process(msg)
+      #endif
+    #endif
+  #endif
+#endif
+
+#if (TESTMODE) && (L1_GPRS)
+  #define TMODE_FB0                     16   // l1a_tmode_fb0_process(msg)
+  #define TMODE_FB1                     17   // l1a_tmode_fb1_process(msg)
+  #define TMODE_SB                      18   // l1a_tmode_sb_process(msg)
+  #define TMODE_BCCH                    19   // l1a_tmode_bcch_reading_process(msg)
+  #define TMODE_RA                      20   // l1a_tmode_access_process(msg)
+  #define TMODE_DEDICATED               21   // l1a_tmode_dedicated_process(msg)
+  #define TMODE_FULL_MEAS               22   // l1a_tmode_full_list_meas_process(msg)
+  #define TMODE_PM                      23   // l1a_tmode_meas_process(msg)
+  #define TMODE_TRANSFER                24   // l1a_tmode_transfer_process(msg)
+  #if (AUDIO_TASK == 1)
+    #define L1A_KEYBEEP_STATE           25   // l1a_mmi_keybeep_process(msg)
+    #define L1A_TONE_STATE              26   // l1a_mmi_tone_process(msg)
+    #define L1A_MELODY0_STATE           27   // l1a_mmi_melody0_process(msg)
+    #define L1A_MELODY1_STATE           28   // l1a_mmi_melody1_process(msg)
+    #define L1A_VM_PLAY_STATE           29   // l1a_mmi_vm_playing_process(msg)
+    #define L1A_VM_RECORD_STATE         30   // l1a_mmi_vm_recording_process(msg)
+    #define L1A_SR_ENROLL_STATE         31   // l1a_mmi_sr_enroll_process(msg)
+    #define L1A_SR_UPDATE_STATE         32   // l1a_mmi_sr_update_process(msg)
+    #define L1A_SR_RECO_STATE           33   // l1a_mmi_sr_reco_process(msg)
+    #define L1A_SR_UPDATE_CHECK_STATE   34   // l1a_mmi_sr_update_check_process(msg)
+    #define L1A_AEC_STATE               35   // l1a_mmi_aec_process(msg)
+    #define L1A_FIR_STATE               36   // l1a_mmi_fir_process(msg)
+    #define L1A_AUDIO_MODE_STATE        37   // l1a_mmi_audio_mode_process(msg)
+    #define L1A_MELODY0_E2_STATE        38   // l1a_mmi_melody0_e2_process(msg)
+    #define L1A_MELODY1_E2_STATE        39   // l1a_mmi_melody1_e2_process(msg)
+    #define L1A_VM_AMR_PLAY_STATE       40   // l1a_mmi_vm_amr_playing_process(msg)
+    #define L1A_VM_AMR_RECORD_STATE     41   // l1a_mmi_vm_amr_recording_process(msg)
+    #define L1A_CPORT_STATE             42   // l1a_mmi_cport_process(msg)
+    #if (L1_GTT == 1)
+      #define L1A_GTT_STATE             43
+      #define INIT_L1                   44   // l1a_init_layer1_process(msg)
+      #if (OP_L1_STANDALONE == 1)
+        #define HSW_CONF                45  // l1a_test_config_process(msg)
+      #endif
+    #else
+      #define INIT_L1                   43   // l1a_init_layer1_process(msg)
+      #if (OP_L1_STANDALONE == 1)
+        #define HSW_CONF                44  // l1a_test_config_process(msg)
+      #endif
+    #endif
+  #else
+    #if (L1_GTT == 1)
+      #define L1A_GTT_STATE             25
+      #define INIT_L1                   26   // l1a_init_layer1_process(msg)
+      #if (OP_L1_STANDALONE == 1)
+        #define HSW_CONF                27  // l1a_test_config_process(msg)
+      #endif
+    #else
+      #define INIT_L1                   25   // l1a_init_layer1_process(msg)
+      #if (OP_L1_STANDALONE == 1)
+        #define HSW_CONF                26  // l1a_test_config_process(msg)
+      #endif
+    #endif
+  #endif
+#endif
+
+#if !(TESTMODE) && (AUDIO_TASK == 1)
+  #define L1A_KEYBEEP_STATE             16   // l1a_mmi_keybeep_process(msg)
+  #define L1A_TONE_STATE                17   // l1a_mmi_tone_process(msg)
+  #define L1A_MELODY0_STATE             18   // l1a_mmi_melody0_process(msg)
+  #define L1A_MELODY1_STATE             19   // l1a_mmi_melody1_process(msg)
+  #define L1A_VM_PLAY_STATE             20   // l1a_mmi_vm_playing_process(msg)
+  #define L1A_VM_RECORD_STATE           21   // l1a_mmi_vm_recording_process(msg)
+  #define L1A_SR_ENROLL_STATE           22   // l1a_mmi_sr_enroll_process(msg)
+  #define L1A_SR_UPDATE_STATE           23   // l1a_mmi_sr_update_process(msg)
+  #define L1A_SR_RECO_STATE             24   // l1a_mmi_sr_reco_process(msg)
+  #define L1A_SR_UPDATE_CHECK_STATE     25   // l1a_mmi_sr_update_check_process(msg)
+  #define L1A_AEC_STATE                 26   // l1a_mmi_aec_process(msg)
+  #define L1A_FIR_STATE                 27   // l1a_mmi_fir_process(msg)
+  #define L1A_AUDIO_MODE_STATE          28   // l1a_mmi_audio_mode_process(msg)
+  #define L1A_MELODY0_E2_STATE          29   // l1a_mmi_melody0_e2_process(msg)
+  #define L1A_MELODY1_E2_STATE          30   // l1a_mmi_melody1_e2_process(msg)
+  #define L1A_VM_AMR_PLAY_STATE         31   // l1a_mmi_vm_amr_playing_process(msg)
+  #define L1A_VM_AMR_RECORD_STATE       32   // l1a_mmi_vm_amr_recording_process(msg)
+  #define L1A_CPORT_STATE               33   // l1a_mmi_cport_process(msg)
+  #if (L1_GTT == 1)
+    #define L1A_GTT_STATE               34   // l1a_mmi_tty_process(msg)
+    #define INIT_L1                     35   // l1a_init_layer1_process(msg)
+    #if (OP_L1_STANDALONE == 1)
+      #define HSW_CONF                  36   // l1a_test_config_process(msg)
+    #endif
+  #else
+    #define INIT_L1                     34   // l1a_init_layer1_process(msg)
+    #if (OP_L1_STANDALONE == 1)
+      #define HSW_CONF                  35   // l1a_test_config_process(msg)
+    #endif
+  #endif
+#elif !(TESTMODE) && !(AUDIO_TASK == 1)
+  #if (L1_GTT == 1)
+    #define L1A_GTT_STATE               16   // l1a_mmi_tty_process(msg)
+    #define INIT_L1                     17   // l1a_init_layer1_process(msg)
+    #if (OP_L1_STANDALONE == 1)
+      #define HSW_CONF                  18   // l1a_test_config_process(msg)
+    #endif   
+  #else
+    #define INIT_L1                     16   // l1a_init_layer1_process(msg)
+    #if (OP_L1_STANDALONE == 1)
+      #define HSW_CONF                  17   // l1a_test_config_process(msg)
+    #endif  
+  #endif
+#endif
+
+#if TESTMODE
+  #define TMODE_UPLINK            (1<<0)
+  #define TMODE_DOWNLINK          (1<<1)
+#endif
+
+//------------------------------------
+// LAYER 1 DOWNLINK & UPLINK TASKS...
+//------------------------------------
+#define TASK_DISABLED            0
+#define TASK_ENABLED             1
+
+#define SEMAPHORE_RESET          0
+#define SEMAPHORE_SET            1
+
+#define NO_NEW_TASK             -1
+
+
+// Tasks in the order of their priority (low to high).
+
+#if !L1_GPRS
+
+  #define NBR_DL_L1S_TASKS  32
+
+  //GSM_TASKS/
+  #define HWTEST       0  // DSP checksum reading
+  #define ADC_CSMODE0  1  // ADC task in CS_MODE0 mode
+  #define DEDIC        2  // Global Dedicated mode switch
+  #define RAACC        3  // Channel access (ul)
+  #define RAHO         4  // Handover access (ul)
+  #define NSYNC        5  // Global Neighbour cell synchro switch
+  #define FBNEW        6  // Frequency burst search (Idle mode)
+  #define SBCONF       7  // Synchro. burst confirmation
+  #define SB2          8  // Synchro. burst read (1 frame uncertainty / SB position)
+  #define FB26         9  // Frequency burst search, dedic/transfer mode MF26 or MF52
+  #define SB26        10  // Synchro burst search, dedic/transfer mode MF26 or MF52
+  #define SBCNF26     11  // Synchro burst confirmation, dedic/transfer mode MF26 or MF52
+  #define FB51        12  // Frequency burst search, dedic mode MF51
+  #define SB51        13  // Synchro burst search, dedic MF51
+  #define SBCNF51     14  // Synchro burst confirmation, dedic MF51
+  #define BCCHN       15  // BCCH Neighbor in GSM Idle
+  #define ALLC        16  // All CCCH Reading
+  #define EBCCHS      17  // Extended BCCH Serving Reading
+  #define NBCCHS      18  // Normal BCCH ServingReading
+  #define SMSCB       19  // CBCH serving Reading
+  #define NP          20  // Normal paging Reading
+  #define EP          21  // Extended pagingReading
+  #define ADL         22  // SACCH(SDCCH) DL
+  #define AUL         23  // SACCH(SDCCH) UL
+  #define DDL         24  // SDCCH DL
+  #define DUL         25  // SDCCH UL
+  #define TCHD        26  // Dummy for TCH Half rate
+  #define TCHA        27  // SACCH(TCH)
+  #define TCHTF       28  // TCH Full rate
+  #define TCHTH       29  // TCH Half rate
+  #define BCCHN_TOP   30  // BCCH Neighbour TOP priority in Idle mode
+  #define SYNCHRO     31  // synchro task: L1S reset
+  //END_GSM_TASKS/
+
+#else
+
+  #define NBR_DL_L1S_TASKS  45
+
+  //GPRS_TASKS/
+  #define HWTEST       0   // DSP checksum reading
+  #define ADC_CSMODE0  1   // ADC task in CS_MODE0 mode
+  #define DEDIC        2   // Global Dedicated mode switch
+  #define RAACC        3   // Channel access (ul)
+  #define RAHO         4   // Handover access (ul)
+  #define NSYNC        5   // Global Neighbour cell synchro switch
+  #define POLL         6   // Packet Polling (Access)
+  #define PRACH        7   // Packet Random Access Channel
+  #define ITMEAS       8   // Interference measurements
+  #define FBNEW        9   // Frequency burst search (Idle mode)
+  #define SBCONF       10   // Synchro. burst confirmation
+  #define SB2          11  // Synchro. burst read (1 frame uncertainty / SB position)
+  #define PTCCH        12  // Packet Timing Advance control channel
+  #define FB26         13  // Frequency burst search, dedic/transfer mode MF26 or MF52
+  #define SB26         14  // Synchro burst search, dedic/transfer mode MF26 or MF52
+  #define SBCNF26      15  // Synchro burst confirmation, dedic/transfer mode MF26 or MF52
+  #define FB51         16  // Frequency burst search, dedic mode MF51
+  #define SB51         17  // Synchro burst search, dedic MF51
+  #define SBCNF51      18  // Synchro burst confirmation, dedic MF51
+  #define PDTCH        19  // Packet Data channel
+  #define BCCHN        20  // BCCH Neighbor in GSM Idle
+  #define ALLC         21  // All CCCH Reading
+  #define EBCCHS       22  // Extended BCCH Serving Reading
+  #define NBCCHS       23  // Normal BCCH Serving Reading
+  #define ADL          24  // SACCH(SDCCH) DL
+  #define AUL          25  // SACCH(SDCCH) UL
+  #define DDL          26  // SDCCH DL
+  #define DUL          27  // SDCCH UL
+  #define TCHD         28  // Dummy for TCH Half rate
+  #define TCHA         29  // SACCH(TCH)
+  #define TCHTF        30  // TCH Full rate
+  #define TCHTH        31  // TCH Half rate
+  #define PALLC        32  // All PCCCH reading
+  #define SMSCB        33  // CBCH serving Reading
+  #define PBCCHS       34  // PBCCH serving reading
+  #define PNP          35  // Packet Normal paging Reading
+  #define PEP          36  // Packet Extended paging Reading
+  #define SINGLE       37  // Single Block for GPRS
+  #define PBCCHN_TRAN  38  // Packet BCCH Neighbor in Packet Transfer mode.
+  #define PBCCHN_IDLE  39  // Packet BCCH Neighbor in Idle mode.
+  #define BCCHN_TRAN   40  // BCCH Neighbour in Packet Transfer mode
+  #define NP           41  // Normal paging Reading
+  #define EP           42  // Extended paging Reading
+  #define BCCHN_TOP    43  // BCCH Neighbour TOP priority in Idle mode
+  #define SYNCHRO      44  // synchro task: L1S reset
+  //END_GPRS_TASKS/
+
+#endif
+
+//------------------------------------
+// LAYER 1 API
+//------------------------------------
+#define MCSI_PORT1 0
+#define MCSI_PORT2 1
+
+
+//---------------------------------
+// DSP vocoder Enable/ Disable
+//---------------------------------
+
+#if (L1M_WAIT_DSP_RESTART_AFTER_VOCODER_ENABLE ==1)
+  #if (FF_L1_TCH_VOCODER_CONTROL == 1)
+    #define TCH_VOCODER_DISABLE_REQ          0
+    #define TCH_VOCODER_ENABLE_REQ           1
+    #define TCH_VOCODER_ENABLED              2
+    #define TCH_VOCODER_DISABLED             3
+
+    // Number of TDMA wait frames until the DSP output is steady
+    #define DSP_VOCODER_ON_TRANSITION      165   
+  #endif // FF_L1_TCH_VOCODER_CONTROL
+#endif 
+
+//---------------------------------
+// Handover Finished cause defines.
+//---------------------------------
+#define HO_COMPLETE              0
+#define HO_TIMEOUT               1
+
+//---------------------------------
+// FB detection algorithm defines.
+//---------------------------------
+#define FB_MODE_0                0                          // FB detec. mode 0.
+#define FB_MODE_1                1                          // FB detec. mode 1.
+
+//---------------------------------
+// AFC control defines.
+//---------------------------------
+#define AFC_INIT                 1
+#define AFC_OPEN_LOOP            2
+#define AFC_CLOSED_LOOP          3
+
+// For VCXO algo.
+#if (VCXO_ALGO)
+#define AFC_INIT_CENTER          4
+#define AFC_INIT_MAX             5
+#define AFC_INIT_MIN             6
+#endif
+//---------------------------------
+// TOA control defines.
+//---------------------------------
+#define TOA_INIT                 1
+#define TOA_RUN                  2
+
+//---------------------------------
+// Neighbour Synchro possible status.
+//---------------------------------
+#define NSYNC_FREE               0
+#define NSYNC_PENDING            1
+#define NSYNC_COMPLETED          2
+#if (L1_12NEIGH ==1)
+  #define NSYNC_WAIT             3
+#endif
+
+/************************************/
+/* Layer 1 constants declaration... */
+/************************************/
+#define MAX_FN           ((UWORD32)26*51*2048)
+
+#if L1_GPRS
+  #define MAX_BLOCK_ID   ((UWORD32) (3 * (UWORD32) (MAX_FN / 13))) // Block ID corresponding to fn = FN MAX
+#endif
+
+//--------------------------------------------------------
+// standard specific constants used in l1_config.std.xxx
+//--------------------------------------------------------
+
+
+// GSM
+#define FIRST_ARFCN_GSM               1    // 1st arfcn is 1
+#define NBMAX_CARRIER_GSM           124    // 124 for GSM, 174 for E_GSM, 374 for DCS1800.
+#define MAX_TXPWR_GSM                19    // lowest power ctrl level value in GSM band
+// GSM_E
+#define FIRST_ARFCN_EGSM              1    // 1st arfcn is 1
+#define NBMAX_CARRIER_EGSM          174    // 174 carriers for GSM_E.
+#define MAX_TXPWR_EGSM               19    // lowest power ctrl level value in GSM-E band
+// PCS1900
+#define FIRST_ARFCN_PCS             512    // 1st arfcn is 512
+#define NBMAX_CARRIER_PCS           299    // 299 carriers for PCS1900.
+#define MAX_TXPWR_PCS                15    // lowest power ctrl level value in PCS band
+#define TXPWR_TURNING_POINT_PCS      21
+// DCS1800
+#define FIRST_ARFCN_DCS             512    // 1st arfcn is 512
+#define NBMAX_CARRIER_DCS           374    // 374 carriers for DCS1800.
+#define MAX_TXPWR_DCS                15    // lowest power ctrl level value in DCS band
+#define TXPWR_TURNING_POINT_DCS      28
+// GSM850
+#define FIRST_ARFCN_GSM850          128    // 1st arfcn is 128
+#define NBMAX_CARRIER_GSM850        124    // 124 carriers for GSM850
+#define NBMEAS_GSM850                 3    // 3 measurement per frame TBD
+#define MAX_TXPWR_GSM850             19    // lowest power ctrl level value in GSM band
+// DUAL
+#define FIRST_DCS_INDEX_DUAL        125    // 1st DCS index within the 498 continu list
+#define NBMAX_CARRIER_DUAL      124+374    // 374 carriers for DCS1800 + 124 carriers for GSM900 Band
+#define TXPWR_TURNING_POINT_DUAL     28
+// DUALEXT
+#define FIRST_DCS_INDEX_DUALEXT     175    // 1st DCS index within the 548 continu list
+#define NBMAX_CARRIER_DUALEXT   174+374    // 374 carriers for DCS1800 + 174 carriers for E-GSM900 Band
+#define TXPWR_TURNING_POINT_DUALEXT  28
+// DUAL_US
+#define FIRST_ARFCN_GSM850_DUAL_US       1    // 1st GSM850 index within the 423 continu list
+#define FIRST_PCS_INDEX_DUAL_US        125    // 1st PCS index within the 423 continu list
+#define NBMAX_CARRIER_DUAL_US      124+299    // 299 carriers for PCS1900 + 124 carriers for GSM850\ Band
+#define NBMEAS_DUAL_US                   4    // 4 measurements per frames.
+#define TXPWR_TURNING_POINT_DUAL_US     28    // TBD
+
+
+#define NBMAX_CARRIER    NBMAX_CARRIER_DUALEXT //used in arrays for power measurement
+                                           //non optimized!!! (dynamic memory allocation to optimize)
+#define BAND1    1
+#define BAND2    2
+
+#define NO_TXPWR 255     // sentinal value used with UWORD8 type.
+
+
+//--------------------------------------------------------
+// Receive level values.
+//--------------------------------------------------------
+#define RXLEV63   63   // max value for RXLEV.
+#define IL_MIN    240  // minimum input level is -120 dbm.
+
+//--------------------------------------------------------
+// Max number of cell to report in MPHC_RXLEV_IND.
+// Nb cells to check to see if cell of MPHC_NETWORK_SYNC_REQ has been detected
+//--------------------------------------------------------
+#define MAX_MEAS_RXLEV_IND_TRACE 10
+#define NB_FQ_TO_CHK 4
+
+/*--------------------------------------------------------*/
+/* Max value for GSM Paging Parameters.                   */
+/*--------------------------------------------------------*/
+#define MAX_AG_BLKS_RES_NCOMB   7
+#define MAX_AG_BLKS_RES_COMB    2
+#define MAX_PG_BLOC_INDEX_NCOMB 8
+#define MAX_PG_BLOC_INDEX_COMB  2
+#define MAX_BS_PA_MFRMS         9
+
+/*--------------------------------------------------------*/
+/* Position of different blocs in a MF51.                 */
+/*--------------------------------------------------------*/
+#define NBCCH_POSITION     2   // Normal BCCH position in a MF51.
+#define EBCCH_POSITION     6   // Extended BCCH position in a MF51.
+#define CCCH_0             6
+#define CCCH_1            12
+#define CCCH_2            16
+#define CCCH_3            22
+#define CCCH_4            26
+#define CCCH_5            32
+#define CCCH_6            36
+#define CCCH_7            42
+#define CCCH_8            46
+#define FB_0               0
+#define FB_1              10
+#define FB_2              20
+#define FB_3              30
+#define FB_4              40
+#define SB_0               1
+#define SB_1              11
+#define SB_2              21
+#define SB_3              31
+#define SB_4              41
+
+/*--------------------------------------------------------*/
+/* System information position in the "si_bit_map".       */
+/*--------------------------------------------------------*/
+#define SI_1              0x0001
+#define SI_2              0x0002
+#define SI_2BIS           0x0100
+#define SI_2TER           0x0200
+#define SI_3              0x0004
+#define SI_4              0x0008
+#define SI_7              0x0040
+#define SI_8              0x0080
+#define ALL_SI            SI_1 | SI_2 | SI_2BIS | SI_2TER | SI_3 | SI_4 | SI_7 | SI_8
+
+/*--------------------------------------------------------*/
+/* CBCH position in the "smscb_bit_map".                  */
+/*--------------------------------------------------------*/
+#define CBCH_TB1            0x0001
+#define CBCH_TB2            0x0002
+#define CBCH_TB3            0x0004
+#define CBCH_TB5            0x0008
+#define CBCH_TB6            0x0010
+#define CBCH_TB7            0x0020
+
+#define CBCH_CONTINUOUS_READING  0
+#define CBCH_SCHEDULED           1
+#define CBCH_INACTIVE            2
+
+/*--------------------------------------------------------*/
+/* Channel type definitions for DEDICATED mode.           */
+/*--------------------------------------------------------*/
+
+//TABLE/ CHAN TYPE
+#define INVALID_CHANNEL    0
+#define TCH_F              1
+#define TCH_H              2
+#define SDCCH_4            3
+#define SDCCH_8            4
+//END_TABLE/
+
+/*--------------------------------------------------------*/
+/* Channel mode definitions for DEDICATED.                */
+/*--------------------------------------------------------*/
+#define SIG_ONLY_MODE      0    // signalling only
+#define TCH_FS_MODE        1    // speech full rate
+#define TCH_HS_MODE        2    // speech half rate
+#define TCH_96_MODE        3    // data 9,6 kb/s
+#define TCH_48F_MODE       4    // data 4,8 kb/s full rate
+#define TCH_48H_MODE       5    // data 4,8 kb/s half rate
+#define TCH_24F_MODE       6    // data 2,4 kb/s full rate
+#define TCH_24H_MODE       7    // data 2,4 kb/s half rate
+#define TCH_EFR_MODE       8    // enhanced full rate
+#define TCH_144_MODE       9    // data 14,4 kb/s half rate
+#if (AMR == 1)
+  #define TCH_AHS_MODE      10    // adaptative speech half rate
+  #define TCH_AFS_MODE      11    // adaptative speech full rate
+#endif
+
+
+/*--------------------------------------------------------*/
+/* Layer 1 functional modes for "mode" setting pupose.    */
+/*--------------------------------------------------------*/
+#define CS_MODE0           0    // functional mode at reset.
+#define CS_MODE            1    // functional mode in CELL SELECTION.
+#define I_MODE             2    // functional mode in IDLE.
+#define CON_EST_MODE1      3    // functional mode in ACCESS (before 1st RA, for TOA convergency).
+#define CON_EST_MODE2      4    // functional mode in ACCESS (after 1st RA).
+#define DEDIC_MODE         5    // functional mode in DEDICATED.
+#define DEDIC_MODE_HALF_DATA 6    // used only for TOA histogram length purpose.
+#if L1_GPRS
+  #define PACKET_TRANSFER_MODE 7
+#endif
+
+/*--------------------------------------------------------*/
+/* Error causes for MPHC_NO_BCCH message.                  */
+/*--------------------------------------------------------*/
+#define NO_FB_SB           0  // FB or SB not found.
+#define NCC_NOT_PERMITTED  1  // Synchro OK! but PLMN not permitted.
+
+/*--------------------------------------------------------*/
+/* MFTAB constants and flags.                             */
+/*--------------------------------------------------------*/
+#define L1_MAX_FCT        5        /* Max number of fctions in a frame */
+#define MFTAB_SIZE       20
+
+/********************************/
+/* Software register/flags      */
+/* definitions.                 */
+/********************************/
+#define NO_CTRL       (TRUE_L << 0)
+#define CTRL_MS       (TRUE_L << 1)
+#define CTRL_TX       (TRUE_L << 2)
+#define CTRL_RX       (TRUE_L << 3)
+#define CTRL_ADC      (TRUE_L << 4)
+#define CTRL_SYNC     (TRUE_L << 5)
+#define CTRL_ABORT    (TRUE_L << 6)
+#define CTRL_TEST     (TRUE_L << 7)
+#define CTRL_SYCB     (TRUE_L << 8)
+#define CTRL_FB_ABORT (TRUE_L << 9)
+#if L1_GPRS
+  #define CTRL_PRACH     (TRUE_L << 10)
+  #define CTRL_SYSINGLE  (TRUE_L << 11)
+#endif
+
+
+/********************************/
+/* MISC management              */
+/********************************/
+#define GSM_CTL           0   // DSP ctrl for a GSM task
+#define MISC_CTL          1   // DSP ctrl for a MISC task
+#define GSM_MISC_CTL      2   // DSP ctrl for a GSM and MISC tasks
+
+/********************************/
+/* TOA management               */
+/********************************/
+#define  ISH_INVALID    128          // value used to disable the toa offset
+
+/********************************/
+/* AGC management               */
+/********************************/
+#define DPAGC_FIFO_LEN    4
+#define DPAGC_MAX_FLAG    1
+#if (AMR == 1)
+  #define DPAGC_AMR_FIFO_LEN 4
+#endif
+
+/********************************/
+/* ADC management               */
+/********************************/
+#define ADC_DISABLED                  0x0000
+  // Traffic part
+#define ADC_MASK_RESET_TRAFFIC        0xFF00
+#define ADC_NEXT_TRAFFIC_UL           0x0001
+#define ADC_EACH_TRAFFIC_UL           0x0002
+#define ADC_NEXT_TRAFFIC_DL           0x0004
+#define ADC_EACH_TRAFFIC_DL           0x0008
+#define ADC_EACH_RACH                 0x0010
+
+
+  // Idle part
+#define ADC_MASK_RESET_IDLE           0x00FF
+#define ADC_NEXT_NORM_PAGING          0x0100
+#define ADC_EACH_NORM_PAGING          0x0200
+#define ADC_NEXT_MEAS_SESSION         0x0400
+#define ADC_EACH_MEAS_SESSION         0x0800
+#define ADC_NEXT_NORM_PAGING_REORG    0x1000
+#define ADC_EACH_NORM_PAGING_REORG    0x2000
+
+
+  // CS_MODE0 part
+#define ADC_NEXT_CS_MODE0             0x4000
+#define ADC_EACH_CS_MODE0             0x8000
+
+
+/********************************/
+/*   Neighbor BCCH priorities   */
+/********************************/
+
+#define TOP_PRIORITY     0
+#define HIGH_PRIORITY    1
+#define NORMAL_PRIORITY  2
+
+/********************************/
+/* Driver constants definitions */
+/********************************/
+
+// Used to identify the 1st and last burst for offset management in Drivers.
+#define BURST_1           0
+#define BURST_2           1
+#define BURST_3           2
+#define BURST_4           3
+
+
+// Identifier for all DSP tasks.
+// ...RX & TX tasks identifiers.
+#define NO_DSP_TASK        0  // No task.
+#define NP_DSP_TASK       21  // Normal Paging reading task.
+#define EP_DSP_TASK       22  // Extended Paging reading task.
+#define NBS_DSP_TASK      19  // Normal BCCH serving reading task.
+#define EBS_DSP_TASK      20  // Extended BCCH serving reading task.
+#define NBN_DSP_TASK      17  // Normal BCCH neighbour reading task.
+#define EBN_DSP_TASK      18  // Extended BCCH neighbour reading task.
+#define ALLC_DSP_TASK     24  // CCCH reading task while performing FULL BCCH/CCCH reading task.
+#define CB_DSP_TASK       25  // CBCH reading task.
+#define DDL_DSP_TASK      26  // SDCCH/D (data) reading task.
+#define ADL_DSP_TASK      27  // SDCCH/A (SACCH) reading task.
+#define DUL_DSP_TASK      12  // SDCCH/D (data) transmit task.
+#define AUL_DSP_TASK      11  // SDCCH/A (SACCH) transmit task.
+#define RACH_DSP_TASK     10  // RACH transmit task.
+#define TCHT_DSP_TASK     13  // TCH Traffic data DSP task id (RX or TX)
+#define TCHA_DSP_TASK     14  // TCH SACCH   data DSP task id (RX or TX)
+#define TCHD_DSP_TASK     28  // TCH Traffic data DSP task id (RX or TX)
+
+#define TCH_DTX_UL        15  // Replace UL task in DSP->MCU com. to say "burst not transmitted".
+
+#if (L1_GPRS)
+  // Identifier for DSP tasks Packet dedicated.
+  // ...RX & TX tasks identifiers.
+  //------------------------------------------------------------------------
+  // WARNING ... Need to aligned following macro with MCU/DSP GPRS Interface
+  //------------------------------------------------------------------------
+  #define PNP_DSP_TASK      30
+  #define PEP_DSP_TASK      31
+  #define PALLC_DSP_TASK    32
+  #define PBS_DSP_TASK      33
+
+  #define PTCCH_DSP_TASK    33
+
+#endif
+
+// Identifier for measurement, FB / SB search tasks.
+// Values 1,2,3 reserved for "number of measurements".
+#define FB_DSP_TASK        5  // Freq. Burst reading task in Idle mode.
+#define SB_DSP_TASK        6  // Sync. Burst reading task in Idle mode.
+#define TCH_FB_DSP_TASK    8  // Freq. Burst reading task in Dedicated mode.
+#define TCH_SB_DSP_TASK    9  // Sync. Burst reading task in Dedicated mode.
+#define IDLE1              1
+
+// Debug tasks
+#define CHECKSUM_DSP_TASK 33
+#define TST_NDB           35  //  Checksum DSP->MCU
+#define TST_DB            36  //  DB communication check
+#define INIT_VEGA         37
+#define DSP_LOOP_C        38
+
+// Identifier for measurement, FB / SB search tasks.
+// Values 1,2,3 reserved for "number of measurements".
+#define TCH_LOOP_A        31
+#define TCH_LOOP_B        32
+
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+  #define SC_CHKSUM_VER     (DB_W_PAGE_0 + (2 * (0x08DB - 0x800)))
+#else
+  #define SC_CHKSUM_VER     (DB_W_PAGE_0 + (2 * (0x09A0 - 0x800)))
+#endif
+
+// bits in d_gsm_bgd_mgt - background task management
+#define B_DSPBGD_RECO           1       // start of reco in dsp background
+#define B_DSPBGD_UPD            2       // start of alignement update in dsp background
+#define B_DSPBGD_STOP_RECO      256     // stop of reco in dsp background
+#define B_DSPBGD_STOP_UPD       512     // stop of alignement update in dsp background
+
+// bit in d_pll_config
+#define B_32KHZ_CALIB      (TRUE_L << 14) // force DSP in Idle1 during 32 khz calibration
+// ****************************************************************
+// NDB AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
+// ****************************************************************
+// bits in d_tch_mode
+#define B_EOTD            (TRUE_L << 0) // EOTD mode
+#define B_PLAY_UL         (TRUE_L << 3) // Play UL
+#define B_DCO_ON          (TRUE_L << 4) // DCO ON/OFF
+#define B_AUDIO_ASYNC     (TRUE_L << 1) // WCP reserved
+
+// ****************************************************************
+// PARAMETER AREA (PARAM) MCU<->DSP COMMUNICATION DEFINITIONS
+// ****************************************************************
+#define C_POND_RED              1L
+// below values are defined in the file l1_time.h
+//#define D_NSUBB_IDLE            296L
+//#define D_NSUBB_DEDIC           30L
+#define D_FB_THR_DET_IACQ       0x3333L
+#define D_FB_THR_DET_TRACK      0x28f6L
+#define D_DC_OFF_THRES          0x7fffL
+#define D_DUMMY_THRES           17408L
+#define D_DEM_POND_GEWL         26624L
+#define D_DEM_POND_RED          20152L
+#define D_HOLE                  0L
+#define D_TRANSFER_RATE         0x6666L
+
+// Full Rate vocoder definitions.
+#define D_MACCTHRESH1           7872L
+#define D_MLDT                  -4L
+#define D_MACCTHRESH            7872L
+#define D_GU                    5772L
+#define D_GO                    7872L
+#define D_ATTMAX                53L
+#define D_SM                    -892L
+#define D_B                     208L
+#define D_SD_MIN_THR_TCHFS      15L                   //(24L   *C_POND_RED)
+#define D_MA_MIN_THR_TCHFS      738L                  //(1200L *C_POND_RED)
+#define D_MD_MAX_THR_TCHFS      1700L                 //(2000L *C_POND_RED)
+#define D_MD1_MAX_THR_TCHFS     99L                   //(160L  *C_POND_RED)
+
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+  // Frequency burst definitions
+  #define D_FB_MARGIN_BEG         24
+  #define D_FB_MARGIN_END         22
+
+  // V42bis definitions
+  #define D_V42B_SWITCH_HYST      16L
+  #define D_V42B_SWITCH_MIN       64L
+  #define D_V42B_SWITCH_MAX       250L
+  #define D_V42B_RESET_DELAY      10L
+
+  // Latencies definitions
+  #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+    // C.f. BUG1404
+    #define D_LAT_MCU_BRIDGE        0x000FL
+  #else
+  #define D_LAT_MCU_BRIDGE        0x0009L
+  #endif
+
+  #define D_LAT_MCU_HOM2SAM       0x000CL
+
+  #define D_LAT_MCU_BEF_FAST_ACCESS 0x0005L
+  #define D_LAT_DSP_AFTER_SAM     0x0004L
+
+  // Background Task in GSM mode: Initialization.
+  #define D_GSM_BGD_MGT           0L
+
+#if (CHIPSET == 4)
+  #define D_MISC_CONFIG           0L
+#elif (CHIPSET == 7)  || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
+  #define D_MISC_CONFIG           1L
+#else
+  #define D_MISC_CONFIG           0L
+#endif
+
+#endif
+
+// Hall Rate vocoder and ched definitions.
+
+#define D_SD_MIN_THR_TCHHS      37L
+#define D_MA_MIN_THR_TCHHS      344L
+#define D_MD_MAX_THR_TCHHS      2175L
+#define D_MD1_MAX_THR_TCHHS     138L
+#define D_SD_AV_THR_TCHHS       1845L
+#define D_WED_FIL_TC            0x7c00L
+#define D_WED_FIL_INI           4650L
+#define D_X_MIN                 15L
+#define D_X_MAX                 23L
+#define D_Y_MIN                 703L
+#define D_Y_MAX                 2460L
+#define D_SLOPE                 135L
+#define D_WED_DIFF_THRESHOLD    406L
+#define D_MABFI_MIN_THR_TCHHS   5320L
+#define D_LDT_HR                -5
+#define D_MACCTRESH_HR          6500
+#define D_MACCTRESH1_HR         6500
+#define D_GU_HR                 2620
+#define D_GO_HR                 3700
+#define D_B_HR                  182
+#define D_SM_HR                 -1608
+#define D_ATTMAX_HR             53
+
+// Enhanced Full Rate vocoder and ched definitions.
+
+#define C_MLDT_EFR              -4
+#define C_MACCTHRESH_EFR        8000
+#define C_MACCTHRESH1_EFR       8000
+#define C_GU_EFR                4522
+#define C_GO_EFR                6500
+#define C_B_EFR                 174
+#define C_SM_EFR                -878
+#define C_ATTMAX_EFR            53
+#define D_SD_MIN_THR_TCHEFS     15L                   //(24L   *C_POND_RED)
+#define D_MA_MIN_THR_TCHEFS     738L                  //(1200L *C_POND_RED)
+#define D_MD_MAX_THR_TCHEFS     1230L                 //(2000L *C_POND_RED)
+#define D_MD1_MAX_THR_TCHEFS    99L                   //(160L  *C_POND_RED)
+
+
+// Integrated Data Services definitions.
+#define D_MAX_OVSPD_UL          8
+// Detect frames containing 90% of 1s as synchro frames
+#define D_SYNC_THRES            0x3f50
+// IDLE frames are only frames with 100 % of 1s
+#define D_IDLE_THRES            0x4000
+#define D_M1_THRES              5
+#define D_MAX_OVSP_DL           8
+
+// d_ra_act: bit field definition
+#define B_F48BLK                5
+
+// Mask for b_itc information (d_ra_conf)
+#define CE_MASK                 0x04
+
+#define D_FACCH_THR             0
+#define D_DSP_TEST              0
+#define D_VERSION_NUMBER        0
+#define D_TI_VERSION            0
+
+
+/*------------------------------------------------------------------------------*/
+/*                                                                              */
+/*                 DEFINITIONS FOR DSP <-> MCU COMMUNICATION.                   */
+/*                 ++++++++++++++++++++++++++++++++++++++++++                   */
+/*                                                                              */
+/*------------------------------------------------------------------------------*/
+// COMMUNICATION Interrupt definition
+//------------------------------------
+#define ALL_16BIT          0xffffL
+#define B_GSM_PAGE         (TRUE_L << 0)
+#define B_GSM_TASK         (TRUE_L << 1)
+#define B_MISC_PAGE        (TRUE_L << 2)
+#define B_MISC_TASK        (TRUE_L << 3)
+
+#define B_GSM_PAGE_MASK    (ALL_16BIT ^ B_GSM_PAGE)
+#define B_GSM_TASK_MASK    (ALL_16BIT ^ B_GSM_TASK)
+#define B_MISC_PAGE_MASK   (ALL_16BIT ^ B_MISC_PAGE)
+#define B_MISC_TASK_MASK   (ALL_16BIT ^ B_MISC_TASK)
+
+// Common definition
+//----------------------------------
+// Index to *_DEMOD* arrays.
+#define D_TOA                    0  // Time Of Arrival.
+#define D_PM                     1  // Power Measurement.
+#define D_ANGLE                  2  // Angle (AFC correction)
+#define D_SNR                    3  // Signal / Noise Ratio.
+
+// Bit name/position definitions.
+#define B_FIRE0                  5  // Fire result bit 0. (00 -> NO ERROR) (01 -> ERROR CORRECTED)
+#define B_FIRE1                  6  // Fire result bit 1. (10 -> ERROR)    (11 -> unused)
+#define B_SCH_CRC                8  // CRC result for SB decoding. (1 for ERROR).
+#define B_BLUD                  15  // Uplink,Downlink data block Present. (1 for PRESENT).
+#define B_AF                    14  // Activity bit: 1 if data block is valid.
+#define B_BFI                    2  // Bad Frame Indicator
+#define B_UFI                    0  // UNRELIABLE FRAME Indicator
+#define B_ECRC                   9  // Enhanced full rate CRC bit
+#define B_EMPTY_BLOCK           10  // for voice memo purpose, this bit is used to determine
+
+#if (DEBUG_DEDIC_TCH_BLOCK_STAT == 1)
+  #define FACCH_GOOD 10
+  #define FACCH_BAD  11
+#endif
+
+#if (AMR == 1)
+  // Place of the RX type in the AMR block header
+  #define RX_TYPE_SHIFT           3
+  #define RX_TYPE_MASK            0x0038
+
+  // Place of the vocoder type in the AMR block header
+  #define VOCODER_TYPE_SHIFT      0
+  #define VOCODER_TYPE_MASK       0x0007
+
+  // List of the possible RX types in a_dd block
+  #define SPEECH_GOOD             0
+  #define SPEECH_DEGRADED         1
+  #define ONSET                   2
+  #define SPEECH_BAD              3
+  #define SID_FIRST               4
+  #define SID_UPDATE              5
+  #define SID_BAD                 6
+  #define AMR_NO_DATA             7
+  #define AMR_INHIBIT             8
+
+  // List of possible RX types in RATSCCH block
+  #define C_RATSCCH_GOOD          5
+
+  // List of the possible AMR channel rate
+  #define AMR_CHANNEL_4_75        0
+  #define AMR_CHANNEL_5_15        1
+  #define AMR_CHANNEL_5_9         2
+  #define AMR_CHANNEL_6_7         3
+  #define AMR_CHANNEL_7_4         4
+  #define AMR_CHANNEL_7_95        5
+  #define AMR_CHANNEL_10_2        6
+  #define AMR_CHANNEL_12_2        7
+
+  // Types of RATSCCH blocks
+  #define C_RATSCCH_UNKNOWN                   0
+  #define C_RATSCCH_CMI_PHASE_REQ             1
+  #define C_RATSCCH_AMR_CONFIG_REQ_MAIN       2
+  #define C_RATSCCH_AMR_CONFIG_REQ_ALT        3
+  #define C_RATSCCH_AMR_CONFIG_REQ_ALT_IGNORE 4    // Alternative AMR_CONFIG_REQ with updates coming in the next THRES_REQ block
+  #define C_RATSCCH_THRES_REQ                 5
+
+  // These flags define a bitmap that indicates which AMR parameters are being modified by a RATSCCH
+  #define C_AMR_CHANGE_CMIP  0
+  #define C_AMR_CHANGE_ACS   1
+  #define C_AMR_CHANGE_ICM   2
+  #define C_AMR_CHANGE_THR1  3
+  #define C_AMR_CHANGE_THR2  4
+  #define C_AMR_CHANGE_THR3  5
+  #define C_AMR_CHANGE_HYST1 6
+  #define C_AMR_CHANGE_HYST2 7
+  #define C_AMR_CHANGE_HYST3 8
+
+  // CMIP default value
+  #define C_AMR_CMIP_DEFAULT 1  // According to ETSI specification 05.09, cmip is always 1 by default (new channel, handover...)
+
+#endif
+// "d_ctrl_tch" bits positions for TCH configuration.
+#define B_CHAN_MODE              0
+#define B_CHAN_TYPE              4
+#define B_RESET_SACCH            6
+#define B_VOCODER_ON             7
+#define B_SYNC_TCH_UL            8
+#if (AMR == 1)
+  #define B_SYNC_AMR               9
+#else
+#define B_SYNC_TCH_DL            9
+#endif
+#define B_STOP_TCH_UL           10
+#define B_STOP_TCH_DL           11
+#define B_TCH_LOOP              12
+#define B_SUBCHANNEL            15
+
+// "d_ctrl_abb" bits positions for conditionnal loading of abb registers.
+#define B_RAMP                   0
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
+  #define B_BULRAMPDEL             3 // Note: this name is changed
+  #define B_BULRAMPDEL2            2 // Note: this name is changed
+  #define B_BULRAMPDEL_BIS         9
+  #define B_BULRAMPDEL2_BIS       10
+#endif
+#define B_AFC                    4
+
+// "d_ctrl_system" bits positions.
+#define B_TSQ                    0
+#define B_BCCH_FREQ_IND          3
+#define B_TASK_ABORT            15  // Abort RF tasks for DSP.
+
+// ****************************************************************
+// POLESTAR EVABOARD 3 REGISTERS & ADRESSES  DEFINITIONS
+// ****************************************************************
+
+
+  //  DSP ADRESSES
+  //--------------------
+
+  #define DB_SIZE                 (4*20L)     // 4 pages of 20 words...
+
+  #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+    #define DB_W_PAGE_0          0xFFD00000L   // DB page 0 write : 20 words long
+    #define DB_W_PAGE_1          0xFFD00028L   // DB page 1 write : 20 words long
+    #define DB_R_PAGE_0          0xFFD00050L   // DB page 0 read  : 20 words long
+    #define DB_R_PAGE_1          0xFFD00078L   // DB page 1 read  : 20 words long
+    #define NDB_ADR              0xFFD001A8L   // NDB start address : 268 words
+    #define PARAM_ADR            0xFFD00862L   // PARAM start address  : 57 words
+
+    #if (DSP_DEBUG_TRACE_ENABLE == 1)
+      #define DB2_R_PAGE_0       0xFFD00184L
+      #define DB2_R_PAGE_1       0xFFD00188L
+    #endif
+  #else
+    #define DB_W_PAGE_0          0xFFD00000L   // DB page 0 write : 20 words long
+    #define DB_W_PAGE_1          0xFFD00028L   // DB page 1 write : 20 words long
+    #define DB_R_PAGE_0          0xFFD00050L   // DB page 0 read  : 20 words long
+    #define DB_R_PAGE_1          0xFFD00078L   // DB page 1 read  : 20 words long
+    #define NDB_ADR              0xFFD000a0L   // NDB start address : 268 words
+    #define PARAM_ADR            0xFFD002b8L   // PARAM start address  : 57 words
+  #endif
+
+// ****************************************************************
+// ADC reading definitions
+// ****************************************************************
+
+#define ADC_READ_PERIOD (40)   //30 * 4.615 = 140ms
+
+
+// ****************************************************************
+// AGC: IL table identifier used by function Cust_get_agc_from_IL
+// ****************************************************************
+#define MAX_ID     1
+#define AV_ID      2
+#define PWR_ID     3
+
+#if TESTMODE
+  // ****************************************************************
+  // Testmode: State of the continous mode
+  // ****************************************************************
+  #define TM_NO_CONTINUOUS        1   // continuous mode isn't active
+  #define TM_START_RX_CONTINUOUS  2   // start the Rx continuous mode
+  #define TM_START_TX_CONTINUOUS  3   // start the Tx continuous mode
+  #define TM_CONTINUOUS           4   // Rx or Tx continuous mode
+#endif
+#if (AMR == 1)
+  // ****************************************************************
+  // AMR: Position of each AMR parameters in the AMR API buffer
+  // ****************************************************************
+  #define NSCB_INDEX    0
+  #define NSCB_SHIFT    6
+  #define ICMUL_INDEX   0
+  #define ICMUL_SHIFT   4
+  #define ICMDL_INDEX   0
+  #define ICMDL_SHIFT   1
+  #define ICMIUL_INDEX  0
+  #define ICMIUL_SHIFT  3
+  #define ICMIDL_INDEX  0
+  #define ICMIDL_SHIFT  0
+  #define ACSUL_INDEX   1
+  #define ACSUL_SHIFT   0
+  #define ACSDL_INDEX   1
+  #define ACSDL_SHIFT   8
+  #define THR1_INDEX    2
+  #define THR1_SHIFT    0
+  #define THR2_INDEX    2
+  #define THR2_SHIFT    6
+  #define THR3_INDEX    3
+  #define THR3_SHIFT    8
+  #define HYST1_INDEX   3
+  #define HYST1_SHIFT   0
+  #define HYST2_INDEX   3
+  #define HYST2_SHIFT   4
+  #define HYST3_INDEX   2
+  #define HYST3_SHIFT   12
+  #define NSYNC_INDEX   3
+  #define NSYNC_SHIFT   14
+  #define CMIP_INDEX    3
+  #define CMIP_SHIFT    15
+
+  #define NSCB_MASK     0x0001
+  #define ICM_MASK      0x0003
+  #define ICMI_MASK     0x0001
+  #define ACS_MASK      0x00FF
+  #define THR_MASK      0x003F
+  #define HYST_MASK     0x000F
+  #define CMIP_MASK     0x0001
+#endif
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_ctl.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_ctl.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,59 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_CTL.H
+ *
+ *        Filename l1_ctl.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+/************************************/
+/* Automatic timing control (TOA)   */
+/************************************/
+#define  C_RED              1   // Factor used to reduce the maximum accumulated values. 
+                                // Default : 1/2 
+#define  C_GEW              1   // Weighting factor. Default : 1/2   
+
+#define  C_SNRGR         2560   // 2.5 F6.10
+#define  C_SNR_THR       8192   // 8   F6.10
+#define  TOA_HISTO_LEN   11     // Histogram length          
+
+/************************************/
+/* Automatic Gain Control (AGC)     */
+/************************************/
+
+#define INDEX_MIN           0
+#define INDEX_MAX         240   // 120
+
+/************************************/
+/* Automatic frequency compensation */
+/************************************/
+#define  C_thr_snr        2560     //  1/0.4    * 2**10               
+#define  C_thr_P          524288L  //  0.5      * 2**20               
+#define  C_cov_start      838861L  //  0.8      * 2**20               
+#define  C_a0_kalman      10486L   //  0.01     * 2**20               
+#define  C_g_kalman       53687091L//  0.05     * 2**30               
+#define  C_N_del          2        //  delay of frequency control loop
+                                   //  due to C W R pipeline          
+#define  C_Q              3L       //  0.000003 * 2**20               
+#define  C_thr_K          209715L  //  0.2      * 2**20               
+#define  C_thr_phi        328      //  0.01     * 2**15
+
+#if (VCXO_ALGO == 1)
+  #define  C_WIN_AVG_SIZE_M       64  // average size M
+  #define  C_PSI_AVG_SIZE_D       32  // distance size D
+  #define  C_MSIZE                (C_WIN_AVG_SIZE_M * C_PSI_AVG_SIZE_D) // Data history for predictor
+  #define  C_RGAP_BAD_SNR_COUNT_B 32  // bad SNR count B 
+  #define  ALGO_AFC_RXGAP            1  // reception gap algo
+  #define  ALGO_AFC_KALMAN           1  // Kalman filter
+  #define  ALGO_AFC_LQG_PREDICTOR    2  // LQG filter + rgap predictor
+  #define  ALGO_AFC_KALMAN_PREDICTOR 3 // Kalman filter + rgap predictor
+#endif
+
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+   // clipping related to AFC DAC linearity range
+  #define  C_max_step        32000   //   4000 * 2**3                    
+  #define  C_min_step       -32000   //  -4000 * 2**3                   
+#endif
+
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_defty.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_defty.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,2939 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software
+ * L1_DEFTY.H
+ *
+ *        Filename l1_defty.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+#if(L1_DYN_DSP_DWNLD == 1)
+  #include "l1_dyn_dwl_defty.h"
+#endif
+
+typedef struct
+{
+  UWORD16  modulus;
+  UWORD16  relative_position;
+}
+T_BCCHS_SCHEDULE;
+
+typedef struct
+{
+  UWORD8            schedule_array_size;
+  T_BCCHS_SCHEDULE  schedule_array[10];
+}
+T_BCCHS;
+
+typedef struct
+{
+  BOOL        status;
+  UWORD16     radio_freq;
+  UWORD32     fn_offset;
+  UWORD32     time_alignmt;
+  UWORD8      sb26_attempt;
+  UWORD8      tsc;
+  UWORD16     bcch_blks_req;
+  UWORD8      timing_validity;
+  UWORD8      search_mode;
+  UWORD8      gprs_priority;
+  UWORD8      sb26_offset; // Set to 1 when SB26 RX win is entirely in frame 25.
+#if (L1_12NEIGH ==1)
+  UWORD32     fn_offset_mem;
+  UWORD32     time_alignmt_mem;
+#endif
+}
+T_NCELL_SINGLE;
+
+typedef struct
+{
+  UWORD8          active_neigh_id_norm;
+  UWORD8          active_neigh_tc_norm;
+  UWORD8          active_neigh_id_top;
+  UWORD8          active_neigh_tc_top;
+  UWORD8          current_list_size;
+  T_NCELL_SINGLE  list[6];
+}
+T_BCCHN_LIST;
+
+typedef struct
+{
+  UWORD8          active_fb_id;
+  UWORD8          active_sbconf_id;
+  UWORD8          active_sb_id;
+  UWORD8          current_list_size;
+  UWORD8          first_in_list;  //point at oldest element in list. Used when parsing the list.
+#if (L1_EOTD==1)
+  #if L1_EOTD_QBIT_ACC
+    // Store serving fn_offset and time_alignmt, so that they can be tracked
+    // independently.
+    UWORD32  serv_fn_offset;
+    UWORD32       serv_time_alignmt;
+  #endif
+  // Need to track any TOA updates in dedicated mode else
+  // QB errors are introduced in the results...
+
+  UWORD8          eotd_toa_phase;
+  WORD32          eotd_toa_tracking;
+  WORD32          eotd_cache_toa_tracking;
+
+  UWORD8          eotd_meas_session;
+  UWORD32         fn_sb_serv;       // for methods 1 & 2
+  UWORD32         ta_sb_serv;       // for methods 1 & 2
+  WORD32          teotdS;           // for method 2 only
+  UWORD32         fn_offset_serv;   // for method 2 only
+#endif
+#if (L1_12NEIGH==1)
+  T_NCELL_SINGLE  list[NBR_NEIGHBOURS+1]; // 1 place (13th) for S.C in EOTD.
+#else
+  T_NCELL_SINGLE  list[6];
+#endif
+}
+T_NSYNC_LIST;
+
+typedef struct
+{
+  UWORD8   cbch_state;
+  UWORD32  starting_fn;
+  UWORD32  first_block[48];
+  UWORD8   cbch_num;
+  UWORD8   schedule_length;
+  UWORD8   next;
+  WORD32   start_continuous_fn;
+}
+T_CBCH_HEAD_SCHEDULE;
+
+typedef struct
+{
+  UWORD8   cbch_num;
+  UWORD8   next;
+  UWORD32  start_fn[6];
+}
+T_CBCH_INFO_SCHEDULE;
+
+/*=========================================================================*/
+/* Moved type definitions from Debis files.                                */
+/*=========================================================================*/
+#if (AMR == 1)
+  // AMR ver 1.0 parameters
+  typedef struct
+  {
+    BOOL    noise_suppression_bit;
+    BOOL    initial_codec_mode_indicator;
+    UWORD8  initial_codec_mode;
+    UWORD8  active_codec_set;
+    UWORD8  threshold[3];
+    UWORD8  hysteresis[3];
+  }
+  T_AMR_CONFIGURATION;
+#endif
+
+typedef struct
+{
+  UWORD8  A[7+1];
+}
+T_ENCRYPTION_KEY;
+
+typedef struct
+{
+  UWORD8  A[22+1];
+}
+T_RADIO_FRAME;
+
+typedef struct
+{
+  UWORD8  n32;
+  UWORD8  n51;
+  UWORD8  n26;
+}
+T_SHORT_FRAME_NUMBER;
+
+typedef struct
+{
+  UWORD16  A[31+1];
+}
+T_CHAN_LIST;
+
+typedef struct
+{
+  UWORD16      num_of_chans;
+  T_CHAN_LIST  chan_number;
+}
+T_BCCH_LIST;
+
+typedef struct
+{
+  UWORD16        rf_chan_num;
+  UWORD8         l2_channel_type;
+  UWORD8         error_cause;
+  T_RADIO_FRAME  l2_frame;
+  UWORD8         bsic;
+  UWORD8         tc;
+}
+T_PH_DATA_IND;
+
+typedef struct
+{
+  UWORD16  A[63+1];
+}
+T_MA_FIELD;
+
+typedef struct
+{
+  UWORD16     rf_chan_cnt;
+  T_MA_FIELD  rf_chan_no;
+}
+T_MOBILE_ALLOCATION;
+
+typedef struct
+{
+  BOOL                  start_time_present;
+  T_SHORT_FRAME_NUMBER  start_time;
+}
+T_STARTING_TIME;
+
+typedef struct
+{
+  UWORD16  radio_freq_no;
+  WORD8   rxlev;
+}
+T_RXLEV_MEAS;
+
+typedef struct
+{
+  UWORD8  maio;
+  UWORD8  hsn;
+}
+T_HOPPING_RF;
+
+typedef struct
+{
+  UWORD16  radio_freq;
+}
+T_SINGLE_RF;
+
+typedef union
+{
+  T_SINGLE_RF   single_rf;
+  T_HOPPING_RF  hopping_rf;
+}
+T_CHN_SEL_CHOICE;
+
+typedef struct
+{
+  BOOL              h;
+  T_CHN_SEL_CHOICE  rf_channel;
+}
+T_CHN_SEL;
+
+typedef struct
+{
+    T_CHN_SEL  chan_sel;
+    UWORD8     channel_type;
+    UWORD8     subchannel;
+    UWORD8     timeslot_no;
+    UWORD8     tsc;
+}
+T_CHANNEL_DESCRIPTION;
+
+typedef struct
+{
+  UWORD8   ncc;
+  UWORD8   bcc;
+  UWORD16  bcch_carrier;
+}
+T_CELL_DESC;
+
+typedef struct
+{
+  T_CELL_DESC            cell_description;
+  T_CHANNEL_DESCRIPTION  channel_desc_1;
+  UWORD8                 channel_mode_1;
+  T_STARTING_TIME        starting_time;
+  UWORD8                 ho_acc;
+  UWORD8                 txpwr;
+  BOOL                   report_time_diff;
+  T_MOBILE_ALLOCATION    frequency_list;
+  T_CHANNEL_DESCRIPTION  channel_desc_2;
+  UWORD8                 channel_mode_2;
+  T_MOBILE_ALLOCATION    frequency_list_bef_sti;
+  T_CHANNEL_DESCRIPTION  channel_desc_1_bef_sti;
+  T_CHANNEL_DESCRIPTION  channel_desc_2_bef_sti;
+  BOOL                   cipher_mode;
+  UWORD8                 a5_algorithm;
+}
+T_HO_PARAMS;
+
+typedef struct
+{
+    T_CHANNEL_DESCRIPTION  channel_desc;
+    T_MOBILE_ALLOCATION    frequency_list;
+    T_STARTING_TIME        starting_time;
+}
+T_MPHC_CHANGE_FREQUENCY;
+
+typedef struct
+{
+  UWORD8  subchannel;
+  UWORD8  channel_mode;
+  #if (AMR == 1)
+    T_AMR_CONFIGURATION  amr_configuration;
+  #endif
+}
+T_MPHC_CHANNEL_MODE_MODIFY_REQ;
+
+typedef struct
+{
+  UWORD8            cipher_mode;
+  UWORD8            a5_algorithm;
+  T_ENCRYPTION_KEY  new_ciph_param;
+}
+T_MPHC_SET_CIPHERING_REQ;
+
+typedef struct
+{
+  UWORD8  sub_channel;
+  UWORD8  frame_erasure;
+}
+T_OML1_CLOSE_TCH_LOOP_REQ;
+
+typedef struct
+{
+  #if (defined _WINDOWS && (OP_RIV_AUDIO == 1))
+    T_RV_HDR  header;
+  #endif
+  UWORD8  tested_device;
+}
+T_OML1_START_DAI_TEST_REQ;
+
+/***********************************************************/
+/* Type definitions for DEBUG...                           */
+/***********************************************************/
+typedef struct                  // translate string in int and int in string
+{
+  CHAR *message;
+  WORD32  SignalCode;
+  WORD32  size;
+}
+MSG_DEBUG;
+
+typedef struct                  // translate string in int and int in string
+{
+  CHAR *name;
+}
+TASK_TRACE;
+
+/***********************************************************/
+/* Type definitions for data structures used for MFTAB     */
+/* managment...                                            */
+/***********************************************************/
+typedef struct
+{
+  void   (*fct_ptr)(UWORD8,UWORD8);
+  CHAR   param1;
+  CHAR   param2;
+}
+T_FCT;
+
+typedef struct
+{
+  T_FCT  fct[L1_MAX_FCT];
+}
+T_FRM;
+
+typedef struct
+{
+  T_FRM  frmlst[MFTAB_SIZE];
+}
+T_MFTAB;
+
+typedef struct
+{
+  const T_FCT    *address;
+  UWORD8  size;
+}
+T_TASK_MFTAB;
+
+/***********************************************************/
+/* TPU controle register components definition.            */
+/***********************************************************/
+
+#if (CODE_VERSION==SIMULATION)
+  typedef struct                      // contents of REG_CMD register
+  {
+    unsigned int  tpu_reset_bit : 1;  // TPU_RESET bit : ON (reset TPU)
+    unsigned int  tpu_pag_bit   : 1;  // TPU_PAG   bit : 0  (page 0)
+    unsigned int  tpu_enb_bit   : 1;  // TPU_ENB   bit : ON (TPU commun.int.)
+    unsigned int  dsp_pag_bit   : 1;  // DSP_PAG   bit : 0  (page 0)
+    unsigned int  dsp_enb_bit   : 1;  // DSP_ENB   bit : ON (DSP commun.int.)
+    unsigned int  tpu_stat_bit  : 1;  // TPU_STAT  bit : ON (if TPU active) OFF (if TPU in IDLE)
+    unsigned int  tpu_idle_bit  : 1;  // TPU_IDLE  bit : ON (force IDLE mode)
+  }
+  T_reg_cmd;  // Rem: we must keep "unsigned int" type for bitmap.
+#else
+  typedef struct                      // contents of REG_CMD register
+  {
+    unsigned int  tpu_reset_bit : 1;  // TPU_RESET bit : ON (reset TPU)
+    unsigned int  tpu_pag_bit   : 1;  // TPU_PAG   bit : 0  (page 0)
+    unsigned int  tpu_enb_bit   : 1;  // TPU_ENB   bit : ON (TPU commun.int.)
+    unsigned int  unused_1      : 1;  //
+    unsigned int  dsp_enb_bit   : 1;  // DSP_ENB   bit : ON (DSP commun.int.)
+    unsigned int  unused_2      : 1;  //
+    unsigned int  unused_3      : 1;  //
+    unsigned int  tsp_reset_bit : 1;  // TSP_RESET bit : ON (reset TSP)
+    unsigned int  tpu_idle_bit  : 1;  // TPU_IDLE  bit : ON (force IDLE mode)
+    unsigned int  tup_wait_bit  : 1;  // TPU_WAIT  bit : ON (TPU ready)
+    unsigned int  tpu_ck_enb_bit: 1;  // TPU_CLK   bit : ON (TPU clock on)
+  }
+    T_reg_cmd;
+#endif
+/***********************************************************/
+/*                                                         */
+/*  Data structure for global info components.             */
+/*                                                         */
+/***********************************************************/
+
+typedef struct
+{
+  API d_task_d;           // (0)  Downlink task command.
+  API d_burst_d;          // (1)  Downlink burst identifier.
+  API d_task_u;           // (2)  Uplink task command.
+  API d_burst_u;          // (3)  Uplink burst identifier.
+  API d_task_md;          // (4)  Downlink Monitoring (FB/SB) command.
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+  API d_background;       // (5) Background tasks
+#else
+  API d_reserved;         // (5)  Reserved
+#endif
+  API d_debug;            // (6)  Debug/Acknowledge/general purpose word.
+  API d_task_ra;          // (7)  RA task command.
+  API d_fn;               // (8)  FN, in Rep. period and FN%104, used for TRAFFIC/TCH only.
+                             //        bit [0..7]  -> b_fn_report, FN in the normalized reporting period.
+                             //        bit [8..15] -> b_fn_sid,    FN % 104, used for SID positionning.
+  API d_ctrl_tch;         // (9)  Tch channel description.
+                             //        bit [0..3]  -> b_chan_mode,    channel  mode.
+                             //        bit [4..5]  -> b_chan_type,    channel type.
+                             //        bit [6]     -> reset SACCH
+                             //        bit [7]     -> vocoder ON
+                             //        bit [8]     -> b_sync_tch_ul,  synchro. TCH/UL.
+                             //        bit [9]     -> b_sync_tch_dl,  synchro. TCH/DL.
+                             //        bit [10]    -> b_stop_tch_ul,  stop TCH/UL.
+                             //        bit [11]    -> b_stop_tch_dl,  stop TCH/DL.
+                             //        bit [12.13] -> b_tch_loop,     tch loops A/B/C.
+  API hole;               // (10) unused hole.
+
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+  API d_ctrl_abb;         // (11) Bit field indicating the analog baseband register to send.
+                             //        bit [0]     -> b_ramp: the ramp information(a_ramp[]) is located in NDB
+                             //        bit [1.2]   -> unused
+                             //        bit [3]     -> b_apcdel: delays-register in NDB
+                             //        bit [4]     -> b_afc: freq control register in DB
+                             //        bit [5..15] -> unused
+#endif
+  API a_a5fn[2];          // (12..13) Encryption Frame number.
+                             //        word 0, bit [0..4]  -> T2.
+                             //        word 0, bit [5..10] -> T3.
+                             //        word 1, bit [0..11] -> T1.
+  API d_power_ctl;        // (14) Power level control.
+  API d_afc;              // (15) AFC value (enabled by "b_afc" in "d_ctrl_TCM4400 or in d_ctrl_abb").
+  API d_ctrl_system;      // (16) Controle Register for RESET/RESUME.
+                             //        bit [0..2] -> b_tsq,           training sequence.
+                             //        bit [3]    -> b_bcch_freq_ind, BCCH frequency indication.
+                             //        bit [15]   -> b_task_abort,    DSP task abort command.
+}
+T_DB_MCU_TO_DSP;
+
+typedef struct
+{
+  API d_task_d;           // (0) Downlink task command.
+  API d_burst_d;          // (1) Downlink burst identifier.
+  API d_task_u;           // (2) Uplink task command.
+  API d_burst_u;          // (3) Uplink burst identifier.
+  API d_task_md;          // (4) Downlink Monitoring (FB/SB) task command.
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+  API d_background;       // (5) Background tasks
+#else
+  API d_reserved;         // (5)  Reserved
+#endif
+  API d_debug;            // (6) Debug/Acknowledge/general purpose word.
+  API d_task_ra;          // (7) RA task command.
+
+#if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 36)
+  API a_serv_demod[4];    // ( 8..11) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
+  API a_pm[3];            // (12..14) Power measurement results, array of 3 words.
+  API a_sch[5];           // (15..19) Header + SB information, array of  5 words.
+#else
+  API a_pm[3];            // ( 8..10) Power measurement results, array of 3 words.
+  API a_serv_demod[4];    // (11..14) Serv. cell demod. result, array of 4 words (D_TOA,D_PM,D_ANGLE,D_SNR).
+  API a_sch[5];           // (15..19) Header + SB information, array of  5 words.
+#endif
+}
+T_DB_DSP_TO_MCU;
+
+#if (DSP == 34) || (DSP == 35) || (DSP == 36) // NDB GSM
+  typedef struct
+  {
+    // MISC Tasks
+    API d_dsp_page;
+
+    // DSP status returned (DSP --> MCU).
+    API d_error_status;
+
+    // RIF control (MCU -> DSP).
+    API d_spcx_rif;
+
+    API d_tch_mode;  // TCH mode register.
+                     // bit [0..1]  -> b_dai_mode.
+                     // bit [2]     -> b_dtx.
+
+    API d_debug1;                // bit 0 at 1 enable dsp f_tx delay for Omega
+
+    API d_dsp_test;
+
+    // Words dedicated to Software version (DSP code + Patch)
+    API d_version_number1;
+    API d_version_number2;
+
+    API d_debug_ptr;
+    API d_debug_bk;
+
+    API d_pll_config;
+
+    // GSM/GPRS DSP Debug trace support
+    API p_debug_buffer;
+    API d_debug_buffer_size;
+    API d_debug_trace_type;
+
+    #if (W_A_DSP_IDLE3 == 1)
+      // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
+      API d_dsp_state;
+      // 5 words are reserved for any possible mapping modification
+      API d_hole1_ndb[2];
+    #else
+      // 6 words are reserved for any possible mapping modification
+      API d_hole1_ndb[3];
+    #endif
+
+    #if (AMR == 1)
+      API p_debug_amr;
+    #else
+      API d_hole_debug_amr;
+    #endif
+
+    #if (CHIPSET == 12)
+      #if (DSP == 35) || (DSP == 36)
+        API d_hole2_ndb[1];
+        API d_mcsi_select;
+      #else
+        API d_hole2_ndb[2];
+      #endif
+    #else
+      API d_hole2_ndb[2];
+    #endif
+
+    // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
+    API d_apcdel1_bis;
+    API d_apcdel2_bis;
+
+
+    // New registers due to IOTA analog base band
+    API d_apcdel2;
+    API d_vbctrl2;
+    API d_bulgcal;
+
+    // Analog Based Band
+    API d_afcctladd;
+
+    API d_vbuctrl;
+    API d_vbdctrl;
+    API d_apcdel1;
+    API d_apcoff;
+    API d_bulioff;
+    API d_bulqoff;
+    API d_dai_onoff;
+    API d_auxdac;
+
+  #if (ANLG_FAM == 1)
+    API d_vbctrl;
+  #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+    API d_vbctrl1;
+  #endif
+  
+    API d_bbctrl;
+
+    // Monitoring tasks control (MCU <- DSP)
+    // FB task
+    API d_fb_det;           // FB detection result. (1 for FOUND).
+    API d_fb_mode;          // Mode for FB detection algorithm.
+    API a_sync_demod[4];    // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
+
+    // SB Task
+    API a_sch26[5];         // Header + SB information, array of  5 words.
+
+    API d_audio_gain_ul;
+    API d_audio_gain_dl;
+
+    // Controller of the melody E2 audio compressor
+    API d_audio_compressor_ctrl;
+
+    // AUDIO module
+    API d_audio_init;
+    API d_audio_status;
+
+    // Audio tasks
+    // TONES (MCU -> DSP)
+    API d_toneskb_init;
+    API d_toneskb_status;
+    API d_k_x1_t0;
+    API d_k_x1_t1;
+    API d_k_x1_t2;
+    API d_pe_rep;
+    API d_pe_off;
+    API d_se_off;
+    API d_bu_off;
+    API d_t0_on;
+    API d_t0_off;
+    API d_t1_on;
+    API d_t1_off;
+    API d_t2_on;
+    API d_t2_off;
+    API d_k_x1_kt0;
+    API d_k_x1_kt1;
+    API d_dur_kb;
+    API d_shiftdl;
+    API d_shiftul;
+
+    API d_aec_ctrl;
+
+    API d_es_level_api;
+    API d_mu_api;
+
+    // Melody Ringer module
+    API d_melo_osc_used;
+    API d_melo_osc_active;
+    API a_melo_note0[4];
+    API a_melo_note1[4];
+    API a_melo_note2[4];
+    API a_melo_note3[4];
+    API a_melo_note4[4];
+    API a_melo_note5[4];
+    API a_melo_note6[4];
+    API a_melo_note7[4];
+
+    // selection of the melody format
+    API d_melody_selection;
+
+    // Holes due to the format melody E1
+    API a_melo_holes[3];
+
+    // Speech Recognition module
+    API d_sr_status;          // status of the DSP speech reco task
+    API d_sr_param;           // paramters for the DSP speech reco task: OOV threshold.
+    API d_sr_bit_exact_test;  // bit exact test
+    API d_sr_nb_words;        // number of words used in the speech recognition task
+    API d_sr_db_level;        // estimate voice level in dB
+    API d_sr_db_noise;        // estimate noise in dB
+    API d_sr_mod_size;        // size of the model
+    API a_n_best_words[4];  // array of the 4 best words
+    API a_n_best_score[8];  // array of the 4 best scores (each score is 32 bits length)
+
+    // Audio buffer
+    API a_dd_1[22];         // Header + DATA traffic downlink information, sub. chan. 1.
+    API a_du_1[22];         // Header + DATA traffic uplink information, sub. chan. 1.
+
+    // V42bis module
+    API d_v42b_nego0;
+    API d_v42b_nego1;
+    API d_v42b_control;
+    API d_v42b_ratio_ind;
+    API d_mcu_control;
+    API d_mcu_control_sema;
+
+    // Background tasks
+    API d_background_enable;
+    API d_background_abort;
+    API d_background_state;
+    API d_max_background;
+    API a_background_tasks[16];
+    API a_back_task_io[16];
+
+    // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
+    API d_gea_mode_ovly;
+    API a_gea_kc_ovly[4];
+
+#if (ANLG_FAM == 3)
+    // SYREN specific registers
+    API d_vbpop;
+    API d_vau_delay_init;
+    API d_vaud_cfg;
+    API d_vauo_onoff;
+    API d_vaus_vol;
+    API d_vaud_pll;
+    API d_hole3_ndb[1];
+#elif ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+
+    API d_hole3_ndb[7];
+
+#endif
+
+    // word used for the init of USF threshold
+    API d_thr_usf_detect;
+
+    // Encryption module
+    API d_a5mode;           // Encryption Mode.
+
+    API d_sched_mode_gprs_ovly;
+
+    // 7 words are reserved for any possible mapping modification
+    API d_hole4_ndb[5];
+
+    // Ramp definition for Omega device
+    API a_ramp[16];
+
+    // CCCH/SACCH downlink information...(!!)
+    API a_cd[15];           // Header + CCCH/SACCH downlink information.
+
+    // FACCH downlink information........(!!)
+    API a_fd[15];           // Header + FACCH downlink information.
+
+    // Traffic downlink data frames......(!!)
+    API a_dd_0[22];         // Header + DATA traffic downlink information, sub. chan. 0.
+
+    // CCCH/SACCH uplink information.....(!!)
+    API a_cu[15];           // Header + CCCH/SACCH uplink information.
+
+    // FACCH downlink information........(!!)
+    API a_fu[15];           // Header + FACCH uplink information
+
+    // Traffic downlink data frames......(!!)
+    API a_du_0[22];         // Header + DATA traffic uplink information, sub. chan. 0.
+
+    // Random access.....................(MCU -> DSP).
+    API d_rach;             // RACH information.
+
+    //...................................(MCU -> DSP).
+    API a_kc[4];            // Encryption Key Code.
+
+    // Integrated Data Services module
+    API d_ra_conf;
+    API d_ra_act;
+    API d_ra_test;
+    API d_ra_statu;
+    API d_ra_statd;
+    API d_fax;
+    API a_data_buf_ul[21];
+    API a_data_buf_dl[37];
+
+  // GTT API mapping for DSP code 34 (for test only)
+  #if (L1_GTT == 1)
+    API d_tty_status;
+    API d_tty_detect_thres;
+    API d_ctm_detect_shift;
+    API d_tty_fa_thres;
+    API d_tty_mod_norm;
+    API d_tty_reset_buffer_ul;
+    API d_tty_loop_ctrl;
+    API p_tty_loop_buffer;
+  #else
+    API a_tty_holes[8];
+  #endif
+
+    API a_sr_holes0[414];
+
+  #if (L1_NEW_AEC)
+    // new AEC
+    API d_cont_filter;
+    API d_granularity_att;
+    API d_coef_smooth;
+    API d_es_level_max;
+    API d_fact_vad;
+    API d_thrs_abs;
+    API d_fact_asd_fil;
+    API d_fact_asd_mut;
+    API d_far_end_pow_h;
+    API d_far_end_pow_l;
+    API d_far_end_noise_h;
+    API d_far_end_noise_l;
+  #else
+    API a_new_aec_holes[12];
+  #endif // L1_NEW_AEC
+
+    // Speech recognition model
+    API a_sr_holes1[145];
+    API d_cport_init;
+    API d_cport_ctrl;
+    API a_cport_cfr[2];
+    API d_cport_tcl_tadt;
+    API d_cport_tdat;
+    API d_cport_tvs;
+    API d_cport_status;
+    API d_cport_reg_value;
+
+    API a_cport_holes[1011];
+
+    API a_model[1041];
+
+    // EOTD buffer
+#if (L1_EOTD==1)
+    API d_eotd_first;
+    API d_eotd_max;
+    API d_eotd_nrj_high;
+    API d_eotd_nrj_low;
+    API a_eotd_crosscor[18];
+#else
+    API a_eotd_holes[22];
+#endif
+    // AMR ver 1.0 buffers
+    API a_amr_config[4];
+    API a_ratscch_ul[6];
+    API a_ratscch_dl[6];
+    API d_amr_snr_est; // estimation of the SNR of the AMR speech block
+  #if (L1_VOICE_MEMO_AMR)
+    API d_amms_ul_voc;
+  #else
+    API a_voice_memo_amr_holes[1];
+  #endif
+    API d_thr_onset_afs;     // thresh detection ONSET AFS
+    API d_thr_sid_first_afs; // thresh detection SID_FIRST AFS
+    API d_thr_ratscch_afs;   // thresh detection RATSCCH AFS
+    API d_thr_update_afs;    // thresh detection SID_UPDATE AFS
+    API d_thr_onset_ahs;     // thresh detection ONSET AHS
+    API d_thr_sid_ahs;       // thresh detection SID frames AHS
+    API d_thr_ratscch_marker;// thresh detection RATSCCH MARKER
+    API d_thr_sp_dgr;   // thresh detection SPEECH DEGRADED/NO_DATA
+    API d_thr_soft_bits;   
+    #if (MELODY_E2)
+      API d_melody_e2_osc_stop;
+      API d_melody_e2_osc_active;
+      API d_melody_e2_semaphore;
+      API a_melody_e2_osc[16][3];
+      API d_melody_e2_globaltimefactor;
+      API a_melody_e2_instrument_ptr[8];
+      API d_melody_e2_deltatime;
+
+      #if (AMR_THRESHOLDS_WORKAROUND)
+        API a_d_macc_thr_afs[8];
+        API a_d_macc_thr_ahs[6];
+      #else
+        API a_melody_e2_holes0[14];
+      #endif
+
+      API a_melody_e2_holes1[693];
+      API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
+      API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
+    #else
+      API d_holes[61];
+      #if (AMR_THRESHOLDS_WORKAROUND)
+        API a_d_macc_thr_afs[8];
+        API a_d_macc_thr_ahs[6];
+      #endif
+    #endif
+
+  }
+  T_NDB_MCU_DSP;
+#elif (DSP == 33) // NDB GSM
+  typedef struct
+  {
+    // MISC Tasks
+    API d_dsp_page;
+
+    // DSP status returned (DSP --> MCU).
+    API d_error_status;
+
+    // RIF control (MCU -> DSP).
+    API d_spcx_rif;
+
+    API d_tch_mode;  // TCH mode register.
+                     // bit [0..1]  -> b_dai_mode.
+                     // bit [2]     -> b_dtx.
+
+    API d_debug1;                // bit 0 at 1 enable dsp f_tx delay for Omega
+
+    API d_dsp_test;
+
+    // Words dedicated to Software version (DSP code + Patch)
+    API d_version_number1;
+    API d_version_number2;
+
+    API d_debug_ptr;
+    API d_debug_bk;
+
+    API d_pll_config;
+
+    // GSM/GPRS DSP Debug trace support
+    API p_debug_buffer;
+    API d_debug_buffer_size;
+    API d_debug_trace_type;
+
+    #if (W_A_DSP_IDLE3 == 1)
+      // DSP report its state: 0 run, 1 Idle1, 2 Idle2, 3 Idle3.
+      API d_dsp_state;
+      // 10 words are reserved for any possible mapping modification
+      API d_hole1_ndb[5];
+    #else
+      // 11 words are reserved for any possible mapping modification
+      API d_hole1_ndb[6];
+    #endif
+
+    // New words APCDEL1 and APCDEL2 for 2TX: TX/PRACH combinations
+    API d_apcdel1_bis;
+    API d_apcdel2_bis;
+
+
+    // New registers due to IOTA analog base band
+    API d_apcdel2;
+    API d_vbctrl2;
+    API d_bulgcal;
+
+    // Analog Based Band
+    API d_afcctladd;
+
+    API d_vbuctrl;
+    API d_vbdctrl;
+    API d_apcdel1;
+    API d_apcoff;
+    API d_bulioff;
+    API d_bulqoff;
+    API d_dai_onoff;
+    API d_auxdac;
+
+  #if (ANLG_FAM == 1)
+    API d_vbctrl;
+  #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+    API d_vbctrl1;
+  #endif
+
+    API d_bbctrl;
+
+    // Monitoring tasks control (MCU <- DSP)
+    // FB task
+    API d_fb_det;           // FB detection result. (1 for FOUND).
+    API d_fb_mode;          // Mode for FB detection algorithm.
+    API a_sync_demod[4];    // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
+
+    // SB Task
+    API a_sch26[5];         // Header + SB information, array of  5 words.
+
+    API d_audio_gain_ul;
+    API d_audio_gain_dl;
+
+    // Controller of the melody E2 audio compressor
+    API d_audio_compressor_ctrl;
+
+    // AUDIO module
+    API d_audio_init;
+    API d_audio_status;
+
+    // Audio tasks
+    // TONES (MCU -> DSP)
+    API d_toneskb_init;
+    API d_toneskb_status;
+    API d_k_x1_t0;
+    API d_k_x1_t1;
+    API d_k_x1_t2;
+    API d_pe_rep;
+    API d_pe_off;
+    API d_se_off;
+    API d_bu_off;
+    API d_t0_on;
+    API d_t0_off;
+    API d_t1_on;
+    API d_t1_off;
+    API d_t2_on;
+    API d_t2_off;
+    API d_k_x1_kt0;
+    API d_k_x1_kt1;
+    API d_dur_kb;
+    API d_shiftdl;
+    API d_shiftul;
+
+    API d_aec_ctrl;
+
+    API d_es_level_api;
+    API d_mu_api;
+
+    // Melody Ringer module
+    API d_melo_osc_used;
+    API d_melo_osc_active;
+    API a_melo_note0[4];
+    API a_melo_note1[4];
+    API a_melo_note2[4];
+    API a_melo_note3[4];
+    API a_melo_note4[4];
+    API a_melo_note5[4];
+    API a_melo_note6[4];
+    API a_melo_note7[4];
+
+    // selection of the melody format
+    API d_melody_selection;
+
+    // Holes due to the format melody E1
+    API a_melo_holes[3];
+
+    // Speech Recognition module
+    API d_sr_status;          // status of the DSP speech reco task
+    API d_sr_param;           // paramters for the DSP speech reco task: OOV threshold.
+    API d_sr_bit_exact_test;  // bit exact test
+    API d_sr_nb_words;        // number of words used in the speech recognition task
+    API d_sr_db_level;        // estimate voice level in dB
+    API d_sr_db_noise;        // estimate noise in dB
+    API d_sr_mod_size;        // size of the model
+    API a_n_best_words[4];  // array of the 4 best words
+    API a_n_best_score[8];  // array of the 4 best scores (each score is 32 bits length)
+
+    // Audio buffer
+    API a_dd_1[22];         // Header + DATA traffic downlink information, sub. chan. 1.
+    API a_du_1[22];         // Header + DATA traffic uplink information, sub. chan. 1.
+
+    // V42bis module
+    API d_v42b_nego0;
+    API d_v42b_nego1;
+    API d_v42b_control;
+    API d_v42b_ratio_ind;
+    API d_mcu_control;
+    API d_mcu_control_sema;
+
+    // Background tasks
+    API d_background_enable;
+    API d_background_abort;
+    API d_background_state;
+    API d_max_background;
+    API a_background_tasks[16];
+    API a_back_task_io[16];
+
+    // GEA module defined in l1p_deft.h (the following section is overlaid with GPRS NDB memory)
+    API d_gea_mode_ovly;
+    API a_gea_kc_ovly[4];
+
+    API d_hole3_ndb[8];
+
+    // Encryption module
+    API d_a5mode;           // Encryption Mode.
+
+    API d_sched_mode_gprs_ovly;
+
+    // 7 words are reserved for any possible mapping modification
+    API d_hole4_ndb[5];
+
+    // Ramp definition for Omega device
+    API a_ramp[16];
+
+    // CCCH/SACCH downlink information...(!!)
+    API a_cd[15];           // Header + CCCH/SACCH downlink information.
+
+    // FACCH downlink information........(!!)
+    API a_fd[15];           // Header + FACCH downlink information.
+
+    // Traffic downlink data frames......(!!)
+    API a_dd_0[22];         // Header + DATA traffic downlink information, sub. chan. 0.
+
+    // CCCH/SACCH uplink information.....(!!)
+    API a_cu[15];           // Header + CCCH/SACCH uplink information.
+
+    // FACCH downlink information........(!!)
+    API a_fu[15];           // Header + FACCH uplink information
+
+    // Traffic downlink data frames......(!!)
+    API a_du_0[22];         // Header + DATA traffic uplink information, sub. chan. 0.
+
+    // Random access.....................(MCU -> DSP).
+    API d_rach;             // RACH information.
+
+    //...................................(MCU -> DSP).
+    API a_kc[4];            // Encryption Key Code.
+
+    // Integrated Data Services module
+    API d_ra_conf;
+    API d_ra_act;
+    API d_ra_test;
+    API d_ra_statu;
+    API d_ra_statd;
+    API d_fax;
+    API a_data_buf_ul[21];
+    API a_data_buf_dl[37];
+
+  #if (L1_NEW_AEC)
+    // new AEC
+    API a_new_aec_holes[422];
+    API d_cont_filter;
+    API d_granularity_att;
+    API d_coef_smooth;
+    API d_es_level_max;
+    API d_fact_vad;
+    API d_thrs_abs;
+    API d_fact_asd_fil;
+    API d_fact_asd_mut;
+    API d_far_end_pow_h;
+    API d_far_end_pow_l;
+    API d_far_end_noise_h;
+    API d_far_end_noise_l;
+  #endif
+
+  // Speech recognition model
+  #if (L1_NEW_AEC)
+    API a_sr_holes[1165];
+  #else
+    API a_sr_holes[1599];
+  #endif // L1_NEW_AEC
+    API a_model[1041];
+
+    // EOTD buffer
+    #if (L1_EOTD==1)
+      API d_eotd_first;
+      API d_eotd_max;
+      API d_eotd_nrj_high;
+      API d_eotd_nrj_low;
+      API a_eotd_crosscor[18];
+    #else
+      API a_eotd_holes[22];
+    #endif
+
+    #if (MELODY_E2)
+      API a_melody_e2_holes0[27];
+      API d_melody_e2_osc_used;
+      API d_melody_e2_osc_active;
+      API d_melody_e2_semaphore;
+      API a_melody_e2_osc[16][3];
+      API d_melody_e2_globaltimefactor;
+      API a_melody_e2_instrument_ptr[8];
+      API a_melody_e2_holes1[708];
+      API a_dsp_trace[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_DSP_TRACE];
+      API a_melody_e2_instrument_wave[SC_AUDIO_MELODY_E2_MAX_SIZE_OF_INSTRUMENT];
+    #endif
+  }
+  T_NDB_MCU_DSP;
+
+#elif ((DSP == 32) || (DSP == 31))
+  typedef struct
+  {
+    // Monitoring tasks control..........(MCU <- DSP)
+    API d_fb_det;           // FB detection result. (1 for FOUND).
+    API d_fb_mode;          // Mode for FB detection algorithm.
+    API a_sync_demod[4];    // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
+
+    // CCCH/SACCH downlink information...(!!)
+    API a_cd[15];           // Header + CCCH/SACCH downlink information.
+
+    // FACCH downlink information........(!!)
+    API a_fd[15];           // Header + FACCH downlink information.
+
+    // Traffic downlink data frames......(!!)
+    API a_dd_0[22];         // Header + DATA traffic downlink information, sub. chan. 0.
+    API a_dd_1[22];         // Header + DATA traffic downlink information, sub. chan. 1.
+
+    // CCCH/SACCH uplink information.....(!!)
+    API a_cu[15];           // Header + CCCH/SACCH uplink information.
+
+    #if (SPEECH_RECO)
+      // FACCH downlink information........(!!)
+      API a_fu[3];              // Header + FACCH uplink information
+                                // The size of this buffer is 15 word but some speech reco words
+                                // are overlayer with this buffer. This is the reason why the size is 3 instead of 15.
+      API d_sr_status;          // status of the DSP speech reco task
+      API d_sr_param;           // paramters for the DSP speech reco task: OOV threshold.
+      API sr_hole1;             // hole
+      API d_sr_bit_exact_test;  // bit exact test
+      API d_sr_nb_words;        // number of words used in the speech recognition task
+      API d_sr_db_level;        // estimate voice level in dB
+      API d_sr_db_noise;        // estimate noise in dB
+      API d_sr_mod_size;        // size of the model
+      API sr_holes_1[4];        // hole
+    #else
+      // FACCH downlink information........(!!)
+      API a_fu[15];           // Header + FACCH uplink information
+    #endif
+
+    // Traffic uplink data frames........(!!)
+    API a_du_0[22];         // Header + DATA traffic uplink information, sub. chan. 0.
+    API a_du_1[22];         // Header + DATA traffic uplink information, sub. chan. 1.
+
+    // Random access.....................(MCU -> DSP).
+    API d_rach;             // RACH information.
+
+    //...................................(MCU -> DSP).
+    API d_a5mode;           // Encryption Mode.
+    API a_kc[4];            // Encryption Key Code.
+    API d_tch_mode;         // TCH mode register.
+                            //   bit [0..1]  -> b_dai_mode.
+                            //   bit [2]     -> b_dtx.
+
+  // OMEGA...........................(MCU -> DSP).
+  #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+    API a_ramp[16];
+    #if (MELODY_E1)
+      API d_melo_osc_used;
+      API d_melo_osc_active;
+      API a_melo_note0[4];
+      API a_melo_note1[4];
+      API a_melo_note2[4];
+      API a_melo_note3[4];
+      API a_melo_note4[4];
+      API a_melo_note5[4];
+      API a_melo_note6[4];
+      API a_melo_note7[4];
+      #if (DSP==31)
+        // selection of the melody format
+        API d_melody_selection;
+        API holes[9];
+      #else // DSP==32
+        API d_dco_type;               // Tide
+        API p_start_IQ;
+        API d_level_off;
+        API d_dco_dbg;
+        API d_tide_resa;
+        API d_asynch_margin;          // Perseus Asynch Audio Workaround
+        API hole[4];
+      #endif // DSP 32
+
+    #else // NO MELODY E1
+      #if (DSP==31)
+      // selection of the melody format
+      API d_melody_selection;
+      API holes[43];               // 43 unused holes.
+      #else // DSP==32
+        API holes[34];               // 34 unused holes.
+        API d_dco_type;               // Tide
+        API p_start_IQ;
+        API d_level_off;
+        API d_dco_dbg;
+        API d_tide_resa;
+        API d_asynch_margin;          // Perseus Asynch Audio Workaround
+        API hole[4];
+      #endif //DSP == 32
+    #endif // NO MELODY E1
+
+    API d_debug3;
+    API d_debug2;
+    API d_debug1;                // bit 0 at 1 enable dsp f_tx delay for Omega
+    API d_afcctladd;
+    API d_vbuctrl;
+    API d_vbdctrl;
+    API d_apcdel1;
+    API d_aec_ctrl;
+    API d_apcoff;
+    API d_bulioff;
+    API d_bulqoff;
+    API d_dai_onoff;
+    API d_auxdac;
+
+    #if (ANLG_FAM == 1)
+      API d_vbctrl;
+    #elif (ANLG_FAM == 2)
+      API d_vbctrl1;
+    #endif
+
+    API d_bbctrl;
+  #else 
+    #error DSPCODE not supported with given ANALOG
+  #endif //(ANALOG)1, 2
+    //...................................(MCU -> DSP).
+    API a_sch26[5];         // Header + SB information, array of  5 words.
+
+    // TONES.............................(MCU -> DSP)
+    API d_toneskb_init;
+    API d_toneskb_status;
+    API d_k_x1_t0;
+    API d_k_x1_t1;
+    API d_k_x1_t2;
+    API d_pe_rep;
+    API d_pe_off;
+    API d_se_off;
+    API d_bu_off;
+    API d_t0_on;
+    API d_t0_off;
+    API d_t1_on;
+    API d_t1_off;
+    API d_t2_on;
+    API d_t2_off;
+    API d_k_x1_kt0;
+    API d_k_x1_kt1;
+    API d_dur_kb;
+
+    // PLL...............................(MCU -> DSP).
+    API d_pll_clkmod1;
+    API d_pll_clkmod2;
+
+    // DSP status returned..........(DSP --> MCU).
+    API d_error_status;
+
+    // RIF control.......................(MCU -> DSP).
+    API d_spcx_rif;
+
+    API d_shiftdl;
+    API d_shiftul;
+
+    API p_saec_prog;
+    API p_aec_prog;
+    API p_spenh_prog;
+
+    API a_ovly[75];
+    API d_ra_conf;
+    API d_ra_act;
+    API d_ra_test;
+    API d_ra_statu;
+    API d_ra_statd;
+    API d_fax;
+    #if (SPEECH_RECO)
+      API a_data_buf_ul[3];
+      API a_n_best_words[4];  // array of the 4 best words
+      API a_n_best_score[8];  // array of the 4 best scores (each score is 32 bits length)
+      API sr_holes_2[6];
+      API a_data_buf_dl[37];
+
+      API a_hole[24];
+
+      API d_sched_mode_gprs_ovly;
+
+      API fir_holes1[384];
+      API a_fir31_uplink[31];
+      API a_fir31_downlink[31];
+      API d_audio_init;
+      API d_audio_status;
+
+      API a_model[1041];  // array of the speech reco model
+    #else
+      API a_data_buf_ul[21];
+      API a_data_buf_dl[37];
+
+      API a_hole[24];
+
+      API d_sched_mode_gprs_ovly;
+
+      API fir_holes1[384];
+      API a_fir31_uplink[31];
+      API a_fir31_downlink[31];
+      API d_audio_init;
+      API d_audio_status;
+
+#if (L1_EOTD ==1)
+      API a_eotd_hole[369];
+
+      API d_eotd_first;
+      API d_eotd_max;
+      API d_eotd_nrj_high;
+      API d_eotd_nrj_low;
+      API a_eotd_crosscor[18];
+#endif
+    #endif
+  }
+  T_NDB_MCU_DSP;
+
+
+#else // OTHER DSP CODE like 17
+
+typedef struct
+{
+  // Monitoring tasks control..........(MCU <- DSP)
+  API d_fb_det;           // FB detection result. (1 for FOUND).
+  API d_fb_mode;          // Mode for FB detection algorithm.
+  API a_sync_demod[4];    // FB/SB demod. result, (D_TOA,D_PM,D_ANGLE,D_SNR).
+
+  // CCCH/SACCH downlink information...(!!)
+  API a_cd[15];           // Header + CCCH/SACCH downlink information.
+
+  // FACCH downlink information........(!!)
+  API a_fd[15];           // Header + FACCH downlink information.
+
+  // Traffic downlink data frames......(!!)
+  #if (DATA14_4 == 0)
+    API a_dd_0[20];         // Header + DATA traffic downlink information, sub. chan. 0.
+    API a_dd_1[20];         // Header + DATA traffic downlink information, sub. chan. 1.
+  #endif
+  #if (DATA14_4 == 1)
+    API a_dd_0[22];         // Header + DATA traffic downlink information, sub. chan. 0.
+    API a_dd_1[22];         // Header + DATA traffic downlink information, sub. chan. 1.
+  #endif
+
+  // CCCH/SACCH uplink information.....(!!)
+  API a_cu[15];           // Header + CCCH/SACCH uplink information.
+
+  #if (SPEECH_RECO)
+    // FACCH downlink information........(!!)
+    API a_fu[3];              // Header + FACCH uplink information
+                              // The size of this buffer is 15 word but some speech reco words
+                              // are overlayer with this buffer. This is the reason why the size is 3 instead of 15.
+    API d_sr_status;          // status of the DSP speech reco task
+    API d_sr_param;           // paramters for the DSP speech reco task: OOV threshold.
+    API sr_hole1;             // hole
+    API d_sr_bit_exact_test;  // bit exact test
+    API d_sr_nb_words;        // number of words used in the speech recognition task
+    API d_sr_db_level;        // estimate voice level in dB
+    API d_sr_db_noise;        // estimate noise in dB
+    API d_sr_mod_size;        // size of the model
+    API sr_holes_1[4];        // hole
+  #else
+    // FACCH downlink information........(!!)
+    API a_fu[15];           // Header + FACCH uplink information
+  #endif
+
+  // Traffic uplink data frames........(!!)
+  #if (DATA14_4 == 0)
+    API a_du_0[20];         // Header + DATA traffic uplink information, sub. chan. 0.
+    API a_du_1[20];         // Header + DATA traffic uplink information, sub. chan. 1.
+  #endif
+  #if (DATA14_4 == 1)
+    API a_du_0[22];         // Header + DATA traffic uplink information, sub. chan. 0.
+    API a_du_1[22];         // Header + DATA traffic uplink information, sub. chan. 1.
+  #endif
+
+  // Random access.....................(MCU -> DSP).
+  API d_rach;             // RACH information.
+
+  //...................................(MCU -> DSP).
+  API d_a5mode;           // Encryption Mode.
+  API a_kc[4];            // Encryption Key Code.
+  API d_tch_mode;         // TCH mode register.
+                               //        bit [0..1]  -> b_dai_mode.
+                               //        bit [2]     -> b_dtx.
+
+  // OMEGA...........................(MCU -> DSP).
+
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+  API a_ramp[16];
+  #if (MELODY_E1)
+    API d_melo_osc_used;
+    API d_melo_osc_active;
+    API a_melo_note0[4];
+    API a_melo_note1[4];
+    API a_melo_note2[4];
+    API a_melo_note3[4];
+    API a_melo_note4[4];
+    API a_melo_note5[4];
+    API a_melo_note6[4];
+    API a_melo_note7[4];
+    #if (DSP == 17)
+    // selection of the melody format
+      API d_dco_type;               // Tide
+      API p_start_IQ;
+      API d_level_off;
+      API d_dco_dbg;
+      API d_tide_resa;
+      API d_asynch_margin;          // Perseus Asynch Audio Workaround
+      API hole[4];
+    #else
+      API d_melody_selection;
+      API holes[9];
+    #endif
+  #else // NO MELODY E1
+    // selection of the melody format
+    #if (DSP == 17)
+      API holes[34];               // 34 unused holes.
+      API d_dco_type;               // Tide
+      API p_start_IQ;
+      API d_level_off;
+      API d_dco_dbg;
+      API d_tide_resa;
+      API d_asynch_margin;          // Perseus Asynch Audio Workaround
+      API hole[4]
+    #else
+      // selection of the melody format
+      API d_melody_selection;
+      API holes[43];               // 43 unused holes.
+    #endif
+  #endif
+  API d_debug3;
+  API d_debug2;
+  API d_debug1;                // bit 0 at 1 enable dsp f_tx delay for Omega
+  API d_afcctladd;
+  API d_vbuctrl;
+  API d_vbdctrl;
+  API d_apcdel1;
+  API d_aec_ctrl;
+  API d_apcoff;
+  API d_bulioff;
+  API d_bulqoff;
+  API d_dai_onoff;
+  API d_auxdac;
+  #if (ANLG_FAM == 1)
+    API d_vbctrl;
+  #elif (ANLG_FAM == 2)
+    API d_vbctrl1;
+  #endif
+  API d_bbctrl;
+
+  #else 
+    #error DSPCODE not supported with given ANALOG
+  #endif //(ANALOG)1, 2
+  //...................................(MCU -> DSP).
+  API a_sch26[5];         // Header + SB information, array of  5 words.
+
+  // TONES.............................(MCU -> DSP)
+  API d_toneskb_init;
+  API d_toneskb_status;
+  API d_k_x1_t0;
+  API d_k_x1_t1;
+  API d_k_x1_t2;
+  API d_pe_rep;
+  API d_pe_off;
+  API d_se_off;
+  API d_bu_off;
+  API d_t0_on;
+  API d_t0_off;
+  API d_t1_on;
+  API d_t1_off;
+  API d_t2_on;
+  API d_t2_off;
+  API d_k_x1_kt0;
+  API d_k_x1_kt1;
+  API d_dur_kb;
+
+  // PLL...............................(MCU -> DSP).
+  API d_pll_clkmod1;
+  API d_pll_clkmod2;
+
+  // DSP status returned..........(DSP --> MCU).
+  API d_error_status;
+
+  // RIF control.......................(MCU -> DSP).
+  API d_spcx_rif;
+
+  API d_shiftdl;
+  API d_shiftul;
+
+  #if (AEC == 1)
+    // AEC control.......................(MCU -> DSP).
+    #if (VOC == FR_EFR)
+      API p_aec_init;
+      API p_aec_prog;
+      API p_spenh_init;
+      API p_spenh_prog;
+    #endif
+
+    #if (VOC == FR_HR_EFR)
+      API p_saec_prog;
+      API p_aec_prog;
+      API p_spenh_prog;
+    #endif
+  #endif
+
+    API a_ovly[75];
+    API d_ra_conf;
+    API d_ra_act;
+    API d_ra_test;
+    API d_ra_statu;
+    API d_ra_statd;
+    API d_fax;
+    #if (SPEECH_RECO)
+      API a_data_buf_ul[3];
+      API a_n_best_words[4];  // array of the 4 best words
+      API a_n_best_score[8];  // array of the 4 best scores (each score is 32 bits length)
+      API sr_holes_2[6];
+      API a_data_buf_dl[37];
+
+      API fir_holes1[409];
+      API a_fir31_uplink[31];
+      API a_fir31_downlink[31];
+      API d_audio_init;
+      API d_audio_status;
+      API a_model[1041];  // array of the speech reco model
+    #else
+      API a_data_buf_ul[21];
+      API a_data_buf_dl[37];
+
+      API fir_holes1[409];
+      API a_fir31_uplink[31];
+      API a_fir31_downlink[31];
+      API d_audio_init;
+      API d_audio_status;
+    #endif
+}
+T_NDB_MCU_DSP;
+#endif
+
+#if (DSP == 34) || (DSP == 35) || (DSP == 36)
+typedef struct
+{
+  API_SIGNED d_transfer_rate;
+
+  // Common GSM/GPRS
+  // These words specified the latencies to applies on some peripherics
+  API_SIGNED d_lat_mcu_bridge;
+  API_SIGNED d_lat_mcu_hom2sam;
+  API_SIGNED d_lat_mcu_bef_fast_access;
+  API_SIGNED d_lat_dsp_after_sam;
+
+  // DSP Start address
+  API_SIGNED d_gprs_install_address;
+
+  API_SIGNED d_misc_config;
+
+  API_SIGNED d_cn_sw_workaround;
+
+  API_SIGNED d_hole2_param[4];
+
+    //...................................Frequency Burst.
+  API_SIGNED d_fb_margin_beg;
+  API_SIGNED d_fb_margin_end;
+  API_SIGNED d_nsubb_idle;
+  API_SIGNED d_nsubb_dedic;
+  API_SIGNED d_fb_thr_det_iacq;
+  API_SIGNED d_fb_thr_det_track;
+    //...................................Demodulation.
+  API_SIGNED d_dc_off_thres;
+  API_SIGNED d_dummy_thres;
+  API_SIGNED d_dem_pond_gewl;
+  API_SIGNED d_dem_pond_red;
+
+    //...................................TCH Full Speech.
+  API_SIGNED d_maccthresh1;
+  API_SIGNED d_mldt;
+  API_SIGNED d_maccthresh;
+  API_SIGNED d_gu;
+  API_SIGNED d_go;
+  API_SIGNED d_attmax;
+  API_SIGNED d_sm;
+  API_SIGNED d_b;
+
+  // V42Bis module
+  API_SIGNED d_v42b_switch_hyst;
+  API_SIGNED d_v42b_switch_min;
+  API_SIGNED d_v42b_switch_max;
+  API_SIGNED d_v42b_reset_delay;
+
+  //...................................TCH Half Speech.
+  API_SIGNED d_ldT_hr;
+  API_SIGNED d_maccthresh_hr;
+  API_SIGNED d_maccthresh1_hr;
+  API_SIGNED d_gu_hr;
+  API_SIGNED d_go_hr;
+  API_SIGNED d_b_hr;
+  API_SIGNED d_sm_hr;
+  API_SIGNED d_attmax_hr;
+
+  //...................................TCH Enhanced FR Speech.
+  API_SIGNED c_mldt_efr;
+  API_SIGNED c_maccthresh_efr;
+  API_SIGNED c_maccthresh1_efr;
+  API_SIGNED c_gu_efr;
+  API_SIGNED c_go_efr;
+  API_SIGNED c_b_efr;
+  API_SIGNED c_sm_efr;
+  API_SIGNED c_attmax_efr;
+
+  //...................................CHED
+  API_SIGNED d_sd_min_thr_tchfs;
+  API_SIGNED d_ma_min_thr_tchfs;
+  API_SIGNED d_md_max_thr_tchfs;
+  API_SIGNED d_md1_max_thr_tchfs;
+
+  API_SIGNED d_sd_min_thr_tchhs;
+  API_SIGNED d_ma_min_thr_tchhs;
+  API_SIGNED d_sd_av_thr_tchhs;
+  API_SIGNED d_md_max_thr_tchhs;
+  API_SIGNED d_md1_max_thr_tchhs;
+
+  API_SIGNED d_sd_min_thr_tchefs;
+  API_SIGNED d_ma_min_thr_tchefs;
+  API_SIGNED d_md_max_thr_tchefs;
+  API_SIGNED d_md1_max_thr_tchefs;
+
+  API_SIGNED d_wed_fil_ini;
+  API_SIGNED d_wed_fil_tc;
+  API_SIGNED d_x_min;
+  API_SIGNED d_x_max;
+  API_SIGNED d_slope;
+  API_SIGNED d_y_min;
+  API_SIGNED d_y_max;
+  API_SIGNED d_wed_diff_threshold;
+  API_SIGNED d_mabfi_min_thr_tchhs;
+
+  // FACCH module
+  API_SIGNED d_facch_thr;
+
+  // IDS module
+  API_SIGNED d_max_ovsp_ul;
+  API_SIGNED d_sync_thres;
+  API_SIGNED d_idle_thres;
+  API_SIGNED d_m1_thres;
+  API_SIGNED d_max_ovsp_dl;
+  API_SIGNED d_gsm_bgd_mgt;
+
+  // FIR coefficients
+  API a_fir_holes[4];
+  API a_fir31_uplink[31];
+  API a_fir31_downlink[31];
+}
+T_PARAM_MCU_DSP;
+#elif (DSP == 33)
+typedef struct
+{
+  API_SIGNED d_transfer_rate;
+
+  // Common GSM/GPRS
+  // These words specified the latencies to applies on some peripherics
+  API_SIGNED d_lat_mcu_bridge;
+  API_SIGNED d_lat_mcu_hom2sam;
+  API_SIGNED d_lat_mcu_bef_fast_access;
+  API_SIGNED d_lat_dsp_after_sam;
+
+  // DSP Start address
+  API_SIGNED d_gprs_install_address;
+
+  API_SIGNED d_misc_config;
+
+  API_SIGNED d_cn_sw_workaround;
+
+  #if DCO_ALGO
+    API_SIGNED d_cn_dco_param;
+
+    API_SIGNED d_hole2_param[3];
+  #else
+    API_SIGNED d_hole2_param[4];
+  #endif
+
+    //...................................Frequency Burst.
+  API_SIGNED d_fb_margin_beg;
+  API_SIGNED d_fb_margin_end;
+  API_SIGNED d_nsubb_idle;
+  API_SIGNED d_nsubb_dedic;
+  API_SIGNED d_fb_thr_det_iacq;
+  API_SIGNED d_fb_thr_det_track;
+    //...................................Demodulation.
+  API_SIGNED d_dc_off_thres;
+  API_SIGNED d_dummy_thres;
+  API_SIGNED d_dem_pond_gewl;
+  API_SIGNED d_dem_pond_red;
+
+    //...................................TCH Full Speech.
+  API_SIGNED d_maccthresh1;
+  API_SIGNED d_mldt;
+  API_SIGNED d_maccthresh;
+  API_SIGNED d_gu;
+  API_SIGNED d_go;
+  API_SIGNED d_attmax;
+  API_SIGNED d_sm;
+  API_SIGNED d_b;
+
+  // V42Bis module
+  API_SIGNED d_v42b_switch_hyst;
+  API_SIGNED d_v42b_switch_min;
+  API_SIGNED d_v42b_switch_max;
+  API_SIGNED d_v42b_reset_delay;
+
+  //...................................TCH Half Speech.
+  API_SIGNED d_ldT_hr;
+  API_SIGNED d_maccthresh_hr;
+  API_SIGNED d_maccthresh1_hr;
+  API_SIGNED d_gu_hr;
+  API_SIGNED d_go_hr;
+  API_SIGNED d_b_hr;
+  API_SIGNED d_sm_hr;
+  API_SIGNED d_attmax_hr;
+
+  //...................................TCH Enhanced FR Speech.
+  API_SIGNED c_mldt_efr;
+  API_SIGNED c_maccthresh_efr;
+  API_SIGNED c_maccthresh1_efr;
+  API_SIGNED c_gu_efr;
+  API_SIGNED c_go_efr;
+  API_SIGNED c_b_efr;
+  API_SIGNED c_sm_efr;
+  API_SIGNED c_attmax_efr;
+
+  //...................................CHED
+  API_SIGNED d_sd_min_thr_tchfs;
+  API_SIGNED d_ma_min_thr_tchfs;
+  API_SIGNED d_md_max_thr_tchfs;
+  API_SIGNED d_md1_max_thr_tchfs;
+
+  API_SIGNED d_sd_min_thr_tchhs;
+  API_SIGNED d_ma_min_thr_tchhs;
+  API_SIGNED d_sd_av_thr_tchhs;
+  API_SIGNED d_md_max_thr_tchhs;
+  API_SIGNED d_md1_max_thr_tchhs;
+
+  API_SIGNED d_sd_min_thr_tchefs;
+  API_SIGNED d_ma_min_thr_tchefs;
+  API_SIGNED d_md_max_thr_tchefs;
+  API_SIGNED d_md1_max_thr_tchefs;
+
+  API_SIGNED d_wed_fil_ini;
+  API_SIGNED d_wed_fil_tc;
+  API_SIGNED d_x_min;
+  API_SIGNED d_x_max;
+  API_SIGNED d_slope;
+  API_SIGNED d_y_min;
+  API_SIGNED d_y_max;
+  API_SIGNED d_wed_diff_threshold;
+  API_SIGNED d_mabfi_min_thr_tchhs;
+
+  // FACCH module
+  API_SIGNED d_facch_thr;
+
+  // IDS module
+  API_SIGNED d_max_ovsp_ul;
+  API_SIGNED d_sync_thres;
+  API_SIGNED d_idle_thres;
+  API_SIGNED d_m1_thres;
+  API_SIGNED d_max_ovsp_dl;
+  API_SIGNED d_gsm_bgd_mgt;
+
+  // FIR coefficients
+  API a_fir_holes[4];
+  API a_fir31_uplink[31];
+  API a_fir31_downlink[31];
+}
+T_PARAM_MCU_DSP;
+
+#else
+
+typedef struct
+{
+    //...................................Frequency Burst.
+  API_SIGNED d_nsubb_idle;
+  API_SIGNED d_nsubb_dedic;
+  API_SIGNED d_fb_thr_det_iacq;
+  API_SIGNED d_fb_thr_det_track;
+    //...................................Demodulation.
+  API_SIGNED d_dc_off_thres;
+  API_SIGNED d_dummy_thres;
+  API_SIGNED d_dem_pond_gewl;
+  API_SIGNED d_dem_pond_red;
+  API_SIGNED hole[1];
+  API_SIGNED d_transfer_rate;
+    //...................................TCH Full Speech.
+  API_SIGNED d_maccthresh1;
+  API_SIGNED d_mldt;
+  API_SIGNED d_maccthresh;
+  API_SIGNED d_gu;
+  API_SIGNED d_go;
+  API_SIGNED d_attmax;
+  API_SIGNED d_sm;
+  API_SIGNED d_b;
+
+  #if (VOC == FR_HR) || (VOC == FR_HR_EFR)
+      //...................................TCH Half Speech.
+    API_SIGNED d_ldT_hr;
+    API_SIGNED d_maccthresh_hr;
+    API_SIGNED d_maccthresh1_hr;
+    API_SIGNED d_gu_hr;
+    API_SIGNED d_go_hr;
+    API_SIGNED d_b_hr;
+    API_SIGNED d_sm_hr;
+    API_SIGNED d_attmax_hr;
+  #endif
+
+  #if (VOC == FR_EFR) || (VOC == FR_HR_EFR)
+      //...................................TCH Enhanced FR Speech.
+    API_SIGNED c_mldt_efr;
+    API_SIGNED c_maccthresh_efr;
+    API_SIGNED c_maccthresh1_efr;
+    API_SIGNED c_gu_efr;
+    API_SIGNED c_go_efr;
+    API_SIGNED c_b_efr;
+    API_SIGNED c_sm_efr;
+    API_SIGNED c_attmax_efr;
+  #endif
+
+    //...................................TCH Full Speech.
+  API_SIGNED d_sd_min_thr_tchfs;
+  API_SIGNED d_ma_min_thr_tchfs;
+  API_SIGNED d_md_max_thr_tchfs;
+  API_SIGNED d_md1_max_thr_tchfs;
+
+  #if (VOC == FR) || (VOC == FR_HR) || (VOC == FR_HR_EFR)
+      //...................................TCH Half Speech.
+    API_SIGNED d_sd_min_thr_tchhs;
+    API_SIGNED d_ma_min_thr_tchhs;
+    API_SIGNED d_sd_av_thr_tchhs;
+    API_SIGNED d_md_max_thr_tchhs;
+    API_SIGNED d_md1_max_thr_tchhs;
+  #endif
+
+  #if (VOC == FR_EFR) || (VOC == FR_HR_EFR)
+      //...................................TCH Enhanced FR Speech.
+    API_SIGNED d_sd_min_thr_tchefs;                       //(24L   *C_POND_RED)
+    API_SIGNED d_ma_min_thr_tchefs;                       //(1200L *C_POND_RED)
+    API_SIGNED d_md_max_thr_tchefs;                       //(2000L *C_POND_RED)
+    API_SIGNED d_md1_max_thr_tchefs;                      //(160L  *C_POND_RED)
+    API_SIGNED d_hole1;
+  #endif
+
+  API_SIGNED d_wed_fil_ini;
+  API_SIGNED d_wed_fil_tc;
+  API_SIGNED d_x_min;
+  API_SIGNED d_x_max;
+  API_SIGNED d_slope;
+  API_SIGNED d_y_min;
+  API_SIGNED d_y_max;
+  API_SIGNED d_wed_diff_threshold;
+  API_SIGNED d_mabfi_min_thr_tchhs;
+  API_SIGNED d_facch_thr;
+  API_SIGNED d_dsp_test;
+
+
+  #if (DATA14_4 == 0 ) || (VOC == FR_HR_EFR)
+    API_SIGNED d_patch_addr1;
+    API_SIGNED d_patch_data1;
+    API_SIGNED d_patch_addr2;
+    API_SIGNED d_patch_data2;
+    API_SIGNED d_patch_addr3;
+    API_SIGNED d_patch_data3;
+    API_SIGNED d_patch_addr4;
+    API_SIGNED d_patch_data4;
+  #endif
+
+    //...................................
+  API_SIGNED d_version_number;    // DSP patch version
+  API_SIGNED d_ti_version;        // customer number. No more used since 1.5
+
+  API_SIGNED d_dsp_page;
+
+  #if IDS
+  API_SIGNED d_max_ovsp_ul;
+  API_SIGNED d_sync_thres;
+  API_SIGNED d_idle_thres;
+  API_SIGNED d_m1_thres;
+  API_SIGNED d_max_ovsp_dl;
+  #endif
+
+
+}
+T_PARAM_MCU_DSP;
+#endif
+
+#if (DSP_DEBUG_TRACE_ENABLE == 1)
+typedef struct
+{
+  API d_debug_ptr_begin;
+  API d_debug_ptr_end;
+}
+T_DB2_DSP_TO_MCU;
+#endif
+
+/*************************************************************/
+/* Time informations...                                      */
+/*************************************************************/
+/*                                                           */
+/*************************************************************/
+typedef struct
+{
+  UWORD32  fn;                   // FN count
+  UWORD16  t1;                   // FN div (26*51), (0..2047).
+  UWORD8   t2;                   // FN modulo 26.
+  UWORD8   t3;                   // FN modulo 51.
+  UWORD8   tc;                   // Scell: TC
+  UWORD8   fn_in_report;         // FN modulo 102 or 104.
+  UWORD16  fn_mod42432;          // FN modulo 42432.
+  UWORD8   fn_mod13;             // FN modulo 13.
+  #if L1_GPRS
+    UWORD8   fn_mod52;             // FN modulo 52.
+    UWORD8   fn_mod104;            // FN modulo 104.
+    UWORD8   fn_mod13_mod4;        // FN modulo 13 modulo 4.
+    UWORD32  block_id;             // Block ID
+  #endif
+}
+T_TIME_INFO;
+
+/*************************************************************/
+/* Idle mode tasks information...                            */
+/*************************************************************/
+/* must be filled according to Idle parameters...            */
+/* ...                                                       */
+/*************************************************************/
+typedef struct
+{
+  UWORD8 pg_position;    // Paging block starting frame.
+  UWORD8 extpg_position; // Extended Paging block starting frame.
+}
+T_IDLE_TASK_INFO;
+
+/*************************************************************/
+/* SDCCH information structure.                              */
+/*************************************************************/
+/*                                                           */
+/*                                                           */
+/*************************************************************/
+typedef struct
+{
+  UWORD8 dl_sdcch_position;
+  UWORD8 dl_sacch_position;
+  UWORD8 ul_sdcch_position;
+  UWORD8 ul_sacch_position;
+  UWORD8 mon_area_position;
+}
+T_SDCCH_DESC;
+
+/*************************************************************/
+/* Random Access Task information structure.                 */
+/*************************************************************/
+/*                                                           */
+/*                                                           */
+/*************************************************************/
+typedef struct
+{
+  WORD32  rand;             // 16 bit signed !!
+  UWORD8  channel_request;
+  UWORD8  ra_to_ctrl;
+  UWORD8  ra_num;
+}
+T_RA_TASK_INFO;
+
+/***************************************************************************************/
+/* Measurement info element for last input level table                                 */
+/***************************************************************************************/
+typedef struct
+{
+  UWORD8  lna_off;              // 1 if lna switch is off.
+  UWORD8  input_level;          // last measured input level in dbm.
+}
+T_INPUT_LEVEL;
+
+/***************************************************************************************/
+/* Measurement info element for Neighbor cell lists.                                   */
+/***************************************************************************************/
+typedef struct
+{
+  UWORD16  radio_freq;                // carrier id.
+  WORD32  acc;                  // Accumulation of measurements already performed.
+  UWORD8   nbr_meas;
+}
+T_MEAS_INFO;
+
+typedef struct
+{
+  UWORD16  bcch_freq;
+  WORD16   rxlev_acc;
+  UWORD8   rxlev_nbr_meas;
+}
+T5_CELL_MEAS;
+
+typedef struct
+{
+  T5_CELL_MEAS A[33];
+}
+T5_NCELL_MEAS;
+
+/***************************************************************************************/
+/* Measurement info element serving cell in dedicated mode                             */
+/***************************************************************************************/
+typedef struct
+{
+  WORD32   acc_sub;            // Subset:  accu. rxlev meas.
+  UWORD32  nbr_meas_sub;       // Subset:  nbr meas. of rxlev.
+  UWORD32  qual_acc_full;      // Fullset: accu. rxqual meas.
+  UWORD32  qual_acc_sub;       // Subset:  accu. rxqual meas.
+  UWORD32  qual_nbr_meas_full; // Fullset: nbr meas. of rxqual.
+  UWORD32  qual_nbr_meas_sub;  // Subset:  nbr meas. of rxqual.
+  UWORD8   dtx_used;           // Set when DTX as been used in current reporting period.
+}
+T_SMEAS;
+
+/***************************************************************************************/
+/*                                                                                     */
+/***************************************************************************************/
+typedef struct
+{
+  UWORD8  new_status;
+  UWORD8  current_status;
+  WORD32  time_to_exec;
+}
+T_TASK_STATUS;
+
+/***************************************************************************************/
+/* Cell/Carrier info: identity, RX level measurement, time info, gain controle info.   */
+/***************************************************************************************/
+typedef struct
+{
+  // Carrier/Cell Identity.
+  UWORD16  radio_freq;                  // carrier id.
+  WORD32   bsic;                   // BSIC.
+
+  // Time difference information.
+  UWORD32  fn_offset;              // offset between fn of this NCELL and the SCELL fn.
+  UWORD32  time_alignmt;           // time alignment.
+
+  // Receive Level Measurement info. structure.
+  T_MEAS_INFO    meas;
+  T_INPUT_LEVEL  traffic_meas;
+  T_INPUT_LEVEL  traffic_meas_beacon;
+
+  // Beacon frequency FIFO
+  UWORD8         buff_beacon[4];
+
+  #if L1_GPRS
+    // Receive Level measurements in packet transfer mode
+    // Daughter frequencies info.
+    T_INPUT_LEVEL  transfer_meas;
+
+    // Power reduction on serving cell PCCCH / PBCCH
+    UWORD8         pb;
+  #endif
+
+  // Number of unsuccessfull attempt on SB reading.
+  UWORD8  attempt_count;
+
+  // System information bitmap.
+  UWORD32  si_bit_map;             // System info. bitmap used for BCCH reading.
+}
+T_CELL_INFO;
+
+
+typedef struct
+{
+  UWORD16  A[32+1];
+}
+TC_CHAN_LIST;
+
+
+typedef struct
+{
+  UWORD8        num_of_chans;
+  TC_CHAN_LIST  chan_list;
+  BOOL          pwrc;
+  BOOL          dtx_allowed;
+  UWORD8        ba_id;
+}
+T_NEW_BA_LIST;
+
+
+typedef struct
+{
+  UWORD8         ba_id;            // BA list identifier.
+
+  UWORD32        nbr_carrier;      // number of carriers in the BA list.
+  UWORD8         np_ctrl;          // Tels the meas_manager which PCH burst has been controled.
+
+  UWORD8         first_index;      // First BA index measured in current session.
+
+  UWORD8         next_to_ctrl;     // Carrier for next power measurement result.
+  UWORD8         next_to_read;     // Measurement session time spent.
+
+  UWORD8         ms_ctrl;
+  UWORD8         ms_ctrl_d;
+  UWORD8         ms_ctrl_dd;
+
+  UWORD8         used_il   [2];
+  UWORD8         used_il_d [2];
+  UWORD8         used_il_dd[2];
+
+  UWORD8         used_lna   [2];
+  UWORD8         used_lna_d [2];
+  UWORD8         used_lna_dd[2];
+
+  T_MEAS_INFO    A[32+1];          // list of 32 neighbors + 1 serving.
+
+  BOOL           new_list_present;
+  T_NEW_BA_LIST  new_list;
+}
+T_BA_LIST;
+
+typedef struct
+{
+  UWORD16  radio_freq;
+  WORD16   accum_power_result;
+}
+T_POWER_ARRAY;
+
+typedef struct
+{
+  UWORD16         power_array_size;
+  T_POWER_ARRAY   power_array[NBMAX_CARRIER];
+}
+T_FULL_LIST_MEAS;
+
+typedef struct
+{
+  UWORD32            nbr_sat_carrier_ctrl;  // Nb of saturated carriers after a pm session in ctrl.
+  UWORD32            nbr_sat_carrier_read;  // Nb of saturated carriers after a pm session in read.
+
+  UWORD8             meas_1st_pass_ctrl;    // flag for 1st pass during a pm session in ctrl.
+  UWORD8             meas_1st_pass_read;    // flag for 1st pass during a pm session in read.
+
+  UWORD32            next_to_ctrl;          // Carrier for next power measurement result.
+  UWORD32            next_to_read;          // Measurement session time spent.
+
+  UWORD8             ms_ctrl;
+  UWORD8             ms_ctrl_d;
+  UWORD8             ms_ctrl_dd;
+
+  UWORD8             sat_flag[NBMAX_CARRIER];
+                                            // last measure was saturated, so not valid
+}
+T_FULL_LIST;
+
+/*************************************************************/
+/* Dedicated channel information structure...                */
+/*************************************************************/
+/*                                                           */
+/*************************************************************/
+typedef struct
+{
+  T_CHANNEL_DESCRIPTION  *desc_ptr;    // Ptr to the Active channel description
+  T_CHANNEL_DESCRIPTION  desc;         // Channel description for AFTER STI.
+  T_CHANNEL_DESCRIPTION  desc_bef_sti; // Channel description for BEFORE STI.
+  UWORD8                 mode;         // Channel mode.
+  UWORD8                 tch_loop;     // TCH loop mode.
+}
+T_CHANNEL_INFO;
+
+/*************************************************************/
+/* Mobile allocation information structure...                */
+/*************************************************************/
+/*                                                           */
+/*************************************************************/
+typedef struct
+{
+  T_MOBILE_ALLOCATION    *alist_ptr;         // Ptr to the Active frequency list
+  T_MOBILE_ALLOCATION    freq_list;
+  T_MOBILE_ALLOCATION    freq_list_bef_sti;
+}
+T_MA_INFO;
+
+/*************************************************************/
+/* Dedicated channel parameter structure...                  */
+/*************************************************************/
+/*                                                           */
+/*************************************************************/
+typedef struct
+{
+  T_CHANNEL_INFO  *achan_ptr;         // Ptr to the Active channel (chan1 or chan2)
+  T_CHANNEL_INFO  chan1;
+  T_CHANNEL_INFO  chan2;
+
+  T_MA_INFO       ma;
+
+  WORD32          serv_sti_fn;        // Chan. desc. change time, serving domain.(-1 for not in use).
+  WORD32          neig_sti_fn;        // Chan. desc. change time, neighbor domain.(-1 for not in use).
+
+  // Frequency redefinition ongoing flag.
+  //-------------------------------------
+  UWORD8          freq_redef_flag;    // Set to TRUE when a Freq. Redef. must be confirmed.
+
+  // Timing Advance management.
+  //---------------------------
+  UWORD8          timing_advance;     // Currently used TA.
+  UWORD8          new_timing_advance; // New timing advance value to be used on 1st frame
+                                             // of the next reporting period.
+  // TXPWR management.
+  //-------------------
+  UWORD8          new_target_txpwr;   // New Target value for TXPWR control algo.
+
+
+  T_CELL_INFO     cell_desc;          // Ptr to the new serving cell to download.
+
+  // DAI test mode... DTX allowed...
+  UWORD8          dai_mode;           // Dai test mode.
+  BOOL            dtx_allowed;        // DTX allowed (flag).
+
+  // Encryption...
+  T_ENCRYPTION_KEY  ciph_key;
+  UWORD8            a5mode;
+
+  // For handover...
+  UWORD8          ho_acc;             // Handover access (part of HO reference)
+  WORD32          ho_acc_to_send;     // Set to 4 for SYNC HO and to -1 for ASYNC HO.
+  UWORD8          t3124;              // Timer used in Async. Ho.
+
+  // For DPAGC algorithms purpose
+  UWORD8          G_all[DPAGC_FIFO_LEN];
+  UWORD8          G_DTX[DPAGC_FIFO_LEN];
+  #if (AMR == 1)
+    UWORD8          G_amr[DPAGC_AMR_FIFO_LEN];
+  #endif
+
+  #if IDS
+  // IDS mode configuration
+    UWORD8        ids_mode;           // Information transfert capability coded on 2 bits
+                                      // 0: speech
+                                      // 1: data service
+                                      // 2: fax service
+  #endif
+  #if (AMR == 1)
+    T_AMR_CONFIGURATION  amr_configuration;
+    UWORD8               cmip;
+  #endif
+}
+T_DEDIC_SET;
+
+/*************************************************************/
+/* Dedicated channel parameter structure...                  */
+/*************************************************************/
+/*                                                           */
+/*************************************************************/
+typedef struct
+{
+  T_DEDIC_SET  *aset;       // Ptr to the Active parameter set
+  T_DEDIC_SET  *fset;       // Ptr to the Free parameter set
+  T_DEDIC_SET  set[2];      // Table of parameter set
+
+  T_MPHC_CHANNEL_MODE_MODIFY_REQ  mode_modif;  // New mode for a given subchannel.
+  WORD32                            SignalCode;  // Message name, set when a new param. set is given
+
+#if (FF_L1_TCH_VOCODER_CONTROL == 1)
+  UWORD8       reset_sacch; // Flag to control SACCH reset (set during CHAN ASSIGN and Hand-overs)
+  UWORD8       vocoder_on; // Flag to control execution of vocoder
+  UWORD8       start_vocoder; // Flag to trigger start of vocoder (vocoder must be started with a synchro start)
+#endif
+
+  UWORD8       sync_tch;    // Flag used to synchronize TCH/F or TCH/H.
+  UWORD8       reset_facch; // Flag used to reset FACCH buffer header on new IAS/CAS/handover
+  UWORD8       stop_tch;    // Flag used to stop TCH/F or TCH/H (VEGA pwrdown).
+
+  UWORD16      radio_freq;       // ARFCN buffer (returned by hopping algo).
+  UWORD16      radio_freq_d;     // 1 frame  delayed ARFCN.
+  UWORD16      radio_freq_dd;    // 2 frames delayed ARFCN.
+
+  BOOL         pwrc;        // Flag used to reject serving pwr meas. on beacon.
+
+  BOOL         handover_fail_mode;  // Flag used to indicate that the L1 wait for an handover fail request
+  #if (AMR == 1)
+    BOOL         sync_amr;        // Flag used to tell to the DSP that a new AMR paramters is ready in the NDB.
+  #endif
+}
+T_DEDIC_PARAM;
+
+/*************************************************************/
+/* Power Management structure...                             */
+/*************************************************************/
+typedef struct
+{
+  // fields of TST_SLEEP_REQ primitive ....
+  UWORD8      mode_authorized;    // NONE,SMALL,BIG,DEEP,ALL
+  UWORD32           clocks;             // clocks disabled in Big sleep
+
+  // 32 Khz gauging ....
+  UWORD8      gauging_task;       // ACTIVE, INACTIVE,WAIT-IQ
+  UWORD8      gaug_duration;      // gauging task duration
+  UWORD8      gaug_count;         // gauging task duration compteur
+  UWORD32     histo[SIZE_HIST][2];// gauging histogram
+  UWORD8      enough_gaug;        // enough good gauging
+  UWORD8      paging_scheduled;   // first Paging Frame
+
+  // flags and variables for wake-up ....
+  UWORD8      Os_ticks_required;  // TRUE : Os ticks to recover
+  UWORD8      frame_adjust;       // TRUE : adjust 1 frame
+  UWORD32     sleep_duration;     // sleep duration computed at wakeup
+
+  // flag for sleep ....
+  UWORD8      sleep_performed;    // NONE,SMALL,BIG,DEEP,ALL
+
+  // status of clocks modules  ....
+  UWORD32           modules_status;     // modules clocks status
+
+  // constantes for 32Khz filtering
+  UWORD32     c_clk_min;          // INIT state
+  UWORD32     c_clk_init_min;     // INIT state
+  UWORD32     c_clk_max;          // INIT state
+  UWORD32     c_clk_init_max;     // INIT state
+  UWORD32     c_delta_hf_acquis;  // ACQUIS state
+  UWORD32     c_delta_hf_update;  // UPDATE state
+
+  // trace gauging parameters
+  UWORD8      state;   // state of the gauging
+  UWORD32     lf;      // Number of the 32KHz
+  UWORD32     hf;	     // HF: nb_hf( Number of the 13MHz *6 )
+  UWORD32     root;	   // root & frac: the ratio of the HF & LF in each state.
+  UWORD32     frac;    
+
+}
+T_POWER_MNGT;
+
+/*************************************************************/
+/* code version structure...                                 */
+/*************************************************************/
+typedef struct
+{
+    // DSP versions & checksum
+    UWORD16 dsp_code_version;
+    UWORD16 dsp_patch_version;
+    UWORD16 dsp_checksum;     // DSP checksum : patch+code
+
+    // MCU versions
+    UWORD16 mcu_tcs_program_release;
+    UWORD16 mcu_tcs_official;
+    UWORD16 mcu_tcs_internal;
+    UWORD16 mcu_tm_version;
+}
+T_VERSION;
+
+#if L1_RECOVERY
+  typedef struct
+  {
+    UWORD32 frame_count;
+  }
+  T_L1S_RECOVER;
+#endif
+
+/***************************************************************************************/
+/* L1S global variable structure...                                                    */
+/***************************************************************************************/
+typedef struct
+{
+  //++++++++++++++++++++
+  // Power Management...
+  //++++++++++++++++++++
+
+  T_POWER_MNGT pw_mgr;             // data base for power management
+
+  // Time for debug & Simulation purpose...
+  //  -> used as base time for BTS simulation.
+  //-----------------------------------------
+  UWORD32      debug_time;         // time counter used by L3 scenario...
+
+  // L1S Tasks management...
+  //-----------------------------------------
+  T_TASK_STATUS  task_status[NBR_DL_L1S_TASKS];        // ...in L1S, scheduler.
+  UWORD8         frame_count;                          // ...nb frames to go.
+  UWORD8         forbid_meas;                          // ...frames where meas. ctrl is not allowed.
+
+  // MFTAB management variables...
+  //-----------------------------------------
+  UWORD8         afrm;             // active frame ID.
+  T_MFTAB  FAR   mftab;            // Multiframe table.
+
+  // Control parameters...
+  //-----------------------------------------
+  UWORD32   afc_frame_count;  // AFC, Frame count between 2 calls to afc control function.
+  WORD16    afc;              // AFC, Common Frequency controle.
+  WORD16    toa_shift;        // TOA, value used to update the TOA
+  UWORD8    toa_snr_mask;     // TOA, mask counter to reject TOA/SNR results.
+
+  UWORD16   toa_period_count;  // TOA frame period used in PACKET TRANSFER MODE
+  BOOL      toa_update;       // TOA, is set at the end of the update period, toa update occurs on next valid frame
+
+  // Flag registers for RF task controle...
+  //-----------------------------------------
+  // Made these control registers short's as more than 8-bits required.
+  UWORD16   tpu_ctrl_reg;     // (x,x,x,x,SYNC,RX,TX,MS) RX/TX/MS/SYNC bit ON whenever an
+                              // according "controle" has been setup in the current frame.
+  UWORD16   dsp_ctrl_reg;     // (x,x,x,x,x,RX,TX,MS) RX/TX/MS bit ON whenever an
+                              // according "controle" has been setup in the current frame.
+
+  //+++++++++++++++++++
+  // Serving...
+  //+++++++++++++++++++
+
+  // Serving frame number management.
+  //---------------------------------
+  T_TIME_INFO      actual_time;          // Time info: current FN, T1, T2, T3...
+  T_TIME_INFO      next_time;            // Time info: next    FN, T1, T2, T3...
+  T_TIME_INFO      next_plus_time;       // Time info: next    FN, T1, T2, T3...
+
+  // TXPWR management.
+  //-------------------
+  UWORD8           reported_txpwr;       // Reported value for TXPWR.
+  UWORD8           applied_txpwr;        // Current value for TXPWR.
+
+  // Last RXQUAL value.
+  //-------------------
+  UWORD8           rxqual;               // last rxqual value.
+
+  // Hardware info.
+  //---------------
+  UWORD32          tpu_offset;           // Current TPU offset register value safeguard.
+  UWORD32          tpu_offset_hw;        // Current TPU offset register value copied in the TPU.
+  UWORD16          tpu_win;              // tpu window identifier inside a TDMA.
+
+  // code versions
+  T_VERSION version;
+
+  #if (L1_GTT == 1)
+    UWORD8         tty_state;  // state for L1S GTT manager.
+    #if L2_L3_SIMUL
+      // GTT test
+      T_GTT_TEST_L1S gtt_test;
+    #endif
+  #endif
+
+ #if (L1_DYN_DSP_DWNLD == 1)
+  UWORD8       dyn_dwnld_state; // state for L1S DYN DWNLD manager
+ #endif
+  #if (AUDIO_TASK == 1)
+    // Audio task.
+    //-----------------------------------------
+    BOOL                  l1_audio_it_com;                  // Flag to enable the ITCOM.
+    UWORD8                audio_state[NBR_AUDIO_MANAGER];  // state for L1S audio manager.
+    #if (MELODY_E1)
+      T_L1S_MELODY_TASK   melody0;
+      T_L1S_MELODY_TASK   melody1;
+    #endif
+    #if (VOICE_MEMO)
+      T_L1S_VM_TASK       voicememo;
+    #endif
+    #if (L1_VOICE_MEMO_AMR)
+      T_L1S_VM_AMR_TASK   voicememo_amr;
+    #endif
+    #if (SPEECH_RECO)
+      T_L1S_SR_TASK       speechreco;
+    #endif
+    #if (AEC)
+      T_L1S_AEC_TASK      aec;
+    #endif
+    #if (MELODY_E2)
+      T_L1S_MELODY_E2_COMMON_VAR  melody_e2;
+      T_L1S_MELODY_E2_TASK        melody0_e2;
+      T_L1S_MELODY_E2_TASK        melody1_e2;
+    #endif
+  #endif
+
+  UWORD8  last_used_txpwr;
+
+  #if L1_GPRS
+    BOOL    ctrl_synch_before;   //control of synchro for CCCH reading en TN-2
+  #endif
+
+  #if L1_RECOVERY
+    T_L1S_RECOVER    recovery;
+  #endif
+  BOOL spurious_fb_detected;
+  
+  // Handling DTX mode
+  BOOL dtx_ul_on;
+  WORD8 facch_bursts;
+
+  // DTX mode in AMR
+  BOOL dtx_amr_dl_on;   // set to TRUE when the AMR is in DTX mode in downlink
+
+}
+T_L1S_GLOBAL;
+
+/***************************************************************************************/
+/* L1A global variable structure...                                                    */
+/***************************************************************************************/
+typedef struct
+{
+  // State for L1A state machines...
+  //-----------------------------------------
+  UWORD8    state[NBR_L1A_PROCESSES];
+
+  // Measurement tasks management...
+  //-----------------------------------------
+  UWORD32   l1a_en_meas[NBR_L1A_PROCESSES];
+
+  // Flag for forward/delete message management.
+  //---------------------------------------------
+  UWORD8    l1_msg_forwarded;
+
+#if (L1_DYN_DSP_DWNLD == 1)
+  // Dynamic donload global variables
+  T_L1A_DYN_DWNLD_GLOBAL dyn_dwnld;
+#endif
+
+  // signal code indicating the reason of L1C_DEDIC_DONE
+  UWORD32   confirm_SignalCode;
+
+  // Trace the best frequencies reported in MPHC_RXLEV_IND 
+#if (L1_MPHC_RXLEV_IND_REPORT_SORT==1)
+  UWORD16 tab_index[MAX_MEAS_RXLEV_IND_TRACE];
+  UWORD16 max_report; //max number of fq reported, can be < MAX_MEAS_RXLEV_IND_TRACE if list is smaller
+#endif
+}
+T_L1A_GLOBAL;
+
+/***************************************************************************************/
+/* L1A -> L1S communication structure...                                               */
+/***************************************************************************************/
+typedef struct
+{
+  //+++++++++++++++++++
+  // Serving Cell...
+  //+++++++++++++++++++
+
+  // Serving Cell identity and information.
+  //---------------------------------------
+  T_CELL_INFO      Scell_info;
+  T_SMEAS          Smeas_dedic;
+
+  UWORD8           Scell_IL_for_rxlev;
+  T_INPUT_LEVEL    Scell_used_IL;
+  T_INPUT_LEVEL    Scell_used_IL_d;
+  T_INPUT_LEVEL    Scell_used_IL_dd;
+
+  T_BCCHS          nbcchs;
+  T_BCCHS          ebcchs;
+
+  // Synchro information.
+  //---------------------------------------
+  WORD8            tn_difference;        // Timeslot difference for next synchro.
+  UWORD8           dl_tn;                // Current timeslot for downlink stuffs.
+  #if L1_GPRS
+    UWORD8           dsp_scheduler_mode; // DSP Scheduler mode (GPRS or GSM).
+  #endif
+
+  // Idle parameters.
+  //-----------------
+  BOOL              bcch_combined;    // BS_CCCH_SDCCH_COMB flag.
+  UWORD8            bs_pa_mfrms;      // BS_PA_MFRMS parameter.
+  UWORD8            bs_ag_blks_res;   // BS_AG_BLKS_RES parameter.
+  UWORD8            ccch_group;       // CCCH_GROUP parameter.
+  UWORD8            page_group;       // PAGING_GROUP parameter.
+  UWORD8            page_block_index; // Paging block index paramter.
+  T_IDLE_TASK_INFO  idle_task_info;   // Idle task positions...
+  UWORD8            nb_pch_per_mf51;  // nbr paging blocks per mf51.
+
+  // CBCH parameters.
+  // ----------------
+  UWORD32               offset_tn0;         // TPU offset for TN=0 (used for SMSCB only).
+  T_CHANNEL_DESCRIPTION cbch_desc;          // CBCH (SMSCB) channel description.
+  T_MOBILE_ALLOCATION   cbch_freq_list;     // CBCH frequency list (hopping freq list).
+  UWORD32               mf51_fn;            // Starting FN (for CBCH reading.
+  UWORD8                cbch_start_in_mf51; // Starting position of CBCH in the MF51.
+  T_CBCH_HEAD_SCHEDULE  norm_cbch_schedule; // Normal CBCH scheduling structure.
+  T_CBCH_HEAD_SCHEDULE  ext_cbch_schedule;  // Extended CBCH scheduling structure.
+  T_CBCH_INFO_SCHEDULE  cbch_info_req;
+  BOOL                  pre_scheduled_cbch; // CBCH task has to be scheduled 1 FN in advance
+  BOOL                  change_synchro_cbch;// A Pseudo Synchro is needed to read CBCH block
+  UWORD8                tn_smscb;           // CBCH TN taking into account new Synchro
+
+  // Random Access information.
+  // ----------------------------
+  T_RA_TASK_INFO   ra_info;
+
+  // ADC management.
+  //-------------------
+  UWORD16          adc_mode;
+  UWORD8           adc_idle_period;
+  UWORD8           adc_traffic_period;
+  UWORD8           adc_cpt;
+
+  // TXPWR management.
+  //-------------------
+  UWORD8           powerclass_band1;     // Power class for the MS, given in ACCESS LINK mode (GSM Band).
+  UWORD8           powerclass_band2;     // Power class for the MS, given in ACCESS LINK mode (DCS Band).
+
+  // Dedicated parameters.
+  //----------------------
+  T_DEDIC_PARAM    dedic_set;             // Dedicated channel parameters.
+
+  //+++++++++++++++++++
+  // Neighbour Cells...
+  //+++++++++++++++++++
+
+  T_BCCHN_LIST     bcchn;
+  T_NSYNC_LIST     nsync;
+
+  // BA list / FULL list.
+  //---------------------
+  T_BA_LIST        ba_list;
+  T_FULL_LIST      full_list;
+  T_FULL_LIST_MEAS *full_list_ptr;
+
+  //+++++++++++++++++++
+  // L1S scheduler...
+  //+++++++++++++++++++
+
+  // L1S tasks management...
+  //-----------------------------------------
+  BOOL            task_param[NBR_DL_L1S_TASKS];   // ...synchro semaphores.
+  BOOL            l1s_en_task[NBR_DL_L1S_TASKS];  // ...enable register.
+  UWORD32         time_to_next_l1s_task;          // time to wait to reach starting frame of next task.
+  UWORD8          l1a_activity_flag;              // Activity flag.
+
+  // Measurement tasks management...
+  //-----------------------------------------
+  UWORD32         meas_param;         // Synchro semaphore bit register.
+  UWORD32         l1s_en_meas;        // Enable task bit register.
+
+  // L1 mode...
+  //-----------------------------------------
+  UWORD32         mode;               // functional mode: CS_MODE, I_MODE...
+
+  //++++++++++++++++++++++++
+  // Controle parameters...
+  //++++++++++++++++++++++++
+  UWORD32         fb_mode;            // Mode for fb detection algorithm.
+  UWORD8          toa_reset;          // Flag for TOA algo. reset.
+
+  // Input level memory for AGC management.
+  //---------------------------------------
+  T_INPUT_LEVEL    last_input_level[NBMAX_CARRIER+1];
+
+  BOOL          recovery_flag;       // in case of the system is down and needs to be recovered
+
+  //++++++++++++++++++++++++
+  // Audio task...
+  //++++++++++++++++++++++++
+  #if (AUDIO_TASK == 1)
+    #if (KEYBEEP)
+      T_KEYBEEP_TASK keybeep_task;
+    #endif
+    #if (TONE)
+      T_TONE_TASK    tone_task;
+    #endif
+    #if (MELODY_E1)
+      T_MELODY_TASK  melody0_task;
+      T_MELODY_TASK  melody1_task;
+    #endif
+    #if (VOICE_MEMO)
+      T_VM_TASK      voicememo_task;
+    #endif
+    #if (L1_VOICE_MEMO_AMR)
+      T_VM_AMR_TASK  voicememo_amr_task;
+    #endif
+    #if (SPEECH_RECO)
+      T_SR_TASK      speechreco_task;
+    #endif
+    #if (AEC)
+      T_AEC_TASK     aec_task;
+    #endif
+    #if (FIR)
+      T_FIR_TASK     fir_task;
+    #endif
+    #if (AUDIO_MODE)
+      T_AUDIO_MODE_TASK audio_mode_task;
+    #endif
+    #if (MELODY_E2)
+      T_MELODY_E2_TASK  melody0_e2_task;
+      T_MELODY_E2_TASK  melody1_e2_task;
+    #endif
+    #if (L1_CPORT == 1)
+      T_CPORT_TASK    cport_task;
+    #endif
+  #endif
+
+  //+++++++++++++
+  // GTT task
+  //+++++++++++++
+
+  #if (L1_GTT == 1)
+    T_GTT_TASK   gtt_task;
+  #endif
+
+  // Dynamic DSP download task
+   #if (L1_DYN_DSP_DWNLD == 1)
+      T_DYN_DWNLD_TASK_COMMAND       dyn_dwnld_task;
+   #endif
+
+}
+T_L1A_L1S_COM;
+
+/***************************************************************************************/
+/* L1A -> DSP communication structure...                                               */
+/***************************************************************************************/
+typedef struct
+{
+  UWORD8           dsp_w_page;       // Active page for ARM "writting" to DSP {0,1}.
+  UWORD8           dsp_r_page;       // Active page for ARM "reading" from DSP {0,1}.
+  UWORD8           dsp_r_page_used;  // Used in "l1_synch" to know if the read page must be chged.
+
+  T_DB_DSP_TO_MCU *dsp_db_r_ptr;     // MCU<->DSP comm. read  page (Double Buffered comm. memory).
+  T_DB_MCU_TO_DSP *dsp_db_w_ptr;     // MCU<->DSP comm. write page (Double Buffered comm. memory).
+  T_NDB_MCU_DSP   *dsp_ndb_ptr;      // MCU<->DSP comm. read/write (Non Double Buffered comm. memory).
+
+  T_PARAM_MCU_DSP *dsp_param_ptr;    // MCU<->DSP comm. read/write (Param comm. memory).
+
+ #if (DSP_DEBUG_TRACE_ENABLE == 1)
+   T_DB2_DSP_TO_MCU *dsp_db2_current_r_ptr;
+   T_DB2_DSP_TO_MCU *dsp_db2_other_r_ptr;
+ #endif
+}
+T_L1S_DSP_COM;
+
+/***************************************************************************************/
+/* L1A -> TPU communication structure...                                               */
+/***************************************************************************************/
+typedef struct
+{
+  UWORD8    tpu_w_page;       // Active page for ARM "writting" to TPU {0,1}.
+  UWORD32  *tpu_page_ptr;     // Current Pointer within the active "tpu_page".
+  #if (CODE_VERSION == SIMULATION)
+    T_reg_cmd  *reg_cmd;      // command register for TPU & DSP enabling and pages pgmation
+  #else
+    UWORD16    *reg_cmd;      // command register for TPU & DSP enabling and pages pgmation
+  #endif
+  UWORD32      *reg_com_int;  // communication int. register
+  UWORD32      *offset;       // offset register
+}
+T_L1S_TPU_COM;
+
+/***************************************************************************************/
+/* L1 configuration structure                                               */
+/***************************************************************************************/
+
+typedef struct
+{
+  UWORD8   id;                   //standard identifier
+
+
+
+  UWORD16  radio_band_support;
+
+
+  UWORD8   swap_iq_band1;
+  UWORD8   swap_iq_band2;
+
+  UWORD32  first_radio_freq;
+  UWORD32  first_radio_freq_band2;
+  UWORD32  radio_freq_index_offset;
+  UWORD32  nbmax_carrier;
+  UWORD32  nbmeas;
+  UWORD32  max_txpwr_band1;
+  UWORD32  max_txpwr_band2;
+  UWORD32  txpwr_turning_point;
+
+  UWORD16  cal_freq1_band1;
+  UWORD16  cal_freq1_band2;
+  UWORD16  g_magic_band1;
+  UWORD16  g_magic_band2;
+  UWORD16  lna_att_band1;
+  UWORD16  lna_att_band2;
+  UWORD16  lna_switch_thr_low_band1;
+  UWORD16  lna_switch_thr_low_band2;
+  UWORD16  lna_switch_thr_high_band1;
+  UWORD16  lna_switch_thr_high_band2;
+}
+T_L1_STD_CNFG;
+
+//RF dependent parameter definitions
+typedef struct
+{
+  UWORD16  rx_synth_setup_time;
+  UWORD8   rx_synth_load_split;
+  WORD16   rx_synth_start_time;
+  WORD16   rx_change_offset_time;
+  WORD16   rx_change_synchro_time;
+  UWORD8   rx_tpu_scenario_ending;
+
+  UWORD16  tx_synth_setup_time;
+  UWORD8   tx_synth_load_split;
+  WORD16   tx_synth_start_time;
+  WORD16   tx_change_offset_time;
+  WORD16   tx_nb_duration;
+  WORD16   tx_ra_duration;
+  UWORD8   tx_nb_load_split;
+  UWORD8   tx_ra_load_split;
+  UWORD8   tx_tpu_scenario_ending;
+
+  WORD16   fb26_anchoring_time;
+  WORD16   fb26_change_offset_time;
+
+  UWORD32  prg_tx_gsm;
+  UWORD32  prg_tx_dcs;
+
+  UWORD16  low_agc_noise_thr;
+  UWORD16  high_agc_sat_thr;
+
+  UWORD16  low_agc;
+  UWORD16  high_agc;
+
+  UWORD16  il_min;
+
+  UWORD16  fixed_txpwr;
+  WORD16   eeprom_afc;
+  WORD8    setup_afc_and_rf;
+
+  UWORD32  psi_sta_inv;
+  UWORD32  psi_st;
+  UWORD32  psi_st_32;
+  UWORD32  psi_st_inv;
+
+  #if (VCXO_ALGO==1)
+    WORD16   afc_dac_center;
+    WORD16   afc_dac_min;
+    WORD16   afc_dac_max;
+    WORD16   afc_snr_thr;
+    UWORD8   afc_algo;
+    UWORD8   afc_win_avg_size_M;
+    UWORD8   rgap_algo;
+    UWORD8   rgap_bad_snr_count_B;
+  #endif
+
+  UWORD8   guard_bits;
+
+  #if DCO_ALGO
+    BOOL     dco_enabled;
+  #endif
+
+  #if (ANLG_FAM == 1)
+    UWORD16 debug1;
+    UWORD16 afcctladd;
+    UWORD16 vbuctrl;
+    UWORD16 vbdctrl;
+    UWORD16 bbctrl;
+    UWORD16 apcoff;
+    UWORD16 bulioff;
+    UWORD16 bulqoff;
+    UWORD16 dai_onoff;
+    UWORD16 auxdac;
+    UWORD16 vbctrl;
+    UWORD16 apcdel1;
+  #endif
+  #if (ANLG_FAM == 2)
+    UWORD16 debug1;
+    UWORD16 afcctladd;
+    UWORD16 vbuctrl;
+    UWORD16 vbdctrl;
+    UWORD16 bbctrl;
+    UWORD16 bulgcal;
+    UWORD16 apcoff;
+    UWORD16 bulioff;
+    UWORD16 bulqoff;
+    UWORD16 dai_onoff;
+    UWORD16 auxdac;
+    UWORD16 vbctrl1;
+    UWORD16 vbctrl2;
+    UWORD16 apcdel1;
+    UWORD16 apcdel2;
+  #endif
+  #if (ANLG_FAM == 3)
+    UWORD16 debug1;
+    UWORD16 afcctladd;
+    UWORD16 vbuctrl;
+    UWORD16 vbdctrl;
+    UWORD16 bbctrl;
+    UWORD16 bulgcal;
+    UWORD16 apcoff;
+    UWORD16 bulioff;
+    UWORD16 bulqoff;
+    UWORD16 dai_onoff;
+    UWORD16 auxdac;
+    UWORD16 vbctrl1;
+    UWORD16 vbctrl2;
+    UWORD16 apcdel1;
+    UWORD16 apcdel2;
+    UWORD16 vbpop;
+    UWORD16 vau_delay_init;
+    UWORD16 vaud_cfg;
+    UWORD16 vauo_onoff;
+    UWORD16 vaus_vol;
+    UWORD16 vaud_pll;
+  #endif
+
+  #if L1_GPRS
+    UWORD16  toa_pm_thres;  // PM threshold for TOA algorithm feeding in packet transfer mode
+  #endif
+}
+T_L1_PARAMS;
+
+typedef struct
+{
+ T_L1_STD_CNFG  std;            //standard: GSM,GSM_E,GSM850,DCS,PCS,DUAL,DUALEXT
+ UWORD8         pwr_mngt;       //power management active
+ UWORD8         tx_pwr_code;
+ UWORD16        dwnld;
+ T_L1_PARAMS    params;
+ double         dpll;           //dpll factor
+
+ #if TESTMODE
+   //Define the TestMode flag and TestMode parameters
+   UWORD8  TestMode;
+
+   UWORD8  agc_enable;
+   UWORD8  afc_enable;
+   UWORD8  adc_enable;
+
+   T_TM_PARAMS tmode;  //TestMode parameters structure
+ #endif
+
+}
+T_L1_CONFIG;
+
+/***************************************************************************************/
+/* API HISR -> L1A communication structure... Defined in case dynamic download is defined                                          */
+/***************************************************************************************/
+/***************************************************************************************/
+/* Global API HISR -Defined in case dynamic download is defined                                          
+/***************************************************************************************/
+
+
+#if(L1_DYN_DSP_DWNLD==1)
+typedef struct
+{
+  T_L1A_DYN_DWNLD_HISR_COM dyn_dwnld;
+} T_L1A_API_HISR_COM;
+
+typedef struct
+{
+  T_L1_DYN_DWNLD_API_HISR dyn_dwnld;
+} T_L1_API_HISR;
+#endif
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_macro.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_macro.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,93 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_MACRO.H
+ *
+ *        Filename l1_macro.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+#include "l1_confg.h"
+
+#if(L1_DYN_DSP_DWNLD == 1)
+  #include "l1_dyn_dwl_const.h"
+#endif
+
+#if (TRACE_TYPE==5) && NUCLEUS_TRACE
+//WARNING : this type of trace takes a lot of space in data RAM (~16kB)
+
+  // switch for Nucleus debugging messages.
+  #define NU_ALLOC_ERR      0
+  #define NU_DEALLOC_ERR    1
+  #define NU_RCVE_QUEUE_ERR 2
+  #define NU_SEND_QUEUE_ERR 3
+  #define NU_OBTA_SEMA_ERR  4
+  #define NU_RLSE_SEMA_ERR  5
+
+  // Nucleus debug function.
+    #define DEBUGMSG(status,type) \
+    if(status) switch(type) \
+    { \
+      case NU_ALLOC_ERR: \
+      printf("NU mem. allocation error %d file %s line %d\n", status,__FILE__,__LINE__); \
+      exit(0);            \
+      break; \
+      \
+      case NU_DEALLOC_ERR: \
+      printf("NU mem. deallocation error %d file %s line %d\n", status,__FILE__,__LINE__); \
+      exit(0);            \
+      break; \
+      \
+      case NU_RCVE_QUEUE_ERR: \
+      printf("NU rcve queue error %d file %s line %d\n", status,__FILE__,__LINE__); \
+      exit(0);            \
+      break; \
+      \
+      case NU_SEND_QUEUE_ERR: \
+      printf("NU send queue error %d file %s line %d\n", status,__FILE__,__LINE__); \
+      exit(0);            \
+      break; \
+      \
+      case NU_OBTA_SEMA_ERR: \
+      printf("NU obtain semaph. error %d file %s line %d\n", status,__FILE__,__LINE__); \
+      exit(0);            \
+      break; \
+      \
+      case NU_RLSE_SEMA_ERR: \
+      printf("NU release semaph. error %d file %s line %d\n", status,__FILE__,__LINE__); \
+      exit(0);            \
+      break; \
+      \
+      default: \
+      printf("Unknown error %d file %s line %d\n", status,__FILE__,__LINE__); \
+      exit(0);            \
+      break; \
+    }
+#else
+  #define DEBUGMSG(status,type)
+#endif
+
+/************************************************************/
+/* Macros for FAST INTEGER MODULO implementation.           */
+/************************************************************/
+#define IncMod(operand, increment, modulo) \
+  if( (operand += increment) >= modulo ) operand -= modulo
+  
+
+// Define MACRO for selecting the min. time to next task.
+#define Select_min_time(Task_Time, Min_Time) \
+  if(Task_Time < Min_Time) Min_Time = Task_Time;
+
+
+/************************************************************/
+/* Macros for MCU/DSP API address conversion    .           */
+/************************************************************/
+#if(L1_DYN_DSP_DWNLD == 1)
+
+#define API_address_dsp2mcu(dsp_address) \
+  (MCU_API_BASE_ADDRESS + ((API)((dsp_address) - DSP_API_BASE_ADDRESS) * 2))
+
+#define API_address_mcu2dsp(mcu_address) \
+  (DSP_API_BASE_ADDRESS + ((UWORD32)((mcu_address) - MCU_API_BASE_ADDRESS) / 2))
+#endif
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_mftab.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_mftab.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,574 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_MFTAB.H
+ *
+ *        Filename l1_mftab.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+/***********************************************************
+ * Content:
+ *   This file contains the MultiFrame tables for all L1S
+ *   basic tasks.
+ ***********************************************************/
+
+/*******************************************************************************************/
+/* Multiframe Blocks for Dynamic MFTAB Building purpose.                                   */
+/*******************************************************************************************/
+// Multiframe table size....
+#define BLOC_FBNEW_SIZE    14 + 2   // FB.
+
+#define BLOC_SB2_SIZE       5 + 2   // SB2.
+
+#define BLOC_SBCONF_SIZE    4 + 2   // SBCONF.
+#define BLOC_BCCHN_SIZE     7 + 2   // BCCHN.
+#define BLOC_BCCHN_TOP_SIZE 7 + 2   // BCCHN_TOP (BCCHN top priority)
+
+#define BLOC_SYNCHRO_SIZE         1       // SYNC.
+#define BLOC_ADC_SIZE             1       // ADC in CS_MODE0
+#define BLOC_ABORT_SIZE           3       // ABORT.
+#define BLOC_RAACC_SIZE           3       // RAACC.
+#define S_RECT4_SIZE              6       // All "rectangular 4" serving tasks: NP/EP/BCCHS/ALLC.
+#define BLOC_TCHT_SIZE            3       // TCHTF / TCHTH / TCHD.
+#define BLOC_TCHA_SIZE            3       // TCHA.
+#define BLOC_SMSCB_SIZE           6       // SMSCB.
+#define BLOC_FB51_SIZE           14       // FB51.
+#define BLOC_SB51_SIZE            4       // SB51.
+#define BLOC_SBCNF51_SIZE         4       // SBCNF51.
+#define BLOC_FB26_SIZE            4       // FB26.
+#define BLOC_SB26_SIZE            5       // SB26.
+#define BLOC_SBCNF26_SIZE         5       // SBCNF26.
+#define BLOC_HWTEST_SIZE          4       // HWTEST.
+#define BLOC_DUL_ADL_MIXED_SIZED  7
+#if (L1_GPRS)
+  #define BLOC_BCCHN_TRAN_SIZE     7  // BCCHN_TRAN.
+#endif
+
+
+        
+#ifdef L1_ASYNC_C
+  /*----------------------------------------------------*/
+  /* TASK: Frequency Burst search...                    */
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_FBNEW[] =      
+  { 
+    {l1s_ctrl_msagc,FBNEW,NO_PAR},                               {NULL,NO_PAR,NO_PAR}, // frame 1
+                                                                 {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_msagc,FBNEW,NO_PAR},{l1s_ctrl_fb,FBNEW,NO_PAR},    {NULL,NO_PAR,NO_PAR}, // frame 3
+                                                                 {NULL,NO_PAR,NO_PAR}, // frame 4
+                                  {l1s_read_mon_result,FBNEW, 1},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                  {l1s_read_mon_result,FBNEW, 2},{NULL,NO_PAR,NO_PAR}, // frame 6
+                                  {l1s_read_mon_result,FBNEW, 3},{NULL,NO_PAR,NO_PAR}, // frame 7
+                                  {l1s_read_mon_result,FBNEW, 4},{NULL,NO_PAR,NO_PAR}, // frame 8
+                                  {l1s_read_mon_result,FBNEW, 5},{NULL,NO_PAR,NO_PAR}, // frame 9
+                                  {l1s_read_mon_result,FBNEW, 6},{NULL,NO_PAR,NO_PAR}, // frame 10
+                                  {l1s_read_mon_result,FBNEW, 7},{NULL,NO_PAR,NO_PAR}, // frame 11
+                                  {l1s_read_mon_result,FBNEW, 8},{NULL,NO_PAR,NO_PAR}, // frame 12
+                                  {l1s_read_mon_result,FBNEW, 9},{NULL,NO_PAR,NO_PAR}, // frame 13
+                                  {l1s_read_mon_result,FBNEW,10},{NULL,NO_PAR,NO_PAR}, // frame 14
+                                  {l1s_read_mon_result,FBNEW,11},{NULL,NO_PAR,NO_PAR}, // frame 15
+                                  {l1s_read_mon_result,FBNEW,12},{NULL,NO_PAR,NO_PAR}  // frame 16
+  };
+                                           
+  /*----------------------------------------------------*/
+  /* TASK: SB2, New Synchro Burst search...             */
+  /*----------------------------------------------------*/
+  /*       C W R           -> AGC                       */  
+  /*           C W W R     -> 1st SB                    */  
+  /*             C W W R   -> 2nd SB                    */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_SB2[] = 
+  {
+    {l1s_ctrl_msagc,SB2,NO_PAR},                              {NULL,NO_PAR,NO_PAR}, // frame 1
+                                                              {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_msagc,SB2,NO_PAR}, {l1s_ctrl_sbgen,SB2,1},      {NULL,NO_PAR,NO_PAR}, // frame 3
+                                 {l1s_ctrl_sbgen,SB2,2},      {NULL,NO_PAR,NO_PAR}, // frame 4
+                                                              {NULL,NO_PAR,NO_PAR}, // frame 5
+                                 {l1s_read_mon_result,SB2,1}, {NULL,NO_PAR,NO_PAR}, // frame 6
+                                 {l1s_read_mon_result,SB2,2}, {NULL,NO_PAR,NO_PAR}  // frame 7
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: SBCONF, Synchro confirmation.                */
+  /*----------------------------------------------------*/
+  /*       C W R           -> AGC                       */  
+  /*           C W W R     -> SBCONF                    */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_SBCONF[] = 
+  {
+    {l1s_ctrl_msagc,SBCONF,1},                               {NULL,NO_PAR,NO_PAR}, // frame 1
+                                                             {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_msagc,SBCONF,1},{l1s_ctrl_sbgen,SBCONF,1},     {NULL,NO_PAR,NO_PAR}, // frame 3
+                                                             {NULL,NO_PAR,NO_PAR}, // frame 4
+                                                             {NULL,NO_PAR,NO_PAR}, // frame 5
+                              {l1s_read_mon_result,SBCONF,1},{NULL,NO_PAR,NO_PAR}  // frame 6
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: Serving cell Normal BCCH reading.            */
+  /*----------------------------------------------------*/
+  /* frame 1 2 3 4 5 6                                  */  
+  /*       | | | | | |                                  */  
+  /*       C W R | | |     -> burst 1                   */  
+  /*         C W R | |     -> burst 2                   */  
+  /*           C W R |     -> burst 3                   */  
+  /*             C W R     -> burst 4                   */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_NBCCHS[] =    
+  { 
+    {l1s_ctrl_snb_dl,NBCCHS,BURST_1},                                 {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_ctrl_snb_dl,NBCCHS,BURST_2},                                 {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_snb_dl,NBCCHS,BURST_1},{l1s_ctrl_snb_dl,NBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_snb_dl,NBCCHS,BURST_2},{l1s_ctrl_snb_dl,NBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                     {l1s_read_snb_dl,NBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                     {l1s_read_snb_dl,NBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: Serving cell Extended BCCH reading.          */
+  /*----------------------------------------------------*/
+  /* frame 1 2 3 4 5 6                                  */  
+  /*       | | | | | |                                  */  
+  /*       C W R | | |     -> burst 1                   */  
+  /*         C W R | |     -> burst 2                   */  
+  /*           C W R |     -> burst 3                   */  
+  /*             C W R     -> burst 4                   */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_EBCCHS[] =    
+  { 
+    {l1s_ctrl_snb_dl,EBCCHS,BURST_1},                                 {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_ctrl_snb_dl,EBCCHS,BURST_2},                                 {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_snb_dl,EBCCHS,BURST_1},{l1s_ctrl_snb_dl,EBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_snb_dl,EBCCHS,BURST_2},{l1s_ctrl_snb_dl,EBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                     {l1s_read_snb_dl,EBCCHS,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                     {l1s_read_snb_dl,EBCCHS,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: Neighbour Cell SYStem info reading.          */
+  /*----------------------------------------------------*/
+  /*   C W R                 -> AGC                     */  
+  /*       C W W W W W R     -> all bursts              */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_BCCHN[] =     
+  { 
+    {l1s_ctrl_msagc,BCCHN,NO_PAR},                            {NULL,NO_PAR,NO_PAR}, // frame 1
+                                                              {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_msagc,BCCHN,NO_PAR},{l1s_ctrl_nnb,BCCHN,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 3
+                                                              {NULL,NO_PAR,NO_PAR}, // frame 4 
+                                                              {NULL,NO_PAR,NO_PAR}, // frame 5 
+                                                              {NULL,NO_PAR,NO_PAR}, // frame 6 
+                                                              {NULL,NO_PAR,NO_PAR}, // frame 7 
+                                                              {NULL,NO_PAR,NO_PAR}, // frame 8  
+                                  {l1s_read_nnb,BCCHN,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 9              
+  }; 
+
+  /*----------------------------------------------------*/
+  /* TASK: Neighbour Cell SYStem info reading.          */
+  /*----------------------------------------------------*/
+  /*   C W R                 -> AGC                     */  
+  /*       C W W W W W R     -> all bursts              */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_BCCHN_TOP[] =     
+  { 
+    {l1s_ctrl_msagc,BCCHN_TOP,NO_PAR},                                {NULL,NO_PAR,NO_PAR}, // frame 1
+                                                                      {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_msagc,BCCHN_TOP,NO_PAR},{l1s_ctrl_nnb,BCCHN_TOP,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 3
+                                                                      {NULL,NO_PAR,NO_PAR}, // frame 4 
+                                                                      {NULL,NO_PAR,NO_PAR}, // frame 5 
+                                                                      {NULL,NO_PAR,NO_PAR}, // frame 6 
+                                                                      {NULL,NO_PAR,NO_PAR}, // frame 7 
+                                                                      {NULL,NO_PAR,NO_PAR}, // frame 8  
+                                      {l1s_read_nnb,BCCHN_TOP,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 9              
+  }; 
+
+  /*----------------------------------------------------*/
+  /* TASK: Neighbour Cell SYStem info reading.          */
+  /*       for packet transfer mode                     */
+  /*----------------------------------------------------*/
+  /*       C W W W W W R     -> all bursts              */  
+  /*----------------------------------------------------*/
+#if (L1_GPRS)
+  const T_FCT BLOC_BCCHN_TRAN[] =     
+  { 
+                                  {l1s_ctrl_nnb,BCCHN_TRAN,NO_PAR},{NULL,NO_PAR,NO_PAR}, // frame 1
+                                                                   {NULL,NO_PAR,NO_PAR}, // frame 2 
+                                                                   {NULL,NO_PAR,NO_PAR}, // frame 3 
+                                                                   {NULL,NO_PAR,NO_PAR}, // frame 4 
+                                                                   {NULL,NO_PAR,NO_PAR}, // frame 5 
+                                                                   {NULL,NO_PAR,NO_PAR}, // frame 6  
+                                  {l1s_read_nnb,BCCHN_TRAN,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 7              
+  }; 
+#endif
+
+  /*----------------------------------------------------*/
+  /* TASK: Synchronization (camp on a new serving cell) */
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_SYNCHRO[] =      
+  { 
+    {l1s_new_synchro,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR} // frame 1
+  }; 
+
+
+  /*----------------------------------------------------*/
+  /* TASK: ADC measurement in CS_MODE0                  */
+  /*       C                                            */
+  /* the ADC is performed inside the frame and the      */
+  /* result is red in the same frame due to an          */
+  /* Interrupt (handle by Riviera)                      */
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_ADC[] =      
+  { 
+    {l1s_ctrl_ADC,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 1
+  };
+
+           
+  /*----------------------------------------------------*/
+  /* TASK: Short Message Service Cell Broadcast         */
+  /*----------------------------------------------------*/
+  /* frame   1 2 3 4 5 6                                */  
+  /*         | | | | | |                                */  
+  /*         C W R | | | -> hopp. + burst 1             */  
+  /*           C W R | | -> hopp. + burst 2             */  
+  /*             C W R | -> hopp. + burst 3             */  
+  /*               C W R -> hopp. + burst 4 + Synch back*/  
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_SMSCB[] =      
+  { 
+    {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_ctrl_smscb, SMSCB,BURST_1},                                {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_ctrl_smscb, SMSCB,BURST_2},                                {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_read_snb_dl,SMSCB,BURST_1},{l1s_ctrl_smscb, SMSCB,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_hopping_algo,SMSCB,NO_PAR},{l1s_read_snb_dl,SMSCB,BURST_2},{l1s_ctrl_smscb, SMSCB,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                                                    {l1s_read_snb_dl,SMSCB,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                                                    {l1s_read_snb_dl,SMSCB,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  }; 
+  
+  /*----------------------------------------------------*/
+  /* TASK: Normal Paging...                             */
+  /*----------------------------------------------------*/
+  /* frame 1 2 3 4 5 6                                  */  
+  /*       | | | | | |                                  */  
+  /*       C W R | | |     -> burst 1                   */  
+  /*         C W R | |     -> burst 2                   */  
+  /*           C W R |     -> burst 3                   */  
+  /*             C W R     -> burst 4                   */  
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_NP[] =      
+  { 
+    {l1s_ctrl_snb_dl,NP,BURST_1},                             {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_ctrl_snb_dl,NP,BURST_2},                             {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_snb_dl,NP,BURST_1},{l1s_ctrl_snb_dl,NP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_snb_dl,NP,BURST_2},{l1s_ctrl_snb_dl,NP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                 {l1s_read_snb_dl,NP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                 {l1s_read_snb_dl,NP,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  }; 
+           
+  /*----------------------------------------------------*/
+  /* TASK: Extended Paging task...                      */
+  /*----------------------------------------------------*/
+  /* frame 1 2 3 4 5 6                                  */  
+  /*       | | | | | |                                  */  
+  /*       C W R | | |     -> burst 1                   */  
+  /*         C W R | |     -> burst 2                   */  
+  /*           C W R |     -> burst 3                   */  
+  /*             C W R     -> burst 4                   */  
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_EP[] =      
+  { 
+    {l1s_ctrl_snb_dl,EP,BURST_1},                             {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_ctrl_snb_dl,EP,BURST_2},                             {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_snb_dl,EP,BURST_1},{l1s_ctrl_snb_dl,EP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_snb_dl,EP,BURST_2},{l1s_ctrl_snb_dl,EP,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                 {l1s_read_snb_dl,EP,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                 {l1s_read_snb_dl,EP,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  }; 
+
+  /*----------------------------------------------------*/
+  /* TASK: All CCCH reading task...                     */
+  /*----------------------------------------------------*/
+  /* frame 1 2 3 4 5 6                                  */  
+  /*       | | | | | |                                  */  
+  /*       C W R | | |     -> burst 1                   */  
+  /*         C W R | |     -> burst 2                   */  
+  /*           C W R |     -> burst 3                   */  
+  /*             C W R     -> burst 4                   */  
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_ALLC[] =      
+  { 
+    {l1s_ctrl_snb_dl,ALLC,BURST_1},                               {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_ctrl_snb_dl,ALLC,BURST_2},                               {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_snb_dl,ALLC,BURST_1},{l1s_ctrl_snb_dl,ALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_snb_dl,ALLC,BURST_2},{l1s_ctrl_snb_dl,ALLC,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                   {l1s_read_snb_dl,ALLC,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                   {l1s_read_snb_dl,ALLC,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  }; 
+
+  /*----------------------------------------------------*/
+  /* TASK: SDCCH                                        */
+  /*----------------------------------------------------*/
+  /* frame 1 2 3 4 5 6                                  */  
+  /*       | | | | | |                                  */  
+  /*       C W R | | |     -> burst 1                   */  
+  /*         C W R | |     -> burst 2                   */  
+  /*           C W R |     -> burst 3                   */  
+  /*             C W R     -> burst 4                   */  
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_DDL[] = 
+  { 
+    {l1s_hopping_algo,DDL,NO_PAR},{l1s_ctrl_snb_dl,  DDL,BURST_1},                                {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_hopping_algo,DDL,NO_PAR},{l1s_ctrl_snb_dl,  DDL,BURST_2},                                {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_hopping_algo,DDL,NO_PAR},{l1s_read_dedic_dl,DDL,BURST_1},{l1s_ctrl_snb_dl,  DDL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_hopping_algo,DDL,NO_PAR},{l1s_read_dedic_dl,DDL,BURST_2},{l1s_ctrl_snb_dl,  DDL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                                                  {l1s_read_dedic_dl,DDL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                                                  {l1s_read_dedic_dl,DDL,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  }; 
+
+  const T_FCT  BLOC_DUL[] = 
+  { 
+    {l1s_hopping_algo,DUL,NO_PAR},{l1s_ctrl_snb_ul,   DUL,BURST_1},                                 {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_hopping_algo,DUL,NO_PAR},{l1s_ctrl_snb_ul,   DUL,BURST_2},                                 {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_hopping_algo,DUL,NO_PAR},{l1s_read_tx_result,DUL,BURST_1},{l1s_ctrl_snb_ul,   DUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_hopping_algo,DUL,NO_PAR},{l1s_read_tx_result,DUL,BURST_2},{l1s_ctrl_snb_ul,   DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                                                   {l1s_read_tx_result,DUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                                                   {l1s_read_tx_result,DUL,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  }; 
+
+  const T_FCT  BLOC_ADL[] = 
+  { 
+    {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl,  ADL,BURST_1},                                {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl,  ADL,BURST_2},                                {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl,ADL,BURST_1},{l1s_ctrl_snb_dl,  ADL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl,ADL,BURST_2},{l1s_ctrl_snb_dl,  ADL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                                                  {l1s_read_dedic_dl,ADL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                                                  {l1s_read_dedic_dl,ADL,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  }; 
+
+  const T_FCT  BLOC_AUL[] = 
+  { 
+    {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul,   AUL,BURST_1},                                 {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul,   AUL,BURST_2},                                 {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_hopping_algo,AUL,NO_PAR},{l1s_read_tx_result,AUL,BURST_1},{l1s_ctrl_snb_ul,   AUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_hopping_algo,AUL,NO_PAR},{l1s_read_tx_result,AUL,BURST_2},{l1s_ctrl_snb_ul,   AUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+                                                                   {l1s_read_tx_result,AUL,BURST_3},{NULL,NO_PAR,NO_PAR}, // frame 5
+                                                                   {l1s_read_tx_result,AUL,BURST_4},{NULL,NO_PAR,NO_PAR}  // frame 6
+  }; 
+                
+  /*-----------------------------------------------------------------------*/
+  /* SPECIAL CASE: (ADL4,DDL4),(ADL5,DDL5),(ADL6,DDL6).                    */
+  /*-----------------------------------------------------------------------*/
+  /* frame 1        2        3        4        5        6        7         */  
+  /*       |        |        |        |        |        |        |         */  
+  /*       C(DUL,1) W(DUL,1) R(DUL,1) |        |        |        |         */
+  /*                C(ADL,1) W(ADL,1) R(ADL,1) |        |        |         */
+  /*                C(DUL,2) W(DUL,2) R(DUL,2) |        |        |         */
+  /*                         C(ADL,2) W(ADL,2) R(ADL,2) |        |         */
+  /*                         C(DUL,3) W(DUL,3) R(DUL,3) |        |         */
+  /*                                  C(ADL,3) W(ADL,3) R(ADL,3) |         */
+  /*                                  C(DUL,4) W(DUL,4) R(DUL,4) |         */
+  /*                                           C(ADL,4) W(ADL,4) R(ADL,4)  */
+  /*-----------------------------------------------------------------------*/
+  const T_FCT  BLOC_DUL_ADL_MIXED[] = 
+  { 
+    {l1s_hopping_algo,AUL,NO_PAR},{l1s_ctrl_snb_ul,   DUL,BURST_1},                                                                                                  {NULL,NO_PAR,NO_PAR}, // frame 1
+    {l1s_hopping_algo,ADL,NO_PAR},{l1s_ctrl_snb_dl,   ADL,BURST_1},{l1s_ctrl_snb_ul,   DUL,BURST_2},                                                                 {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_tx_result,DUL,BURST_1},{l1s_ctrl_snb_dl,   ADL,BURST_2},{l1s_ctrl_snb_ul,  DUL,BURST_3},                                 {NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl, ADL,BURST_1},{l1s_read_tx_result,DUL,BURST_2},{l1s_ctrl_snb_dl,  ADL,BURST_3},{l1s_ctrl_snb_ul,   DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 4
+    {l1s_hopping_algo,ADL,NO_PAR},{l1s_read_dedic_dl, ADL,BURST_2},{l1s_read_tx_result,DUL,BURST_3},{l1s_ctrl_snb_dl,  ADL,BURST_4},                                 {NULL,NO_PAR,NO_PAR}, // frame 5
+                                                                                                    {l1s_read_dedic_dl,ADL,BURST_3},{l1s_read_tx_result,DUL,BURST_4},{NULL,NO_PAR,NO_PAR}, // frame 6
+                                                                                                    {l1s_read_dedic_dl,ADL,BURST_4},                                 {NULL,NO_PAR,NO_PAR}  // frame 7
+  };
+  
+  /*----------------------------------------------------*/
+  /* ABORT: used to abort a running task when a new     */
+  /* task with higher priority occurs.                  */
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_ABORT[] =      
+  { 
+    {l1s_abort,NO_PAR,NO_PAR},     {NULL,NO_PAR,NO_PAR}, // frame 1
+                                   {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_dummy,NO_PAR,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 3
+  }; 
+   
+  /*----------------------------------------------------*/
+  /* TASK: RACH in access mode...                       */
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_RAACC[] =      
+  { 
+    {l1s_ctrl_rach,RAACC,NO_PAR},     {NULL,NO_PAR,NO_PAR}, // frame 1
+                                      {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_tx_result,RAACC,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 3
+  }; 
+
+  /*----------------------------------------------------*/
+  /* TASK: TCH                                          */
+  /*----------------------------------------------------*/
+  /*       C W R                                        */  
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_TCHTF[] =      
+  {
+    {l1s_hopping_algo,TCHTF,NO_PAR},{l1s_ctrl_tchtf,TCHTF,NO_PAR},   {NULL,NO_PAR}, // frame 1
+                                                                     {NULL,NO_PAR}, // frame 2
+                                   {l1s_read_dedic_dl,TCHTF,NO_PAR}, {NULL,NO_PAR}  // frame 3
+  };
+  
+  const T_FCT  BLOC_TCHTH[] =      
+  {
+    {l1s_hopping_algo,TCHTH,NO_PAR},{l1s_ctrl_tchth,TCHTH,NO_PAR},   {NULL,NO_PAR}, // frame 1
+                                                                     {NULL,NO_PAR}, // frame 2
+                                   {l1s_read_dedic_dl,TCHTH,NO_PAR}, {NULL,NO_PAR}  // frame 3
+  };
+  
+  const T_FCT  BLOC_TCHD[] =      
+  {
+                                   {l1s_ctrl_tchtd,TCHD,NO_PAR},    {NULL,NO_PAR}, // frame 1
+                                                                    {NULL,NO_PAR}, // frame 2
+                                   {l1s_read_dummy,TCHD,NO_PAR},    {NULL,NO_PAR}  // frame 3
+  };
+
+  const T_FCT  BLOC_TCHA[] =      
+  {
+    {l1s_hopping_algo,TCHA,NO_PAR},{l1s_ctrl_tcha,TCHA,NO_PAR},     {NULL,NO_PAR}, // frame 1
+                                                                    {NULL,NO_PAR}, // frame 2
+                                   {l1s_read_dedic_dl,TCHA,NO_PAR}, {NULL,NO_PAR}  // frame 3
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: Frequency Burst search in dedic/SDCCH...     */
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_FB51[] =      
+  { 
+    {l1s_ctrl_fb,FB51,NO_PAR},    {NULL,NO_PAR,NO_PAR}, // frame 1
+                                  {NULL,NO_PAR,NO_PAR}, // frame 2
+    {l1s_read_mon_result,FB51, 1},{NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_mon_result,FB51, 2},{NULL,NO_PAR,NO_PAR}, // frame 4
+    {l1s_read_mon_result,FB51, 3},{NULL,NO_PAR,NO_PAR}, // frame 5
+    {l1s_read_mon_result,FB51, 4},{NULL,NO_PAR,NO_PAR}, // frame 6
+    {l1s_read_mon_result,FB51, 5},{NULL,NO_PAR,NO_PAR}, // frame 7
+    {l1s_read_mon_result,FB51, 6},{NULL,NO_PAR,NO_PAR}, // frame 8
+    {l1s_read_mon_result,FB51, 7},{NULL,NO_PAR,NO_PAR}, // frame 9
+    {l1s_read_mon_result,FB51, 8},{NULL,NO_PAR,NO_PAR}, // frame 10
+    {l1s_read_mon_result,FB51, 9},{NULL,NO_PAR,NO_PAR}, // frame 11
+    {l1s_read_mon_result,FB51,10},{NULL,NO_PAR,NO_PAR}, // frame 12
+    {l1s_read_mon_result,FB51,11},{NULL,NO_PAR,NO_PAR}, // frame 13
+    {l1s_read_mon_result,FB51,12},{NULL,NO_PAR,NO_PAR}  // frame 14
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: SB51, Synchro Burst reading. Dedic/SDCCH.    */
+  /*----------------------------------------------------*/
+  /*           C W W R     -> SB                        */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_SB51[] = 
+  {
+    {l1s_ctrl_sbgen,SB51,NO_PAR},     {NULL,NO_PAR,NO_PAR}, // frame 1
+                                      {NULL,NO_PAR,NO_PAR}, // frame 2
+                                      {NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_mon_result,SB51,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 4
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: SBCNF51, Synchro confirmation. Dedic/SDCCH.  */
+  /*----------------------------------------------------*/
+  /*           C W W R     -> SBCONF                    */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_SBCNF51[] = 
+  {
+    {l1s_ctrl_sbgen,SBCNF51,NO_PAR},     {NULL,NO_PAR,NO_PAR}, // frame 1
+                                         {NULL,NO_PAR,NO_PAR}, // frame 2
+                                         {NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_mon_result,SBCNF51,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 4
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: FB26, Frequency Burst search in dedic/TCH... */
+  /*----------------------------------------------------*/
+  /*           C W W R                                  */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_FB26[] =      
+  { 
+    {l1s_ctrl_fb26,FB26,NO_PAR},      {NULL,NO_PAR,NO_PAR}, // frame 1
+                                      {NULL,NO_PAR,NO_PAR}, // frame 2
+                                      {NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_mon_result,FB26,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 4
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: SB26, Synchro. Burst reading in dedic/TCH... */
+  /*----------------------------------------------------*/
+  /*           C W W W R                                */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_SB26[] =      
+  { 
+    {l1s_ctrl_sb26,SB26,NO_PAR},      {NULL,NO_PAR,NO_PAR}, // frame 1
+                                      {NULL,NO_PAR,NO_PAR}, // frame 2
+                                      {NULL,NO_PAR,NO_PAR}, // frame 3
+                                      {NULL,NO_PAR,NO_PAR}, // frame 4
+    {l1s_read_mon_result,SB26,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 5
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: SBCNF26, Synchro. Burst reading in dedic/TCH.*/
+  /*----------------------------------------------------*/
+  /*           C W W W R                                */  
+  /*----------------------------------------------------*/
+  const T_FCT BLOC_SBCNF26[] =      
+  { 
+    {l1s_ctrl_sb26,SBCNF26,NO_PAR},      {NULL,NO_PAR,NO_PAR}, // frame 1
+                                         {NULL,NO_PAR,NO_PAR}, // frame 2
+                                         {NULL,NO_PAR,NO_PAR}, // frame 3
+                                         {NULL,NO_PAR,NO_PAR}, // frame 4
+    {l1s_read_mon_result,SBCNF26,NO_PAR},{NULL,NO_PAR,NO_PAR}  // frame 5
+  };
+
+  /*----------------------------------------------------*/
+  /* TASK: HWTEST after power-on...                     */
+  /*----------------------------------------------------*/
+  const T_FCT  BLOC_HWTEST[] =      
+  { 
+    {l1s_ctrl_hwtest,HWTEST,NO_PAR},     {NULL,NO_PAR,NO_PAR}, // frame 1
+                                         {NULL,NO_PAR,NO_PAR}, // frame 2
+                                         {NULL,NO_PAR,NO_PAR}, // frame 3
+    {l1s_read_hwtest,HWTEST,NO_PAR},     {NULL,NO_PAR,NO_PAR}  // frame 4
+  }; 
+
+#else                                                                         
+  extern   T_FCT  BLOC_FB[];
+  extern   T_FCT  BLOC_SB[];
+  extern   T_FCT  BLOC_BCCHS[];
+  extern   T_FCT  BLOC_BCCHN[];
+  extern   T_FCT  BLOC_BCCHN_TOP[];
+  extern   T_FCT  BLOC_EP[]; 
+  extern   T_FCT  BLOC_SYNCHRO[];      
+  extern   T_FCT  BLOC_ADC[];      
+  extern   T_FCT  BLOC_SMSCB[];
+  extern   T_FCT  BLOC_NP[];
+  extern   T_FCT  BLOC_ALLC[];      
+  extern   T_FCT  BLOC_DDL[];
+  extern   T_FCT  BLOC_DUL[];
+  extern   T_FCT  BLOC_ADL[];
+  extern   T_FCT  BLOC_AUL[];
+  extern   T_FCT  BLOC_DUL_ADL_MIXED[];
+  extern   T_FCT  BLOC_ABORT[];
+  extern   T_FCT  BLOC_RAACC[];
+  extern   T_FCT  BLOC_TCHTF[];      
+  extern   T_FCT  BLOC_TCHTH[];      
+  extern   T_FCT  BLOC_TCHTD[];      
+  extern   T_FCT  BLOC_TCHA[];      
+  extern   T_FCT  BLOC_FB51[];      
+  extern   T_FCT BLOC_SB51[]; 
+  extern   T_FCT BLOC_SBCNF51[]; 
+  extern   T_FCT BLOC_FB26[];      
+  extern   T_FCT BLOC_SB26[];      
+  extern   T_FCT BLOC_SBCNF26[]; 
+  extern   T_FCT BLOC_HWTEST[]; 
+
+  #if (L1_GPRS)
+    extern T_FCT  BLOC_BCCHN_TRAN[];
+  #endif
+
+#endif
+
+
+
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_msgty.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_msgty.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,651 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_MSGTY.H
+ *
+ *        Filename l1_msgty.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+
+
+/* channels types */
+#define L2_CHANNEL_SACCH    1
+#define L2_CHANNEL_SDCCH    2
+#define L2_CHANNEL_FACCH_H  3
+#define L2_CHANNEL_FACCH_F  4
+#define L2_CHANNEL_CCCH     5
+#define L2_CHANNEL_NBCCH    6
+#define L2_CHANNEL_PCH      7
+#define L2_CHANNEL_EPCH     8
+#define L2_CHANNEL_CBCH     9
+#define L2_CHANNEL_EBCCH   10
+
+/****************************************************************/
+/* Structure definition for L1S <-> DATA ADAPTOR data blocks    */
+/* TCH/9.6 -> 30 bytes                                          */
+/* TCH/4.8 -> 15 bytes                                          */
+/* TCH/2.4 ->  9 bytes                                          */
+/****************************************************************/
+typedef struct 
+{  
+  UWORD8 A[30];  
+}  
+T_DATA_FRAME;
+
+/****************************************************************/
+/* Structure definition for L1A <-> MMI messages                */
+/****************************************************************/
+
+typedef struct 
+{
+  UWORD8  tx_flag;
+  UWORD8  traffic_period;
+  UWORD8  idle_period;
+}  
+T_MMI_ADC_REQ;
+
+/****************************************************************/
+/* Structure definition for L1S <-> L1A messages                */
+/****************************************************************/
+typedef T_PH_DATA_IND  T_L1_BCCH_INFO;
+typedef T_PH_DATA_IND  T_L1_CCCH_INFO;
+
+/****************************************************************/
+/* Structure definition for new L3 <-> L1 messages              */
+/****************************************************************/
+
+#if (OP_L1_STANDALONE == 1)
+/* Message used for hardware dynamic configuration */
+typedef struct
+{
+  UWORD8   num_of_clock_cfg;    // Dynamic clock configuration index
+}
+T_TST_HW_CONFIG_REQ;
+#endif // OP_L1_STANDALONE
+
+typedef struct
+{
+  UWORD32  mf51_fn;
+}
+T_MPHC_START_CBCH_READING;
+
+typedef struct
+{
+  T_RXLEV_MEAS     A[8]; 
+  UWORD8           nbr_of_carriers;
+  WORD8            s_rxlev;
+  UWORD8           ba_id;
+}
+T_MPHC_RXLEV_PERIODIC_IND;
+
+typedef struct
+{
+  TC_CHAN_LIST  chan_list;
+  UWORD8        num_of_chans;
+  UWORD8        ba_id;
+  UWORD8        next_radio_freq_measured;  // index of first radio_freq to be measured
+}
+T_MPHC_RXLEV_PERIODIC_REQ;
+
+typedef struct
+{
+  UWORD16  radio_freq;          // carrier id.
+}
+T_MPHC_NCELL_FB_SB_READ;
+
+typedef struct
+{
+  UWORD16  radio_freq;          // carrier id.
+}
+T_MPHC_START_BCCH_READING;
+
+typedef struct
+{
+  UWORD16  radio_freq;          // carrier id.
+  UWORD32  fn_offset;      // offset between fn of this NCELL and the SCELL fn.
+  UWORD32  time_alignmt;   // time alignment.
+  UWORD8   bsic;           // BSIC.
+  UWORD16  si_bit_map;     // System Info. bit map.
+}
+T_MPHC_NCELL_BCCH_READ;
+
+typedef struct 
+{
+  UWORD32  fn;
+  UWORD8   channel_request;
+} 
+T_MPHC_RA_CON;
+
+typedef struct
+{
+  T_CHANNEL_DESCRIPTION  channel_desc;
+  UWORD8                 timing_advance;
+  T_MOBILE_ALLOCATION    frequency_list;
+  T_STARTING_TIME        starting_time;
+  T_MOBILE_ALLOCATION    frequency_list_bef_sti;
+  UWORD8                 maio_bef_sti;
+  BOOL                   dtx_allowed;
+  T_BCCH_LIST            bcch_allocation;
+  UWORD8                 ba_id;
+  BOOL                   pwrc;
+}  
+T_MPHC_IMMED_ASSIGN_REQ;
+
+typedef struct 
+{
+  T_CHANNEL_DESCRIPTION  channel_desc_1;
+  UWORD8                 channel_mode_1;
+  UWORD8                 txpwr;
+  T_MOBILE_ALLOCATION    frequency_list;
+  T_STARTING_TIME        starting_time;
+  T_CHANNEL_DESCRIPTION  channel_desc_2;
+  UWORD8         channel_mode_2;
+  T_MOBILE_ALLOCATION    frequency_list_bef_sti;
+  T_CHANNEL_DESCRIPTION  channel_desc_1_bef_sti;
+  T_CHANNEL_DESCRIPTION  channel_desc_2_bef_sti;
+  UWORD8                 cipher_mode;
+  UWORD8                 a5_algorithm;
+  T_ENCRYPTION_KEY       cipher_key;
+  BOOL                   dtx_allowed;
+  #if (AMR == 1)
+    T_AMR_CONFIGURATION  amr_configuration;
+  #endif
+}  
+T_MPHC_CHANNEL_ASSIGN_REQ;
+
+
+typedef struct
+{
+  UWORD8   txpwr;
+  UWORD8   rand;
+  UWORD8   channel_request;
+  UWORD8   powerclass_band1;
+  UWORD8   powerclass_band2;
+
+}
+T_MPHC_RA_REQ;
+
+
+typedef struct 
+{
+  T_HO_PARAMS          handover_command;
+  UWORD32              fn_offset;     
+  UWORD32              time_alignmt;  
+  T_ENCRYPTION_KEY     cipher_key;
+  #if (AMR == 1)  
+    T_AMR_CONFIGURATION  amr_configuration;
+  #endif
+}
+T_MPHC_ASYNC_HO_REQ;
+
+typedef struct 
+{
+  T_HO_PARAMS          handover_command;
+  UWORD32              fn_offset;     
+  UWORD32              time_alignmt;  
+  T_ENCRYPTION_KEY     cipher_key;
+  BOOL                 nci;
+  BOOL                 timing_advance_valid;
+  UWORD8               timing_advance;
+  #if (AMR == 1)  
+    T_AMR_CONFIGURATION  amr_configuration;
+  #endif
+}  
+T_MPHC_PRE_SYNC_HO_REQ;
+
+typedef struct 
+{
+  T_HO_PARAMS       handover_command;
+  UWORD32           fn_offset;     
+  UWORD32           time_alignmt;  
+  T_ENCRYPTION_KEY  cipher_key;
+  BOOL              nci;
+  UWORD8            real_time_difference;
+}  
+T_MPHC_PSEUDO_SYNC_HO_REQ;
+
+typedef struct
+{
+  T_HO_PARAMS          handover_command;
+  UWORD32              fn_offset;     
+  UWORD32              time_alignmt;  
+  T_ENCRYPTION_KEY     cipher_key;
+  BOOL                 nci;
+  #if (AMR == 1)  
+    T_AMR_CONFIGURATION  amr_configuration;
+  #endif
+}  
+T_MPHC_SYNC_HO_REQ;
+
+typedef struct
+{
+  UWORD8  cause;
+}  
+T_MPHC_HANDOVER_FINISHED;
+
+typedef struct 
+{
+  BOOL           dtx_used;
+  BOOL           meas_valid;
+  WORD16         rxlev_full_acc;
+  UWORD8         rxlev_full_nbr_meas;
+  WORD16         rxlev_sub_acc;
+  UWORD8         rxlev_sub_nbr_meas;
+  UWORD16        rxqual_full_acc_errors;
+  UWORD16        rxqual_full_nbr_bits;
+  UWORD16        rxqual_sub_acc_errors;
+  UWORD16        rxqual_sub_nbr_bits;
+  UWORD8         no_of_ncell_meas;
+  T5_NCELL_MEAS  ncell_meas;
+  UWORD8         ba_id;
+  UWORD8         timing_advance;
+  UWORD8         txpwr_used;
+
+  // RESERVED: for trace/debug only
+  UWORD8         facch_dl_count;
+  UWORD8         facch_ul_count;
+}  
+T_MPHC_MEAS_REPORT;
+
+typedef T_NEW_BA_LIST  T_MPHC_UPDATE_BA_LIST;
+
+
+typedef struct 
+{
+  UWORD8  bs_pa_mfrms;
+  UWORD8  bs_ag_blks_res;
+  BOOL    bcch_combined;
+  UWORD8  ccch_group;
+  UWORD8  page_group;
+  UWORD8  page_block_index;
+  UWORD8  page_mode;
+}
+T_MPHC_START_CCCH_REQ;
+
+typedef struct
+{
+  UWORD8   sb_flag;         //TRUE if SB found and belongs to PLMN, otherwise FALSE
+  UWORD16  radio_freq;          // carrier id.
+  UWORD8   bsic;           // BSIC.
+  UWORD32  fn_offset;      // offset between fn of this NCELL and the SCELL fn.
+  UWORD32  time_alignmt;   // time alignment.
+}
+T_MPHC_NCELL_SB_READ;
+
+typedef T_FULL_LIST_MEAS           T_MPHC_RXLEV_REQ;
+typedef T_FULL_LIST_MEAS           T_L1C_VALID_MEAS_INFO;
+typedef T_MPHC_RXLEV_PERIODIC_IND  T_L1C_RXLEV_PERIODIC_DONE;
+
+
+
+typedef struct
+{
+  UWORD8 radio_band_config; // frequency band configuration: E-GSM, DCS, GSM/DCS, PCS
+}
+T_MPHC_INIT_L1_REQ;
+
+/****************************************************************/
+/* Structure definition for Test <-> L1A messages                */
+/****************************************************************/
+
+typedef struct
+{
+  UWORD16  dsp_code_version;                      
+  UWORD16  dsp_checksum;
+  UWORD16  dsp_patch_version;
+  UWORD16  mcu_tcs_program_release;
+  UWORD16  mcu_tcs_official;
+  UWORD16  mcu_tcs_internal;
+}
+T_TST_TEST_HW_CON;
+  
+typedef struct
+{
+  UWORD8  type;
+}
+T_L1_STATS_REQ;
+
+////////////////////
+// Trace messages //
+////////////////////
+
+#if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4) || (TRACE_TYPE == 7))
+
+#if (DSP_DEBUG_TRACE_ENABLE == 1)
+// DSP DEBUG buffer display
+typedef struct
+{
+  UWORD16  size;
+  UWORD32  fn;
+  UWORD16  debug_time;
+  UWORD16  patch_version;
+  UWORD16  trace_level;
+  API      buffer[2];  // ANOTHER DEFINITION ???
+}
+T_DSP_DEBUG_INFO;
+
+// DSP AMR trace
+typedef struct
+{
+  UWORD16  size;
+  UWORD32  fn;
+  API      buffer[2];  // ANOTHER DEFINITION ???
+}
+T_DSP_AMR_DEBUG_INFO;
+
+#endif
+
+typedef struct
+{
+  UWORD32        trace_config;
+  UWORD32        rtt_cell_enable[8];
+  UWORD32        rtt_event;
+}
+T_TRACE_CONFIG_CHANGE;
+
+#if (L1_GPRS)
+// Packet transfer trace
+typedef struct
+{
+  UWORD32 fn;
+  UWORD8  rx_allocation;
+  UWORD8  tx_allocation;
+  BOOL    blk_status;
+  UWORD8  dl_cs_type;
+  UWORD8  dl_status[4];
+  UWORD8  ul_status[8];
+}
+T_CONDENSED_PDTCH_INFO;
+#endif
+
+typedef struct
+{
+  UWORD8   debug_code;
+  UWORD32  fn;
+  UWORD32  tab[7];
+}
+T_QUICK_TRACE;
+
+#endif
+
+#if ((TRACE_TYPE == 1) || (TRACE_TYPE == 4) || (TRACE_TYPE == 7))
+typedef struct
+{
+  UWORD8   debug_code;
+  UWORD32  tab[8];
+}
+T_TRACE_INFO;
+#endif
+
+#if (TRACE_TYPE==7) // CPU LOAD
+
+// Number of measurements before output to UART
+
+#define C_MESURE_DEPTH    13
+
+/*
+ *  cpu        : hisr cpu load in microseconds
+ *  cpu_access : lisr -> hisr begining cpu load in microseconds
+ *  fn         : Frame number modulo 104 
+ */
+
+typedef struct
+{
+ UWORD16 cpu;
+ UWORD16 cpu_access;
+ UWORD8  fn;
+ BOOL    valid;
+} 
+T_MESURE;
+
+typedef struct
+{
+  UWORD8   debug_code;
+  T_MESURE tab[C_MESURE_DEPTH];
+}
+T_TRACE_INFO_CPU_LOAD;
+
+#endif
+
+
+/****************************************************************/
+/* Structure definition for POWER MANAGEMENt.                   */
+/****************************************************************/
+typedef struct
+{
+  UWORD8   sleep_mode;
+  UWORD16  clocks;
+}
+T_TST_SLEEP_REQ;
+
+// ...................NEW FOR ALR....................
+typedef struct
+{
+  UWORD8            schedule_array_size;
+  T_BCCHS_SCHEDULE  schedule_array[10];
+}
+T_MPHC_SCELL_NBCCH_REQ;
+
+typedef struct
+{
+  UWORD8            schedule_array_size;
+  T_BCCHS_SCHEDULE  schedule_array[10];
+}
+T_MPHC_SCELL_EBCCH_REQ;
+
+typedef struct
+{
+  UWORD16  radio_freq;
+  UWORD32  fn_offset;
+  UWORD32  time_alignmt;
+  UWORD8   tsc;
+  UWORD16  bcch_blks_req;
+#if L1_GPRS
+  UWORD8   gprs_priority;
+#endif
+}
+T_MPHC_NCELL_BCCH_REQ;
+
+typedef struct
+{
+  UWORD16        radio_freq;
+  UWORD8         l2_channel;
+  BOOL           error_flag;
+  T_RADIO_FRAME  l2_frame;
+  UWORD8         tc;
+  WORD8          ccch_lev;
+  UWORD32        fn;
+
+  // L1S -> L1A data only
+  UWORD8         neigh_id;
+}
+T_MPHC_DATA_IND;
+
+typedef T_MPHC_DATA_IND  T_MPHC_NCELL_BCCH_IND;
+typedef T_MPHC_DATA_IND  T_L1C_BCCHS_INFO;
+typedef T_MPHC_DATA_IND  T_L1C_BCCHN_INFO;
+
+typedef struct
+{
+  UWORD16     radio_freq;
+  UWORD32     fn_offset;
+  UWORD32     time_alignmt;
+  UWORD8      timing_validity;
+  UWORD8      search_mode;
+}
+T_MPHC_NETWORK_SYNC_REQ;
+
+typedef struct
+{
+  UWORD16     radio_freq;
+  BOOL        sb_flag;
+  UWORD32     fn_offset;
+  UWORD32     time_alignmt;
+  UWORD8      bsic;
+}
+T_MPHC_NETWORK_SYNC_IND;
+
+typedef struct
+{
+  UWORD16     radio_freq;
+  UWORD32     fn_offset;
+  UWORD32     time_alignmt;
+  UWORD8      timing_validity;
+}
+T_MPHC_NCELL_SYNC_REQ;
+
+#if (L1_12NEIGH ==1)
+typedef struct
+{
+  UWORD8     eotd;
+  UWORD8     list_size;
+  T_MPHC_NCELL_SYNC_REQ ncell_list[NBR_NEIGHBOURS];
+}
+T_MPHC_NCELL_LIST_SYNC_REQ;
+#endif
+
+
+
+typedef struct
+{
+  UWORD16     radio_freq;
+  BOOL        sb_flag;          // used to fill "data_valid" field for Cursor
+  UWORD32     fn_offset;
+  UWORD32     time_alignmt;
+  UWORD8      bsic;
+
+  // L1S -> L1A data only
+  UWORD8      neigh_id;
+  UWORD8      attempt;
+
+  // RESERVED: for trace/debug and test mode only
+  UWORD32     pm;
+  UWORD32     toa;
+  UWORD32     angle;
+  UWORD32     snr;
+
+  // EOTD data : L1S -> L1A
+#if (L1_EOTD==1)
+  UWORD8      eotd_data_valid;  // indicates to L3 that it's an EOTD result
+  UWORD8      mode;             // indicates to CURSOR that it's Idle(0) or Dedicated (1)
+  WORD16      d_eotd_first;
+  WORD16      d_eotd_max;
+  UWORD32     d_eotd_nrj;
+  WORD16      a_eotd_crosscor[18];
+  UWORD32     timetag; 
+  UWORD32     fn_sb_neigh;      // used for Timetag computation
+  UWORD32     fn_in_SB;         // sent to CURSOR for SC fn (header=46 ...) 
+
+  // TOA correction for timetag in dedicated mode...
+  WORD32      toa_correction;
+
+  // for Debug traces ............
+  UWORD32     delta_fn;
+  WORD32      delta_qbit;
+#endif 
+}
+T_MPHC_NCELL_SYNC_IND;
+
+typedef T_MPHC_NCELL_SYNC_IND  T_L1C_SB_INFO;
+typedef T_MPHC_NCELL_SYNC_IND  T_L1C_SBCONF_INFO;
+
+typedef struct
+{
+  UWORD16     radio_freq;
+  UWORD32     fn_offset;
+  UWORD32     time_alignmt;
+  UWORD8      bsic;
+}
+T_MPHC_NEW_SCELL_REQ;
+
+typedef struct
+{
+  BOOL    fb_flag;
+  WORD8   ntdma;
+  UWORD8  neigh_id;
+#if (L1_12NEIGH ==1)
+  // L1S --> L1A data only 
+  UWORD8   attempt;
+#endif
+  // RESERVED: for Trace/Debug and test mode only
+  UWORD32  pm;
+  UWORD32  toa;
+  UWORD32  angle;
+  UWORD32  snr;
+  UWORD16 radio_freq;
+}
+T_L1C_FB_INFO;
+
+typedef struct
+{
+  WORD8     radio_freq_array_size;
+#if (L1_12NEIGH ==1)
+  UWORD16   radio_freq_array[NBR_NEIGHBOURS];
+#else
+  UWORD16   radio_freq_array[6];
+#endif
+}
+T_MPHC_STOP_NCELL_SYNC_REQ;
+
+typedef struct
+{
+  UWORD8    radio_freq_array_size;
+  UWORD16   radio_freq_array[6];
+}
+T_MPHC_STOP_NCELL_BCCH_REQ;
+
+typedef struct
+{
+  T_CHANNEL_DESCRIPTION cbch_desc;
+  T_MOBILE_ALLOCATION   cbch_freq_list;
+}
+T_MPHC_CONFIG_CBCH_REQ;
+
+typedef struct
+{
+  BOOL    extended_cbch;
+  UWORD8  schedule_length;
+  UWORD32 first_block_0;
+  UWORD16 first_block_1;
+}
+T_MPHC_CBCH_SCHEDULE_REQ;
+
+typedef struct
+{
+  UWORD8  tb_bitmap;
+}
+T_MPHC_CBCH_INFO_REQ;
+
+typedef struct
+{
+  BOOL    extended_cbch;
+  UWORD32 first_block_0;
+  UWORD16 first_block_1;
+}
+T_MPHC_CBCH_UPDATE_REQ;
+
+typedef struct
+{
+  BOOL  normal_cbch;
+  BOOL  extended_cbch;
+}
+T_MPHC_STOP_CBCH_REQ;
+
+// ...................NEW FOR ALR....................
+
+/****************************************************************/
+/* Structure definition for L1 configuration.                   */
+/****************************************************************/
+typedef struct
+{
+ UWORD8   std;
+ UWORD8   swap_iq_band1;
+ UWORD8   swap_iq_band2;
+ UWORD8   pwr_mngt;
+ UWORD8   tx_pwr_code;
+ UWORD16  dwnld;
+ UWORD8   pwr_mngt_mode_authorized;
+ UWORD32  pwr_mngt_clocks;
+}
+T_MMI_L1_CONFIG;
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_proto.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_proto.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,525 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software
+ * L1_PROTO.H
+ *
+ *        Filename l1_proto.h
+ *  Copyright 2003 (C) Texas Instruments
+ *
+ ************* Revision Controle System Header *************/
+
+/**************************************/
+/* prototypes of L1_SYNC.C  functions */
+/**************************************/
+void  hisr                        (void);
+
+void  frit_task                   (UWORD32 argc, void *argv);
+void  l1s_task                    (UWORD32 argc, void *argv);
+void  l1s_synch                   (void);
+
+void  l1s_task_scheduler_process  (void);
+void  l1s_execute_frame           (void);
+void  l1s_meas_manager            (void);
+void  l1s_end_manager             (void);
+void  l1s_schedule_tasks          (WORD32 *pending_task);
+void  l1s_merge_manager           (WORD32 dl_pending_task);
+
+void  l1s_dedicated_mode_manager  (void);
+
+/**************************************/
+/* prototypes of L1_PWMGR.C functions */
+/**************************************/
+void  l1s_sleep_manager           (void);
+void l1s_gauging_task             (void);
+void  l1s_gauging_task_end        (void);
+WORD32 l1s_get_next_gauging_in_Packet_Idle(void);
+void  l1s_wakeup                  (void);
+void  l1s_wakeup_adjust           (void);
+void  GAUGING_Handler             (void);
+UWORD8 l1s_recover_Os             (void);
+UWORD8 l1s_check_System           (void);
+void  l1s_recover_Frame           (void);
+void l1s_recover_HWTimers         (void);
+BOOL l1s_compute_wakeup_ticks     (void);
+
+/**************************************/
+/* prototypes of L1_MFMGR.C functions */
+/**************************************/
+void  l1s_clear_mftab             (T_FRM *frmlst);
+void  l1s_exec_mftab              (void);
+void  l1s_load_mftab              (const T_FCT *fct,
+                                   const UWORD8 size,
+                                   UWORD8 frame,
+                                   T_FRM  *frmlst);
+
+/**************************************/
+/* prototypes of L1_CMPLX.C functions */
+/**************************************/
+void  l1s_new_synchro             (UWORD8 param1, UWORD8 param2);
+void  l1s_abort                   (UWORD8 param1, UWORD8 param2);
+void  l1s_ctrl_ADC                (UWORD8 param1, UWORD8 param2);
+
+void  l1s_ctrl_msagc              (UWORD8 task,   UWORD8 param2);
+void  l1s_ctrl_fb                 (UWORD8 param1, UWORD8 param2);
+void  l1s_ctrl_fb26               (UWORD8 task,   UWORD8 param2);
+void  l1s_ctrl_sbgen              (UWORD8 task,   UWORD8 attempt);
+void  l1s_ctrl_sb26               (UWORD8 task,   UWORD8 param2);
+
+void  l1s_ctrl_smscb              (UWORD8 task,   UWORD8 burst_id);
+
+void  l1s_ctrl_snb_dl             (UWORD8 task, UWORD8 param2);
+void  l1s_ctrl_snb_ul             (UWORD8 task, UWORD8 param2);
+void  l1s_ctrl_nnb                (UWORD8 task, UWORD8 param2);
+
+void  l1s_ctrl_rach               (UWORD8 task,   UWORD8 param2);
+void  l1s_ctrl_tchtf              (UWORD8 task,   UWORD8 param2);
+void  l1s_ctrl_tchth              (UWORD8 task,   UWORD8 param2);
+void  l1s_ctrl_tchtd              (UWORD8 task,   UWORD8 param2);
+void  l1s_ctrl_tcha               (UWORD8 task,   UWORD8 param2);
+void  l1s_hopping_algo            (UWORD8 param1, UWORD8 param2);
+
+void  l1s_ctrl_hwtest             (UWORD8 task, UWORD8 param2);
+void  l1s_read_hwtest             (UWORD8 task, UWORD8 param2);
+
+void  l1s_read_dummy              (UWORD8 task, UWORD8 param2);
+void  l1s_read_msagc              (UWORD8 task, UWORD8 param2);
+void  l1s_read_mon_result         (UWORD8 task, UWORD8 param2);
+
+void  l1s_read_rx_result          (UWORD8 param1, UWORD8 attempt_for_sb2);
+
+void  l1s_read_snb_dl             (UWORD8 task, UWORD8 burst_id);
+void  l1s_read_nnb                (UWORD8 task, UWORD8 param);
+void  l1s_read_dedic_dl           (UWORD8 task, UWORD8 burst_id);
+
+void  l1s_read_tx_result          (UWORD8 param1, UWORD8 param2);
+void  l1s_read_dedic_scell_meas   (UWORD8 meas,   UWORD8 sub_flag);
+void  l1s_dedic_reporting         (void);
+
+void  l1s_read_fb                 (UWORD8 task, UWORD32 fb_flag, UWORD32 toa, UWORD32 attempt,
+                                   UWORD32 pm,  UWORD32 angle,   UWORD32 snr);
+void  l1s_read_sb                 (UWORD8  task,UWORD32 flag,    API *data, UWORD32 toa, UWORD8 attempt,
+                                   UWORD32 pm,  UWORD32 angle,   UWORD32 snr);
+void  l1s_read_sacch_dl           (API *info_address, UWORD32 task_rx);
+void  l1s_read_dcch_dl            (API *info_address, UWORD32 task_rx);
+void  l1s_read_l3frm              (UWORD8 pwr_level, API *info_address, UWORD32 task_rx);
+
+
+/**************************************/
+/* prototypes of L1_AFUNC functions   */
+/**************************************/
+void           l1a_reset_full_list            (void);
+void           l1a_reset_ba_list              (void);
+void           l1a_add_time_for_nb            (UWORD32 *time_alignmt, UWORD32 *fn_offset);
+void           l1a_add_timeslot               (UWORD32 *time_alignmt, UWORD32 *fn_offset, UWORD8 tn);
+void           l1a_sub_time_for_nb            (UWORD32 *time_alignmt, UWORD32 *fn_offset);
+void           l1a_sub_timeslot               (UWORD32 *time_alignmt, UWORD32 *fn_offset, UWORD8 tn);
+
+T_DEDIC_SET   *l1a_get_free_dedic_set         (void);
+void           l1a_fill_bef_sti_param         (T_DEDIC_SET *set_ptr, BOOL start_time_present);
+WORD32         l1a_decode_starting_time       (T_STARTING_TIME coded_starting_time);
+void           l1a_reset_cell_info            (T_CELL_INFO *cell_info);
+void           l1a_send_confirmation          (UWORD32 SignalCode,UWORD8 queue_type);
+void           l1a_send_result                (UWORD32 SignalCode, xSignalHeaderRec *msg, UWORD8 queue);
+UWORD8         l1a_encode_rxqual              (UWORD32 inlevel);
+void           l1a_report_failling_ncell_sync (UWORD32 SignalCode, UWORD8 neigh_id);
+UWORD8         l1a_clip_txpwr                 (UWORD8 supplied_txpwr, UWORD16 radio_freq);
+void           l1a_correct_timing             (UWORD8 neigh_id,UWORD32 time_alignmt,UWORD32 fn_offset);
+void           l1a_add_time_delta             (UWORD32 *time_alignmt, UWORD32 *fn_offset, WORD32 delta);
+void           l1a_compensate_sync_ind        (T_MPHC_NCELL_SYNC_IND * msg);
+void           l1a_compute_Eotd_data          (UWORD8 *first_scell, UWORD8 neigh_id, UWORD32 SignalCode, xSignalHeaderRec *msg);
+#if (L1_MPHC_RXLEV_IND_REPORT_SORT==1)
+void           l1a_sort_freq_reported_in_rxlev_ind(T_POWER_ARRAY *data_tab,UWORD16 data_tab_size,UWORD16 *index_tab,UWORD16 index_tab_size);
+#endif
+
+/**************************************/
+/* prototypes of L1_FUNC functions    */
+/**************************************/
+void            dsp_power_on                (void);
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+   void         l1_abb_power_on              (void);
+#endif
+void            tpu_init                    (void);
+
+void            l1s_reset_db_mcu_to_dsp     (T_DB_MCU_TO_DSP *page_ptr);
+void            l1s_reset_db_dsp_to_mcu     (T_DB_DSP_TO_MCU *page_ptr);
+void            initialize_l1var            (void);
+void            l1_initialize               (T_MMI_L1_CONFIG *mmi_l1_config);
+void            l1_pwr_mgt_init             (void);
+void            l1_dpll_init_var            (void);
+
+void            l1s_increment_time          (T_TIME_INFO *time, UWORD32 fn_offset);
+WORD16          l1s_encode_rxlev            (UWORD8 inlevel);
+void            l1s_send_ho_finished        (UWORD8  cause);
+void            l1s_reset_dedic_serving_meas(void);
+UWORD32         l1s_swap_iq_dl              (UWORD16 radio_freq, UWORD8 task);
+UWORD32         l1s_swap_iq_ul              (UWORD16 radio_freq, UWORD8 task);
+UWORD8          l1s_ADC_decision_on_NP      (void);
+#if (AMR == 1)
+UWORD8          l1s_amr_get_ratscch_type    (API *a_ratscch_dl);
+void            l1s_amr_update_from_ratscch (API *a_ratscch_dl);
+#endif
+
+
+/**************************************/
+/* prototypes of L1_DRIVE functions   */
+/**************************************/
+// MCU-DSP interface drivers.
+//---------------------------
+void   l1ddsp_load_info           (UWORD32   task,
+                                   API       *info_ptr,
+                                   UWORD8    *data);
+void   l1ddsp_load_monit_task     (API       monit_task,
+                                   API       fb_mode);
+void   l1ddsp_load_afc            (API       afc);
+void   l1ddsp_load_rx_task        (API       rx_task,
+                                   UWORD8    burst_id,
+                                   UWORD8    tsq);
+void   l1ddsp_load_tx_task        (API       tx_task,
+                                   UWORD8    burst_id,
+                                   UWORD8    tsq);
+void   l1ddsp_load_ra_task        (API       ra_task);
+
+
+void   l1ddsp_load_txpwr          (UWORD8           txpwr,
+                                   UWORD16          radio_freq);
+#if (AMR == 1)
+  #if (FF_L1_TCH_VOCODER_CONTROL == 1)
+    // Add the AMR synchro bit in the driver's paramters
+    void   l1ddsp_load_tch_param      (T_TIME_INFO      *next_time,
+                                       UWORD8           chan_mode,
+                                       UWORD8           chan_type,
+                                       UWORD8           subchannel,
+                                       UWORD8           tch_loop,
+                                       UWORD8           sync_tch,
+                                       UWORD8           sync_amr,
+                                       UWORD8           reset_sacch,
+                                       UWORD8           vocoder_on);
+  #else
+    void   l1ddsp_load_tch_param      (T_TIME_INFO      *next_time,
+                                       UWORD8           chan_mode,
+                                       UWORD8           chan_type,
+                                       UWORD8           subchannel,
+                                       UWORD8           tch_loop,
+                                       UWORD8           sync_tch,
+                                       UWORD8           sync_amr);
+  #endif
+#else
+  #if (FF_L1_TCH_VOCODER_CONTROL == 1)
+    void   l1ddsp_load_tch_param      (T_TIME_INFO      *next_time,
+                                       UWORD8           chan_mode,
+                                       UWORD8           chan_type,
+                                       UWORD8           subchannel,
+                                       UWORD8           tch_loop,
+                                       UWORD8           sync_tch,
+                                       UWORD8           reset_sacch,
+                                       UWORD8           vocoder_on);
+  #else
+    void   l1ddsp_load_tch_param      (T_TIME_INFO      *next_time,
+                                       UWORD8           chan_mode,
+                                       UWORD8           chan_type,
+                                       UWORD8           subchannel,
+                                       UWORD8           tch_loop,
+                                       UWORD8           sync_tch);
+  #endif
+#endif
+
+BOOL enable_tch_vocoder           (BOOL             vocoder_on);
+
+BOOL   l1_select_mcsi_port            (UWORD8           port);
+
+void   l1ddsp_load_ciph_param     (UWORD8           a5mode,
+                                   T_ENCRYPTION_KEY *ciph_key);
+void   l1ddsp_load_tch_mode       (UWORD8           dai_mode,
+                                   BOOL             dtx_allowed);
+#if (AMR == 1)
+void l1ddsp_load_amr_param          (T_AMR_CONFIGURATION amr_param, UWORD8 cmip);
+#endif
+
+void   l1ddsp_stop_tch            (void);
+
+
+// MCU-TPU interface drivers.
+//---------------------------
+void l1dtpu_meas                  (UWORD16  radio_freq,
+                                   WORD8    agc,
+                                   UWORD8   lna_off,
+                                   UWORD16   win_id,
+                                   UWORD16  tpu_synchro,
+                                   UWORD8   adc_active);
+void l1dtpu_neig_fb               (UWORD16  radio_freq,
+                                   WORD8    agc,
+                                   UWORD8   lna_off);
+void l1dtpu_neig_fb26             (UWORD16  radio_freq,
+                                   WORD8    agc,
+                                   UWORD8   lna_off,
+                                   UWORD32  offset_serv);
+void l1dtpu_neig_sb               (UWORD16  radio_freq,
+                                   WORD8    agc,
+                                   UWORD8   lna_off,
+                                   UWORD32  time_alignmt,
+                                   UWORD32  offset_serv,
+                                   UWORD8   reload_flag,
+                                   UWORD8   attempt);
+void l1dtpu_neig_sb26             (UWORD16  radio_freq,
+                                   WORD8    agc,
+                                   UWORD8   lna_off,
+                                   UWORD32  time_alignmt,
+                                   UWORD32  fn_offset,
+                                   UWORD32  offset_serv);
+void l1dtpu_serv_rx_nb            (UWORD16  radio_freq,
+                                   WORD8    agc,
+                                   UWORD8   lna_off,
+                                   UWORD32  synchro_serv,
+                                   UWORD32  new_offset,
+                                   BOOL     change_offset,
+                                   UWORD8   adc_active);
+void l1dtpu_serv_tx_nb            (UWORD16  radio_freq,
+                                   UWORD8   timing_advance,
+                                   UWORD32  offset_serv,
+                                   UWORD8   txpwr,
+                                   UWORD8   adc_active);
+void l1dtpu_neig_rx_nb            (UWORD16  radio_freq,
+                                   WORD8    agc,
+                                   UWORD8   lna_off,
+                                   UWORD32  time_alignmt,
+                                   UWORD32  offset_serv,
+                                   UWORD8   reload_flag,
+                                   UWORD8   nop);
+void l1dtpu_serv_tx_ra            (UWORD16  radio_freq,
+                                   UWORD32  offset_serv,
+                                   UWORD8   txpwr,
+                                   UWORD8   adc_active);
+
+// MCU-DSP interface drivers for POWER-ON.
+//----------------------------------------
+void l1dtpu_init_dpram            (UWORD8   process);
+
+// MCU-DSP interface drivers for RESET.
+//-------------------------------------
+void l1ddsp_end_scenario          (UWORD8 type);
+void l1dtpu_end_scenario          (void);
+void l1d_reset_hw                 (UWORD32 offset_value);
+
+
+
+/**************************************/
+/* Prototypes for L1 ASYNCH task      */
+/**************************************/
+
+void  l1a_task                                   (UWORD32 argc, void *argv);
+void  l1a_balance_l1a_tasks                      (void);
+
+void  l1a_mmi_adc_req                            (xSignalHeaderRec *msg);
+void  l1a_network_lost                           (xSignalHeaderRec *msg);
+void  l1a_idle_6strongest_monitoring_process     (xSignalHeaderRec *msg);
+void  l1a_idle_serving_cell_bcch_reading_process (xSignalHeaderRec *msg);
+void  l1a_idle_serving_cell_paging_process       (xSignalHeaderRec *msg);
+void  l1a_idle_smscb_process                     (xSignalHeaderRec *msg);
+void  l1a_initial_network_sync_process           (xSignalHeaderRec *msg);
+void  l1a_cres_process                           (xSignalHeaderRec *msg);
+void  l1a_dedic_ba_list_meas_process             (xSignalHeaderRec *msg);
+
+void  l1a_full_list_meas_process      (xSignalHeaderRec *msg);
+void  l1a_csel_bcch_process           (xSignalHeaderRec *msg);
+
+void  l1a_idle_serv_meas_process      (xSignalHeaderRec *msg);
+
+void  l1a_idle_neigh_meas_process     (xSignalHeaderRec *msg);
+void  l1a_idle_neigh_full_bcch_process(xSignalHeaderRec *msg);
+void  l1a_idle_neigh_norm_bcch_process(xSignalHeaderRec *msg);
+void  l1a_idle_neigh_ext_bcch_process (xSignalHeaderRec *msg);
+void  l1a_idle_6conf_process          (xSignalHeaderRec *msg);
+
+void  l1a_idle_smscb_process          (xSignalHeaderRec *msg);
+
+void  l1a_access_process              (xSignalHeaderRec *msg);
+void  l1a_dedicated_process           (xSignalHeaderRec *msg);
+void  l1a_dedic_bcch_process          (xSignalHeaderRec *msg);
+void  l1a_dedic6_process              (xSignalHeaderRec *msg);
+void  l1a_dedic_neigh_meas_process    (xSignalHeaderRec *msg);
+
+void  l1a_idle_ba_list_meas_process   (xSignalHeaderRec *msg);
+void  l1a_idle_full_list_meas_process (xSignalHeaderRec *msg);
+void  l1a_test_process                (xSignalHeaderRec *msg);
+void  l1a_freq_band_configuration     (xSignalHeaderRec *msg);
+
+#if (OP_L1_STANDALONE == 1)
+// Dynamic configuration process for L1 standalone only
+  void   l1a_test_config_process        (xSignalHeaderRec *msg);
+#endif
+
+// ...................NEW FOR ALR....................
+void  l1a_neighbour_cell_bcch_reading_process (xSignalHeaderRec *msg);
+// ...................NEW FOR ALR....................
+
+/**************************************/
+/* Prototypes for l3 task             */
+/**************************************/
+void  l3_task                         (UWORD32 argc, void *argv);
+void  l3_expire_fct                   (UWORD32 id);
+
+#if TESTMODE
+  void  mmi_task                      (UWORD32 argc, void *argv);
+#endif
+
+
+
+
+
+/**************************************/
+/* Prototypes for Nu_main.            */
+/**************************************/
+UWORD32            get_arm_version (void);
+void               usart_hisr      (void);
+void               Adc_timer       (UWORD32 id);
+/**************************************/
+/* Prototypes for l2 task             */
+/**************************************/
+T_RADIO_FRAME  *dll_read_dcch     (UWORD8  chn_mode);
+T_RADIO_FRAME  *dll_read_sacch    (UWORD8  chn_mode);
+void           l2_task            (UWORD32 argc, void *argv);
+
+#if (DSP_BACKGROUND_TASKS == 1)
+// Task for backgrounds DSP testing
+void background_task(UWORD32 argc, void *argv);
+#endif
+
+void           rx_tch_data        (API     *data_address,
+                                   UWORD8  channel_mode,
+                                   UWORD8  blk_seq_number);
+UWORD8           *tx_tch_data     (void);
+
+#if (SEND_FN_TO_L2_IN_DCCH==1)
+void           dll_dcch_downlink  (API     *info_address,
+                                   UWORD8  valid_flag, 
+                                   UWORD32 frame_number);
+#else
+void           dll_dcch_downlink  (API     *info_address,
+                                   UWORD8  valid_flag);
+#endif
+
+/***************************************/
+/* Prototypes of L1_TRACE.c functions  */
+/***************************************/
+void l1_trace_message          (xSignalHeaderRec *msg);
+void send_debug_sig            (UWORD8 debug_code, UWORD8 task);
+void l1_trace_cpu_load         (UWORD8 cpu_load);
+void l1_trace_ratscch(UWORD16 fn, UWORD16 amr_change_bitmap);
+
+#if (TRACE_TYPE==7) // CPU_LOAD
+void l1_cpu_load_start          (void);
+void l1_cpu_load_stop           (void);
+void l1_cpu_load_init           (void);
+void l1_cpu_load_interm         (void);
+#endif
+
+/***************************************/
+/* Prototypes of HW_DEBUG.c functions  */
+/***************************************/
+void  get_usart_characters        (void);  // HISR for Rx characters
+void  wait_for_next_message       (CHAR *);
+
+/***************************************/
+/* Prototypes of L1_DEBUG.c functions  */
+/***************************************/
+void scenario_and_log_files   (void);
+void decode_msg               (xSignalHeaderRec *msg, CHAR *filename);
+void trace_mft                (CHAR *fct_name, WORD32 frame);
+#if (L1_EOTD ==1)
+  void trace_EOTD_serving     (UWORD16 arfcn, UWORD32 timetag, CHAR *text);
+  void trace_EOTD_serving1    (CHAR *text);
+  void trace_EOTD_neighbour   (UWORD8 nbr, UWORD16 arfcn, UWORD32 delta_fn, WORD32 delta_qbit,
+                                 UWORD32 timetag, CHAR *text);
+#endif
+void trace_ULPD               (CHAR *text, UWORD32 frame_number);
+void log_fct                  (CHAR *fct_name, UWORD32 radio_freq);
+void trace_msg                (CHAR *msg_name, CHAR *queue_name);
+void log_msg                  (CHAR *msg_name, CHAR *queue_name);
+void trace_dedic              (void);
+void trace_fct_simu           (CHAR *fct_name, WORD32 radio_freq);
+void trace_flowchart_msg      (CHAR *msg_name, CHAR *dest_queue_name);
+void trace_flowchart_l1tsk    (UWORD32 bit_register, UWORD32 *src_register_set);
+void trace_flowchart_dedic    (WORD32 SignalCode);
+void trace_flowchart_tpu      (CHAR *task_name);
+void trace_flowchart_dsp      (CHAR *task_name);
+void trace_flowchart_dsp_tpu  (CHAR *task_name);
+void trace_flowchart_dspres   (CHAR *task_name);
+void trace_flowchart_dsptx    (CHAR *task_name);
+void trace_flowchart_header   (void);
+void trace_sim_freq_band_configuration  (UWORD8 freq_band_config);
+
+/**************************************/
+/* prototypes of control functions    */
+/**************************************/
+#if (VCXO_ALGO == 0)
+WORD16 l1ctl_afc                 (UWORD8  phase,
+                                 UWORD32  *frame_count,
+                                 WORD16   angle,
+                                 WORD32   snr,
+                                 UWORD16  radio_freq);
+#else
+WORD16 l1ctl_afc                 (UWORD8  phase,
+                                 UWORD32  *frame_count,
+                                 WORD16   angle,
+                                 WORD32   snr,
+                                 UWORD16  radio_freq,
+                                 UWORD32  l1_mode);
+#endif
+WORD16 l1ctl_toa                 (UWORD8  phase,
+                                 UWORD32  l1_mode,
+                                 UWORD16  SNR_val,
+                                 UWORD16  TOA_val,
+                                 BOOL     *toa_update,
+                                 UWORD16  *toa_period_count);
+UWORD8 l1ctl_txpwr             (UWORD8    target_txpwr,
+                                 UWORD8   current_txpwr);
+
+// Utility for agc control algorithms
+
+void l1ctl_encode_lna  (UWORD8  input_level,
+                        UWORD8  * lna_state,
+                        UWORD16 radio_freq);
+UWORD8 l1ctl_find_max  (UWORD8  *buff,
+                        UWORD8  buffer_len);
+// Automatic Gain Control Algorithms
+void l1ctl_pgc2          (UWORD8        pm_high_agc,
+                          UWORD8        pm_low_agc,
+                          UWORD16       radio_freq);
+UWORD8 l1ctl_csgc        (UWORD8        pm,
+                          UWORD16       radio_freq);
+UWORD8 l1ctl_pgc         (UWORD8        pm,
+                          UWORD8        used_IL,
+                          UWORD8        lna_off,
+                          UWORD16       radio_freq);
+UWORD8 l1ctl_pagc        (UWORD8        pm,
+                          UWORD16       radio_freq,
+                          T_INPUT_LEVEL *traffic_meas_ptr);
+UWORD8 l1ctl_dpagc       (BOOL          dtx_on,
+                          BOOL          beacon,
+                          UWORD8        pm,
+                          UWORD16       radio_freq,
+                          T_INPUT_LEVEL *traffic_meas_ptr);
+#if (AMR == 1)
+  UWORD8 l1ctl_dpagc_amr   (BOOL          dtx_on,
+                            BOOL          beacon,
+                            UWORD8        pm,
+                            UWORD16       radio_freq,
+                            T_INPUT_LEVEL *traffic_meas_ptr);
+#endif
+
+UWORD16 l1ctl_get_g_magic (UWORD16 radio_freq);
+UWORD16 l1ctl_get_lna_att (UWORD16 radio_freq);
+void    l1ctl_update_TPU_with_toa(void);
+
+//functions for customization
+void Cust_init_std         (void);
+void Cust_init_params      (void);
+WORD8 Cust_get_agc_from_IL (UWORD16 radio_freq, UWORD16 agc_index, UWORD8 table_id);
+WORD8 l1ctl_encode_delta1  (UWORD16 radio_freq);
+WORD8 l1ctl_encode_delta2  (UWORD16 radio_freq);
+void Cust_get_ramp_tab     (API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq);
+#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+  UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq);
+#endif
+
+
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_rtt_macro.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_rtt_macro.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,314 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_RTT_MACRO.H
+ *
+ *        Filename %M%
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+#if (defined RVM_RTT_SWE || (OP_L1_STANDALONE == 1))
+
+#include "rvt_gen.h"
+#include "rtt_gen.h"
+
+extern T_TRACE_INFO_STRUCT trace_info;
+                                                                    
+/***********************************************************************************************************/
+/* Macro for cell enabling checking                                                                        */
+/***********************************************************************************************************/
+
+#define SELECTED_BITMAP(enable_bit) \
+  enable_bit < 32  ? (0x0001 << (enable_bit -   0)) & trace_info.current_config->rttl1_cell_enable[0] : \
+  enable_bit < 64  ? (0x0001 << (enable_bit -  32)) & trace_info.current_config->rttl1_cell_enable[1] : \
+  enable_bit < 96  ? (0x0001 << (enable_bit -  64)) & trace_info.current_config->rttl1_cell_enable[2] : \
+  enable_bit < 128 ? (0x0001 << (enable_bit -  96)) & trace_info.current_config->rttl1_cell_enable[3] : \
+  enable_bit < 160 ? (0x0001 << (enable_bit - 128)) & trace_info.current_config->rttl1_cell_enable[4] : \
+  enable_bit < 192 ? (0x0001 << (enable_bit - 160)) & trace_info.current_config->rttl1_cell_enable[5] : \
+  enable_bit < 224 ? (0x0001 << (enable_bit - 192)) & trace_info.current_config->rttl1_cell_enable[6] : \
+                     (0x0001 << (enable_bit - 224)) & trace_info.current_config->rttl1_cell_enable[7]
+
+/***********************************************************************************************************/
+/* Macros for buffer filling                                                                               */
+/***********************************************************************************************************/
+
+//-----------------------------------------------------------------------------------------------------------
+// L1 RTT cell filling: FN
+                                     
+#define RTTL1_FILL_FN(param1) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_FN)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_FN))) != NULL) \
+      { \
+        ((T_RTTL1_FN *)ptr)->fn          = param1; \
+        ((T_RTTL1_FN *)ptr)->cell_id     = RTTL1_ENABLE_FN; \
+      } \
+  }
+
+//-----------------------------------------------------------------------------------------------------------
+// L1 RTT cell filling: Downlink burst
+                                     
+#define RTTL1_FILL_DL_BURST(param1,param2,param3,param4,param5,param6,param7) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_DL_BURST))                                                                  \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_BURST))) != NULL) \
+      { \
+        ((T_RTTL1_DL_BURST *)ptr)->angle       = param1; \
+        ((T_RTTL1_DL_BURST *)ptr)->snr         = param2; \
+        ((T_RTTL1_DL_BURST *)ptr)->afc         = param3; \
+        ((T_RTTL1_DL_BURST *)ptr)->task        = param4; \
+        ((T_RTTL1_DL_BURST *)ptr)->pm          = param5; \
+        ((T_RTTL1_DL_BURST *)ptr)->toa         = param6; \
+        ((T_RTTL1_DL_BURST *)ptr)->input_level = param7; \
+        ((T_RTTL1_DL_BURST *)ptr)->cell_id     = RTTL1_ENABLE_DL_BURST; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Uplink Normal Burst                                                                   
+                                                                                                              
+#define RTTL1_FILL_UL_NB(param1, param2, param3) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_UL_NB)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_NB))) != NULL) \
+      { \
+        ((T_RTTL1_UL_NB *)ptr)->task    = param1; \
+        ((T_RTTL1_UL_NB *)ptr)->ta      = param2; \
+        ((T_RTTL1_UL_NB *)ptr)->txpwr   = param3; \
+        ((T_RTTL1_UL_NB *)ptr)->cell_id = RTTL1_ENABLE_UL_NB; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Uplink Access Burst                                                                   
+                                                                                                              
+#define RTTL1_FILL_UL_AB(param1, param2) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_UL_AB)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_AB))) != NULL) \
+      { \
+        ((T_RTTL1_UL_AB *)ptr)->task    = param1; \
+        ((T_RTTL1_UL_AB *)ptr)->txpwr   = param2; \
+        ((T_RTTL1_UL_AB *)ptr)->cell_id = RTTL1_ENABLE_UL_AB; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Full list measurement                                                                           
+                                                                                                              
+#define RTTL1_FILL_FULL_LIST_MEAS(param1, param2, param3, param4) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_FULL_LIST_MEAS)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_FULL_LIST_MEAS))) != NULL) \
+      {                                                                                                       \
+        ((T_RTTL1_FULL_LIST_MEAS *)ptr)->pm          = param1; \
+        ((T_RTTL1_FULL_LIST_MEAS *)ptr)->input_level = param2; \
+        ((T_RTTL1_FULL_LIST_MEAS *)ptr)->task        = param3; \
+        ((T_RTTL1_FULL_LIST_MEAS *)ptr)->radio_freq  = param4; \
+        ((T_RTTL1_FULL_LIST_MEAS *)ptr)->cell_id     = RTTL1_ENABLE_FULL_LIST_MEAS; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Full list measurement                                                                           
+                                                                                                              
+#define RTTL1_FILL_MON_MEAS(param1, param2, param3, param4) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_MON_MEAS)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MON_MEAS))) != NULL) \
+      { \
+        ((T_RTTL1_MON_MEAS *)ptr)->pm          = param1; \
+        ((T_RTTL1_MON_MEAS *)ptr)->input_level = param2; \
+        ((T_RTTL1_MON_MEAS *)ptr)->task        = param3; \
+        ((T_RTTL1_MON_MEAS *)ptr)->radio_freq  = param4; \
+        ((T_RTTL1_MON_MEAS *)ptr)->cell_id     = RTTL1_ENABLE_MON_MEAS; \
+      } \
+  }                                                                                                           
+
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Downlink DCCH block                                                                   
+                                                                                                              
+#define RTTL1_FILL_DL_DCCH(param1, param2) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_DL_DCCH)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_DCCH))) != NULL) \
+      { \
+        ((T_RTTL1_DL_DCCH *)ptr)->valid_flag    = param1; \
+        ((T_RTTL1_DL_DCCH *)ptr)->physical_info = param2; \
+        ((T_RTTL1_DL_DCCH *)ptr)->cell_id       = RTTL1_ENABLE_DL_DCCH; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Downlink PTCCH block                                                                  
+                                                                                                              
+#define RTTL1_FILL_DL_PTCCH(param1, param2) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_DL_PTCCH)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_PTCCH))) != NULL) \
+      { \
+        ((T_RTTL1_DL_PTCCH *)ptr)->crc        = param1; \
+        ((T_RTTL1_DL_PTCCH *)ptr)->ordered_ta = param2; \
+        ((T_RTTL1_DL_PTCCH *)ptr)->cell_id    = RTTL1_ENABLE_DL_PTCCH; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Uplink DCCH block                                                                     
+                                                                                                              
+#define RTTL1_FILL_UL_DCCH \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_UL_DCCH)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_DCCH))) != NULL) \
+      { \
+        ((T_RTTL1_UL_DCCH *)ptr)->cell_id = RTTL1_ENABLE_UL_DCCH; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Uplink SACCH block                                                                    
+                                                                                                              
+#define RTTL1_FILL_UL_SACCH(param1, param2, param3) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_UL_SACCH)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_SACCH))) != NULL) \
+      { \
+        ((T_RTTL1_UL_SACCH *)ptr)->data_present   = param1; \
+        ((T_RTTL1_UL_SACCH *)ptr)->reported_ta    = param2; \
+        ((T_RTTL1_UL_SACCH *)ptr)->reported_txpwr = param3; \
+        ((T_RTTL1_UL_SACCH *)ptr)->cell_id        = RTTL1_ENABLE_UL_SACCH; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Downlink PDTCH block                                                                  
+                                                                                                              
+#define RTTL1_FILL_DL_PDTCH(param1, param2, param3, param4, param5) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_DL_PDTCH)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_DL_PDTCH))) != NULL) \
+      { \
+        ((T_RTTL1_DL_PDTCH *)ptr)->mac_header = param1; \
+        ((T_RTTL1_DL_PDTCH *)ptr)->tfi_result = param2; \
+        ((T_RTTL1_DL_PDTCH *)ptr)->crc        = param3; \
+        ((T_RTTL1_DL_PDTCH *)ptr)->cs_type    = param4; \
+        ((T_RTTL1_DL_PDTCH *)ptr)->timeslot   = param5; \
+        ((T_RTTL1_DL_PDTCH *)ptr)->cell_id    = RTTL1_ENABLE_DL_PDTCH; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: Uplink PDTCH block                                                                    
+                                                                                                              
+#define RTTL1_FILL_UL_PDTCH(param1, param2, param3) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_UL_PDTCH)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_UL_PDTCH))) != NULL) \
+      { \
+        ((T_RTTL1_UL_PDTCH *)ptr)->cs_type      = param1; \
+        ((T_RTTL1_UL_PDTCH *)ptr)->data_allowed = param2; \
+        ((T_RTTL1_UL_PDTCH *)ptr)->timeslot     = param3; \
+        ((T_RTTL1_UL_PDTCH *)ptr)->cell_id      = RTTL1_ENABLE_UL_PDTCH; \
+      } \
+  }                                                                                                           
+                                                                                                              
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: MAC-S error                                                                           
+                                                                                                              
+#define RTTL1_FILL_MACS_STATUS(param1, param2) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_MACS_STATUS)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MACS_STATUS))) != NULL) \
+      { \
+        ((T_RTTL1_MACS_STATUS *)ptr)->status   = param1; \
+        ((T_RTTL1_MACS_STATUS *)ptr)->timeslot = param2; \
+        ((T_RTTL1_MACS_STATUS *)ptr)->cell_id  = RTTL1_ENABLE_MACS_STATUS; \
+      } \
+  }
+
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: L1S task enable                                                                       
+                                                                                                              
+#define RTTL1_FILL_L1S_TASK_ENABLE(param1, param2) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_L1S_TASK_ENABLE)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_L1S_TASK_ENABLE))) != NULL) \
+      { \
+        ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->bitmap1  = param1; \
+        ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->bitmap2  = param2; \
+        ((T_RTTL1_L1S_TASK_ENABLE *)ptr)->cell_id  = RTTL1_ENABLE_L1S_TASK_ENABLE; \
+      } \
+  }
+
+//----------------------------------------------------------------------------------------------------------- 
+// L1 RTT cell filling: MFTAB trace                                                                       
+                                                                                                              
+#define RTTL1_FILL_MFTAB(param1) \
+  if(SELECTED_BITMAP(RTTL1_ENABLE_MFTAB)) \
+  { \
+      T_RTT_PTR  ptr; \
+\
+      if ((ptr = trace_info.l1s_rtt_func.rtt_get_fill_ptr(trace_info.l1s_trace_user_id, sizeof(T_RTTL1_MFTAB))) != NULL) \
+      { \
+        ((T_RTTL1_MFTAB *)ptr)->func     = param1; \
+        ((T_RTTL1_MFTAB *)ptr)->cell_id  = RTTL1_ENABLE_MFTAB; \
+      } \
+  }
+
+/***********************************************************************************************************/ 
+/* Macro for events                                                                                        */ 
+/***********************************************************************************************************/
+                                                                                                              
+#define RTTL1_EVENT(id,size) \
+  if (trace_info.current_config->rttl1_event_enable & (0x1 << id)) \
+    trace_info.l1s_rtt_func.rtt_dump_buffer(trace_info.l1s_trace_user_id, size);
+#else // RVM_RTT_SWE || OP_L1_STANDALONE
+
+// No RTT: all macros are empty
+#define SELECTED_BITMAP(enable_bit) (0)                                   
+#define RTTL1_FILL_FN(param1)                                      
+#define RTTL1_FILL_DL_BURST(param1,param2,param3,param4,param5,param6,param7)                                                                                                               
+#define RTTL1_FILL_UL_NB(param1, param2, param3)                                                                                                               
+#define RTTL1_FILL_UL_AB(param1, param2)                                                                                                               
+#define RTTL1_FILL_FULL_LIST_MEAS(param1, param2, param3, param4)                                                                                                               
+#define RTTL1_FILL_MON_MEAS(param1, param2, param3, param4)                                                                                                               
+#define RTTL1_FILL_DL_DCCH(param1, param2)                                                                                                               
+#define RTTL1_FILL_DL_PTCCH(param1, param2)                                                                                                               
+#define RTTL1_FILL_UL_DCCH                                                                                                               
+#define RTTL1_FILL_UL_SACCH(param1, param2, param3)                                                                                                              
+#define RTTL1_FILL_DL_PDTCH(param1, param2, param3, param4, param5)                                                                                                              
+#define RTTL1_FILL_UL_PDTCH(param1, param2, param3)                                                                                                              
+#define RTTL1_FILL_MACS_STATUS(param1, param2)                                                                                                              
+#define RTTL1_FILL_L1S_TASK_ENABLE(param1, param2)                                                                                                              
+#define RTTL1_FILL_MFTAB(param1)
+#define RTTL1_EVENT(id,size)
+
+#endif // RVM_RTT_SWE || OP_L1_STANDALONE
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_signa.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_signa.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,184 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_SIGNA.H
+ *
+ *        Filename l1_signa.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+#define P_L1C  0
+#define P_DLL  ( P_L1C + 1 )
+
+// Messages Test/PWRMNGT <-> L1A
+
+#if (OP_L1_STANDALONE == 1)
+  /* Message used for hardware dynamic configuration */
+  #define TST_HW_CONFIG_REQ              ( ( P_L1C << 8 ) | 116)
+#endif
+
+#define TST_TEST_HW_REQ                  ( ( P_L1C << 8 ) | 1  )
+#define TST_TEST_HW_CON                  ( ( P_L1C << 8 ) | 2  )
+#define TST_TIMESTAMP_MSG                ( ( P_L1C << 8 ) | 3  )
+#define TST_SLEEP_REQ                    ( ( P_L1C << 8 ) | 4  )
+
+
+// Messages L3 <-> L1A
+#define MPHC_RXLEV_REQ                   ( ( P_L1C << 8 ) | 11 )
+#define MPHC_RXLEV_IND                   ( ( P_L1C << 8 ) | 12 )
+
+#define MPHC_STOP_RXLEV_REQ              ( ( P_L1C << 8 ) | 13 )
+#define MPHC_STOP_RXLEV_CON              ( ( P_L1C << 8 ) | 14 )
+
+#define MPHC_NETWORK_SYNC_REQ            ( ( P_L1C << 8 ) | 15 )
+#define MPHC_NETWORK_SYNC_IND            ( ( P_L1C << 8 ) | 16 )
+
+#define MPHC_STOP_NETWORK_SYNC_REQ       ( ( P_L1C << 8 ) | 17 )
+#define MPHC_STOP_NETWORK_SYNC_CON       ( ( P_L1C << 8 ) | 18 )
+
+#define MPHC_NEW_SCELL_REQ               ( ( P_L1C << 8 ) | 19 )
+#define MPHC_NEW_SCELL_CON               ( ( P_L1C << 8 ) | 20 )
+
+#define MPHC_START_CCCH_REQ              ( ( P_L1C << 8 ) | 21 )
+#define MPHC_STOP_CCCH_REQ               ( ( P_L1C << 8 ) | 22 )
+#define MPHC_STOP_CCCH_CON               ( ( P_L1C << 8 ) | 23 )
+
+#define MPHC_SCELL_NBCCH_REQ             ( ( P_L1C << 8 ) | 24 )
+#define MPHC_SCELL_EBCCH_REQ             ( ( P_L1C << 8 ) | 25 )
+#define MPHC_STOP_SCELL_BCCH_REQ         ( ( P_L1C << 8 ) | 26 )
+#define MPHC_STOP_SCELL_BCCH_CON         ( ( P_L1C << 8 ) | 27 )
+
+#define MPHC_NCELL_BCCH_REQ              ( ( P_L1C << 8 ) | 28 )
+#define MPHC_NCELL_BCCH_IND              ( ( P_L1C << 8 ) | 29 )
+#define MPHC_STOP_NCELL_BCCH_REQ         ( ( P_L1C << 8 ) | 30 )
+#define MPHC_STOP_NCELL_BCCH_CON         ( ( P_L1C << 8 ) | 31 )
+
+#define MPHC_NCELL_SYNC_REQ              ( ( P_L1C << 8 ) | 32 )
+#define MPHC_NCELL_SYNC_IND              ( ( P_L1C << 8 ) | 33 )
+#define MPHC_STOP_NCELL_SYNC_REQ         ( ( P_L1C << 8 ) | 34 )
+#define MPHC_STOP_NCELL_SYNC_CON         ( ( P_L1C << 8 ) | 35 )
+
+#define MPHC_RXLEV_PERIODIC_REQ          ( ( P_L1C << 8 ) | 36 )
+#define MPHC_RXLEV_PERIODIC_IND          ( ( P_L1C << 8 ) | 37 )
+#define MPHC_STOP_RXLEV_PERIODIC_REQ     ( ( P_L1C << 8 ) | 38 )
+#define MPHC_STOP_RXLEV_PERIODIC_CON     ( ( P_L1C << 8 ) | 39 )
+
+#define MPHC_CONFIG_CBCH_REQ             ( ( P_L1C << 8 ) | 40 )
+#define MPHC_CBCH_SCHEDULE_REQ           ( ( P_L1C << 8 ) | 41 )
+#define MPHC_CBCH_UPDATE_REQ             ( ( P_L1C << 8 ) | 42 )
+#define MPHC_CBCH_INFO_REQ               ( ( P_L1C << 8 ) | 43 )
+#define MPHC_STOP_CBCH_REQ               ( ( P_L1C << 8 ) | 44 )
+#define MPHC_STOP_CBCH_CON               ( ( P_L1C << 8 ) | 45 )
+
+#define MPHC_RA_REQ                      ( ( P_L1C << 8 ) | 46 )
+#define MPHC_RA_CON                      ( ( P_L1C << 8 ) | 47 )
+
+#define MPHC_STOP_RA_REQ                 ( ( P_L1C << 8 ) | 48 )
+#define MPHC_STOP_RA_CON                 ( ( P_L1C << 8 ) | 49 )
+
+#define MPHC_DATA_IND                    ( ( P_L1C << 8 ) | 50 )
+
+#define MPHC_IMMED_ASSIGN_REQ            ( ( P_L1C << 8 ) | 51 )
+#define MPHC_CHANNEL_ASSIGN_REQ          ( ( P_L1C << 8 ) | 52 )
+#define MPHC_ASYNC_HO_REQ                ( ( P_L1C << 8 ) | 53 )
+#define MPHC_SYNC_HO_REQ                 ( ( P_L1C << 8 ) | 54 )
+#define MPHC_PRE_SYNC_HO_REQ             ( ( P_L1C << 8 ) | 55 )
+#define MPHC_PSEUDO_SYNC_HO_REQ          ( ( P_L1C << 8 ) | 56 )
+#define MPHC_STOP_DEDICATED_REQ          ( ( P_L1C << 8 ) | 57 )
+#define MPHC_STOP_DEDICATED_CON          ( ( P_L1C << 8 ) | 128 )
+
+#define MPHC_CHANGE_FREQUENCY_CON        ( ( P_L1C << 8 ) | 58 )
+#define MPHC_ASYNC_HO_CON                ( ( P_L1C << 8 ) | 59 )
+#define MPHC_CHANNEL_ASSIGN_CON          ( ( P_L1C << 8 ) | 60 )
+#define MPHC_CHANNEL_MODE_MODIFY_CON     ( ( P_L1C << 8 ) | 61 )
+#define MPHC_HANDOVER_FAIL_CON           ( ( P_L1C << 8 ) | 62 )
+#define MPHC_IMMED_ASSIGN_CON            ( ( P_L1C << 8 ) | 63 )
+#define MPHC_PRE_SYNC_HO_CON             ( ( P_L1C << 8 ) | 64 )
+#define MPHC_SET_CIPHERING_CON           ( ( P_L1C << 8 ) | 65 )
+#define MPHC_SYNC_HO_CON                 ( ( P_L1C << 8 ) | 66 )
+#define MPHC_TA_FAIL_IND                 ( ( P_L1C << 8 ) | 67 )
+
+#define MPHC_HANDOVER_FINISHED           ( ( P_L1C << 8 ) | 68 )
+
+#define MPHC_CHANGE_FREQUENCY            ( ( P_L1C << 8 ) | 69 )
+#define MPHC_CHANNEL_MODE_MODIFY_REQ     ( ( P_L1C << 8 ) | 70 )
+#define MPHC_HANDOVER_FAIL_REQ           ( ( P_L1C << 8 ) | 71 )
+#define MPHC_SET_CIPHERING_REQ           ( ( P_L1C << 8 ) | 72 )
+
+#define MPHC_MEAS_REPORT                 ( ( P_L1C << 8 ) | 73 )
+#define MPHC_UPDATE_BA_LIST              ( ( P_L1C << 8 ) | 74 )
+
+#define MPHC_NCELL_FB_SB_READ            ( ( P_L1C << 8 ) | 75 )
+#define MPHC_NCELL_SB_READ               ( ( P_L1C << 8 ) | 76 )
+#define MPHC_NCELL_BCCH_READ             ( ( P_L1C << 8 ) | 77 )
+
+
+
+// Messages L1S -> L1A
+#define L1C_VALID_MEAS_INFO              ( ( P_L1C << 8 ) | 80 )
+#define L1C_FB_INFO                      ( ( P_L1C << 8 ) | 81 )
+#define L1C_SB_INFO                      ( ( P_L1C << 8 ) | 82 )
+#define L1C_SBCONF_INFO                  ( ( P_L1C << 8 ) | 83 )
+#define L1C_BCCHS_INFO                   ( ( P_L1C << 8 ) | 84 )
+#define L1C_BCCHN_INFO                   ( ( P_L1C << 8 ) | 85 )
+#define L1C_NP_INFO                      ( ( P_L1C << 8 ) | 86 )
+#define L1C_EP_INFO                      ( ( P_L1C << 8 ) | 87 )
+#define L1C_ALLC_INFO                    ( ( P_L1C << 8 ) | 88 )
+#define L1C_RXLEV_PERIODIC_DONE          ( ( P_L1C << 8 ) | 89 )
+#define L1C_CB_INFO                      ( ( P_L1C << 8 ) | 90 )
+#define L1C_RA_DONE                      ( ( P_L1C << 8 ) | 91 )
+#define L1C_SACCH_INFO                   ( ( P_L1C << 8 ) | 92 )
+#define L1C_MEAS_DONE                    ( ( P_L1C << 8 ) | 93 )
+#define L1C_DEDIC_DONE                   ( ( P_L1C << 8 ) | 94 )
+#define L1C_HANDOVER_FINISHED            ( ( P_L1C << 8 ) | 95 )
+#define L1C_REDEF_DONE                   ( ( P_L1C << 8 ) | 96 )
+#define L1C_STOP_DEDICATED_DONE          ( ( P_L1C << 8 ) | 129 )
+
+// Messages O&M <-> L1A
+#define OML1_CLOSE_TCH_LOOP_REQ          ( ( P_L1C << 8 ) | 97 )
+#define OML1_OPEN_TCH_LOOP_REQ           ( ( P_L1C << 8 ) | 98 )
+#define OML1_START_DAI_TEST_REQ          ( ( P_L1C << 8 ) | 99 )
+#define OML1_STOP_DAI_TEST_REQ           ( ( P_L1C << 8 ) | 100 )
+
+#define OML1_CLOSE_TCH_LOOP_CON          ( ( P_L1C << 8 ) | 101 )
+#define OML1_OPEN_TCH_LOOP_CON           ( ( P_L1C << 8 ) | 102 )
+#define OML1_START_DAI_TEST_CON          ( ( P_L1C << 8 ) | 103 )
+#define OML1_STOP_DAI_TEST_CON           ( ( P_L1C << 8 ) | 104 )
+
+
+// Message Custom I/F <- L1S
+#define CST_ADC_RESULT                   ( ( P_L1C << 8 ) | 105 )
+
+
+// Messages for trace
+#define L1_STATS_REQ                     ( ( P_L1C << 8 ) | 107 )
+#define L1_DUMMY_FOR_SIM                 ( ( P_L1C << 8 ) | 108 )
+
+#define TRACE_DSP_DEBUG                  ( ( P_L1C << 8 ) | 106 )
+#define TRACE_CONFIG                     ( ( P_L1C << 8 ) | 123 )
+#define TRACE_CONDENSED_PDTCH            ( ( P_L1C << 8 ) | 124 )
+#define TRACE_INFO                       ( ( P_L1C << 8 ) | 125 )
+#define QUICK_TRACE                      ( ( P_L1C << 8 ) | 126 )
+#define TRACE_DSP_AMR_DEBUG              ( ( P_L1C << 8 ) | 127 )
+
+#define MPHC_NETWORK_LOST_IND            ( ( P_L1C << 8 ) | 110 )
+
+// Messages MMI <-> L1A
+#define MMI_ADC_REQ                      ( ( P_L1C << 8 ) | 111 )
+#define MMI_STOP_ADC_REQ                 ( ( P_L1C << 8 ) | 112 )
+#define MMI_STOP_ADC_CON                 ( ( P_L1C << 8 ) | 113 )
+
+#define L1_TEST_HW_INFO                  ( ( P_L1C << 8 ) | 119 )
+
+// Multi-band selection E-GSM900/DCS1800/PCS1900/GSM850
+  #define MPHC_INIT_L1_REQ              ( ( P_L1C << 8 ) | 114 )
+  #define MPHC_INIT_L1_CON              ( ( P_L1C << 8 ) | 115 )
+
+// MEssage RR -> L1A for Enhanced meas.
+#if (L1_12NEIGH ==1)
+#define  MPHC_NCELL_LIST_SYNC_REQ        ( ( P_L1C << 8 ) | 122 )    
+#endif
+
+// Messages L2 <-> L1A
+#define PH_DATA_IND                     ( ( P_DLL << 8 ) | 109   )
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_tabs.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_tabs.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,557 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_TABS.H
+ *
+ *        Filename l1_tabs.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+/***********************************************************
+ * Content:
+ *   This file contains the miscelaneous ROM tables.
+ ***********************************************************/
+
+#ifdef L1_ASYNC_C
+  /*-----------------------------------------------------------------*/
+  /* Idle Tasks info. (Paging position, extended Paging position...) */
+  /*-----------------------------------------------------------------*/
+  /* REM:                                                            */
+  /* The "working area" field gives the starting position of an area */
+  /* it will be used for neighbour:  - FB search,                    */
+  /*                                 - SB reading,                   */
+  /* The value given for each parameter set takes into account the   */
+  /* size of the "FB search" task and the CBCH task.                 */                                 
+  /*-----------------------------------------------------------------*/
+  //  NP or EP task size: 1 + 4 + 1 = 6.
+  //  BCCHS task size: 1 + 4 + 1 = 6.
+  //  FB task size: 1 + 12 + 1 = 14.    --+-- FB + SB task take 15 TDMA (pipeline overlay).
+  //  SB task size: 1 + 2 + 1 = 4.      --+
+  //  CNF, SB task size: 1 + 2 + 1 = 4.
+  //  BC (Broad. Channel): 1 + 4 + 1 = 6     
+   
+  const T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)] =
+  // BS_CCCH_SDCCH_COMB = False, BCCH not combined.
+  { 
+    // BS_AG_BLKS_RES = 0.
+    // -------------------
+    // Paging, Ext Paging
+    {  CCCH_0,     CCCH_2  },  // Paging Block Index = 0.
+    {  CCCH_1,     CCCH_3  },  // Paging Block Index = 1.
+    {  CCCH_2,     CCCH_4  },  // Paging Block Index = 2.
+    {  CCCH_3,     CCCH_5  },  // Paging Block Index = 3.
+    {  CCCH_4,     CCCH_6  },  // Paging Block Index = 4.
+    {  CCCH_5,     CCCH_7  },  // Paging Block Index = 5.
+    {  CCCH_6,     CCCH_8  },  // Paging Block Index = 6.
+    {  CCCH_7,     CCCH_0  },  // Paging Block Index = 7.
+    {  CCCH_8,     CCCH_1  },  // Paging Block Index = 8.
+
+    // BS_AG_BLKS_RES = 1.
+    // -------------------
+    // Paging, Ext Paging
+    {  CCCH_1,     CCCH_3  },  // Paging Block Index = 0.
+    {  CCCH_2,     CCCH_4  },  // Paging Block Index = 1.
+    {  CCCH_3,     CCCH_5  },  // Paging Block Index = 2.
+    {  CCCH_4,     CCCH_6  },  // Paging Block Index = 3.
+    {  CCCH_5,     CCCH_7  },  // Paging Block Index = 4.
+    {  CCCH_6,     CCCH_8  },  // Paging Block Index = 5.
+    {  CCCH_7,     CCCH_1  },  // Paging Block Index = 6.
+    {  CCCH_8,     CCCH_2  },  // Paging Block Index = 7.
+    {  NULL,       NULL    },  // Paging Block Index = 8.
+
+    // BS_AG_BLKS_RES = 2.
+    // -------------------
+    // Paging, Ext Paging
+    {  CCCH_2,     CCCH_4  },  // Paging Block Index = 0.
+    {  CCCH_3,     CCCH_5  },  // Paging Block Index = 1.
+    {  CCCH_4,     CCCH_6  },  // Paging Block Index = 2.
+    {  CCCH_5,     CCCH_7  },  // Paging Block Index = 3.
+    {  CCCH_6,     CCCH_8  },  // Paging Block Index = 4.
+    {  CCCH_7,     CCCH_2  },  // Paging Block Index = 5.
+    {  CCCH_8,     CCCH_3  },  // Paging Block Index = 6.
+    {  NULL,       NULL    },  // Paging Block Index = 7.
+    {  NULL,       NULL    },  // Paging Block Index = 8.
+
+    // BS_AG_BLKS_RES = 3.
+    // -------------------
+    // Paging, Ext Paging, 
+    {  CCCH_3,     CCCH_5  },  // Paging Block Index = 0.
+    {  CCCH_4,     CCCH_6  },  // Paging Block Index = 1.
+    {  CCCH_5,     CCCH_7  },  // Paging Block Index = 2.
+    {  CCCH_6,     CCCH_8  },  // Paging Block Index = 3.
+    {  CCCH_7,     CCCH_3  },  // Paging Block Index = 4.
+    {  CCCH_8,     CCCH_4  },  // Paging Block Index = 5.
+    {  NULL,       NULL    },  // Paging Block Index = 6.
+    {  NULL,       NULL    },  // Paging Block Index = 7.
+    {  NULL,       NULL    },  // Paging Block Index = 8.
+
+    // BS_AG_BLKS_RES = 4.
+    // -------------------
+    // Paging, Ext Paging
+    {  CCCH_4,     CCCH_6  },  // Paging Block Index = 0.
+    {  CCCH_5,     CCCH_7  },  // Paging Block Index = 1.
+    {  CCCH_6,     CCCH_8  },  // Paging Block Index = 2.
+    {  CCCH_7,     CCCH_4  },  // Paging Block Index = 3.
+    {  CCCH_8,     CCCH_5  },  // Paging Block Index = 4.
+    {  NULL,       NULL    },  // Paging Block Index = 5.
+    {  NULL,       NULL    },  // Paging Block Index = 6.
+    {  NULL,       NULL    },  // Paging Block Index = 7.
+    {  NULL,       NULL    },  // Paging Block Index = 8.
+
+    // BS_AG_BLKS_RES = 5.
+    // -------------------
+    // Paging, Ext Paging
+    {  CCCH_5,     CCCH_7  },  // Paging Block Index = 0.
+    {  CCCH_6,     CCCH_8  },  // Paging Block Index = 1.
+    {  CCCH_7,     CCCH_5  },  // Paging Block Index = 2.
+    {  CCCH_8,     CCCH_6  },  // Paging Block Index = 3.
+    {  NULL,       NULL    },  // Paging Block Index = 4.
+    {  NULL,       NULL    },  // Paging Block Index = 5.
+    {  NULL,       NULL    },  // Paging Block Index = 6.
+    {  NULL,       NULL    },  // Paging Block Index = 7.
+    {  NULL,       NULL    },  // Paging Block Index = 8.
+
+    // BS_AG_BLKS_RES = 6.
+    // -------------------
+    // Paging, Ext Paging, 
+    {  CCCH_6,     CCCH_8  },  // Paging Block Index = 0.
+    {  CCCH_7,     CCCH_6  },  // Paging Block Index = 1.
+    {  CCCH_8,     CCCH_7  },  // Paging Block Index = 2.
+    {  NULL,       NULL    },  // Paging Block Index = 3.
+    {  NULL,       NULL    },  // Paging Block Index = 4.
+    {  NULL,       NULL    },  // Paging Block Index = 5.
+    {  NULL,       NULL    },  // Paging Block Index = 6.
+    {  NULL,       NULL    },  // Paging Block Index = 7.
+    {  NULL,       NULL    },  // Paging Block Index = 8.
+
+    // BS_AG_BLKS_RES = 7.
+    // -------------------
+    // Paging, Ext Paging
+    {  CCCH_7,     CCCH_7  },  // Paging Block Index = 0.
+    {  CCCH_8,     CCCH_8  },  // Paging Block Index = 1.
+    {  NULL,       NULL    },  // Paging Block Index = 2.
+    {  NULL,       NULL    },  // Paging Block Index = 3.
+    {  NULL,       NULL    },  // Paging Block Index = 4.
+    {  NULL,       NULL    },  // Paging Block Index = 5.
+    {  NULL,       NULL    },  // Paging Block Index = 6.
+    {  NULL,       NULL    },  // Paging Block Index = 7.
+    {  NULL,       NULL    }   // Paging Block Index = 8.
+  };
+
+  const T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)] =
+  // BS_CCCH_SDCCH_COMB = TRUE, BCCH combined.
+  { 
+    // BS_AG_BLKS_RES = 0.
+    // -------------------
+    // Paging, Ext Paging, offset, working_area
+    {  CCCH_0,     CCCH_2  },  // Paging Block Index = 0.
+    {  CCCH_1,     CCCH_0  },  // Paging Block Index = 1.
+    {  CCCH_2,     CCCH_1  },  // Paging Block Index = 2.
+
+    // BS_AG_BLKS_RES = 1.
+    // -------------------
+    // Paging, Ext Paging, offset, working_area
+    {  CCCH_1,     CCCH_1  },  // Paging Block Index = 0.
+    {  CCCH_2,     CCCH_2  },  // Paging Block Index = 1.
+    {  NULL,       NULL    },  // Paging Block Index = 2.
+
+    // BS_AG_BLKS_RES = 2.
+    // -------------------
+    // Paging, Ext Paging, offset, working_area
+    {  CCCH_2,     CCCH_2  },  // Paging Block Index = 0.
+    {  NULL,       NULL    },  // Paging Block Index = 1.
+    {  NULL,       NULL    }   // Paging Block Index = 2.
+  };
+
+    
+  /*-------------------------------------*/
+  /* Table giving the number of Paging   */
+  /* blocks in a MF51.                   */
+  /* (called "N div BS_PA_MFRMS" in      */
+  /* GSM05.02, Page 21).                 */
+  /*-------------------------------------*/
+
+  // BS_CCCH_SDCCH_COMB = False, BCCH not combined.
+  const UWORD8 NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)] =
+  {
+    9,    // BS_AG_BLKS_RES = 0. 
+    8,    // BS_AG_BLKS_RES = 1. 
+    7,    // BS_AG_BLKS_RES = 2. 
+    6,    // BS_AG_BLKS_RES = 3. 
+    5,    // BS_AG_BLKS_RES = 4. 
+    4,    // BS_AG_BLKS_RES = 5. 
+    3,    // BS_AG_BLKS_RES = 6. 
+    2     // BS_AG_BLKS_RES = 7. 
+  };    
+
+  // BS_CCCH_SDCCH_COMB = True, BCCH combined.
+  const UWORD8 NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)] =
+  {
+    3,    // BS_AG_BLKS_RES = 0. 
+    2,    // BS_AG_BLKS_RES = 1. 
+    1     // BS_AG_BLKS_RES = 2. 
+  };    
+
+  // Initial value for Downlink Signalling failure Counter (DSC).
+  const UWORD8 DSC_INIT_VALUE[MAX_BS_PA_MFRMS-1] =
+  {
+    45,   // BS_PA_MFRMS = 2.
+    30,   // BS_PA_MFRMS = 3.
+    23,   // BS_PA_MFRMS = 4.
+    18,   // BS_PA_MFRMS = 5.
+    15,   // BS_PA_MFRMS = 6.
+    13,   // BS_PA_MFRMS = 7.
+    11,   // BS_PA_MFRMS = 8.
+    10    // BS_PA_MFRMS = 9.
+  };
+
+  // REM: 2nd block of SDCCH is always at the same position as the first block
+  //      but 1 mf51 later.
+  // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks).
+  //      Here is given the area starting position. This position is chosen
+  //      to allow the equations for SBCNF51 occurence as it is in the l1s
+  //      scheduler (the area do not overlap the end of 102 multiframe 
+  //      structure).
+  // Table for SDCCH description, Down Link & Up link, Not combined case.
+   const T_SDCCH_DESC SDCCH_DESC_NCOMB[8] =
+  {
+    //  "dl_D" , "dl_A"  , "ul_D"  , "ul_A".        , "monit. area"
+    {  51 - 12 , 32 - 12 , 15 - 12 ,  47 - 12       ,  70 - 12     }, // SDCCH, D0
+    {  55 - 12 , 36 - 12 , 19 - 12 ,  51 - 12       ,  74 - 12     }, // SDCCH, D1
+    {  59 - 12 , 40 - 12 , 23 - 12 ,  55 - 12       ,  78 - 12     }, // SDCCH, D2
+    {  12 - 12 , 44 - 12 , 27 - 12 ,  59 - 12       ,  82 - 12     }, // SDCCH, D3
+    {  16 - 12 , 83 - 12 , 31 - 12 ,  98 - 12       ,  35 - 12     }, // SDCCH, D4
+    {  20 - 12 , 87 - 12 , 35 - 12 , 102 - 12       ,  39 - 12     }, // SDCCH, D5
+    {  24 - 12 , 91 - 12 , 39 - 12 ,   4 - 12 + 102 ,  43 - 12     }, // SDCCH, D6
+    {  28 - 12 , 95 - 12 , 43 - 12 ,   8 - 12 + 102 ,  47 - 12     }  // SDCCH, D7
+  };  
+
+  // REM: monitoring during SDCCH used a fixe area (FB51/SB51/SBCNF51 tasks).
+  //      Here is given the area starting position. This position is chosen
+  //      to allow the equations for SBCNF51 occurence as it is in the l1s
+  //      scheduler (the area do not overlap the end of 102 multiframe 
+  //      structure).
+  // Table for SDCCH description, Down Link & Up link, Combined case.
+  const T_SDCCH_DESC SDCCH_DESC_COMB[4] =
+  {
+    // "dl_D"  , "dl_A"  , "ul_D"  , "ul_A".       , "monit. area"
+    {  73 - 37 , 42 - 37 , 37 - 37 , 57 - 37       ,  92 - 37     }, // SDCCH, D0
+    {  77 - 37 , 46 - 37 , 41 - 37 , 61 - 37       ,  96 - 37     }, // SDCCH, D1
+    {  83 - 37 , 93 - 37 , 47 - 37 , 6  - 37 + 102 ,  51 - 37     }, // SDCCH, D2
+    {  87 - 37 , 97 - 37 , 51 - 37 , 10 - 37 + 102 ,  55 - 37     }  // SDCCH, D3
+  };                                                               
+
+  // Table for HOPPING SEQUENCE GENERATION ALGORITHM.
+  const UWORD8 RNTABLE[114] =
+  {
+     48,  98,  63,   1,  36,  95,  78, 102,  94,  73,
+      0,  64,  25,  81,  76,  59, 124,  23, 104, 100,
+    101,  47, 118,  85,  18,  56,  96,  86,  54,   2,
+     80,  34, 127,  13,   6,  89,  57, 103,  12,  74,
+     55, 111,  75,  38, 109,  71, 112,  29,  11,  88,
+     87,  19,   3,  68, 110,  26,  33,  31,   8,  45,
+     82,  58,  40, 107,  32,   5, 106,  92,  62,  67,
+     77, 108, 122,  37,  60,  66, 121,  42,  51, 126,
+    117, 114,   4,  90,  43,  52,  53, 113, 120,  72,
+     16,  49,   7,  79, 119,  61,  22,  84,   9,  97,
+     91,  15,  21,  24,  46,  39,  93, 105,  65,  70,
+    125,  99,  17, 123
+  };
+
+
+  // Table giving the RACH slot positions when COMBINED.
+  // Rem: all is shifted left by 1 to map the position of the possible "contoles".
+  const UWORD8 COMBINED_RA_DISTRIB[51] =
+  { 
+    0, 0, 0, 
+    1, 1, 
+    0, 0, 0, 0, 0, 0, 0, 0, 
+    1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
+    0, 0, 0, 0, 0, 0, 0, 0,
+    1, 1, 
+    0, 0, 0, 0, 0
+  };
+
+#if !L1_GPRS
+  const T_TASK_MFTAB  TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] =
+  {
+    { BLOC_HWTEST,   BLOC_HWTEST_SIZE   },  // HWTEST 
+    { BLOC_ADC    ,  BLOC_ADC_SIZE      },  // ADC in CS_MODE0
+    { NULL,          0                  },  // DEDIC   (not meaningfull)
+    { BLOC_RAACC,    BLOC_RAACC_SIZE    },  // RAACC                 
+    { NULL,          0                  },  // RAHO    (not meaningfull)             
+    { NULL,          0                  },  // NSYNC   (not meaningfull)             
+    { BLOC_FBNEW,    BLOC_FBNEW_SIZE    },  // FBNEW 
+    { BLOC_SBCONF,   BLOC_SBCONF_SIZE   },  // SBCONF 
+    { BLOC_SB2,      BLOC_SB2_SIZE      },  // SB2 
+    { BLOC_FB26,     BLOC_FB26_SIZE     },  // FB26               
+    { BLOC_SB26,     BLOC_SB26_SIZE     },  // SB26
+    { BLOC_SBCNF26,  BLOC_SBCNF26_SIZE  },  // SBCNF26
+    { BLOC_FB51,     BLOC_FB51_SIZE     },  // FB51               
+    { BLOC_SB51,     BLOC_SB51_SIZE     },  // SB51               
+    { BLOC_SBCNF51,  BLOC_SBCNF51_SIZE  },  // SBCNF51               
+    { BLOC_BCCHN,    BLOC_BCCHN_SIZE    },  // BCCHN   
+    { BLOC_ALLC,     S_RECT4_SIZE       },  // ALLC
+    { BLOC_EBCCHS,   S_RECT4_SIZE       },  // EBCCHS 
+    { BLOC_NBCCHS,   S_RECT4_SIZE       },  // NBCCHS 
+    { BLOC_SMSCB,    BLOC_SMSCB_SIZE    },  // SMSCB
+    { BLOC_NP,       S_RECT4_SIZE       },  // NP  
+    { BLOC_EP,       S_RECT4_SIZE       },  // EP  
+    { BLOC_ADL,      S_RECT4_SIZE       },  // ADL
+    { BLOC_AUL,      S_RECT4_SIZE       },  // AUL                 
+    { BLOC_DDL,      S_RECT4_SIZE       },  // DDL
+    { BLOC_DUL,      S_RECT4_SIZE       },  // DUL     
+    { BLOC_TCHD,     BLOC_TCHT_SIZE     },  // TCHD
+    { BLOC_TCHA,     BLOC_TCHA_SIZE     },  // TCHA
+    { BLOC_TCHTF,    BLOC_TCHT_SIZE     },  // TCHTF
+    { BLOC_TCHTH,    BLOC_TCHT_SIZE     },  // TCHTH
+    { BLOC_BCCHN_TOP,BLOC_BCCHN_TOP_SIZE},  // BCCHN_TOP  
+    { BLOC_SYNCHRO,  BLOC_SYNCHRO_SIZE  }   // SYNCHRO
+  };
+
+  const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] =
+  {
+    CHECKSUM_DSP_TASK,// HWTEST 
+    0,                // DEDIC (not meaningfull)
+    0,                // ADC   (not meaningfull)
+    RACH_DSP_TASK,    // RAACC     
+    RACH_DSP_TASK,    // RAHO
+    0,                // NSYNC (not meaningfull)
+    FB_DSP_TASK,      // FBNEW    
+    SB_DSP_TASK,      // SBCONF
+    SB_DSP_TASK,      // SB2     
+    TCH_FB_DSP_TASK,  // FB26               
+    TCH_SB_DSP_TASK,  // SB26               
+    TCH_SB_DSP_TASK,  // SBCNF26               
+    FB_DSP_TASK,      // FB51               
+    SB_DSP_TASK,      // SB51               
+    SB_DSP_TASK,      // SBCNF51               
+    NBN_DSP_TASK,     // BCCHN         
+    ALLC_DSP_TASK,    // ALLC      
+    NBS_DSP_TASK,     // EBCCHS       
+    NBS_DSP_TASK,     // NBCCHS       
+    DDL_DSP_TASK,     // Temporary (BUG IN SIMULATOR)  CB_DSP_TASK,    // SMSCB
+    NP_DSP_TASK,      // NP        
+    EP_DSP_TASK,      // EP        
+    ADL_DSP_TASK,     // ADL     
+    AUL_DSP_TASK,     // AUL     
+    DDL_DSP_TASK,     // DDL     
+    DUL_DSP_TASK,     // DUL     
+    TCHD_DSP_TASK,    // TCHD 
+    TCHA_DSP_TASK,    // TCHA
+    TCHT_DSP_TASK,    // TCHTF
+    TCHT_DSP_TASK,    // TCHTH
+    NBN_DSP_TASK,     // BCCHN_TOP == BCCHN
+    0,                // SYNCHRO (not meaningfull)
+  };                
+#else
+  const T_TASK_MFTAB  TASK_ROM_MFTAB[NBR_DL_L1S_TASKS] =
+  {
+    { BLOC_HWTEST,       BLOC_HWTEST_SIZE  },       // HWTEST 
+    { BLOC_ADC,          BLOC_ADC_SIZE     },       // ADC in CS_MODE0
+    { NULL,              0                 },       // DEDIC   (not meaningfull)
+    { BLOC_RAACC,        BLOC_RAACC_SIZE   },       // RAACC                 
+    { NULL,              0                 },       // RAHO    (not meaningfull)
+    { NULL,              0                 },       // NSYNC   (not meaningfull)             
+    { BLOC_POLL ,        BLOC_POLL_SIZE    },       // POLL
+    { BLOC_PRACH,        BLOC_PRACH_SIZE   },       // PRACH  
+    { BLOC_ITMEAS,       BLOC_ITMEAS_SIZE  },       // ITMEAS 
+    { BLOC_FBNEW,        BLOC_FBNEW_SIZE   },       // FBNEW 
+    { BLOC_SBCONF,       BLOC_SBCONF_SIZE  },       // SBCONF 
+    { BLOC_SB2,          BLOC_SB2_SIZE     },       // SB2 
+    { BLOC_PTCCH,        BLOC_PTCCH_SIZE   },       // PTCCH  
+    { BLOC_FB26,         BLOC_FB26_SIZE    },       // FB26               
+    { BLOC_SB26,         BLOC_SB26_SIZE    },       // SB26
+    { BLOC_SBCNF26,      BLOC_SBCNF26_SIZE },       // SBCNF26
+    { BLOC_FB51,         BLOC_FB51_SIZE    },       // FB51               
+    { BLOC_SB51,         BLOC_SB51_SIZE    },       // SB51               
+    { BLOC_SBCNF51,      BLOC_SBCNF51_SIZE },       // SBCNF51
+    { BLOC_PDTCH,        BLOC_PDTCH_SIZE   },       // PDTCH   
+    { BLOC_BCCHN,        BLOC_BCCHN_SIZE   },       // BCCHN   
+    { BLOC_ALLC,         S_RECT4_SIZE      },       // ALLC
+    { BLOC_EBCCHS,       S_RECT4_SIZE      },       // EBCCHS 
+    { BLOC_NBCCHS,       S_RECT4_SIZE      },       // NBCCHS 
+    { BLOC_ADL,          S_RECT4_SIZE      },       // ADL
+    { BLOC_AUL,          S_RECT4_SIZE      },       // AUL                 
+    { BLOC_DDL,          S_RECT4_SIZE      },       // DDL
+    { BLOC_DUL,          S_RECT4_SIZE      },       // DUL     
+    { BLOC_TCHD,         BLOC_TCHT_SIZE    },       // TCHD
+    { BLOC_TCHA,         BLOC_TCHA_SIZE    },       // TCHA
+    { BLOC_TCHTF,        BLOC_TCHT_SIZE    },       // TCHTF
+    { BLOC_TCHTH,        BLOC_TCHT_SIZE    },       // TCHTH
+    { BLOC_PALLC,        BLOC_PCCCH_SIZE   },       // PALLC
+    { BLOC_SMSCB,        BLOC_SMSCB_SIZE   },       // SMSCB
+    { BLOC_PBCCHS,       BLOC_PBCCHS_SIZE  },       // PBCCHS
+    { BLOC_PNP,          BLOC_PCCCH_SIZE   },       // PNP
+    { BLOC_PEP,          BLOC_PCCCH_SIZE   },       // PEP
+    { BLOC_SINGLE,       BLOC_SINGLE_SIZE  },       // SINGLE        
+    { BLOC_PBCCHN_TRAN,  BLOC_PBCCHN_TRAN_SIZE },   // PBCCHN_TRAN   
+    { BLOC_PBCCHN_IDLE,  BLOC_PBCCHN_IDLE_SIZE },   // PBCCHN_IDLE   
+    { BLOC_BCCHN_TRAN,   BLOC_BCCHN_TRAN_SIZE },    // BCCHN_TRAN  
+    { BLOC_NP,           S_RECT4_SIZE      },       // NP  
+    { BLOC_EP,           S_RECT4_SIZE      },       // EP  
+    { BLOC_BCCHN_TOP,    BLOC_BCCHN_TOP_SIZE},      // BCCHN_TOP  
+    { BLOC_SYNCHRO,      BLOC_SYNCHRO_SIZE }        // SYNCHRO
+  };
+
+  const UWORD8 DSP_TASK_CODE[NBR_DL_L1S_TASKS] =
+  {
+    CHECKSUM_DSP_TASK,// HWTEST 
+    0,                // ADC   (not meaningfull)
+    0,                // DEDIC (not meaningfull)
+    RACH_DSP_TASK,    // RAACC     
+    RACH_DSP_TASK,    // RAHO
+    0,                // NSYNC  (not meaningfull)
+    0,                // POLL   (not meaningfull)
+    0,                // PRACH  (not meaningfull)
+    0,                // ITMEAS 
+    FB_DSP_TASK,      // FBNEW    
+    SB_DSP_TASK,      // SBCONF
+    SB_DSP_TASK,      // SB2     
+    PTCCHU_DSP_TASK,  // PTCCH  
+    TCH_FB_DSP_TASK,  // FB26               
+    TCH_SB_DSP_TASK,  // SB26               
+    TCH_SB_DSP_TASK,  // SBCNF26               
+    FB_DSP_TASK,      // FB51               
+    SB_DSP_TASK,      // SB51               
+    SB_DSP_TASK,      // SBCNF51               
+    0,                // PDTCH  (not meaningfull)
+    NBN_DSP_TASK,     // BCCHN         
+    ALLC_DSP_TASK,    // ALLC      
+    NBS_DSP_TASK,     // EBCCHS       
+    NBS_DSP_TASK,     // NBCCHS       
+    ADL_DSP_TASK,     // ADL     
+    AUL_DSP_TASK,     // AUL     
+    DDL_DSP_TASK,     // DDL     
+    DUL_DSP_TASK,     // DUL     
+    TCHD_DSP_TASK,    // TCHD 
+    TCHA_DSP_TASK,    // TCHA
+    TCHT_DSP_TASK,    // TCHTF
+    TCHT_DSP_TASK,    // TCHTH
+    0,                // PALLC  (not meaningfull)
+    DDL_DSP_TASK,     // Temporary (BUG IN SIMULATOR)  CB_DSP_TASK,    // SMSCB
+    DDL_DSP_TASK,     // PBCCHS (In order to allow PBCCHS running in CS or Idle mode, we have to specify a valid DSP task in order to request a PBCCHS with the GSM scheduler)
+    0,                // PNP    (not meaningfull)
+    0,                // PEP    (not meaningfull)
+    0,                // SINGLE (not meaningfull) 
+    0,                // PBCCHN_TRAN (not meaningfull)    
+    DDL_DSP_TASK,     // PBCCHN_IDLE (only for GSM scheduler the task used is the same as SMSCB task)
+    NBN_DSP_TASK,     // BCCHN_TRAN == BCCHN
+    NP_DSP_TASK,      // NP        
+    EP_DSP_TASK,      // EP        
+    NBN_DSP_TASK,     // BCCHN_TOP == BCCHN
+    0                 // SYNCHRO (not meaningfull)
+  };                
+
+#endif
+
+  const UWORD8 REPORTING_PERIOD[] =
+  {
+    255,            // INVALID_CHANNEL -> invalid reporting period
+    104,            // TCH_F              
+    104,            // TCH_H              
+    102,            // SDCCH_4            
+    102             // SDCCH_8            
+  }; 
+  
+  const UWORD8 TOA_PERIOD_LEN[] =
+  {
+    0,              // CS_MODE0 not used for histogram filling       
+    12,             // CS_MODE histogram length            
+    12,             // I_MODE histogram length            
+    12,             // CON_EST_MODE1 histogram length  
+   144,             // CON_EST_MODE2 histogram length      
+    36,             // DEDIC_MODE (Full rate) histogram length        
+    42              // DEDIC_MODE (Half rate) histogram length        
+    #if L1_GPRS
+      ,16           // PACKET TRANSFER MODE histogram length
+    #endif
+  }; 
+  
+ // #if (STD == GSM) 
+    const UWORD8 MIN_TXPWR_GSM[] =
+    {
+      0,  // unused.
+      0,  // Power class = 1, unused for GSM900
+      2,  // Power class = 2.
+      3,  // Power class = 3.
+      5,  // Power class = 4.
+      7   // Power class = 5.
+    };
+ // #elif (STD == PCS1900)
+    const UWORD8 MIN_TXPWR_PCS[] =
+    {
+      0,  // unused.
+      0,  // Power class = 1.
+      3,  // Power class = 2.
+     30   // Power class = 3.
+    };
+ // #elif (STD == DCS1800)
+    const UWORD8 MIN_TXPWR_DCS[] =
+    {
+      0,  // unused.
+      0,  // Power class = 1.
+      3,  // Power class = 2.
+     29   // Power class = 3.
+    };
+
+     const UWORD8 MIN_TXPWR_GSM850[] =
+    {
+      0,  // unused.
+      0,  // Power class = 1, unused for GSM900
+      2,  // Power class = 2.
+      3,  // Power class = 3.
+      5,  // Power class = 4.
+      7   // Power class = 5.
+    };
+
+//  #elif (STD == DUAL)
+ //   const UWORD8 MIN_TXPWR_GSM[] =
+ //  {
+ //     0,  // unused.
+ //     0,  // Power class = 1, unused for GSM900
+ //     2,  // Power class = 2.
+ //     3,  // Power class = 3.
+ //     5,  // Power class = 4.
+ //     7   // Power class = 5.
+ //   };
+ //   const UWORD8 MIN_TXPWR_DCS[] =
+ //   {
+ //     0,  // unused.
+ //     0,  // Power class = 1.
+ //     3,  // Power class = 2.
+ //    29   // Power class = 3.
+ //   };
+//  #endif
+
+const UWORD8 GAUG_VS_PAGING_RATE[] =
+{
+  4,   // bs_pa_mfrms = 2, 1 gauging every 4 Paging blocs
+  3,   // bs_pa_mfrms = 3, 1 gauging every 3 Paging blocs
+  2,   // bs_pa_mfrms = 4, 1 gauging every 2 Paging blocs
+  1,   // bs_pa_mfrms = 5, 1 gauging every 1 Paging bloc
+  1,   // bs_pa_mfrms = 6, 1 gauging every 1 Paging bloc
+  1,   // bs_pa_mfrms = 7, 1 gauging every 1 Paging bloc
+  1,   // bs_pa_mfrms = 8, 1 gauging every 1 Paging bloc
+  1    // bs_pa_mfrms = 9, 1 gauging every 1 Paging bloc
+};   
+  
+#else
+  extern T_IDLE_TASK_INFO IDLE_INFO_COMB[(MAX_AG_BLKS_RES_COMB+1) * (MAX_PG_BLOC_INDEX_COMB+1)];
+  extern T_IDLE_TASK_INFO IDLE_INFO_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1) * (MAX_PG_BLOC_INDEX_NCOMB+1)];
+  extern UWORD8           NBPCH_IN_MF51_NCOMB[(MAX_AG_BLKS_RES_NCOMB+1)];
+  extern UWORD8           NBPCH_IN_MF51_COMB[(MAX_AG_BLKS_RES_COMB+1)];
+  extern UWORD8           DSC_INIT_VALUE[MAX_BS_PA_MFRMS-2];
+  extern T_SDCCH_DESC     SDCCH_DESC_NCOMB[];
+  extern T_SDCCH_DESC     SDCCH_DESC_COMB[];
+  extern UWORD8           RNTABLE[114];
+  extern UWORD8           COMBINED_RA_DISTRIB[51];
+  extern T_TASK_MFTAB     TASK_ROM_MFTAB[NBR_DL_L1S_TASKS];
+  extern UWORD8           DSP_TASK_CODE[NBR_DL_L1S_TASKS];
+  extern UWORD8           REPORTING_PERIOD[];
+  extern UWORD8           TOA_PERIOD_LEN[];
+  extern UWORD8           MIN_TXPWR_GSM[];
+  extern UWORD8           MIN_TXPWR_DCS[];
+  extern UWORD8           MIN_TXPWR_PCS[];
+  extern UWORD8           MIN_TXPWR_GSM850[];
+  extern UWORD8           GAUG_VS_PAGING_RATE[];
+#endif
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_time.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_time.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,266 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software
+ * L1_TIME.H
+ *
+ *        Filename l1_time.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+// *********************************************************************
+// *                                                                   *
+// *        This file contains only RF independant defines.            *
+// *                                                                   *
+// *********************************************************************
+// Remarks:
+// --------
+// PRG_TX is RF dependant, it is therefore provided within
+// "l1_rf#.h".
+// **************************************************************************
+//
+// measurements
+// ------------
+//
+//                       |        +-----+
+//                       |        | PW  |
+//    -------------------|--------+     +--------------
+//                  clk=offset    |     |
+//                 (frame int.)  >|-----|<-PW_BURST_DURATION
+//                       |        |     |
+//    |      SYNTH_SETUP_TIME     |     |
+//    |<--------------------------|<    |
+//    |                  |        |
+//                       |        |
+//                      >|--------|<-PROVISION_TIME
+//
+//
+// Normal Burst reception
+// ----------------------
+//
+//                       |        +---------+
+//                       |        |  RX WIN |
+//  ---------------------|--------+         +----------
+//                  clk=offset    |         |
+//                 (frame int.)  >|---------|<-NB_BURST_DURATION_DL
+//                       |        |         |
+//    |      SYNTH_SETUP_TIME     |         |
+//    |<--------------------------|<        |
+//    |                  |        |
+//                       |        |
+//                      >|--------|<-PROVISION_TIME
+//
+//
+// Normal Burst transmission
+// -------------------------
+//
+//                            .
+//                            +---------+
+//                            |  TX WIN |
+//  --------------------------+         +----------
+//                            .         |
+//                       clk=offset     |
+//                            .         |
+//                            .         |<--STOP_TX_**
+//   |    SYNTH_SETUP_TIME    .
+//   |<---------------------->.<--START_TX
+//   |                        .
+//
+//
+//
+// Frequency Burst search in Dedicated TCH
+// ---------------------------------------
+//
+//                       .        +-----------(...)-------------+
+//                       .        |      FB search in TCH       |
+//    -------------------.--------+                             +--------------
+//                       .        |                             |
+//           (FB26_ANCHORING_TIME)|                             |
+//                       .        |                             |
+//            SYNTH_SETUP_TIME    |                             |
+//    |<------------------------->|                             |<-STOP_RX_FB26
+//                       .        |
+//                       .        |<-START_RX_FB26
+//                       .        |
+//                       .        |
+//                      >.--------|<-PROVISION_TIME
+//
+//
+// **************************************************************************
+
+
+#define D_NSUBB_IDLE         296L                                                    // Nb of 48 samples window for FBNEW task.
+#if (CODE_VERSION==SIMULATION)
+  #define D_NSUBB_DEDIC        31L                                                     // Nb of 48 samples window for FB26 task.
+#else
+  #if (DSP == 33) || (DSP == 34) || (DSP == 35) || (DSP == 32) || (DSP == 36)
+    #define D_NSUBB_DEDIC        30L                                                     // Nb of 48 samples window for FB26 task.
+  #else
+    #define D_NSUBB_DEDIC        31L                                                     // Nb of 48 samples window for FB26 task.
+  #endif
+#endif
+
+
+#define IMM                  ( 5000L )                                               // Immediate command for TPU.
+#define TN_WIDTH             ( 625L )
+#define BP_DURATION          TN_WIDTH
+#define TAIL_WIDTH           ( 3L * 4L )                                             // = 12
+#define EXTENDED_TAIL_WIDTH  ( 8L * 4L )
+#define TPU_CLOCK_RANGE      ( 5000L )
+#define SWITCH_TIME          ( TPU_CLOCK_RANGE - EPSILON_SYNC )                      // = 4990, time for offset change.
+
+#define PROVISION_TIME       ( 66L )
+#define EPSILON_SYNC         ( 10L )                                                 // synchro change: max TOA shift=8qbits, 2qbits TPU scenario exec.
+#define EPSILON_OFFS         (  2L )                                                 // offset change: 2qbits for TPU scenario exec.
+#define EPSILON_MEAS         ( 20L )                                                 // margin kept between RX and PW meas or between PW meas
+#define SERV_OFFS_REST_LOAD  (  1L )                                                 // 1qbit TPU scen exec. for serv. cell offset restore
+#define TPU_SLEEP_LOAD       (  2L )                                                 // 2qbit TPU scen exec. for TPU sleep
+#if (CODE_VERSION==SIMULATION)
+  #define DL_ABB_DELAY         ( 32L )                                             // RX ABB filter delay
+#else
+  #define DL_ABB_DELAY         ( 32L + 4L)                                         // RX ABB filter delay
+#endif
+
+// DMA threshold used for sample acquisition by the DSP
+#if (CODE_VERSION==SIMULATION)
+  #define RX_DMA_THRES       (  1L )
+#else
+  #if (CHIPSET == 4) || (CHIPSET == 7)  || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
+    #define RX_DMA_THRES       (  2L )
+  #else
+    #define RX_DMA_THRES       (  1L )
+  #endif
+#endif
+
+// BDLENA durations are calculated for a DMA threshold of 1
+// For a DMA threshold > 1 additional I/Q samples have to be acquired
+// An increase of BDLENA length by 2qbit is sufficient to acquire one additional I/Q sample
+// (ABB always outputs pairs of I/Q samples)
+#define RX_DMA_DELAY  (RX_DMA_THRES - 1) * 2
+
+#if (CODE_VERSION==SIMULATION)
+  #define TULSET_DURATION    ( 16L )                                                 // Uplink power on setup time
+  #define BULRUDEL_DURATION  ( 2L )
+  #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+     // 16 qbits are added because the Calibration time is reduced of 4 GSM bit
+     // due to a slow APC ramp of OMEGA (Cf. START_TX_NB)
+     #define UL_VEGA_DELAY      ( TULSET_DURATION + BULRUDEL_DURATION +16L )         // = 18qbits, TX Vega delay
+   #endif
+#endif
+
+#define SB_MARGIN            ( 23L * 4L )                                            // = 92
+#define NB_MARGIN            (  3L * 4L )                                            // = 12
+#define TA_MAX               ( 63L * 4L )                                            // = 252
+
+#define SB_BURST_DURATION    ( TAIL_WIDTH + ( 142L * 4L) )                           // = 580, required for Demodulation
+#define NB_BURST_DURATION_DL ( TAIL_WIDTH + ( 142L * 4L) )                           // = 580, required for Demodulation
+#define PW_BURST_DURATION    ( 64L * 4L )                                            // = 256
+#define RA_BURST_DURATION    ( EXTENDED_TAIL_WIDTH + TAIL_WIDTH + ( 77L * 4L ) )     // = 352 = 88*4
+#define NB_BURST_DURATION_UL ( 2*TAIL_WIDTH + ( 142L * 4L) )                         // = 592 = 148 * 4
+
+// PRG_TX has become a variable and will be substracted directly in the code
+#define TIME_OFFSET_TX       ( PROVISION_TIME + (3L * TN_WIDTH))                  // = 1902, Offset difference for TX with TA=0.
+
+//================================
+// Definitions used by TPU drivers
+//================================
+
+// BENA durations...
+//------------------
+#define SB_ACQUIS_DURATION   ( SB_MARGIN + SB_BURST_DURATION + SB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY )    // = 796 + DMA delay
+#define NB_ACQUIS_DURATION   ( NB_MARGIN + NB_BURST_DURATION_DL + NB_MARGIN + DL_ABB_DELAY + RX_DMA_DELAY ) // = 636 + DMA delay
+#define PW_ACQUIS_DURATION   ( PW_BURST_DURATION + DL_ABB_DELAY + RX_DMA_DELAY )                            // = 288 + DMA delay
+#define FB_ACQUIS_DURATION   ( ( D_NSUBB_IDLE  * 48L * 4L ) + ( 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY )  // = 57056 + DMA delay
+#define FB26_ACQUIS_DURATION ( ( D_NSUBB_DEDIC * 48L * 4L ) + DL_ABB_DELAY + RX_DMA_DELAY)                 // = 5984 + DMA delay
+
+#define START_RX_FB          ( PROVISION_TIME )                                                // = 66
+#define START_RX_SB          ( PROVISION_TIME )                                                // = 66
+#define START_RX_SNB         ( PROVISION_TIME )                                                // = 66
+#define START_RX_PW_1        ( PROVISION_TIME )                                                // = 66
+#define START_RX_FB26        ( PROVISION_TIME )                                                // = 66
+
+#define START_TX_NB          ( 0L )
+#define START_TX_RA          ( 0L )
+
+#define STOP_RX_FB           ( (PROVISION_TIME + FB_ACQUIS_DURATION)   % TPU_CLOCK_RANGE )       // = 2122
+#define STOP_RX_SB           ( (START_RX_SB    + SB_ACQUIS_DURATION)   % TPU_CLOCK_RANGE )       // = 862
+#define STOP_RX_SNB          ( (START_RX_SNB   + NB_ACQUIS_DURATION)   % TPU_CLOCK_RANGE )       // = 702
+#define STOP_RX_PW_1         ( (START_RX_PW_1  + PW_ACQUIS_DURATION)   % TPU_CLOCK_RANGE )       // = 354
+#define STOP_RX_FB26         ( (START_RX_FB26  + FB26_ACQUIS_DURATION) % TPU_CLOCK_RANGE )     // = 4314
+
+
+//================================
+// Definitions used for GPRS
+//================================
+
+#if L1_GPRS
+  #ifdef L1P_DRIVE_C
+
+    // Window positions for RX normal burst reception durations
+    const UWORD16 RX_DOWN_TABLE[8] =
+    {
+      PROVISION_TIME + NB_ACQUIS_DURATION,             //special case: only 1 RX, 151 IQ samples
+      PROVISION_TIME + 2*BP_DURATION + DL_ABB_DELAY,  // 2 * 156.25 samples
+      PROVISION_TIME + 3*BP_DURATION + DL_ABB_DELAY,  // 3 * 156.25 samples
+      PROVISION_TIME + 4*BP_DURATION + DL_ABB_DELAY,  // 4 * 156.25 samples
+      PROVISION_TIME + 5*BP_DURATION + DL_ABB_DELAY,  // 5 * 156.25 samples
+      PROVISION_TIME + 6*BP_DURATION + DL_ABB_DELAY,  // 6 * 156.25 samples
+      PROVISION_TIME + 7*BP_DURATION + DL_ABB_DELAY,  // 7 * 156.25 samples
+      PROVISION_TIME + 8*BP_DURATION + DL_ABB_DELAY   // 8 * 156.25 samples
+    };
+
+    // Window positions for TX normal burst and PRACH transmission
+    const UWORD16 TX_TABLE[8] =
+    {
+      0,
+        BP_DURATION,
+      2*BP_DURATION,
+      3*BP_DURATION,
+      4*BP_DURATION,
+      5*BP_DURATION,
+      6*BP_DURATION,
+      7*BP_DURATION
+    };
+
+  #else
+
+    extern UWORD16 RX_DOWN_TABLE[8];
+    extern UWORD16 TX_TABLE[8];
+
+  #endif
+#endif
+
+//===============================================
+// New Definitions for new WIN-ID implementation
+//===============================================
+
+#define  BP_SPLIT_PW2                  5
+#define  BP_SPLIT                     32
+#define  FRAME_SPLIT          8*BP_SPLIT
+
+// Load for TPU activity according to frame split
+#define  PWR_LOAD    1 + PW_ACQUIS_DURATION / (BP_DURATION/BP_SPLIT)
+#define  RX_LOAD     1 + NB_ACQUIS_DURATION / (BP_DURATION/BP_SPLIT)
+
+#if L1_GPRS
+  #ifdef L1P_DRIVE_C
+
+    // RX split load in case of multislot
+    const UWORD16 RX_SPLIT_TABLE[8] =
+    {
+      1 + (NB_ACQUIS_DURATION           ) / (BP_DURATION/BP_SPLIT),
+      1 + (2*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
+      1 + (3*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
+      1 + (4*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
+      1 + (5*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
+      1 + (6*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
+      1 + (7*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT),
+      1 + (8*BP_DURATION + DL_ABB_DELAY) / (BP_DURATION/BP_SPLIT)
+    };
+
+  #else
+
+    extern UWORD16 RX_SPLIT_TABLE[8];
+
+  #endif
+#endif
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_trace.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_trace.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,6713 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software
+ * L1_TRACE.H
+ *
+ *        Filename l1_trace.h
+ *  Copyright 2003 (C) Texas Instruments
+ *
+ ************* Revision Controle System Header *************/
+
+
+#ifndef __L1_TRACE_H__
+#define __L1_TRACE_H__
+
+#include "rvt_gen.h"
+#include <string.h>
+
+#if (defined RVM_RTT_SWE || (OP_L1_STANDALONE == 1))
+#include "rtt_gen.h"
+#endif
+
+#define L1_BINARY_TRACE 0
+
+/********************/
+/* Main definitions */
+/********************/
+
+#define TR_HEADER_FN_DELAY 10            // Delay applied to store the FN in the trace cell header
+#define TR_HEADER_ID_MASK  0x000003FF    // Mask on the cell ID stored in the cell header
+
+// Opcodes for communication with L1 Tracer
+//-----------------------------------------
+
+#define TRACE_CONFIG_OPCODE   0
+#define TRACE_CHECKING_OPCODE 1
+
+#define TRACE_CHECK_RESULT_OPCODE 1023 // WARNING: UL opcode 1023 reseved for trace version
+                                       // (cannot be used for trace)
+
+/****************************** ASCII trace only *****************************************/
+
+#if (L1_BINARY_TRACE == 0) || (TRACE_TYPE == 5)
+  #if (OP_L1_STANDALONE == 1)
+    #define DEFAULT_DYN_TRACE_CONFIG       0x00000A67
+  #elif (OP_WCP == 1)
+    // WCP patch: default config is no Layer1 trace
+    #define DEFAULT_DYN_TRACE_CONFIG       0x00000000  // default was 0x00000BB7
+    // End WCP patch
+  #else  
+    #define DEFAULT_DYN_TRACE_CONFIG       0x00000BB7
+  #endif
+
+  // Possible EVENTS for L1S traces using TRACE_INFO.
+  //-------------------------------------------------
+
+  #define PM_EQUAL_0              1
+  #define NO_PM_EQUAL_0           2
+  #define MCU_DSP_MISMATCH        3
+  #define NO_MCU_DSP_MISMATCH     4
+  #define L1S_ABORT               5
+  #define L1S_PACKET_TRANSFER     6
+  #define L1S_RLC_STAT            7
+  #define DL_PTCCH                8
+  #define L1S_D_ERROR_STATUS      9
+  #define TRACE_CPU_LOAD         10 // Only works with TRACE_TYPE 7
+  #define RLC_DL_PARAM           11
+  #define RLC_UL_PARAM           12
+  #define FORBIDDEN_UPLINK       13
+  #define DYN_TRACE_CHANGE       14 // Currently only work with TRACE_TYPE 4
+  #define TRACE_SLEEP            15
+  #define TRACE_GAUGING_RESET    16
+  #define TRACE_GAUGING          17
+  #define NEW_TOA                18
+  #define TOA_NOT_UPDATED        19
+  #define IT_DSP_ERROR           20
+  #define TRACE_ADC              21
+  #define PTCCH_DISABLED         22
+  #define DYN_TRACE_DEBUG        23 // Currently only work with TRACE_TYPE 4
+  #define DEDIC_TCH_BLOCK_STAT   24
+  #define TRACE_RATSCCH          25
+
+  // Wakeup Type for Power management
+  //--------------------------------
+  #define WAKEUP_FOR_UNDEFINED       0
+  #define WAKEUP_FOR_L1_TASK         1
+  #define WAKEUP_FOR_OS_TASK         2
+  #define WAKEUP_FOR_HW_TIMER_TASK   3
+  #define WAKEUP_FOR_GAUGING_TASK    4
+  #define WAKEUP_BY_ASYNC_INTERRUPT  5
+  #define WAKEUP_ASYNCHRONOUS_ULPD_0           6
+  #define WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0 7
+
+  // Big Sleep source for Power management
+  //-------------------------------------
+  #define BIG_SLEEP_DUE_TO_UNDEFINED  0  // deep sleep is forbiden : cause undefined
+  #define BIG_SLEEP_DUE_TO_LIGHT_ON   1  // deep sleep is forbiden by ligth on activitie
+  #define BIG_SLEEP_DUE_TO_UART       2  // deep sleep is forbiden by UART activitie
+  #define BIG_SLEEP_DUE_TO_SIM        3  // deep sleep is forbiden by SIM activitie
+  #define BIG_SLEEP_DUE_TO_GAUGING    4  // deep sleep is forbiden by not enought gauging
+  #define BIG_SLEEP_DUE_TO_SLEEP_MODE 5  // deep sleep is forbiden by the sleep mode enabled
+  #define BIG_SLEEP_DUE_TO_DSP_TRACES 6  // deep sleep is forbiden by the DSP
+  #define BIG_SLEEP_DUE_TO_BLUETOOTH  7  // deep sleep is forbiden by the Bluetooth module
+
+  void  Trace_Packet_Transfer      (UWORD8  prev_crc_error); // Previous RX blocks CRC_ERROR summary
+  void  l1_display_buffer_trace_fct(void);
+
+ //===================================================
+ //=========== BUFFER TRACE ==========================
+ //===================================================
+
+// buffer size
+#define TRACE_FCT_BUFF_SIZE 40
+
+////////////////
+// fonctions id
+/////////////////
+
+// fonction name to display
+#ifdef L1_TRACE_C
+
+  #if (TRACE_TYPE==5) || TRACE_FULL_NAME
+  const char string_fct_trace[][35]={
+
+    // L1S_CTRL_XXXXX
+    "l1s_ctrl_ADC()",
+    "l1s_ctrl_msagc()",
+    "l1s_ctrl_sb2()",
+    "l1s_ctrl_sb26()",
+    "l1s_ctrl_sb51()",
+    "l1s_ctrl_sbconf()",
+    "l1s_ctrl_sbcnf26()",
+    "l1s_ctrl_sbcnf51()",
+    "l1s_ctrl_fb()",
+    "l1s_ctrl_fb26()",
+    "l1s_ctrl_smscb()",
+    "l1s_ctrl_snb_dl()",
+    "l1s_ctrl_snb_dl(burst 0)",
+    "l1s_ctrl_snb_dl(burst 1)",
+    "l1s_ctrl_snb_dl(burst 2)",
+    "l1s_ctrl_snb_dl(burst 3)",
+    "l1s_ctrl_snb_ul()",
+    "l1s_ctrl_nnb()",
+    "l1s_ctrl_rach()",
+    "l1s_ctrl_tcht_dummy(DL)",
+    "l1s_ctrl_tchth(DL)",
+    "l1s_ctrl_tchth(UL)",
+    "l1s_ctrl_tcha(DL)",
+    "l1s_ctrl_tcha(UL)",
+    "l1s_ctrl_tchtf(DL)",
+    "l1s_ctrl_tchtf(UL)",
+
+    // L1PS_CTRL_XXXXX
+    "l1ps_ctrl_poll()",
+    "l1ps_ctrl_snb_dl",
+    "l1ps_ctrl_single()",
+    "l1ps_ctrl_pbcchs()",
+    "l1ps_ctrl_pbcchn()",
+    "l1ps_ctrl_itmeas()",
+    "l1ps_ctrl_pdtch",
+    "l1ps_ctrl_pdtch(UL)",
+    "l1ps_ctrl_pdtch(DL)",
+    "l1ps_ctrl_pdtch(DL burst0)",
+    "l1ps_ctrl_pdtch(DL burst1)",
+    "l1ps_ctrl_pdtch(DL burst2)",
+    "l1ps_ctrl_pdtch(DL burst3)",
+    "l1ps_ctrl_pdtch(RA)",
+    "l1ps_ctrl_pdtch(dummy)",
+    "l1ps_ctrl_ptcch(UL)",
+    "l1ps_ctrl_ptcch(empty)",
+    "l1ps_ctrl_ptcch(DL burst0)",
+    "l1ps_ctrl_ptcch(DL burst1)",
+    "l1ps_ctrl_ptcch(DL burst2)",
+    "l1ps_ctrl_ptcch(DL burst3)",
+
+     // others CTRL
+    "ctrl_cr_meas",
+    "ctrl_i_ba_meas",
+    "ctrl_d_ba_meas",
+    "ctrl_tcr_meas_1",
+    "ctrl_tcr_meas_2",
+    "ctrl_pc_meas_chan",
+    "ctrl_transfer_meas",
+    "ctrl_full_list_meas",
+    "ctrl_Scell_transfer_meas",
+
+     // L1S_READ_XXXXX
+    "l1s_read_ra()",
+    "l1s_read_nnb",
+    "l1s_read_snb_dl",
+    "l1s_read_tx_nb(DUL)",
+    "l1s_read_tx_nb(AUL)",
+    "l1s_read_tx_nb(TCHF)",
+    "l1s_read_tx_nb(TCHH)",
+    "l1s_read_fb()",
+    "l1s_read_fb51()",
+    "l1s_read_fb26()",
+    "l1s_read_sb()",
+    "l1s_read_sbconf()",
+    "l1s_read_l3frm(CB)",
+    "l1s_read_l3frm(NP)",
+    "l1s_read_l3frm(EP)",
+    "l1s_read_l3frm(ALLC)",
+    "l1s_read_l3frm(NBCCHS)",
+    "l1s_read_l3frm(EBCCHS)",
+    "l1s_read_l3frm(BCCHN)",
+    "l1s_read_sacch_dl(ADL)",
+    "l1s_read_sacch_dl(TCHA)",
+    "l1s_read_dcch_dl(DDL)",
+    "l1s_read_dcch_dl(TCHTF)",
+    "l1s_read_dcch_dl(TCHTH)",
+    "l1s_read_dedic_dl",
+    "l1s_read_mon_result",
+    "l1s_read_dummy",
+    "l1s_read_msagc()",
+
+     // L1PS_READ_XXXXX
+    "l1ps_read_nb_dl",
+    "l1ps_read_itmeas()",
+    "l1ps_read_single",
+    "l1ps_read_single_dummy",
+    "l1ps_read_l3frm(PNP)",
+    "l1ps_read_l3frm(PEP)",
+    "l1ps_read_l3frm(PALLC)",
+    "l1ps_read_l3frm(PBCCHS)",
+    "l1ps_read_l3frm(PBCCHN)",
+    "l1ps_read_l3frm(SINGLE)",
+    "l1ps_read_l3frm(?)",
+    "l1ps_read_pra()",
+    "l1ps_read_poll()",
+    "  l1ps_read_pdtch()",
+    "l1ps_read_pdtch(burst)",
+    "l1ps_read_ptcch(DL)",
+    "l1ps_read_ptcch(UL)",
+
+     // others READ
+    "read_cr_meas",
+    "read_tcr_meas",
+    "read_i_ba_meas",
+    "read_d_ba_meas",
+    "read_pc_meas_chan",
+    "read_full_list_meas",
+
+    // miscellaneous
+    "SYNCHRO...",
+    "L1S_ABORT...",
+    "L1S_ABORT(PAGE:R0 W0)",
+    "unknown_fb()",
+    "STI PASSED...",
+    "task KILLED...",
+    "ALLOC EXHAUSTION",
+    "UL task does not correspond",
+    "DL task does not correspond",
+    "DL burst does not correspond",
+    "=>NEW_FRAME(PAGE:R0 W0)",
+    "=>NEW_FRAME(PAGE:R0 W1)",
+    "=>NEW_FRAME(PAGE:R1 W0)",
+    "=>NEW_FRAME(PAGE:R1 W1)",
+    "l1dmacro_synchro",
+    "tx_tch_data()",
+    "dll_read_dcch()",
+    "dll_read_sacch()",
+    "Time adjustment",
+  };
+
+  #endif
+#endif // L1_TRACE_C
+
+
+ //===================================================
+ //=========== BUFFER TRACE END ======================
+ //===================================================
+
+ #if (OP_L1_STANDALONE == 0)
+   // Dynamic trace: message content
+   //-------------------------------
+   #define DYN_TRACE_0    0
+   #define DYN_TRACE_1    1
+   #define DYN_TRACE_2    2
+   #define DYN_TRACE_3    3  
+   #define DYN_TRACE_4    4  
+   #define DYN_TRACE_5    5  
+   #define DYN_TRACE_6    6  
+   #define DYN_TRACE_7    7  
+   #define DYN_TRACE_8    8
+   #define DYN_TRACE_9    9  
+   #define DYN_TRACE_10   10
+   #define DYN_TRACE_11   11
+   #define DYN_TRACE_12   12
+   #define DYN_TRACE_13   13
+   #define DYN_TRACE_14   14
+   #define DYN_TRACE_15   15
+   #define DYN_TRACE_16   16
+ #endif
+
+/****************************** Binary trace only *****************************************/
+
+#else
+  #define DEFAULT_DYN_TRACE_CONFIG       0x000007a7
+#endif
+
+
+/***********************************************************/
+/* Trace structures                                        */
+/***********************************************************/
+
+// Trace version
+typedef struct
+{
+  UWORD32 Opcode;
+  UWORD32 checksum;
+  UWORD16 version;
+}
+T_TRACE_VERSION;
+
+// Condensed trace structure definition
+typedef struct
+{
+  BOOL   blk_status;
+  UWORD8 dl_cs_type;
+  UWORD8 dl_status[8];
+  UWORD8 ul_status[8];
+} T_PDTCH_TRACE;
+
+
+#if (defined RVM_RTT_SWE || (OP_L1_STANDALONE == 1))
+// L1S trace function pointers
+typedef struct
+{
+  T_RTT_RET (*rtt_refresh_status) (T_RTT_USER_ID  user_id);
+
+  T_RTT_PTR (*rtt_get_fill_ptr)   (T_RTT_USER_ID  user_id,
+                                   T_RTT_SIZE     size);
+
+  T_RTT_RET (*rtt_dump_buffer)    (T_RTT_USER_ID  user_id,
+                                   T_RTT_SIZE     dump_size);
+} T_L1S_TRACE_FUNC;
+#endif
+
+
+// L1S trace buffer size
+#define L1S_RTT_BUF_LENGTH 1000
+
+// Trace configuration
+typedef struct
+{
+  UWORD32   l1_dyn_trace;
+  UWORD32   rttl1_cell_enable[8];
+  UWORD32   rttl1_event_enable;
+} T_TRACE_CONFIG;
+
+// Debug info structure
+typedef struct
+{
+  // User IDs
+  T_RVT_USER_ID       l1_trace_user_id;
+#if (defined RVM_RTT_SWE || (OP_L1_STANDALONE == 1))
+  T_RTT_USER_ID       l1s_trace_user_id;
+#endif
+
+  UWORD8    PM_equal_0;
+  UWORD8    PM_Task;
+  UWORD8    Not_PM_Task;
+
+  UWORD8    DSP_misaligned;
+
+  UWORD8    facch_dl_count;
+  UWORD8    facch_ul_count;
+  UWORD8    facch_dl_fail_count;
+  UWORD8    facch_dl_fail_count_trace;
+
+  UWORD8    sacch_d_nerr;
+
+  UWORD8    rxlev_req_count;
+  BOOL      init_trace;
+  UWORD8    abort_task;
+
+#if (L1_BINARY_TRACE == 0)
+  UWORD8    l1_memorize_error;
+
+  UWORD8    trace_fct_buff[TRACE_FCT_BUFF_SIZE];
+  UWORD8    trace_fct_buff_index;
+  BOOL      trace_buff_stop;
+  BOOL      trace_filter;
+#endif
+
+  BOOL      sleep_performed;
+  UWORD8    reset_gauging_algo;
+
+#if L1_GPRS
+  BOOL          new_tcr_list;
+  T_PDTCH_TRACE pdtch_trace;
+#endif
+
+#if L1_GTT
+  T_RVT_USER_ID  gtt_trace_user_id;
+#endif
+
+#if (D_ERROR_STATUS_TRACE_ENABLE)
+  // define a mask array for handling of the d_error_status field
+  UWORD16 d_error_status_masks[2];
+  API     d_error_status_old;
+#endif
+
+#if (DSP_DEBUG_TRACE_ENABLE == 1)
+  // Variable used to flag a DSP error, COM mismatch or PM=0 occured
+  // Array x 2 --> double buffered
+  // Contains 0 if no error / DSP trace start address if an error occured
+  UWORD16 dsp_debug_buf_start[2];
+  UWORD32 dsp_debug_fn[2];
+  UWORD16 dsp_debug_time[2];
+  UWORD32 fn_last_dsp_debug;
+#endif
+
+  // RTT
+#if (defined RVM_RTT_SWE || (OP_L1_STANDALONE == 1))
+  T_L1S_TRACE_FUNC l1s_rtt_func;
+  UWORD8           l1s_trace_buf[L1S_RTT_BUF_LENGTH];
+#endif
+  UWORD32          task_bitmap[8];
+  UWORD32          mem_task_bitmap[8];
+
+  // Dynamic trace
+  T_TRACE_CONFIG   config[2];
+  T_TRACE_CONFIG   *current_config;
+  T_TRACE_CONFIG   *pending_config;
+}
+T_TRACE_INFO_STRUCT;
+
+extern T_TRACE_INFO_STRUCT trace_info;
+
+
+/***********************/
+/* Function prototypes */
+/***********************/
+
+void  l1_trace_init              ();
+void  Trace_L1s_Abort            (UWORD8 task);
+void  Trace_MCU_DSP_Com_Mismatch (UWORD8 task);
+void  Trace_PM_Equal_0           (UWORD32 pm, UWORD8 task);
+void  Trace_rlc_ul_param         (UWORD8  assignment_id,
+                                  UWORD8  tx_no,
+                                  UWORD32 fn,
+                                  UWORD8  ta,
+                                  UWORD32 a_pu_gprs,
+                                  UWORD32 a_du_gprs,
+                                  BOOL    fix_alloc_exhaust);
+void  Trace_rlc_dl_param         (UWORD8  assignment_id,
+                                  UWORD32 fn,
+                                  UWORD32 d_rlcmac_rx_no_gprs,
+                                  UWORD8  rx_no,
+                                  UWORD8  rlc_blocks_sent,
+                                  UWORD8  last_poll_response);
+void  Trace_uplink_no_TA         ();
+void  Trace_condensed_pdtch      (UWORD8  rx_allocation, UWORD8 tx_allocation);
+void  Trace_dl_ptcch             (UWORD8 ordered_ta,
+                                  UWORD8 crc,
+                                  UWORD8 ta_index,
+                                  UWORD8 ts,
+                                  UWORD16 elt1,
+                                  UWORD16 elt2,
+                                  UWORD16 elt3,
+                                  UWORD16 elt4,
+                                  UWORD16 elt5,
+                                  UWORD16 elt6,
+                                  UWORD16 elt7,
+                                  UWORD16 elt8
+                                 );
+
+void  Trace_d_error_status       ();
+void  Trace_dsp_debug            ();
+#if (AMR == 1)
+  void Trace_dsp_amr_debug       (void);
+#endif
+void  Trace_params               (UWORD8   debug_code,
+                                  UWORD32  param0,
+                                  UWORD32  param1,
+                                  UWORD32  param2,
+                                  UWORD32  param3,
+                                  UWORD32  param4,
+                                  UWORD32  param5,
+                                  UWORD32  param6);
+void  Trace_L1S_CPU_load         ();
+void  Trace_dyn_trace_change     ();
+
+#if (AMR == 1)
+void  l1_trace_ratscch           (UWORD16 fn, UWORD16 amr_change_bitmap);
+#endif
+
+void  l1_trace_sleep             (UWORD32 start_fn,
+                                  UWORD32 end_fn,
+                                  UWORD8 type_sleep,
+                                  UWORD8 wakeup_type,
+                                  UWORD8 big_sleep_type);
+void  l1_trace_gauging_reset     (void);
+void  l1_trace_gauging           (void);
+void  l1_trace_new_toa           (void);
+void  l1_trace_toa_not_updated   (void);
+void  l1_trace_IT_DSP_error      (void);
+void  l1_trace_ADC               (UWORD8 type);
+void  l1_check_com_mismatch      (UWORD8 task);
+void  l1_check_pm_error          (UWORD32 pm,UWORD8 task);
+void  Trace_PM_Equal_0_balance   (void);
+void  l1_trace_ptcch_disable     (void);
+void trace_fct                   (UWORD8 fct_id, WORD32 radio_freq);
+
+/****************/
+/* Trace macros */
+/****************/
+
+#if (CODE_VERSION != SIMULATION)
+#define GTT_send_trace_cpy(s)    rvt_send_trace_cpy    ((T_RVT_BUFFER)s, trace_info.gtt_trace_user_id, strlen(s), RVT_ASCII_FORMAT)
+#define GTT_send_trace_no_cpy(s) rvt_send_trace_no_cpy ((T_RVT_BUFFER)s, trace_info.gtt_trace_user_id, strlen(s), RVT_ASCII_FORMAT)
+#else
+  void GTT_send_trace_cpy(char *s);
+#endif
+
+/***********************************************************/
+/* Trace data (parsed by the decoder)                      */
+/***********************************************************/
+
+// Trace version
+//--------------
+
+#define L1_TRACE_VERSION 5
+
+// Dynamic traces
+//---------------
+
+//TRACE_CONF/
+#define L1_DYN_TRACE_L1A_MESSAGES      0 //NAME/ L1A messages
+#define L1_DYN_TRACE_L1S_DEBUG         1 //NAME/ L1S errors
+#define L1_DYN_TRACE_DSP_DEBUG         2 //NAME/ DSP debug trace
+#define L1_DYN_TRACE_RLC_PARAM         3 //NAME/ RLC parameters
+#define L1_DYN_TRACE_UL_NO_TA          4 //NAME/ Uplink while no TA
+#define L1_DYN_TRACE_DL_PTCCH          5 //NAME/ DL PTCCH blocks
+#define L1_DYN_TRACE_CONDENSED_PDTCH   7 //NAME/ PDTCH UL + DL
+#define L1_DYN_TRACE_L1S_CPU_LOAD      8 //NAME/ L1S CPU load peaks
+#define L1_DYN_TRACE_ULPD              9 //NAME/ ULPD
+#define L1_DYN_TRACE_FULL_LIST_REPORT 10 //NAME/ Full list report
+#define L1_DYN_TRACE_GTT              11 //NAME/ GTT trace
+#define L1_DYN_TRACE_DSP_AMR_DEBUG    12 //NAME/ DSP AMR debug trace
+#if(L1_DYN_DSP_DWNLD == 1)
+ #define L1_DYN_TRACE_DYN_DWNLD       13 //NAME/ DYN DWNLD trace
+#endif // L1_DYN_DSP_DWNLD == 1
+#define L1_DYN_TRACE_GAUGING          14 //NAME/ Gauging parameters 
+//END_TRACE_CONF/
+
+#define L1_DYN_TRACE_DL_PDTCH_CRC      6 // DL PDTCH blocks CRC, only used if L1_BINARY_TRACE == 0
+
+// L1 RTT event definitions
+//-------------------------
+
+//RTT_EVENTS/
+#define RTTL1_EVENT_FNMOD13_EQUAL_12                         0 //NAME/ Every FN%13 = 12
+#define RTTL1_EVENT_ERROR                                    1 //NAME/ When error occurs
+//END_RTT_EVENTS/
+
+// Buffer length for each event
+#define RTTL1_EVENT_SIZE_FNMOD13_EQUAL_12   L1S_RTT_BUF_LENGTH  // All buffer is traced because it's a regular trace
+#define RTTL1_EVENT_SIZE_ERROR              L1S_RTT_BUF_LENGTH
+
+// Measurement codes used in trace
+//--------------------------------
+
+//MEAS_ID/
+#define FULL_LIST_MEAS_ID   200 //NAME/ Full list meas
+#define I_BA_MEAS_ID        201 //NAME/ Idle BA list meas
+#define D_BA_MEAS_ID        202 //NAME/ Dedicated BA list meas
+#define MS_AGC_ID           203 //NAME/ AGC setting meas
+#define CR_MEAS_ID          204 //NAME/ CR meas
+#define TCR_MEAS_ID         205 //NAME/ Packet transfer CR meas
+#define PC_MEAS_CHAN_ID     206 //NAME/ Beacon meas
+//END_MEAS_ID/
+
+// Trace tables
+//-------------
+
+//TABLE/ RRBP
+#define RRBP_BLOCK1   0 //NAME/ N+1
+#define RRBP_BLOCK2   1 //NAME/ N+2
+#define RRBP_BLOCK3   2 //NAME/ N+3
+#define RRBP_BLOCK4   3 //NAME/ N+4
+//END_TABLE/
+
+//TABLE/ DL CS
+#define DL_CS1   0 //NAME/ CS1
+#define DL_CS2   1 //NAME/ CS2
+#define DL_CS3   2 //NAME/ CS3
+#define DL_CS4   3 //NAME/ CS4
+//END_TABLE/
+
+//TABLE/ MFTAB
+#define CST_L1S_CTRL_ADC                    0  //NAME/ l1s_ctrl_ADC()
+#define CST_L1S_CTRL_MSAGC                  1  //NAME/ l1s_ctrl_msagc()
+#define CST_L1S_CTRL_SB2                    2  //NAME/ l1s_ctrl_sb2()
+#define CST_L1S_CTRL_SB26                   3  //NAME/ l1s_ctrl_sb26()
+#define CST_L1S_CTRL_SB51                   4  //NAME/ l1s_ctrl_sb51()
+#define CST_L1S_CTRL_SBCONF                 5  //NAME/ l1s_ctrl_sbconf()
+#define CST_L1S_CTRL_SBCNF26                6  //NAME/ l1s_ctrl_sbcnf26()
+#define CST_L1S_CTRL_SBCNF51                7  //NAME/ l1s_ctrl_sbcnf51()
+#define CST_L1S_CTRL_FB                     8  //NAME/ l1s_ctrl_fb()
+#define CST_L1S_CTRL_FB26                   9  //NAME/ l1s_ctrl_fb26()
+#define CST_L1S_CTRL_SMSCB                 10  //NAME/ l1s_ctrl_smscb()
+#define CST_L1S_CTRL_SNB_DL                11  //NAME/ l1s_ctrl_snb_dl()
+#define CST_L1S_CTRL_SNB_DL_BURST0         12  //NAME/ l1s_ctrl_snb_dl(burst 0)
+#define CST_L1S_CTRL_SNB_DL_BURST1         13  //NAME/ l1s_ctrl_snb_dl(burst 1)
+#define CST_L1S_CTRL_SNB_DL_BURST2         14  //NAME/ l1s_ctrl_snb_dl(burst 2)
+#define CST_L1S_CTRL_SNB_DL_BURST3         15  //NAME/ l1s_ctrl_snb_dl(burst 3)
+#define CST_L1S_CTRL_SNB_UL                16  //NAME/ l1s_ctrl_snb_ul()
+#define CST_L1S_CTRL_NNB                   17  //NAME/ l1s_ctrl_nnb()
+#define CST_L1S_CTRL_RACH                  18  //NAME/ l1s_ctrl_rach()
+#define CST_L1S_CTRL_TCHT_DUMMY__DL        19  //NAME/ l1s_ctrl_tcht_dummy(DL)
+#define CST_L1S_CTRL_TCHTH__DL             20  //NAME/ l1s_ctrl_tchth(DL)
+#define CST_L1S_CTRL_TCHTH__UL             21  //NAME/ l1s_ctrl_tchth(UL)
+#define CST_L1S_CTRL_TCHA___DL             22  //NAME/ l1s_ctrl_tcha(DL)
+#define CST_L1S_CTRL_TCHA___UL             23  //NAME/ l1s_ctrl_tcha(UL)
+#define CST_L1S_CTRL_TCHTF__DL             24  //NAME/ l1s_ctrl_tchtf(DL)
+#define CST_L1S_CTRL_TCHTF__UL             25  //NAME/ l1s_ctrl_tchtf(UL)
+#define CST_L1PS_CTRL_POLL                 26  //NAME/ l1ps_ctrl_poll()
+#define CST_L1PS_CTRL_SNB_DL               27  //NAME/ l1ps_ctrl_snb_dl
+#define CST_L1PS_CTRL_SINGLE               28  //NAME/ l1ps_ctrl_single()
+#define CST_L1PS_CTRL_PBCCHS               29  //NAME/ l1ps_ctrl_pbcchs()
+#define CST_L1PS_CTRL_PBCCHN               30  //NAME/ l1ps_ctrl_pbcchn()
+#define CST_L1PS_CTRL_ITMEAS               31  //NAME/ l1ps_ctrl_itmeas()
+#define CST_L1PS_CTRL_PDTCH                32  //NAME/ l1ps_ctrl_pdtch
+#define CST_L1PS_CTRL_PDTCH_UL             33  //NAME/ l1ps_ctrl_pdtch(UL)
+#define CST_L1PS_CTRL_PDTCH_DL             34  //NAME/ l1ps_ctrl_pdtch(DL)
+#define CST_L1PS_CTRL_PDTCH_DL_BURST0      35  //NAME/ l1ps_ctrl_pdtch(DL burst0)
+#define CST_L1PS_CTRL_PDTCH_DL_BURST1      36  //NAME/ l1ps_ctrl_pdtch(DL burst1)
+#define CST_L1PS_CTRL_PDTCH_DL_BURST2      37  //NAME/ l1ps_ctrl_pdtch(DL burst2)
+#define CST_L1PS_CTRL_PDTCH_DL_BURST3      38  //NAME/ l1ps_ctrl_pdtch(DL burst3)
+#define CST_L1PS_CTRL_PDTCH_RA             39  //NAME/ l1ps_ctrl_pdtch(RA)
+#define CST_L1PS_CTRL_PDTCH_DUMMY          40  //NAME/ l1ps_ctrl_pdtch(dummy)
+#define CST_L1PS_CTRL_PTCCH_UL             41  //NAME/ l1ps_ctrl_ptcch(UL)
+#define CST_L1PS_CTRL_PTCCH_EMPTY          42  //NAME/ l1ps_ctrl_ptcch(empty)
+#define CST_L1PS_CTRL_PTCCH_DL_BURST0      43  //NAME/ l1ps_ctrl_ptcch(DL burst0)
+#define CST_L1PS_CTRL_PTCCH_DL_BURST1      44  //NAME/ l1ps_ctrl_ptcch(DL burst1)
+#define CST_L1PS_CTRL_PTCCH_DL_BURST2      45  //NAME/ l1ps_ctrl_ptcch(DL burst2)
+#define CST_L1PS_CTRL_PTCCH_DL_BURST3      46  //NAME/ l1ps_ctrl_ptcch(DL burst3)
+#define CST_CTRL_CR_MEAS                   47  //NAME/ ctrl_cr_meas
+#define CST_CTRL_I_BA_MEAS                 48  //NAME/ ctrl_i_ba_meas
+#define CST_CTRL_D_BA_MEAS                 49  //NAME/ ctrl_d_ba_meas
+#define CST_CTRL_TCR_MEAS_1                50  //NAME/ ctrl_tcr_meas_1
+#define CST_CTRL_TCR_MEAS_2                51  //NAME/ ctrl_tcr_meas_2
+#define CST_CTRL_PC_MEAS_CHAN              52  //NAME/ ctrl_pc_meas_chan
+#define CST_CTRL_TRANSFER_MEAS             53  //NAME/ ctrl_transfer_meas
+#define CST_CTRL_FULL_LIST_MEAS            54  //NAME/ ctrl_full_list_meas
+#define CST_CTRL_SCELL_TRANSFER_MEAS       55  //NAME/ ctrl_Scell_transfer_meas
+#define CST_L1S_READ_RA                    56  //NAME/ l1s_read_ra()
+#define CST_L1S_READ_NNB                   57  //NAME/ l1s_read_nnb
+#define CST_L1S_READ_SNB_DL                58  //NAME/ l1s_read_snb_dl
+#define CST_L1S_READ_TX_NB__DUL            59  //NAME/ l1s_read_tx_nb(DUL)
+#define CST_L1S_READ_TX_NB__AUL            60  //NAME/ l1s_read_tx_nb(AUL)
+#define CST_L1S_READ_TX_NB__TCHF           61  //NAME/ l1s_read_tx_nb(TCHF)
+#define CST_L1S_READ_TX_NB__TCHH           62  //NAME/ l1s_read_tx_nb(TCHH)
+#define CST_L1S_READ_FB                    63  //NAME/ l1s_read_fb()
+#define CST_L1S_READ_FB51                  64  //NAME/ l1s_read_fb51()
+#define CST_L1S_READ_FB26                  65  //NAME/ l1s_read_fb26()
+#define CST_L1S_READ_SB                    66  //NAME/ l1s_read_sb()
+#define CST_L1S_READ_SBCONF                67  //NAME/ l1s_read_sbconf()
+#define CST_L1S_READ_L3FRM__CB             68  //NAME/ l1s_read_l3frm(CB)
+#define CST_L1S_READ_L3FRM__NP             69  //NAME/ l1s_read_l3frm(NP)
+#define CST_L1S_READ_L3FRM__EP             70  //NAME/ l1s_read_l3frm(EP)
+#define CST_L1S_READ_L3FRM__ALLC           71  //NAME/ l1s_read_l3frm(ALLC)
+#define CST_L1S_READ_L3FRM__NBCCHS         72  //NAME/ l1s_read_l3frm(NBCCHS)
+#define CST_L1S_READ_L3FRM__EBCCHS         73  //NAME/ l1s_read_l3frm(EBCCHS)
+#define CST_L1S_READ_L3FRM__BCCHN          74  //NAME/ l1s_read_l3frm(BCCHN)
+#define CST_L1S_READ_SACCH_DL__ADL         75  //NAME/ l1s_read_sacch_dl(ADL)
+#define CST_L1S_READ_SACCH_DL__TCHA        76  //NAME/ l1s_read_sacch_dl(TCHA)
+#define CST_L1S_READ_DCCH_DL__DDL          77  //NAME/ l1s_read_dcch_dl(DDL)
+#define CST_L1S_READ_DCCH_DL__TCHTF        78  //NAME/ l1s_read_dcch_dl(TCHTF)
+#define CST_L1S_READ_DCCH_DL__TCHTH        79  //NAME/ l1s_read_dcch_dl(TCHTH)
+#define CST_L1S_READ_DEDIC_DL              80  //NAME/ l1s_read_dedic_dl
+#define CST_L1S_READ_MON_RESULT            81  //NAME/ l1s_read_mon_result
+#define CST_L1S_READ_DUMMY                 82  //NAME/ l1s_read_dummy
+#define CST_L1S_READ_MSAGC                 83  //NAME/ l1s_read_msagc()
+#define CST_L1PS_READ_NB_DL                84  //NAME/ l1ps_read_nb_dl
+#define CST_L1PS_READ_ITMEAS               85  //NAME/ l1ps_read_itmeas()
+#define CST_L1PS_READ_SINGLE               86  //NAME/ l1ps_read_single
+#define CST_L1PS_READ_SINGLE_DUMMY         87  //NAME/ l1ps_read_single_dummy
+#define CST_L1PS_READ_L3FRM__PNP           88  //NAME/ l1ps_read_l3frm(PNP)
+#define CST_L1PS_READ_L3FRM__PEP           89  //NAME/ l1ps_read_l3frm(PEP)
+#define CST_L1PS_READ_L3FRM__PALLC         90  //NAME/ l1ps_read_l3frm(PALLC)
+#define CST_L1PS_READ_L3FRM__PBCCHS        91  //NAME/ l1ps_read_l3frm(PBCCHS)
+#define CST_L1PS_READ_L3FRM__PBCCHN        92  //NAME/ l1ps_read_l3frm(PBCCHN)
+#define CST_L1PS_READ_L3FRM__SINGLE        93  //NAME/ l1ps_read_l3frm(SINGLE)
+#define CST_L1PS_READ_L3FRM__UNKNOWN       94  //NAME/ l1ps_read_l3frm(?)
+#define CST_L1PS_READ_PRA                  95  //NAME/ l1ps_read_pra()
+#define CST_L1PS_READ_POLL                 96  //NAME/ l1ps_read_poll()
+#define CST_L1PS_READ_PDTCH                97  //NAME/ l1ps_read_pdtch()
+#define CST_L1PS_READ_PDTCH_BURST          98  //NAME/ l1ps_read_pdtch(burst)
+#define CST_L1PS_READ_PTCCH_DL             99  //NAME/ l1ps_read_ptcch(DL)
+#define CST_L1PS_READ_PTCCH_UL            100  //NAME/ l1ps_read_ptcch(UL)
+#define CST_READ_CR_MEAS                  101  //NAME/ read_cr_meas
+#define CST_READ_TCR_MEAS                 102  //NAME/ read_tcr_meas
+#define CST_READ_I_BA_MEAS                103  //NAME/ read_i_ba_meas
+#define CST_READ_D_BA_MEAS                104  //NAME/ read_d_ba_meas
+#define CST_READ_PC_MEAS_CHAN             105  //NAME/ read_pc_meas_chan
+#define CST_READ_FULL_LIST_MEAS           106  //NAME/ read_full_list_meas
+#define CST_L1S_NEW_SYNCHRO               107  //NAME/ SYNCHRO...
+#define CST_L1S_ABORT                     108  //NAME/ L1S_ABORT...
+#define CST_L1S_ABORT_W0_R0               109  //NAME/ L1S_ABORT(PAGE:R0 W0)
+#define CST_UNKNOWN_FB                    110  //NAME/ unknown_fb()
+#define CST_STI_PASSED                    111  //NAME/ STI PASSED...
+#define CST_TASK_KILLED                   112  //NAME/ task KILLED...
+#define CST_ALLOC_EXHAUSTION              113  //NAME/ ALLOC EXHAUSTION
+#define CST_UL_TASKS_DO_NOT_CORRESPOND    114  //NAME/ UL task does not correspond
+#define CST_DL_TASKS_DO_NOT_CORRESPOND    115  //NAME/ DL task does not correspond
+#define CST_DL_BURST_DOES_NOT_CORRESPOND  116  //NAME/ DL burst does not correspond
+#define CST_NEW_FRAME_PAGE_R0_W0          117  //NAME/ =>NEW_FRAME(PAGE:R0 W0)
+#define CST_NEW_FRAME_PAGE_R0_W1          118  //NAME/ =>NEW_FRAME(PAGE:R0 W1)
+#define CST_NEW_FRAME_PAGE_R1_W0          119  //NAME/ =>NEW_FRAME(PAGE:R1 W0)
+#define CST_NEW_FRAME_PAGE_R1_W1          120  //NAME/ =>NEW_FRAME(PAGE:R1 W1)
+#define CST_L1DMACRO_SYNCHRO              121  //NAME/ l1dmacro_synchro
+#define CST_TX_TCH_DATA                   122  //NAME/ tx_tch_data()
+#define CST_DLL_READ_DCCH                 123  //NAME/ dll_read_dcch()
+#define CST_DLL_READ_SACCH                124  //NAME/ dll_read_sacch()
+#define CST_L1S_ADJUST_TIME               125  //NAME/ Time adjustment
+//END_TABLE/
+
+/***********************************************************/
+/* Classic Trace structures                                */
+/***********************************************************/
+
+// !!! IMPORTANT NOTE !!!
+
+// Trace structures:
+// -----------------
+// For 32 bit alignment, all structures should be mapped like this:
+//  1- header
+//  2- 32-bit words (arrays of 32-bit words included)
+//  3- 16-bit words (arrays of 16-bit words included)
+//  4-  8-bit words (arrays of 8-bit words included)
+// This permit to avoid holes between variables and to have a structure independant of
+// alignment
+
+//////////////////
+// ALR messages //
+//////////////////
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_INIT_L1_REQ
+   //FULL/
+     "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+     "#@Fdl7# |->|  |  |  | INIT_L1_REQ              |   radio_band_config: #@1=1:GSM|=2:GSM_E|=3:PCS1900|=4:DCS1800|=5:DUAL|=6:DUALEXT|=7:GSM850|=8:DUAL_US|#"
+   //COND/
+     "#@Fdl7#  INIT_L1_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_INIT_L1_REQ 1
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           radio_band_config;
+}
+T_TR_MPHC_INIT_L1_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_INIT_L1_CON
+   //FULL/
+     "        |  |  |  |  |                          |"
+     "#@Fdl7# |<----|  |  | INIT_L1_CON              |"
+   //COND/
+     "#@Fdl7#  INIT_L1_CON"
+   End header */
+//ID/
+#define TRL1_MPHC_INIT_L1_CON 2
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_INIT_L1_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_RXLEV_PERIODIC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | RXLEV_PERIODIC_REQ       |         num_of_chans: #@1d#"
+    "        |  |  |  |  |                          |               ba_id : #@2d#"
+    "        |  |  |  |  |                          | next_radio_freq_meas: #@3d#"
+   //COND/
+    "#@Fdl7#  RXLEV_PERIODIC_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_RXLEV_PERIODIC_REQ 3
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           num_of_chans;
+  UWORD8           ba_id;
+  UWORD8           next_radio_freq_measured;
+}
+T_TR_MPHC_RXLEV_PERIODIC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NCELL_FB_SB_READ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | NCELL_FB_SB_READ         |           radio_freq: #@1d#"
+    "        |  |  |  |  |                          |"
+   //COND/
+    "#@Fdl7#  NCELL_FB_SB_READ                                               radio_freq: #@1d#"
+   End header */
+//ID/
+#define TRL1_MPHC_NCELL_FB_SB_READ 4
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq;
+}
+T_TR_MPHC_NCELL_FB_SB_READ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_RA_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MPHC_RA_CON              |"
+   //COND/
+    "#@Fdl7#  MPHC_RA_CON"
+   End header */
+//ID/
+#define TRL1_MPHC_RA_CON 5
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_RA_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_IMMED_ASSIGN_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | IMMED_ASSIGN_REQ         |           radio_freq: #@1dl10#          rf_chan_cnt: #@2d#"
+    "        |  |  |  |  |                          |  bef_sti_rf_chan_cnt: #@3dl10#                    h: #@4=0:Single RF|=1:Hopping RF|#"
+    "        |  |  |  |  |                          |         channel_type: #@5T[CHAN TYPE]#"
+    "        |  |  |  |  |                          |           subchannel: #@6dl10#          timeslot_no: #@7d#"
+    "        |  |  |  |  |                          |                  tsc: #@8dl10#       timing_advance: #@9d#"
+    "        |  |  |  |  |                          |   starting_time_pres: #@10=0:No|=1:Yes|~|l10#        starting_time: # (26 + @12 - @13) % 26 + @12 + (1326 * @11 * 51)d#"
+    "        |  |  |  |  |                          |          dtx_allowed: #@14dl10#                pwrc: #@15d#"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  IMMED_ASSIGN_REQ                                               #@5=0:Invalid|=1:TCH_F|=2:TCH_H|=3:SDCCH_4|=4:SDCCH_8|#"
+   End header */
+//ID/
+#define TRL1_MPHC_IMMED_ASSIGN_REQ 6
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD16          bef_sti_rf_chan_cnt;
+  BOOL             h;
+  UWORD8           channel_type;
+  UWORD8           subchannel;
+  UWORD8           timeslot_no;
+  UWORD8           tsc;
+  UWORD8           timing_advance;
+  BOOL             starting_time_present;
+  UWORD8           n32;
+  UWORD8           n51;
+  UWORD8           n26;
+  BOOL             dtx_allowed;
+  BOOL             pwrc;
+}
+T_TR_MPHC_IMMED_ASSIGN_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_CHANNEL_ASSIGN_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | CHANNEL_ASSIGN_REQ       |           radio_freq: #@1dl10#          rf_chan_cnt: #@2d#"
+    "        |  |  |  |  |                          |  bef_sti_rf_chan_cnt: #@3dl10#                    h: #@4=0:Single RF|=1: Hopping RF|#"
+    "        |  |  |  |  |                          |         channel_type: #@5T[CHAN TYPE]#"
+    "        |  |  |  |  |                          |           subchannel: #@6dl10#          timeslot_no: #@7d#"
+    "        |  |  |  |  |                          |                  tsc: #@8dl10#       channel_mode_1: #@9=0:SIG only|=1:TCH_FS|=2:TCH_HS|=3:TCH_96|=4:TCH_48F|=5:TCH_48H|=6:TCH_24F|=7:TCH_24H|=8:TCH_EFR|=9:TCH_144|=10:TCH_AHS|=11:TCH_AFS|#"
+    "        |  |  |  |  |                          |                txpwr: #@10dl10#   starting_time_pres: #@11=0:No|=1:Yes|#"
+    "        |  |  |  |  |                          |        starting_time: # (26 + @13 - @14) % 26 + @13 + (1326 * @12 * 51)dl10#          cipher_mode: #@15d#"
+    "        |  |  |  |  |                          |         a5_algorithm: #@16dl10#          dtx_allowed: #@17=0:false|=1:true|#"
+    "        |  |  |  |  |                          |      noise_suppr_bit: #@18dl10#  init_codec_mode_ind: #@19d#"
+    "        |  |  |  |  |                          |   initial_codec_mode: #@20dl10#     active_codec_set: #@21d#"
+    "        |  |  |  |  |                          |            threshold: #@22dr3#"
+    "        |  |  |  |  |                          |           hysteresis: #@23dr3#"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  CHANNEL_ASSIGN_REQ                                             #@5=0:Invalid|=1:TCH_F|=2:TCH_H|=3:SDCCH_4|=4:SDCCH_8|#"
+   End header */
+//ID/
+#define TRL1_MPHC_CHANNEL_ASSIGN_REQ 7
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD16          bef_sti_rf_chan_cnt;
+  BOOL             h;
+  UWORD8           channel_type;
+  UWORD8           subchannel;
+  UWORD8           timeslot_no;
+  UWORD8           tsc;
+  UWORD8           channel_mode_1;
+  UWORD8           txpwr;
+  BOOL             starting_time_present;
+  UWORD8           n32;
+  UWORD8           n51;
+  UWORD8           n26;
+  UWORD8           cipher_mode;
+  UWORD8           a5_algorithm;
+  BOOL             dtx_allowed;
+  BOOL             noise_suppression_bit;
+  BOOL             initial_codec_mode_indicator;
+  UWORD8           initial_codec_mode;
+  UWORD8           active_codec_set;
+  UWORD8           threshold[3];
+  UWORD8           hysteresis[3];
+}
+T_TR_MPHC_CHANNEL_ASSIGN_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_RA_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | MPHC_RA_REQ              |                txpwr: #@1dl10#                 rand: #@2d#"
+    "        |  |  |  |  |                          |      channel_request: #@3dl10#     powerclass_band1: #@4d#"
+    "        |  |  |  |  |                          |     powerclass_band2: #@5d#"
+   //COND/
+    "#@Fdl7#  RA_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_RA_REQ 8
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           txpwr;
+  UWORD8           rand;
+  UWORD8           channel_request;
+  UWORD8           powerclass_band1;
+  UWORD8           powerclass_band2;
+}
+T_TR_MPHC_RA_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_ASYNC_HO_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | ASYNC_HO_REQ             |            fn_offset: #@1dl10#         time_alignmt: #@2d#"
+    "        |  |  |  |  |                          |         bcch_carrier: #@3dl10#           radio_freq: #@4d#"
+    "        |  |  |  |  |                          |          rf_chan_cnt: #@5dl10#  bef_sti_rf_chan_cnt: #@6d#"
+    "        |  |  |  |  |                          |                  ncc: #@7dl10#                  bcc: #@8d#"
+    "        |  |  |  |  |                          |                    h: #@9=0:Single RF|=1: Hopping RF|~|l10#         channel_type: #@10T[CHAN TYPE]#"
+    "        |  |  |  |  |                          |           subchannel: #@11dl10#          timeslot_no: #@12d#"
+    "        |  |  |  |  |                          |                  tsc: #@13dl10#       channel_mode_1: #@14=0:SIG only|=1:TCH_FS|=2:TCH_HS|=3:TCH_96|=4:TCH_48F|=5:TCH_48H|=6:TCH_24F|=7:TCH_24H|=8:TCH_EFR|=9:TCH_144|=10:TCH_AHS|=11:TCH_AFS|#"
+    "        |  |  |  |  |                          |                txpwr: #@15dl10#   starting_time_pres: #@16=0:No|=1:Yes|#"
+    "        |  |  |  |  |                          |        starting_time: # (26 + @18 - @19) % 26 + @18 + (1326 * @17 * 51)dl10#               ho_acc: #@20d#"
+    "        |  |  |  |  |                          |     report_time_diff: #@21dl10#          cipher_mode: #@22d#"
+    "        |  |  |  |  |                          |         a5_algorithm: #@23dl10#      noise_suppr_bit: #@24d#"
+    "        |  |  |  |  |                          |  init_codec_mode_ind: #@25dl10#   initial_codec_mode: #@26d#"
+    "        |  |  |  |  |                          |     active_codec_set: #@27dl#"
+    "        |  |  |  |  |                          |            threshold: #@28dr3#"
+    "        |  |  |  |  |                          |           hysteresis: #@29dr3#"
+   //COND/
+    "#@Fdl7#  ASYNC_HO_REQ                                                   bcch_carrier: #@3d# channel_type: #@10T[CHAN TYPE]#"
+   End header */
+//ID/
+#define TRL1_MPHC_ASYNC_HO_REQ 9
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD16          bcch_carrier;
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD16          bef_sti_rf_chan_cnt;
+  UWORD8           ncc;
+  UWORD8           bcc;
+  BOOL             h;
+  UWORD8           channel_type;
+  UWORD8           subchannel;
+  UWORD8           timeslot_no;
+  UWORD8           tsc;
+  UWORD8           channel_mode_1;
+  UWORD8           txpwr;
+  BOOL             starting_time_present;
+  UWORD8           n32;
+  UWORD8           n51;
+  UWORD8           n26;
+  UWORD8           ho_acc;
+  BOOL             report_time_diff;
+  UWORD8           cipher_mode;
+  UWORD8           a5_algorithm;
+  BOOL             noise_suppression_bit;
+  BOOL             initial_codec_mode_indicator;
+  UWORD8           initial_codec_mode;
+  UWORD8           active_codec_set;
+  UWORD8           threshold[3];
+  UWORD8           hysteresis[3];
+}
+T_TR_MPHC_ASYNC_HO_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_SYNC_HO_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SYNC_HO_REQ              |            fn_offset: #@1dl10#         time_alignmt: #@2d#"
+    "        |  |  |  |  |                          |         bcch_carrier: #@3dl10#           radio_freq: #@4d#"
+    "        |  |  |  |  |                          |          rf_chan_cnt: #@5dl10#  bef_sti_rf_chan_cnt: #@6d#"
+    "        |  |  |  |  |                          |                  ncc: #@7dl10#                  bcc: #@8d#"
+    "        |  |  |  |  |                          |                    h: #@9=0:Single RF|=1: Hopping RF|~|l10#         channel_type: #@10T[CHAN TYPE]#"
+    "        |  |  |  |  |                          |           subchannel: #@11dl10#          timeslot_no: #@12d#"
+    "        |  |  |  |  |                          |                  tsc: #@13dl10#       channel_mode_1: #@14=0:SIG only|=1:TCH_FS|=2:TCH_HS|=3:TCH_96|=4:TCH_48F|=5:TCH_48H|=6:TCH_24F|=7:TCH_24H|=8:TCH_EFR|=9:TCH_144|=10:TCH_AHS|=11:TCH_AFS|#"
+    "        |  |  |  |  |                          |                txpwr: #@15dl10#   starting_time_pres: #@16=0:No|=1:Yes|#"
+    "        |  |  |  |  |                          |        starting_time: # (26 + @18 - @19) % 26 + @18 + (1326 * @17 * 51)dl10#               ho_acc: #@20d#"
+    "        |  |  |  |  |                          |     report_time_diff: #@21dl10#          cipher_mode: #@22d#"
+    "        |  |  |  |  |                          |         a5_algorithm: #@23dl10#      noise_suppr_bit: #@24d#"
+    "        |  |  |  |  |                          |  init_codec_mode_ind: #@25dl10#   initial_codec_mode: #@26d#"
+    "        |  |  |  |  |                          |     active_codec_set: #@27dl10#"
+    "        |  |  |  |  |                          |            threshold: #@28dr3#"
+    "        |  |  |  |  |                          |           hysteresis: #@29dr3#"
+   //COND/
+    "#@Fdl7#  SYNC_HO_REQ                                                    bcch_carrier: #@3d# channel_type: #@10T[CHAN TYPE]#"
+   End header */
+//ID/
+#define TRL1_MPHC_SYNC_HO_REQ 10
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD16          bcch_carrier;
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD16          bef_sti_rf_chan_cnt;
+  UWORD8           ncc;
+  UWORD8           bcc;
+  BOOL             h;
+  UWORD8           channel_type;
+  UWORD8           subchannel;
+  UWORD8           timeslot_no;
+  UWORD8           tsc;
+  UWORD8           channel_mode_1;
+  UWORD8           txpwr;
+  BOOL             starting_time_present;
+  UWORD8           n32;
+  UWORD8           n51;
+  UWORD8           n26;
+  UWORD8           ho_acc;
+  BOOL             report_time_diff;
+  UWORD8           cipher_mode;
+  UWORD8           a5_algorithm;
+  BOOL             noise_suppression_bit;
+  BOOL             initial_codec_mode_indicator;
+  UWORD8           initial_codec_mode;
+  UWORD8           active_codec_set;
+  UWORD8           threshold[3];
+  UWORD8           hysteresis[3];
+}
+T_TR_MPHC_SYNC_HO_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_HANDOVER_FINISHED
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |        HANDOVER_FINISHED | #@1=0:Complete|=1:TIMEOUT|#"
+   //COND/
+    "#@Fdl7#                          HANDOVER_FINISHED       #@1=1:TIMEOUT|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_HANDOVER_FINISHED 11
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           cause;
+}
+T_TR_L1C_HANDOVER_FINISHED;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_MEAS_DONE
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                MEAS_DONE |  rxqual_full_acc_err: #@1dl10# rxqual_full_nbr_bits: #@2d#"
+    "        |  |  |  |  |                          |rxqual_sub_acc_errors: #@3dl10#  rxqual_sub_nbr_bits: #@4d#"
+    "        |  |  |  |  |                          |        rxlev_sub_acc: #@5dl10#       rxlev_full_acc: #@6d#"
+    "        |  |  |  |  |                          |           meas_valid: #@9dl10#           txpwr_used: #@10d#"
+    "        |  |  |  |  |                          |       timing_advance: #@11dl10#   rxlev_sub_nbr_meas: #@13d#"
+    "        |  |  |  |  |                          |       facch_dl_count: #@14dl10#       facch_ul_count: #@15d#"
+    "        |  |  |  |  |                          |            bcch_freq: #@7dr5#"
+    "        |  |  |  |  |                          |            rxlev_acc: #@8dr5#"
+    "        |  |  |  |  |                          |       rxlev_nbr_meas: #@16dr5#"
+   //COND/
+    "#@Fdl7#                          MEAS_DONE"
+   End header */
+//ID/
+#define TRL1_L1C_MEAS_DONE 12
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          rxqual_full_acc_errors;
+  UWORD16          rxqual_full_nbr_bits;
+  UWORD16          rxqual_sub_acc_errors;
+  UWORD16          rxqual_sub_nbr_bits;
+  WORD16           rxlev_sub_acc;
+  WORD16           rxlev_full_acc;
+  UWORD16          bcch_freq[6];
+  WORD16           rxlev_acc[6];
+  BOOL             meas_valid;
+  UWORD8           txpwr_used;
+  UWORD8           timing_advance;
+  UWORD8           rxlev_full_nbr_meas;
+  UWORD8           rxlev_sub_nbr_meas;
+  UWORD8           facch_dl_count;
+  UWORD8           facch_ul_count;
+  UWORD8           rxlev_nbr_meas[6];
+}
+T_TR_L1C_MEAS_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_START_CCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "=========================================================================================================================================================================================="
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | START_CCCH_REQ           |          bs_pa_mfrms: #@1dl10#       bs_ag_blks_res: #@2d#"
+    "        |  |  |  |  |                          |        bcch_combined: #@3dl10#           ccch_group: #@4d#"
+    "        |  |  |  |  |                          |           page_group: #@5dl10#     page_block_index: #@6d#"
+    "        |  |  |  |  |                          |            page_mode: #@7=0:NORMAL|=1:EXTENDED|=2:REORG|~INVALID|#"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  START_CCCH_REQ                                                 #@7=0:Normal|=1:Extended|=2:Reorg|~INVALID|#"
+   End header */
+//ID/
+#define TRL1_MPHC_START_CCCH_REQ 13
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           bs_pa_mfrms;
+  UWORD8           bs_ag_blks_res;
+  BOOL             bcch_combined;
+  UWORD8           ccch_group;
+  UWORD8           page_group;
+  UWORD8           page_block_index;
+  UWORD8           page_mode;
+}
+T_TR_MPHC_START_CCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NCELL_SB_READ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | NCELL_SB_READ            |           radio_freq: #@3dl10#            fn_offset: #@1d#"
+    "        |  |  |  |  |                          |         time_alignmt: #@2d#"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  NCELL_SB_READ                                                  radio_freq: #@3d#"
+   End header */
+//ID/
+#define TRL1_MPHC_NCELL_SB_READ 14
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD16          radio_freq;
+}
+T_TR_MPHC_NCELL_SB_READ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_RXLEV_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | RXLEV_REQ                |     power_array_size: #@1d#"
+   //COND/
+    "#@Fdl7#  RXLEV_REQ                                                      nb_rf: #@1d#"
+   End header */
+//ID/
+#define TRL1_MPHC_RXLEV_REQ  15
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          power_array_size;
+}
+T_TR_MPHC_RXLEV_REQ;
+
+#define MAX_MEAS 10
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_VALID_MEAS_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |          VALID_MEAS_INFO |     power array size: #@1dl10#      rxlev_req_count: #@2dl#"
+   //COND/
+    "#@Fdl7#                          VALID_MEAS_INFO"
+   End header */
+//ID/*/
+#define TRL1_L1C_VALID_MEAS_INFO  16
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          power_array_size;
+  UWORD8           rxlev_req_count;
+}
+T_TR_L1C_VALID_MEAS_INFO;
+
+/***********************************************************************************************************/
+/* Special trace: display is implemented in the trace decoder
+ */
+#define TRL1_FULL_LIST_REPORT  184
+
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          size;
+  UWORD32          content[1];
+}
+T_TR_FULL_LIST_REPORT;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_RXLEV_PERIODIC_DONE
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |      RXLEV_PERIODIC_DONE |                ba_id: #@2dl10#              s_rxlev: #@3d#"
+    "        |  |  |  |  |                          |           radio_freq: #@1dr5#"
+    "        |  |  |  |  |                          |                rxlev: #@4dr5#"
+   //COND/
+    "#@Fdl7#                          RXLEV_PERIODIC_DONE"
+   End header */
+//ID/
+#define TRL1_L1C_RXLEV_PERIODIC_DONE 17
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq_no[8];
+  UWORD8           ba_id;
+  WORD8            s_rxlev;
+  WORD8            rxlev[8];
+}
+T_TR_L1C_RXLEV_PERIODIC_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_SCELL_NBCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SCELL_NBCCH_REQ          |  schedule_array_size: #@3d#"
+    "        |  |  |  |  |                          |              modulus: #@1dr5#"
+    "        |  |  |  |  |                          |    relative_position: #@2dr5#"
+   //COND/
+    "#@Fdl7#  SCELL_NBCCH_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_SCELL_NBCCH_REQ 18
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          modulus[10];
+  UWORD16          relative_position[10];
+  UWORD8           schedule_array_size;
+}
+T_TR_MPHC_SCELL_NBCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_SCELL_EBCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SCELL_EBCCH_REQ          |  schedule_array_size: #@3d#"
+    "        |  |  |  |  |                          |              modulus: #@1dr5#"
+    "        |  |  |  |  |                          |    relative_position: #@2dr5#"
+   //COND/
+    "#@Fdl7#  SCELL_EBCCH_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_SCELL_EBCCH_REQ 19
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          modulus[10];
+  UWORD16          relative_position[10];
+  UWORD8           schedule_array_size;
+}
+T_TR_MPHC_SCELL_EBCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NCELL_BCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | NCELL_BCCH_REQ           |           radio_freq: #@3dl10#            fn_offset: #@1d#"
+    "        |  |  |  |  |                          |         time_alignmt: #@2dl10#        bcch_blks_req: #@4d#"
+    "        |  |  |  |  |                          |                  tsc: #@5dl10#        gprs_priority: #@6=0:TOP|=1:HIGH|=2:NORMAL|#"
+   //COND/
+    "#@Fdl7#  NCELL_BCCH_REQ                                                 radio_freq: #@3d#"
+   End header */
+//ID/
+#define TRL1_MPHC_NCELL_BCCH_REQ 20
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD16          radio_freq;
+  UWORD16          bcch_blks_req;
+  UWORD8           tsc;
+  UWORD8           gprs_priority;
+}
+T_TR_MPHC_NCELL_BCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_BCCHN_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |               BCCHN_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |          input_level: #-@5 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          BCCHN_INFO              #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_BCCHN_INFO 21
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           input_level;
+}
+T_TR_L1C_BCCHN_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_NP_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                  NP_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |          input_level: #-@5 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          NP_INFO                 #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_NP_INFO 22
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           input_level;
+}
+T_TR_L1C_NP_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_EP_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                  EP_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |          input_level: #-@5 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          EP_INFO                 #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_EP_INFO 23
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           input_level;
+}
+T_TR_L1C_EP_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_ALLC_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                ALLC_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |          input_level: #-@5 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          ALLC_INFO               #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_ALLC_INFO 24
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           input_level;
+}
+T_TR_L1C_ALLC_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_BCCHS_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |               BCCHS_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |          input_level: #-@5 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          BCCHS_INFO              #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_BCCHS_INFO 25
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           input_level;
+}
+T_TR_L1C_BCCHS_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_CB_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                  CB_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |          input_level: #-@5 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          CB_INFO                 #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_CB_INFO 26
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           input_level;
+}
+T_TR_L1C_CB_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NETWORK_SYNC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | NETWORK_SYNC_REQ         |           radio_freq: #@3dl10#            fn_offset: #@1d#"
+    "        |  |  |  |  |                          |         time_alignmt: #@2dl10#      timing_validity: #@4d#"
+    "        |  |  |  |  |                          |          search_mode: #@5d#"
+   //COND/
+    "#@Fdl7#  NETWORK_SYNC_REQ                                               radio_freq: #@3d#"
+   End header */
+//ID/
+#define TRL1_MPHC_NETWORK_SYNC_REQ 27
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD16          radio_freq;
+  UWORD8           timing_validity;
+  UWORD8           search_mode;
+}
+T_TR_MPHC_NETWORK_SYNC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NETWORK_SYNC_IND
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  |         NETWORK_SYNC_IND |              sb_flag: #@4=1:OK|=0:FAILED|~|l10#            fn_offset: #@1d#"
+    "        |  |  |  |  |                          |         time_alignmt: #@2dl10#           radio_freq: #@3d#"
+    "        |  |  |  |  |                          |                 bsic: #@5d#"
+   //COND/
+    "#@Fdl7#  NETWORK_SYNC_IND                                #@4=0:Syncho failed|=1:               Synchro done|#"
+   End header */
+//ID/
+#define TRL1_MPHC_NETWORK_SYNC_IND 28
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD16          radio_freq;
+  BOOL             sb_flag;
+  UWORD8           bsic;
+}
+T_TR_MPHC_NETWORK_SYNC_IND;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NCELL_SYNC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | NCELL_SYNC_REQ           |           radio_freq: #@3dl10#      timing_validity: #@4d#"
+    "        |  |  |  |  |                          |            fn_offset: #@1dl10#         time_alignmt: #@2d#"
+   //COND/
+    "#@Fdl7#  NCELL_SYNC_REQ                                                 radio_freq: #@3d#"
+   End header */
+//ID/
+#define TRL1_MPHC_NCELL_SYNC_REQ 29
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD16          radio_freq;
+  UWORD8           timing_validity;
+}
+T_TR_MPHC_NCELL_SYNC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NCELL_LIST_SYNC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | MPHC_NCELL_LIST_SYNC_REQ |                 eotd: #@5=0:FALSE|=1:TRUE|l10#            list_size: #@6d#"
+    "        |  |  |  |  |                          |           radio_freq: #@3dr10#"
+    "        |  |  |  |  |                          |      timing_validity: #@4dr10#"
+    "        |  |  |  |  |                          |            fn_offset: #@1dr10#"
+    "        |  |  |  |  |                          |         time_alignmt: #@2dr10#"
+   //COND/
+    "#@Fdl7#  MPHC_NCELL_LIST_SYNC_REQ                                       eotd: #@5dl10# list_size: #@6d#"
+   End header */
+//ID/
+#define TRL1_MPHC_NCELL_LIST_SYNC_REQ 217
+//STRUCT/
+typedef struct
+{
+  UWORD32    header;
+//--------------------------------------------------
+  UWORD32    fn_offset[12];
+  UWORD32    time_alignmt[12];
+  UWORD16    radio_freq[12];
+  UWORD8     timing_validity[12];
+  UWORD8     eotd;
+  UWORD8     list_size;
+}
+T_TR_MPHC_NCELL_LIST_SYNC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NCELL_SYNC_IND
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  |           NCELL_SYNC_IND |              sb_flag: #@9=0:Not Found|=1:Found|~|l10#           radio_freq: #@8d#"
+    "        |  |  |  |  |                          |                 bsic: #@10dl10#             neigh_id: #@11d#"
+    "        |  |  |  |  |                          |            fn_offset: #@1dl10#         time_alignmt: #@2d#"
+    "        |  |  |  |  |                          |            list_size: #@12dl10#          fn_sb_neigh: #@3d#"
+    "        |  |  |  |  |                          |            fn_in_SB: #@4dl10#        toa_correction: #@5d#"
+    "        |  |  |  |  |                          |            delta_fn: #@6dl10#            delta_qbit: #@7d#"
+    "        |  |  |  |  |                          |     eotd_data_valid: #@13dl10#                  mode: #@14d#"
+   //COND/
+    "#@Fdl7#  NCELL_SYNC_IND                                  #@4=0:not found|~|l10#     radio_freq: #@3d#"
+   End header */
+//ID/
+#define TRL1_MPHC_NCELL_SYNC_IND 30
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD32          fn_sb_neigh;
+  UWORD32          fn_in_SB;
+  WORD32           toa_correction;
+  UWORD32          delta_fn;
+  WORD32           delta_qbit;
+  UWORD16          radio_freq;
+  BOOL             sb_flag;
+  UWORD8           bsic;
+  UWORD8           neigh_id;
+  UWORD8           list_size;
+  UWORD8           eotd_data_valid;
+  UWORD8           mode;
+}
+T_TR_MPHC_NCELL_SYNC_IND;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_SB_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                  SB_INFO |              sb_flag: #@10=0:Not found|=1:Found|~|l10#            fn_offset: #@1d#"
+    "        |  |  |  |  |                          |         time_alignmt: #@2dl10#                   pm: #@3d#"
+    "        |  |  |  |  |                          |                  toa: #@4dl10#                angle: #@5d#"
+    "        |  |  |  |  |                          |                  snr: #@6dl10#           tpu_offset: #@7d#"
+    "        |  |  |  |  |                          |           radio_freq: #@8dl10#                  afc: #@9d#"
+    "        |  |  |  |  |                          |                 bsic: #@11dl10#          input_level: #-@12 / 2d# dBm"
+   //COND/
+    "#@Fdl7#                          SB_INFO                 #@10=0:not found|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_SB_INFO 31
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD32          pm;
+  UWORD32          toa;
+  UWORD32          angle;
+  UWORD32          snr;
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             sb_flag;
+  UWORD8           bsic;
+  UWORD8           input_level;
+}
+T_TR_L1C_SB_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_SBCONF_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |              SBCONF_INFO |              sb_flag: #@10=0:Not found|=1:Found|~|l10#            fn_offset: #@1d#"
+    "        |  |  |  |  |                          |         time_alignmt: #@2dl10#                   pm: #@3d#"
+    "        |  |  |  |  |                          |                  toa: #@4dl10#                angle: #@5d#"
+    "        |  |  |  |  |                          |                  snr: #@6dl10#           tpu_offset: #@7d#"
+    "        |  |  |  |  |                          |           radio_freq: #@8dl10#                  afc: #@9d#"
+    "        |  |  |  |  |                          |                 bsic: #@11dl10#          input_level: #-@12 / 2d# dBm"
+   //COND/
+    "#@Fdl7#                          SBCONF_INFO             #@10=0:not found|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_SBCONF_INFO 32
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD32          pm;
+  UWORD32          toa;
+  UWORD32          angle;
+  UWORD32          snr;
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             sb_flag;
+  UWORD8           bsic;
+  UWORD8           input_level;
+}
+T_TR_L1C_SBCONF_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NEW_SCELL_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | NEW_SCELL_REQ            |            fn_offset: #@1dl10#         time_alignmt: #@2d#"
+    "        |  |  |  |  |                          |           radio_freq: #@3dl10#                 bsic: #@4d#"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  NEW_SCELL_REQ                                                  radio_freq: #@3d#"
+   End header */
+//ID/
+#define TRL1_MPHC_NEW_SCELL_REQ 33
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignmt;
+  UWORD16          radio_freq;
+  UWORD8           bsic;
+}
+T_TR_MPHC_NEW_SCELL_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_FB_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                  FB_INFO |              fb_flag: #@8=0:Not found|=1:Found|~|l10#                   pm: #@1d#"
+    "        |  |  |  |  |                          |                  toa: #@2dl10#                angle: #@3d#"
+    "        |  |  |  |  |                          |                  snr: #@4dl10#           tpu_offset: #@5d#"
+    "        |  |  |  |  |                          |           radio_freq: #@6dl10#                  afc: #@7d#"
+    "        |  |  |  |  |                          |          input_level: #-@9 / 2d# dBm"
+   //COND/
+    "#@Fdl7#                          FB_INFO                 #@8=0:not found|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_FB_INFO 34
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          pm;
+  UWORD32          toa;
+  UWORD32          angle;
+  UWORD32          snr;
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             fb_flag;
+  UWORD8           input_level;
+}
+T_TR_L1C_FB_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_NCELL_SYNC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | STOP_NCELL_SYNC_REQ      | radio_freq_array_size: #@2d#"
+    "        |  |  |  |  |                          |      radio_freq_array: #@1dr5#"
+   //COND/
+    "#@Fdl7#  STOP_NCELL_SYNC_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_NCELL_SYNC_REQ 35
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq_array[6];
+  WORD8            radio_freq_array_size;
+}
+T_TR_MPHC_STOP_NCELL_SYNC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_NCELL_BCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | STOP_NCELL_BCCH_REQ      | radio_freq_array_size: #@2d#"
+    "        |  |  |  |  |                          |      radio_freq_array: #@1dr5#"
+   //COND/
+    "#@Fdl7#  STOP_NCELL_BCCH_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_NCELL_BCCH_REQ 36
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq_array[6];
+  UWORD8           radio_freq_array_size;
+}
+T_TR_MPHC_STOP_NCELL_BCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_CONFIG_CBCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | CONFIG_CBCH_REQ          |           radio_freq: #@1dl10#                    h: #@2=0:Single RF|=1: Hopping RF|#"
+    "        |  |  |  |  |                          |          timeslot_no: #@3d#"
+   //COND/
+    "#@Fdl7#  CONFIG_CBCH_REQ                                                radio_freq: #@1d#"
+   End header */
+//ID/
+#define TRL1_MPHC_CONFIG_CBCH_REQ 37
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq;
+  BOOL             h;
+  UWORD8           timeslot_no;
+}
+T_TR_MPHC_CONFIG_CBCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_CBCH_SCHEDULE_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | CBCH_SCHEDULE_REQ        |        extended_cbch: #@3=0:NORMAL|=1:EXTENDED|~|l10#      schedule_length: #@4d#"
+    "        |  |  |  |  |                          |        first_block_0: #@1xl10#        first_block_1: #@2x#"
+    "        |  |  |  |  |                          |         "
+   //COND/
+    "#@Fdl7#  CBCH_SCHEDULE_REQ                                              #@3=0:NORMAL|=1:EXTENDED|#"
+   End header */
+//ID/
+#define TRL1_MPHC_CBCH_SCHEDULE_REQ 38
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          first_block_0;
+  UWORD16          first_block_1;
+  BOOL             extended_cbch;
+  UWORD8           schedule_length;
+}
+T_TR_MPHC_CBCH_SCHEDULE_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_CBCH_INFO_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | CBCH_INFO_REQ            |            tb_bitmap: #@1bz8#"
+   //COND/
+    "#@Fdl7#  CBCH_INFO_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_CBCH_INFO_REQ 39
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           tb_bitmap;
+}
+T_TR_MPHC_CBCH_INFO_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_CBCH_UPDATE_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | CBCH_UPDATE_REQ          |        extended_cbch: #@3=0:NORMAL|=1:EXTENDED|#"
+    "        |  |  |  |  |                          |        first_block_0: #@1xl10#        first_block_1: #@2x#"
+   //COND/
+    "#@Fdl7#  CBCH_UPDATE_REQ                                                #@3=0:NORMAL|=1:EXTENDED|#"
+   End header */
+//ID/
+#define TRL1_MPHC_CBCH_UPDATE_REQ 40
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          first_block_0;
+  UWORD16          first_block_1;
+  BOOL             extended_cbch;
+}
+T_TR_MPHC_CBCH_UPDATE_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_CBCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | STOP_CBCH_REQ            |          normal_cbch: #@1=0:No|=1:Yes|~|l10#         extended_cbch: #@2=0:No|=1:Yes|#"
+   //COND/
+    "#@Fdl7#  STOP_CBCH_REQ                                                  #@1=1:NORMAL|~|##@2=1:EXTENDED|~|#"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_CBCH_REQ 41
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  BOOL             normal_cbch;
+  BOOL             extended_cbch;
+}
+T_TR_MPHC_STOP_CBCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_SACCH_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |               SACCH_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |   beacon_input_level: #-@5/2 f1l6# dBm          input_level: #-@6/2f1# dBm"
+   //COND/
+    "#@Fdl7#                          SACCH_INFO              #@5=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1C_SACCH_INFO 42
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          rf_chan_num;
+  WORD16           afc;
+  UWORD8           error_cause;
+  UWORD8           beacon_input_level;
+  UWORD8           input_level;
+}
+T_TR_L1C_SACCH_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_CHANGE_FREQUENCY
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | CHANGE_FREQUENCY         |           radio_freq: #@1dl10#          rf_chan_cnt: #@2d#"
+    "        |  |  |  |  |                          |                    h: #@3=0:Single RF|=1: Hopping RF|~|l10#         channel_type: #@4T[CHAN TYPE]#"
+    "        |  |  |  |  |                          |           subchannel: #@5dl10#          timeslot_no: #@6d#"
+    "        |  |  |  |  |                          |                  tsc: #@7dl10#   start_time_present: #@8=0:No|=1:Yes|#"
+    "        |  |  |  |  |                          |        starting_time: # (26 + @10 - @11) % 26 + @10 + (1326 * @9 * 51)dl10#"
+   //COND/
+    "#@Fdl7#  CHANGE_FREQUENCY                                               radio_freq: #@1d#"
+   End header */
+//ID/
+#define TRL1_MPHC_CHANGE_FREQUENCY 43
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  BOOL             h;
+  UWORD8           channel_type;
+  UWORD8           subchannel;
+  UWORD8           timeslot_no;
+  UWORD8           tsc;
+  BOOL             start_time_present;
+  UWORD8           n32;
+  UWORD8           n51;
+  UWORD8           n26;
+}
+T_TR_MPHC_CHANGE_FREQUENCY;
+
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_CHANNEL_MODE_MODIFY_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | CHANNEL_MODE_MODIFY_REQ  |           subchannel: #@1dl10#         channel_mode: #@2=0:SIG only|=1:TCH_FS|=2:TCH_HS|=3:TCH_96|=4:TCH_48F|=5:TCH_48H|=6:TCH_24F|=7:TCH_24H|=8:TCH_EFR|=9:TCH_144|=10:TCH_AHS|=11:TCH_AFS|#"
+    "        |  |  |  |  |                          |      noise_suppr_bit: #@3dl10#   initial_codec_mode: #@4d#"
+    "        |  |  |  |  |                          |   initial_codec_mode: #@5dl10#     active_codec_set: #@6d#"
+    "        |  |  |  |  |                          |            threshold: #@7dr3#"
+    "        |  |  |  |  |                          |           hysteresis: #@8dr3#"
+   //COND/
+    "#@Fdl7#  CHANNEL_MODE_MODIFY_REQ                                        #@2=0:SIG only|=1:TCH_FS|=2:TCH_HS|=3:TCH_96|=4:TCH_48F|=5:TCH_48H|=6:TCH_24F|=7:TCH_24H|=8:TCH_EFR|=9:TCH_144|=10:TCH_AHS|=11:TCH_AFS|#"
+   End header */
+//ID/
+#define TRL1_MPHC_CHANNEL_MODE_MODIFY_REQ 44
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           subchannel;
+  UWORD8           channel_mode;
+  BOOL             noise_suppression_bit;
+  BOOL             initial_codec_mode_indicator;
+  UWORD8           initial_codec_mode;
+  UWORD8           active_codec_set;
+  UWORD8           threshold[3];
+  UWORD8           hysteresis[3];
+}
+T_TR_MPHC_CHANNEL_MODE_MODIFY_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_SET_CIPHERING_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SET_CIPHERING_REQ        |          cipher_mode: #@1=0:No ciphering|~ON|l10#         a5_algorithm: #@2=0:A5/1|=1:A5/2|=2:A5/3|=3:A5/4|=4:A5/5|=5:A5/6|=6:A5/7|#"
+    "        |  |  |  |  |                          |                    A: #@3dr5#"
+   //COND/
+    "#@Fdl7#  SET_CIPHERING_REQ                                              #@1=0:No ciphering|~Ciphering on|#"
+   End header */
+//ID/
+#define TRL1_MPHC_SET_CIPHERING_REQ 45
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           cipher_mode;
+  UWORD8           a5_algorithm;
+  UWORD8           A[8];
+}
+T_TR_MPHC_SET_CIPHERING_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_UPDATE_BA_LIST
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | UPDATE_BA_LIST           |         num_of_chans: #@1dl10#                 pwrc: #@2d#"
+    "        |  |  |  |  |                          |          dtx_allowed: #@3=0:NO|=1:YES|~|l10#                ba_id: #@4d#"
+   //COND/
+    "#@Fdl7#  UPDATE_BA_LIST"
+   End header */
+//ID/
+#define TRL1_MPHC_UPDATE_BA_LIST 46
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           num_of_chans;
+  BOOL             pwrc;
+  BOOL             dtx_allowed;
+  UWORD8           ba_id;
+}
+T_TR_MPHC_UPDATE_BA_LIST;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_NETWORK_LOST_IND
+   //FULL/
+	"        |  |  |  |  |                          |"
+	"#@Fdl7# |<----|  |  | NETWORK_LOST_IND         |"
+   //COND/
+    "#@Fdl7#  NETWORK_LOST_IND"
+   End header */
+//ID/
+#define TRL1_MPHC_NETWORK_LOST_IND 47
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_NETWORK_LOST_IND;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_CCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_CCCH_REQ            |"
+   //COND/
+    "#@Fdl7#  STOP_CCCH_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_CCCH_REQ 48
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_CCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_SCELL_BCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_SCELL_BCCH_REQ      |"
+   //COND/
+    "#@Fdl7#  STOP_SCELL_BCCH_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_SCELL_BCCH_REQ 49
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_SCELL_BCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_CBCH_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_CBCH_REQ            |"
+   //COND/
+    "#@Fdl7#  STOP_CBCH_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_CBCH_CON 50
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_CBCH_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_RA_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_RA_REQ              |"
+   //COND/
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_RA_REQ 51
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_RA_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_RA_DONE
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |              L1C_RA_DONE |"
+   //COND/
+    "#@Fdl7#                          L1C_RA_DONE"
+   End header */
+//ID/
+#define TRL1_L1C_RA_DONE 52
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1C_RA_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_IMMED_ASSIGN_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "=========================================================================================================================================================================================="
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |         IMMED_ASSIGN_CON |"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  IMMED_ASSIGN_CON"
+   End header */
+//ID/
+#define TRL1_MPHC_IMMED_ASSIGN_CON 53
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_IMMED_ASSIGN_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_CHANNEL_ASSIGN_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "=========================================================================================================================================================================================="
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |       CHANNEL_ASSIGN_CON |"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  CHANNEL_ASSIGN_CON"
+   End header */
+//ID/
+#define TRL1_MPHC_CHANNEL_ASSIGN_CON 54
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_CHANNEL_ASSIGN_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_REDEF_DONE
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |               REDEF_DONE |"
+   //COND/
+    "#@Fdl7#                          REDEF_DONE"
+   End header */
+//ID/
+#define TRL1_L1C_REDEF_DONE 55
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1C_REDEF_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_DEDICATED_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_DEDICATED_REQ       |"
+   //COND/
+    "#@Fdl7#  STOP_DEDICATED_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_DEDICATED_REQ 56
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_DEDICATED_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_ASYNC_HO_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |             ASYNC_HO_CON |"
+   //COND/
+    "#@Fdl7#  ASYNC_HO_CON"
+   End header */
+//ID/
+#define TRL1_MPHC_ASYNC_HO_CON 57
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_ASYNC_HO_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_SYNC_HO_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |              SYNC_HO_CON |"
+   //COND/
+    "#@Fdl7#  SYNC_HO_CON"
+   End header */
+//ID/
+#define TRL1_MPHC_SYNC_HO_CON 58
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_SYNC_HO_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_TA_FAIL_IND
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |              TA_FAIL_IND |"
+   //COND/
+    "#@Fdl7#  TA_FAIL_IND"
+   End header */
+//ID/
+#define TRL1_MPHC_TA_FAIL_IND 59
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_TA_FAIL_IND;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_HANDOVER_FAIL_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | HANDOVER_FAIL_REQ        |"
+   //COND/
+    "#@Fdl7#  HANDOVER_FAIL_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_HANDOVER_FAIL_REQ 60
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_HANDOVER_FAIL_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_HANDOVER_FAIL_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |        HANDOVER_FAIL_CON |"
+   //COND/
+    "#@Fdl7#  HANDOVER_FAIL_CON"
+   End header */
+//ID/
+#define TRL1_MPHC_HANDOVER_FAIL_CON 61
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_HANDOVER_FAIL_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_RXLEV_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_RXLEV_REQ           |"
+   //COND/
+    "#@Fdl7#  STOP_RXLEV_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_RXLEV_REQ 62
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_RXLEV_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_RXLEV_PERIODIC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_RXLEV_PERIODIC_REQ  |"
+   //COND/
+    "#@Fdl7#  STOP_RXLEV_PERIODIC_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_RXLEV_PERIODIC_REQ 63
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_RXLEV_PERIODIC_REQ;
+
+///////////////////
+// GPRS messages //
+///////////////////
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_RA_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | MPHP_RA_REQ              |                 rand: #@1dl10# channel_request_data: #@2d#"
+    "        |  |  |  |  |                          |                txpwr: #@3dl10#        bs_prach_blks: #@4d#"
+    "        |  |  |  |  |                          |    access_burst_type: #@5=0: 8 bit|=1:11 bit|#"
+   //COND/
+    "#@Fdl7#  MPHP_RA_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_RA_REQ 64
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          rand;
+  UWORD16          channel_request_data;
+  UWORD8           txpwr;
+  UWORD8           bs_prach_blks;
+  UWORD8           access_burst_type;
+}
+T_TR_MPHP_RA_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_RA_DONE
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |              L1P_RA_DONE | channel_request_data: #@1d#"
+   //COND/
+    "#@Fdl7#                          L1P_RA_DONE"
+   End header */
+//ID/
+#define TRL1_L1P_RA_DONE 65
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          channel_request_data;
+}
+T_TR_L1P_RA_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_POLLING_RESPONSE_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | POLLING_RESPONSE_REQ     |               fn_req: #@1dl10#        pol_resp_type: #@2=3:CS1|=7:PRACH 8 bit|=8:PRACH 11 bit|#"
+    "        |  |  |  |  |                          |       timing_advance: #@3dl10#                txpwr: #@4d#"
+   //COND/
+    "#@Fdl7#  POLLING_RESPONSE_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_POLLING_RESPONSE_REQ 66
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_req;
+  UWORD8           pol_resp_type;
+  UWORD8           timing_advance;
+  UWORD8           txpwr;
+}
+T_TR_MPHP_POLLING_RESPONSE_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_POLL_DONE
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |                POLL_DONE |"
+   //COND/
+    "#@Fdl7#                          POLL_DONE"
+   End header */
+//ID/
+#define TRL1_L1P_POLL_DONE 67
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1P_POLL_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_ASSIGNMENT_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | ASSIGNMENT_REQ           |              tbf_sti: #@1<0:Not present|l10#           radio_freq: #@2d#"
+    "        |  |  |  |  |                          |          rf_chan_cnt: #@3dl10#        assignment_id: #@4d#"
+    "        |  |  |  |  |                          |   assignment_command: #@5=0:DL TBF|=1:UL TBF|=2:BOTH TBF|~|l10#      multislot_class: #@6d#"
+    "        |  |  |  |  |                          |   interf_meas_enable: #@7=0:NO|=1:YES|~|l10#         pc_meas_chan: #@8=0:BCCH|=1:PDTCH|#"
+    "        |  |  |  |  |                          |    access_burst_type: #@9=0:8 bit|=1:11 bit|~|l10#                   ta: #@10d#"
+    "        |  |  |  |  |                          |             ta_index: #@11dl10#                ta_tn: #@12d#"
+    "        |  |  |  |  |                          |     bts_pwr_ctl_mode: #@14=0:Mode A|=1:Mode B|~|l10#                   p0: #@13 * 2=510:Constant output power mode|#"
+    "        |  |  |  |  |                          |              pr_mode: #@15=0:Mode A|=1:Mode B|~|l10#                  tsc: #@16d#"
+    "        |  |  |  |  |                          |                    h: #@17=0:Single RF|=1:Hopping RF|~|l10#             mac_mode: #@18=0:Dynamic allocation|=1:Extended dynamic|=2:Fixed allocation|=3:Fixed allocation Half Duplex|#"
+    "        |  |  |  |  |                          |   dl_ressource_alloc: #@19bz8#b"
+    "        |  |  |  |  |                          |   ul_ressource_alloc: #@20bz8#b"
+    "        |  |  |  |  |                          |      usf_granularity: #@21=0:1 block|=1:4 blocks|#"
+    "        |  |  |  |  |                          |        ctrl_timeslot: #@22dl10#        bitmap_length: #@23d#"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  ASSIGNMENT_REQ                                                 #@5=0:DL TBF|=1:UL TBF|=2:BOTH TBF|#"
+   End header */
+//ID/
+#define TRL1_MPHP_ASSIGNMENT_REQ 68
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  WORD32           tbf_sti;
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD8           assignment_id;
+  UWORD8           assignment_command;
+  UWORD8           multislot_class;
+  BOOL             interf_meas_enable;
+  BOOL             pc_meas_chan;
+  BOOL             access_burst_type;
+  UWORD8           ta;
+  UWORD8           ta_index;
+  UWORD8           ta_tn;
+  UWORD8           p0;
+  BOOL             bts_pwr_ctl_mode;
+  BOOL             pr_mode;
+  UWORD8           tsc;
+  BOOL             h;
+  UWORD8           mac_mode;
+  UWORD8           dl_ressource_alloc;
+  UWORD8           ul_ressource_alloc;
+  BOOL             usf_granularity;
+  UWORD8           ctrl_timeslot;
+  UWORD8           bitmap_length;
+}
+T_TR_MPHP_ASSIGNMENT_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_REPEAT_UL_FIXED_ALLOC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | REPEAT_UL_FIXED_ALLOC    |              tbf_sti: #@1dl10#    repeat_allocation: #@2=0:CANCEL|=1:REPEAT|#"
+    "        |  |  |  |  |                    _REQ  |          ts_override: #@3x#"
+   //COND/
+    "#@Fdl7#  REPEAT_UL_FIXED_ALLOC_REQ                                      #@2=0:CANCEL|=1:REPEAT|~|#"
+   End header */
+//ID/
+#define TRL1_MPHP_REPEAT_UL_FIXED_ALLOC_REQ 69
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  WORD32           tbf_sti;
+  BOOL             repeat_allocation;
+  UWORD8           ts_override;
+}
+T_TR_MPHP_REPEAT_UL_FIXED_ALLOC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_REPEAT_ALLOC_DONE
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |        REPEAT_ALLOC_DONE |                dl_tn: #@1d#"
+   //COND/
+    "#@Fdl7#                          REPEAT_ALLOC_DONE                      dl_tn: #@1d#"
+   End header */
+//ID/
+#define TRL1_L1P_REPEAT_ALLOC_DONE  70
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           dl_tn;
+}
+T_TR_L1P_REPEAT_ALLOC_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_ALLOC_EXHAUST_DONE
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |       ALLOC_EXHAUST_DONE |                dl_tn: #@1d#"
+   //COND/
+    "#@Fdl7#                          ALLOC_EXHAUST_DONE                     dl_tn: #@1d#"
+   End header */
+//ID/
+#define TRL1_L1P_ALLOC_EXHAUST_DONE 71
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           dl_tn;
+}
+T_TR_L1P_ALLOC_EXHAUST_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_SINGLE_BLOCK_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SINGLE_BLOCK_REQ         |              tbf_sti: #@1<0:Not present|l10#           radio_freq: #@2d#"
+    "        |  |  |  |  |                          |          rf_chan_cnt: #@3dl10#        assignment_id: #@4d#"
+    "        |  |  |  |  |                          |              purpose: #@5=3:DL block|=4:UL block|=5:Two phase access|l16#   pc_meas_chan: #@6=0:BCCH|=1:PDTCH|#"
+    "        |  |  |  |  |                          |    access_burst_type: #@7=0:8 bit|=1:11 bit|~|l10#                   ta: #@8d#"
+    "        |  |  |  |  |                          |     bts_pwr_ctl_mode: #@10=0:Mode A|=1:Mode B|~|l10#                   p0: #@9 * 2=510:Constant output power mode|#"
+    "        |  |  |  |  |                          |              pr_mode: #@11=0:Mode A|=1:Mode B|~|l10#                  tsc: #@12d#"
+    "        |  |  |  |  |                          |                    h: #@13=0:Single RF|=1:Hopping RF|~|l10#      timeslot_number: #@14d#"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#  SINGLE_BLOCK_REQ                                               #@5=3:DL blk|=4:UL blk|=5:Two phase|#"
+   End header */
+//ID/
+#define TRL1_MPHP_SINGLE_BLOCK_REQ 72
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  WORD32           tbf_sti;
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD8           assignment_id;
+  UWORD8           purpose;
+  BOOL             pc_meas_chan;
+  BOOL             access_burst_type;
+  UWORD8           ta;
+  UWORD8           p0;
+  BOOL             bts_pwr_ctl_mode;
+  BOOL             pr_mode;
+  UWORD8           tsc;
+  BOOL             h;
+  UWORD8           timeslot_number;
+}
+T_TR_MPHP_SINGLE_BLOCK_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_SINGLE_BLOCK_CON
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |         SINGLE_BLOCK_CON |        assignment_id: #@1dl10#              purpose: #@2=3:DL block|=4:UL block|=5:Two phase access|l10#"
+    "        |  |  |  |  |                          |               status: #@3=0:no error|=1:STI passed|=2:No valid TA|=3:CRC ERROR|l10#        dl_error_flag: #@4=0:No error|=1:CRC ERROR|#"
+    "        |  |  |  |  |                          |                txpwr: #@5dr5#"
+   //COND/
+    "#@Fdl7#                          SINGLE_BLOCK_CON        #@3=1:STI passed|=2:No valid TA|=3:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1P_SINGLE_BLOCK_CON 73
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           assignment_id;
+  UWORD8           purpose;
+  UWORD8           status;
+  BOOL             dl_error_flag;
+  UWORD8           txpwr[4];
+}
+T_TR_L1P_SINGLE_BLOCK_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_PDCH_RELEASE_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | PDCH_RELEASE_REQ         |        assignment_id: #@1dl10#   timeslot_available: #@2x#"
+   //COND/
+    "#@Fdl7#  PDCH_RELEASE_REQ                                               timeslot_available: #@2x#"
+   End header */
+//ID/
+#define TRL1_MPHP_PDCH_RELEASE_REQ 74
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           assignment_id;
+  UWORD8           timeslot_available;
+}
+T_TR_MPHP_PDCH_RELEASE_REQ;
+
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_TIMING_ADVANCE_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | TIMING_ADVANCE_REQ       |        assignment_id: #@1dl10#                   ta: #@2d#"
+    "        |  |  |  |  |                          |             ta_index: #@3dl10#                ta_tn: #@4d#"
+   //COND/
+    "#@Fdl7#  TIMING_ADVANCE_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_TIMING_ADVANCE_REQ 75
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           assignment_id;
+  UWORD8           ta;
+  UWORD8           ta_index;
+  UWORD8           ta_tn;
+}
+T_TR_MPHP_TIMING_ADVANCE_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_TBF_RELEASE_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | TBF_RELEASE_REQ          |             tbf_type: #@1=0:DL TBF|=1:UL TBF|=2:BOTH TBF|#"
+   //COND/
+    "#@Fdl7#  TBF_RELEASE_REQ                                                tbf_type: #@1=0:DL TBF|=1:UL TBF|=2:BOTH TBF|#"
+   End header */
+//ID/
+#define TRL1_MPHP_TBF_RELEASE_REQ 76
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           tbf_type;
+}
+T_TR_MPHP_TBF_RELEASE_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_START_PCCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | START_PCCCH_REQ          |              imsimod: #@1dl10#                  kcn: #@2d#"
+    "        |  |  |  |  |                          |       split_pg_cycle: #@3dl10#           radio_freq: #@4d#"
+    "        |  |  |  |  |                          |          rf_chan_cnt: #@5dl10#      bs_pag_blks_res: #@6d#"
+    "        |  |  |  |  |                          |        bs_pbcch_blks: #@7dl10#                   pb: - #@8*2d# dBm"
+    "        |  |  |  |  |                          |            page_mode: #@9=0:Normal|=1:Extended|=2:Reorg|l10#                    h: #@10=0:Single RF|=1:Hopping RF|~|l10#"
+    "        |  |  |  |  |                          |          timeslot_no: #@11dl10#                  tsc: #@12d#"
+   //COND/
+    "#@Fdl7#  START_PCCCH_REQ                                                #@9=0:Normal|=1:Extended|=2:Reorg|~|#"
+   End header */
+//ID/
+#define TRL1_MPHP_START_PCCCH_REQ 77
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          imsimod;
+  UWORD16          kcn;
+  UWORD16          split_pg_cycle;
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD8           bs_pag_blks_res;
+  UWORD8           bs_pbcch_blks;
+  UWORD8           pb;
+  UWORD8           page_mode;
+  BOOL             h;
+  UWORD8           timeslot_no;
+  UWORD8           tsc;
+}
+T_TR_MPHP_START_PCCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_PBCCHN_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |              PBCCHN_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |    relative_position: #@5dl10#          input_level: #-@6 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          PBCCHN_INFO             #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1P_PBCCHN_INFO 78
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           relative_position;
+  UWORD8           input_level;
+}
+T_TR_L1P_PBCCHN_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_PNP_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                 PNP_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |    relative_position: #@5dl10#          input_level: #-@6 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          PNP_INFO                #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1P_PNP_INFO 79
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           relative_position;
+  UWORD8           input_level;
+}
+T_TR_L1P_PNP_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_PEP_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |                 PEP_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |    relative_position: #@5dl10#          input_level: #-@6 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          PEP_INFO                #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1P_PEP_INFO 80
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           relative_position;
+  UWORD8           input_level;
+}
+T_TR_L1P_PEP_INFO;
+
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_PALLC_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |               PALLC_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |    relative_position: #@5dl10#          input_level: #-@6 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          PALLC_INFO              #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1P_PALLC_INFO 81
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           relative_position;
+  UWORD8           input_level;
+}
+T_TR_L1P_PALLC_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_PBCCHS_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |              PBCCHS_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |    relative_position: #@5dl10#          input_level: #-@6 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          PBCCHS_INFO             #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1P_PBCCHS_INFO 82
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           relative_position;
+  UWORD8           input_level;
+}
+T_TR_L1P_PBCCHS_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_PACCH_INFO
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |               PACCH_INFO |           error_flag: #@4=0:OK|=1:CRC ERROR|l10#           tpu_offset: #@1d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dl10#                  afc: #@3d#"
+    "        |  |  |  |  |                          |    relative_position: #@5dl10#          input_level: #-@6 / 2f1# dBm"
+   //COND/
+    "#@Fdl7#                          PACCH_INFO              #@4=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_L1P_PACCH_INFO 83
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq;
+  WORD16           afc;
+  BOOL             error_flag;
+  UWORD8           relative_position;
+  UWORD8           input_level;
+}
+T_TR_L1P_PACCH_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_SCELL_PBCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | SCELL_PBCCH_REQ          |           radio_freq: #@1dl10#          rf_chan_cnt: #@2d#"
+    "        |  |  |  |  |                          |              nbr_psi: #@3dl10#        bs_pbcch_blks: #@4d#"
+    "        |  |  |  |  |                          |                   pb: - #@5*2dl5# dBm  psi1_repeat_period: #@6d#"
+    "        |  |  |  |  |                          |                    h: #@7=0:Single RF|=1:Hopping RF|~|l10#          timeslot_no: #@8dl10#"
+    "        |  |  |  |  |                          |                  tsc: #@9d#"
+    "        |  |  |  |  |                          |    relative_position: #@10dr5#"
+   //COND/
+    "#@Fdl7#  SCELL_PBCCH_REQ                                                nbr_psi: #@3dl10#"
+   End header */
+//ID/
+#define TRL1_MPHP_SCELL_PBCCH_REQ 84
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD8           nbr_psi;
+  UWORD8           bs_pbcch_blks;
+  UWORD8           pb;
+  UWORD8           psi1_repeat_period;
+  BOOL             h;
+  UWORD8           timeslot_no;
+  UWORD8           tsc;
+  UWORD8           relative_position_array[20];
+}
+T_TR_MPHP_SCELL_PBCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_CR_MEAS_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | CR_MEAS_REQ              |           nb_carrier: #@1dl10#              list_id: #@2d#"
+   //COND/
+    "#@Fdl7#  CR_MEAS_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_CR_MEAS_REQ 85
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           nb_carrier;
+  UWORD8           list_id;
+}
+T_TR_MPHP_CR_MEAS_REQ;
+
+#define MAX_CR 20
+
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_CR_MEAS_DONE
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |             CR_MEAS_DONE |                nmeas: #@3dl10#              list_id: #@4d#"
+    "        |  |  |  |  |                          |     reporting_period: #@1d#"
+    "        |  |  |  |  |                          |                 freq: #@2dr5#"
+    "        |  |  |  |  |                          |                rxlev: #@5dr5#"
+   //COND/
+    "#@Fdl7#                          CR_MEAS_DONE"
+   End header */
+//ID/
+#define TRL1_L1P_CR_MEAS_DONE 86
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          reporting_period;
+  UWORD16          freq[20];
+  UWORD8           nmeas;
+  UWORD8           list_id;
+  WORD8            rxlev[20];
+}
+T_TR_L1P_CR_MEAS_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_INT_MEAS_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | INT_MEAS_REQ             |           radio_freq: #@1dl10#               rf_chan_cnt: #@2d#"
+    "        |  |  |  |  |                          |                    h: #@3=0:Single RF|=1:Hopping RF|~|l10#               tn: #@4d#"
+    "        |  |  |  |  |                          |      multislot_class: #@5dl10#"
+   //COND/
+    "#@Fdl7#  INT_MEAS_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_INT_MEAS_REQ 87
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  BOOL             h;
+  UWORD8           tn;
+  UWORD8           multislot_class;
+}
+T_TR_MPHP_INT_MEAS_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_INT_MEAS_IND
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  | INT_MEAS_IND             |                rxlev: #@1dr5#"
+    "        |  |  |  |  |                          |                       #@2dr5#"
+   //COND/
+    "#@Fdl7#  INT_MEAS_IND"
+   End header */
+//ID/
+#define TRL1_MPHP_INT_MEAS_IND 88
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  WORD8            rxlev_0[8];
+  WORD8            rxlev_1[8];
+}
+T_TR_MPHP_INT_MEAS_IND;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_TINT_MEAS_IND
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  | TINT_MEAS_IND            |                rxlev: #@1dr5#"
+    "        |  |  |  |  |                          |                       #@2dr5#"
+   //COND/
+    "#@Fdl7#  TINT_MEAS_IND"
+   End header */
+//ID/
+#define TRL1_MPHP_TINT_MEAS_IND 89
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  WORD8            rxlev_0[8];
+  WORD8            rxlev_1[8];
+}
+T_TR_MPHP_TINT_MEAS_IND;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_ITMEAS_IND
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |               ITMEAS_IND |             position: #@1dl10#          meas_bitmap: #@2x#"
+   //COND/
+    "#@Fdl7#                          ITMEAS_IND"
+   End header */
+//ID/
+#define TRL1_L1P_ITMEAS_IND 90
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           position;
+  UWORD8           meas_bitmap;
+}
+T_TR_L1P_ITMEAS_IND;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_NCELL_PBCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | NCELL_PBCCH_REQ          |            fn_offset: #@1dl10#       time_alignment: #@2d#"
+    "        |  |  |  |  |                          |           radio_freq: #@3dl10#          rf_chan_cnt: #@4d#"
+    "        |  |  |  |  |                          |         bcch_carrier: #@5dl10#        bs_pbcch_blks: #@6d#"
+    "        |  |  |  |  |                          |                   pb: - #@7*2dl5# dBm  psi1_repeat_period: #@8d#"
+    "        |  |  |  |  |                          |                    h: #@10=0:Single RF|=1:Hopping RF|~|l10#          timeslot_no: #@11dl10#"
+    "        |  |  |  |  |                          |                  tsc: #@12d#"
+    "        |  |  |  |  |                          |    relative_position: #@9dr5#"
+   //COND/
+    "#@Fdl7#  NCELL_PBCCH_REQ                                                radio_freq: #@3dl10#"
+   End header */
+//ID/
+#define TRL1_MPHP_NCELL_PBCCH_REQ 91
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_offset;
+  UWORD32          time_alignment;
+  UWORD16          radio_freq;
+  UWORD16          rf_chan_cnt;
+  UWORD16          bcch_carrier;
+  UWORD8           bs_pbcch_blks;
+  UWORD8           pb;
+  UWORD8           psi1_repeat_period;
+  UWORD8           relative_position;
+  BOOL             h;
+  UWORD8           timeslot_no;
+  UWORD8           tsc;
+}
+T_TR_MPHP_NCELL_PBCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_UPDATE_PSI_PARAM_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | UPDATE_PSI_PARAM_REQ     |                   pb: - #@1*2dl5# dBm   access_burst_type: #@2=0: 8 bit|=1:11 bit|#"
+   //COND/
+    "#@Fdl7#  UPDATE_PSI_PARAM_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_UPDATE_PSI_PARAM_REQ 92
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           pb;
+  BOOL             access_burst_type;
+}
+T_TR_MPHP_UPDATE_PSI_PARAM_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_TBF_RELEASED
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |             TBF_RELEASED |         released_all: #@1=0:NO|=1:YES|l10#                dl_tn: #@2d#"
+    "        |  |  |  |  |                          |             tbf_type: #@3=0:DL TBF|=1:UL TBF|=2:BOTH TBF|#"
+   //COND/
+    "#@Fdl7#                          TBF_RELEASED                           tbf_type: #@3=0:DL TBF |=1:UL TBF |=2:BOTH TBF|~|#  #@2=1:All released|~|# dl_tn: #@2d#"
+   End header */
+//ID/
+#define TRL1_L1P_TBF_RELEASED 93
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  BOOL             released_all;
+  UWORD8           dl_tn;
+  UWORD8           tbf_type;
+}
+T_TR_L1P_TBF_RELEASED;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_PDCH_RELEASED
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |            PDCH_RELEASED |         assignment_id: #@1dl10#               dl_tn: #@2d#"
+   //COND/
+    "#@Fdl7#                          PDCH_RELEASED                          dl_tn: #@2d#"
+   End header */
+//ID/
+#define TRL1_L1P_PDCH_RELEASED 94
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           assignment_id;
+  UWORD8           dl_tn;
+}
+T_TR_L1P_PDCH_RELEASED;
+
+#define MAX_TCR 10
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_TCR_MEAS_DONE
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |            TCR_MEAS_DONE |              list_id: #@4dl10#           nb_carrier: #@5d#"
+    "        |  |  |  |  |                          |           radio_freq: #@2dr5#"
+    "        |  |  |  |  |                          |            acc_level: #@3dr5#"
+    "        |  |  |  |  |                          |           acc_nbmeas: #@6dr5#"
+    "        |  |  |  |  |                          |           tpu_offset: #@1d#"
+   //COND/
+    "#@Fdl7#                          TCR_MEAS_DONE"
+   End header */
+//ID/
+#define TRL1_L1P_TCR_MEAS_DONE 95
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD16          radio_freq[10];
+  WORD16           acc_level[10];
+  UWORD8           list_id;
+  UWORD8           nb_carrier;
+  UWORD8           acc_nbmeas[10];
+}
+T_TR_L1P_TCR_MEAS_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_ASSIGNMENT_CON
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |           ASSIGNMENT_CON |                dl_tn: #@1d#"
+   //COND/
+    "#@Fdl7#  ASSIGNMENT_CON                                                 dl_tn: #@1d#"
+   End header */
+//ID/
+#define TRL1_MPHP_ASSIGNMENT_CON 96
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           dl_tn;
+}
+T_TR_MPHP_ASSIGNMENT_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_TCR_MEAS_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | TCR_MEAS_REQ             |           nb_carrier: #@1dl10#              list_id: #@2d#"
+   //COND/
+    "#@Fdl7#  TCR_MEAS_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_TCR_MEAS_REQ 97
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           nb_carrier;
+  UWORD8           list_id;
+}
+T_TR_MPHP_TCR_MEAS_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_NETWORK_SYNC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_NETWORK_SYNC_REQ    |"
+   //COND/
+    "#@Fdl7#  STOP_NETWORK_SYNC_REQ"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_NETWORK_SYNC_REQ 98
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_NETWORK_SYNC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_NCELL_PBCCH_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | NCELL_PBCCH_STOP_REQ     |"
+   //COND/
+    "#@Fdl7#  NCELL_PBCCH_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_NCELL_PBCCH_STOP_REQ 99
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHP_NCELL_PBCCH_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_STOP_PCCCH_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_PCCCH_REQ           |"
+   //COND/
+    "#@Fdl7#  STOP_PCCCH_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_STOP_PCCCH_REQ 100
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHP_STOP_PCCCH_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_SCELL_PBCCH_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | SCELL_PBCCH_STOP_REQ     |"
+   //COND/
+    "#@Fdl7#  SCELL_PBCCH_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_SCELL_PBCCH_STOP_REQ 101
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHP_SCELL_PBCCH_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_RA_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | RA_STOP_REQ              |"
+   //COND/
+    "#@Fdl7#  RA_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_RA_STOP_REQ 102
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHP_RA_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_STOP_SINGLE_BLOCK_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_SINGLE_BLOCK_REQ    |"
+   //COND/
+    "#@Fdl7#  STOP_SINGLE_BLOCK_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_STOP_SINGLE_BLOCK_REQ 103
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHP_STOP_SINGLE_BLOCK_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1P_TA_CONFIG_DONE
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  |           TA_CONFIG_DONE |"
+   //COND/
+    "#@Fdl7#                          TA_CONFIG_DONE"
+   End header */
+//ID/
+#define TRL1_L1P_TA_CONFIG_DONE 104
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1P_TA_CONFIG_DONE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_CR_MEAS_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | CR_MEAS_STOP_REQ         |"
+   //COND/
+    "#@Fdl7#  CR_MEAS_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_CR_MEAS_STOP_REQ 105
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHP_CR_MEAS_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_TCR_MEAS_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | TCR_MEAS_STOP_REQ        |"
+   //COND/
+    "#@Fdl7#  TCR_MEAS_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_TCR_MEAS_STOP_REQ 106
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHP_TCR_MEAS_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHP_INT_MEAS_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | INT_MEAS_STOP_REQ        |"
+   //COND/
+    "#@Fdl7#  INT_MEAS_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MPHP_INT_MEAS_STOP_REQ 107
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHP_INT_MEAS_STOP_REQ;
+
+////////////////////
+// AUDIO messages //
+////////////////////
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_KEYBEEP_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | KEYBEEP_START_REQ        |           d_k_x1_kt0: #@1dl10#           d_k_x1_kt1: #@2d#"
+    "        |  |  |  |  |                          |             d_dur_kb: #@3d#"
+   //COND/
+    "#@Fdl7#  KEYBEEP_START_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_KEYBEEP_START_REQ 108
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          d_k_x1_kt0;
+  UWORD16          d_k_x1_kt1;
+  UWORD16          d_dur_kb;
+}
+T_TR_MMI_KEYBEEP_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_KEYBEEP_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | KEYBEEP_START_CON        |"
+   //COND/
+    "#@Fdl7#  KEYBEEP_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_KEYBEEP_START_CON 109
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_KEYBEEP_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_KEYBEEP_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | KEYBEEP_STOP_REQ         |"
+   //COND/
+    "#@Fdl7#  KEYBEEP_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_KEYBEEP_STOP_REQ 110
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_KEYBEEP_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_KEYBEEP_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | KEYBEEP_STOP_CON         |"
+   //COND/
+    "#@Fdl7#  KEYBEEP_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_KEYBEEP_STOP_CON 111
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_KEYBEEP_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_TONE_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | TONE_START_REQ           |            d_k_x1_t0: #@1dl10#            d_k_x1_t1: #@2d#"
+    "        |  |  |  |  |                          |            d_k_x1_t2: #@3dl10#             d_pe_rep: #@4d#"
+    "        |  |  |  |  |                          |             d_pe_off: #@5dl10#             d_se_off: #@6d#"
+    "        |  |  |  |  |                          |             d_bu_off: #@7dl10#"
+    "        |  |  |  |  |                          |              d_t0_on: #@8dl10#             d_t0_off: #@9d#"
+    "        |  |  |  |  |                          |              d_t1_on: #@10dl10#             d_t1_off: #@11d#"
+    "        |  |  |  |  |                          |              d_t2_on: #@12dl10#             d_t2_off: #@13d#"
+   //COND/
+    "#@Fdl7#  TONE_START_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_TONE_START_REQ 112
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          d_k_x1_t0;
+  UWORD16          d_k_x1_t1;
+  UWORD16          d_k_x1_t2;
+  UWORD16          d_pe_rep;
+  UWORD16          d_pe_off;
+  UWORD16          d_se_off;
+  UWORD16          d_bu_off;
+  UWORD16          d_t0_on;
+  UWORD16          d_t0_off;
+  UWORD16          d_t1_on;
+  UWORD16          d_t1_off;
+  UWORD16          d_t2_on;
+  UWORD16          d_t2_off;
+}
+T_TR_MMI_TONE_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_TONE_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | TONE_START_CON           |"
+   //COND/
+    "#@Fdl7#  TONE_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_TONE_START_CON 113
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_TONE_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_TONE_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | TONE_STOP_REQ            |"
+   //COND/
+    "#@Fdl7#  TONE_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_TONE_STOP_REQ 114
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_TONE_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_TONE_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | TONE_STOP_CON            |"
+   //COND/
+    "#@Fdl7#  TONE_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_TONE_STOP_CON 115
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_TONE_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY0_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | MELODY0_START_REQ        |           session_id: #@2dl10#             loopback: #@3=0:NO|=1:YES|~|#"
+    "        |  |  |  |  |                          |    oscillator_bitmap: #@3bz16#"
+   //COND/
+    "#@Fdl7#  MELODY0_START_REQ                                              id: #@2d#"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY0_START_REQ 116
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          oscillator_used_bitmap;
+  UWORD8           session_id;
+  BOOL             loopback;
+}
+T_TR_MMI_MELODY0_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY1_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | MELODY1_START_REQ        |           session_id: #@2dl10#             loopback: #@3=0:NO|=1:YES|~|#"
+    "        |  |  |  |  |                          |    oscillator_bitmap: #@3bz16#"
+   //COND/
+    "#@Fdl7#  MELODY1_START_REQ                                              id: #@2d#"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY1_START_REQ 117
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          oscillator_used_bitmap;
+  UWORD8           session_id;
+  BOOL             loopback;
+}
+T_TR_MMI_MELODY1_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY0_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MELODY0_START_CON        |"
+   //COND/
+    "#@Fdl7#  MELODY0_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY0_START_CON 118
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY0_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY0_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | MELODY0_STOP_REQ         |"
+   //COND/
+    "#@Fdl7#  MELODY0_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY0_STOP_REQ 119
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY0_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY0_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MELODY0_STOP_CON         |"
+   //COND/
+    "#@Fdl7#  MELODY0_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY0_STOP_CON 120
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY0_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY1_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MELODY1_START_CON        |"
+   //COND/
+    "#@Fdl7#  MELODY1_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY1_START_CON 121
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY1_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY1_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | MELODY1_STOP_REQ         |"
+   //COND/
+    "#@Fdl7#  MELODY1_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY1_STOP_REQ 122
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY1_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY1_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MELODY1_STOP_CON         |"
+   //COND/
+    "#@Fdl7#  MELODY1_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY1_STOP_CON 123
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY1_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_PLAY_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | VM_PLAY_START_REQ        |           session_id: #@1d#"
+   //COND/
+    "#@Fdl7#  VM_PLAY_START_REQ                                              id: #@1d#"
+   End header */
+//ID/
+#define TRL1_MMI_VM_PLAY_START_REQ 124
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           session_id;
+}
+T_TR_MMI_VM_PLAY_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_PLAY_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | VM_PLAY_START_CON        |"
+   //COND/
+    "#@Fdl7#  VM_PLAY_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_VM_PLAY_START_CON 125
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_PLAY_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_PLAY_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | VM_PLAY_STOP_REQ         |"
+   //COND/
+    "#@Fdl7#  VM_PLAY_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_VM_PLAY_STOP_REQ 126
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_PLAY_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_PLAY_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | VM_PLAY_STOP_CON         |"
+   //COND/
+    "#@Fdl7#  VM_PLAY_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_VM_PLAY_STOP_CON 127
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_PLAY_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_RECORD_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | VM_RECORD_START_REQ      |           session_id: #@17dl10#             dtx_used: #@18=0:NO|=1:YES|~|#"
+    "        |  |  |  |  |                          |         maximum_size: #@1dl10#            d_k_x1_t0: #@4d#"
+    "        |  |  |  |  |                          |            d_k_x1_t1: #@5dl10#            d_k_x1_t2: #@6d#"
+    "        |  |  |  |  |                          |      record_coeff_dl: #@2dl10#      record_coeff_ul: #@3d#"
+    "        |  |  |  |  |                          |             d_pe_rep: #@7dl10#             d_pe_off: #@8d#"
+    "        |  |  |  |  |                          |             d_se_off: #@9dl10#             d_bu_off: #@10d#"
+    "        |  |  |  |  |                          |              d_t0_on: #@11dl10#             d_t0_off: #@12d#"
+    "        |  |  |  |  |                          |              d_t1_on: #@13dl10#             d_t1_off: #@14d#"
+    "        |  |  |  |  |                          |              d_t2_on: #@15dl10#             d_t2_off: #@16d#"
+   //COND/
+    "#@Fdl7#  VM_RECORD_START_REQ                                            id: #@17d#"
+   End header */
+//ID/
+#define TRL1_MMI_VM_RECORD_START_REQ 128
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          maximum_size;
+  UWORD16          record_coeff_dl;
+  UWORD16          record_coeff_ul;
+  UWORD16          d_k_x1_t0;
+  UWORD16          d_k_x1_t1;
+  UWORD16          d_k_x1_t2;
+  UWORD16          d_pe_rep;
+  UWORD16          d_pe_off;
+  UWORD16          d_se_off;
+  UWORD16          d_bu_off;
+  UWORD16          d_t0_on;
+  UWORD16          d_t0_off;
+  UWORD16          d_t1_on;
+  UWORD16          d_t1_off;
+  UWORD16          d_t2_on;
+  UWORD16          d_t2_off;
+  UWORD8           session_id;
+  BOOL             dtx_used;
+}
+T_TR_MMI_VM_RECORD_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_RECORD_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | VM_RECORD_START_CON      |"
+   //COND/
+    "#@Fdl7#  VM_RECORD_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_VM_RECORD_START_CON 129
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_RECORD_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_RECORD_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | VM_RECORD_STOP_REQ       |"
+   //COND/
+    "#@Fdl7#  VM_RECORD_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_VM_RECORD_STOP_REQ 130
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_RECORD_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_RECORD_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | VM_RECORD_STOP_CON       |"
+   //COND/
+    "#@Fdl7#  VM_RECORD_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_VM_RECORD_STOP_CON 131
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_RECORD_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_AMR_PLAY_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | VM_AMR_PLAY_START_REQ    |           session_id: #@1d#"
+   //COND/
+    "#@Fdl7#  VM_AMR_PLAY_START_REQ                                          id: #@1d#"
+   End header */
+//ID/
+#define TRL1_MMI_VM_AMR_PLAY_START_REQ 209
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           session_id;
+}
+T_TR_MMI_VM_AMR_PLAY_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_AMR_PLAY_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | VM_AMR_PLAY_START_CON    |"
+   //COND/
+    "#@Fdl7#  VM_AMR_PLAY_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_VM_AMR_PLAY_START_CON 210
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_AMR_PLAY_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_AMR_PLAY_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | VM_AMR_PLAY_STOP_REQ     |"
+   //COND/
+    "#@Fdl7#  VM_AMR_PLAY_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_VM_AMR_PLAY_STOP_REQ 211
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_AMR_PLAY_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_AMR_PLAY_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | VM_AMR_PLAY_STOP_CON     |"
+   //COND/
+    "#@Fdl7#  VM_AMR_PLAY_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_VM_AMR_PLAY_STOP_CON 212
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_AMR_PLAY_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_AMR_RECORD_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | VM_AMR_RECORD_START_REQ  |           session_id: #@3dl10#              dtx_used: #@5=0:NO|=1:YES|~|#"
+    "        |  |  |  |  |                          |         maximum_size: #@1dl10#       record_coeff_ul: #@2d#"
+    "        |  |  |  |  |                          |          amr_vocoder: #@4dl10#"
+   //COND/
+    "#@Fdl7#  VM_AMR_RECORD_START_REQ                                        id: #@3d# vocoder: #@4d#"
+   End header */
+//ID/
+#define TRL1_MMI_VM_AMR_RECORD_START_REQ 213
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          maximum_size;
+  UWORD16          record_coeff_ul;
+  UWORD8           session_id;
+  UWORD8           amr_vocoder;
+  BOOL             dtx_used;
+}
+T_TR_MMI_VM_AMR_RECORD_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_AMR_RECORD_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | VM_AMR_RECORD_START_CON  |"
+   //COND/
+    "#@Fdl7#  VM_AMR_RECORD_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_VM_AMR_RECORD_START_CON 214
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_AMR_RECORD_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_AMR_RECORD_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | VM_AMR_RECORD_STOP_REQ   |"
+   //COND/
+    "#@Fdl7#  VM_AMR_RECORD_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_VM_AMR_RECORD_STOP_REQ 215
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_AMR_RECORD_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_VM_AMR_RECORD_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | VM_AMR_RECORD_STOP_CON   |"
+   //COND/
+    "#@Fdl7#  VM_AMR_RECORD_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_VM_AMR_RECORD_STOP_CON 216
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_VM_AMR_RECORD_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_ENROLL_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SR_ENROLL_START_REQ      |          database_id: #@2dl10#           word_index: #@3d#"
+    "        |  |  |  |  |                          |               speech: #@4=0:NO|=1:YES|~|l10#       speech_address: #@1x#"
+   //COND/
+    "#@Fdl7#  SR_ENROLL_START_REQ                                            id: #@2dl10#"
+   End header */
+//ID/
+#define TRL1_MMI_SR_ENROLL_START_REQ 132
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          speech_address;
+  UWORD8           database_id;
+  UWORD8           word_index;
+  BOOL             speech;
+}
+T_TR_MMI_SR_ENROLL_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_ENROLL_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | SR_ENROLL_START_CON      |"
+   //COND/
+    "#@Fdl7#  SR_ENROLL_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_SR_ENROLL_START_CON 133
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_SR_ENROLL_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_ENROLL_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | SR_ENROLL_STOP_REQ       |"
+   //COND/
+    "#@Fdl7#  SR_ENROLL_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_SR_ENROLL_STOP_REQ 134
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_SR_ENROLL_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_ENROLL_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  | SR_ENROLL_STOP_CON       |             error_id: #@1=0:No error|=1:Bad acquisition|=2:Timeout|#"
+   //COND/
+    "#@Fdl7#  SR_ENROLL_STOP_CON                              #@1=1:Bad acquisition|=2:Timeout|~|#"
+   End header */
+//ID/
+#define TRL1_MMI_SR_ENROLL_STOP_CON 135
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           error_id;
+}
+T_TR_MMI_SR_ENROLL_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_UPDATE_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SR_UPDATE_START_REQ      |          database_id: #@2dl10#           word_index: #@3d#"
+    "        |  |  |  |  |                          |               speech: #@4=0:NO|=1:YES|~|l10#       speech_address: #@1x#"
+   //COND/
+    "#@Fdl7#  SR_UPDATE_START_REQ                                            id: #@2dl10#"
+   End header */
+//ID/
+#define TRL1_MMI_SR_UPDATE_START_REQ 136
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          *speech_address;
+  UWORD8           database_id;
+  UWORD8           word_index;
+  BOOL             speech;
+}
+T_TR_MMI_SR_UPDATE_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_UPDATE_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | SR_UPDATE_STOP_REQ       |"
+   //COND/
+    "#@Fdl7#  SR_UPDATE_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_SR_UPDATE_STOP_REQ 137
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_SR_UPDATE_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_UPDATE_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | SR_UPDATE_START_CON      |"
+   //COND/
+    "#@Fdl7#  SR_UPDATE_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_SR_UPDATE_START_CON 138
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_SR_UPDATE_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_UPDATE_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  | SR_UPDATE_STOP_CON       |             error_id: #@1=0:No error|=1:Bad acquisition|=2:Timeout|=3:Bad update|#"
+   //COND/
+    "#@Fdl7#  SR_UPDATE_STOP_CON                              #@1=1:Bad acquisition|=2:Timeout|=3:Bad update|~|#"
+   End header */
+//ID/
+#define TRL1_MMI_SR_UPDATE_STOP_CON 139
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           error_id;
+}
+T_TR_MMI_SR_UPDATE_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_RECO_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SR_RECO_START_REQ        |          database_id: #@1dl10#      vocabulary_size: #@2d#"
+   //COND/
+    "#@Fdl7#  SR_RECO_START_REQ                                              id: #@1d#"
+   End header */
+//ID/
+#define TRL1_MMI_SR_RECO_START_REQ 140
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           database_id;
+  UWORD8           vocabulary_size;
+}
+T_TR_MMI_SR_RECO_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_RECO_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | SR_RECO_STOP_REQ         |"
+   //COND/
+    "#@Fdl7#  SR_RECO_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_SR_RECO_STOP_REQ 141
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_SR_RECO_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_RECO_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | SR_RECO_START_CON        |"
+   //COND/
+    "#@Fdl7#  SR_RECO_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_SR_RECO_START_CON 142
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_SR_RECO_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_RECO_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  | SR_RECO_STOP_CON         |             error_id: #@12=0:No error|=1:Bad acquisition|=2:Timeout|=3:Bad recognition|=4:CTO word|l10#  d_sr_model_size: #@11d#"
+    "        |  |  |  |  |                          |      best_word_score: #@1dl10#  2nd_best_word_score: #@2d#"
+    "        |  |  |  |  |                          |  3rd_best_word_score: #@3dl10#  4th_best_word_score: #@4d#"
+    "        |  |  |  |  |                          |      best_word_index: #@5dl10#  2nd_best_word_index: #@6d#"
+    "        |  |  |  |  |                          |  3rd_best_word_index: #@7dl10#  4th_best_word_index: #@8d#"
+    "        |  |  |  |  |                          |        d_sr_db_level: #@9dl10#        d_sr_db_noise: #@10d#"
+   //COND/
+    "#@Fdl7#  SR_RECO_STOP_CON                                #@12=1:Bad acquisition|=2:Timeout|=3:Bad recognition|=4:CTO word|~|#"
+   End header */
+//ID/
+#define TRL1_MMI_SR_RECO_STOP_CON 143
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          best_word_score;
+  UWORD32          second_best_word_score;
+  UWORD32          third_best_word_score;
+  UWORD32          fourth_best_word_score;
+  UWORD16          best_word_index;
+  UWORD16          second_best_word_index;
+  UWORD16          third_best_word_index;
+  UWORD16          fourth_best_word_index;
+  UWORD16          d_sr_db_level;
+  UWORD16          d_sr_db_noise;
+  UWORD16          d_sr_model_size;
+  UWORD8           error_id;
+}
+T_TR_MMI_SR_RECO_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_UPDATE_CHECK_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SR_UPDATE_CHECK_START    |          database_id: #@3dl10#           word_index: #@4d#"
+    "        |  |  |  |  |                     _REQ |               speech: #@5dl10#      vocabulary_size: #@6d#"
+    "        |  |  |  |  |                          |        model_address: #@1dl10#       speech_address: #@2d#"
+   //COND/
+    "#@Fdl7#  SR_UPDATE_CHECK_START_REQ                                      id: #@3dl10#"
+   End header */
+//ID/
+#define TRL1_MMI_SR_UPDATE_CHECK_START_REQ 144
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          model_address;
+  UWORD32          speech_address;
+  UWORD8           database_id;
+  UWORD8           word_index;
+  BOOL             speech;
+  UWORD8           vocabulary_size;
+}
+T_TR_MMI_SR_UPDATE_CHECK_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_UPDATE_CHECK_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | SR_UPDATE_CHECK_STOP_REQ |"
+   //COND/
+    "#@Fdl7#  SR_UPDATE_CHECK_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_SR_UPDATE_CHECK_STOP_REQ 145
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_SR_UPDATE_CHECK_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_UPDATE_CHECK_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | SR_UPDATE_CHECK_START    |"
+    "        |  |  |  |  |                     _CON |"
+   //COND/
+    "#@Fdl7#  SR_UPDATE_CHECK_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_SR_UPDATE_CHECK_START_CON 146
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_SR_UPDATE_CHECK_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_SR_UPDATE_CHECK_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  | SR_UPDATE_CHECK_STOP_CON |             error_id: #@12=0:No error|=1:Bad acquisition|=2:Timeout|=3:Bad recognition|=4:CTO word|l10#  d_sr_model_size: #@11d#"
+    "        |  |  |  |  |                          |      best_word_score: #@1dl10#  2nd_best_word_score: #@2d#"
+    "        |  |  |  |  |                          |  3rd_best_word_score: #@3dl10#  4th_best_word_score: #@4d#"
+    "        |  |  |  |  |                          |      best_word_index: #@5dl10#  2nd_best_word_index: #@6d#"
+    "        |  |  |  |  |                          |  3rd_best_word_index: #@7dl10#  4th_best_word_index: #@8d#"
+    "        |  |  |  |  |                          |        d_sr_db_level: #@9dl10#        d_sr_db_noise: #@10d#"
+   //COND/
+    "#@Fdl7#  SR_UPDATE_CHECK_STOP_CON                        #@12=1:Bad acquisition|=2:Timeout|=3:Bad recognition|=4:CTO word|~|#"
+   End header */
+//ID/
+#define TRL1_MMI_SR_UPDATE_CHECK_STOP_CON 147
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          best_word_score;
+  UWORD32          second_best_word_score;
+  UWORD32          third_best_word_score;
+  UWORD32          fourth_best_word_score;
+  UWORD16          best_word_index;
+  UWORD16          second_best_word_index;
+  UWORD16          third_best_word_index;
+  UWORD16          fourth_best_word_index;
+  UWORD16          d_sr_db_level;
+  UWORD16          d_sr_db_noise;
+  UWORD16          d_sr_model_size;
+  UWORD8           error_id;
+}
+T_TR_MMI_SR_UPDATE_CHECK_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_SRBACK_SAVE_DATA_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SRBACK_SAVE_DATA_REQ     |          database_id: #@6dl10#          model_index: #@7d#"
+    "        |  |  |  |  |                          |    model_RAM_address: #@1xl10#               speech: #@8=0:No|=1:Yes|#"
+    "        |  |  |  |  |                          |         start_buffer: #@2xl10#          stop_buffer: #@3x#"
+    "        |  |  |  |  |                          |        start_address: #@4xl10#         stop_address: #@5x#"
+   //COND/
+    "#@Fdl7#  SRBACK_SAVE_DATA_REQ                                           id: #@6d#"
+   End header */
+//ID/
+#define TRL1_L1_SRBACK_SAVE_DATA_REQ 148
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          model_RAM_address;
+  UWORD32          start_buffer;
+  UWORD32          stop_buffer;
+  UWORD32          start_address;
+  UWORD32          stop_address;
+  UWORD8           database_id;
+  UWORD8           model_index;
+  BOOL             speech;
+}
+T_TR_L1_SRBACK_SAVE_DATA_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_SRBACK_SAVE_DATA_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | SRBACK_SAVE_DATA_CON     |"
+   //COND/
+    "#@Fdl7#  SRBACK_SAVE_DATA_CON"
+   End header */
+//ID/
+#define TRL1_L1_SRBACK_SAVE_DATA_CON 149
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1_SRBACK_SAVE_DATA_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_SRBACK_LOAD_MODEL_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SRBACK_LOAD_MODEL_REQ    |          database_id: #@2dl10#          model_index: #@3d#"
+    "        |  |  |  |  |                          |           CTO_enable: #@4=0:No|=1:Yes|l10#    model_RAM_address: #@1x#"
+   //COND/
+    "#@Fdl7#  SRBACK_LOAD_MODEL_REQ                                          id: #@2d#"
+   End header */
+//ID/
+#define TRL1_L1_SRBACK_LOAD_MODEL_REQ 150
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          model_RAM_address;
+  UWORD8           database_id;
+  UWORD8           model_index;
+  BOOL             CTO_enable;
+}
+T_TR_L1_SRBACK_LOAD_MODEL_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_SRBACK_LOAD_MODEL_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | SRBACK_LOAD_MODEL_CON    |"
+   //COND/
+    "#@Fdl7#  SRBACK_LOAD_MODEL_CON"
+   End header */
+//ID/
+#define TRL1_L1_SRBACK_LOAD_MODEL_CON 151
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1_SRBACK_LOAD_MODEL_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_SRBACK_TEMP_SAVE_DATA_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | SRBACK_TEMP_SAVE_DATA    | model_RAM_addr_input: #@1xl10# model_RAM_add_output: #@2x#"
+    "        |  |  |  |  |                     _REQ |"
+   //COND/
+    "#@Fdl7#  SRBACK_TEMP_SAVE_DATA_REQ"
+   End header */
+//ID/
+#define TRL1_L1_SRBACK_TEMP_SAVE_DATA_REQ 152
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          model_RAM_address_input;
+  UWORD32          model_RAM_address_output;
+}
+T_TR_L1_SRBACK_TEMP_SAVE_DATA_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_SRBACK_TEMP_SAVE_DATA_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | SRBACK_TEMP_SAVE_DATA    |"
+    "        |  |  |  |  |                     _CON |"
+   //COND/
+    "#@Fdl7#  SRBACK_TEMP_SAVE_DATA_CON"
+   End header */
+//ID/
+#define TRL1_L1_SRBACK_TEMP_SAVE_DATA_CON 153
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1_SRBACK_TEMP_SAVE_DATA_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_AEC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | AEC_REQ                  |          aec_control: #@1bz16#    cont_filter: #@2h#"
+    "#@Fdl7# |  |  |  |  |                          |      granularity_att: #@3xl10#          coef_smooth: #@4h#"
+    "#@Fdl7# |  |  |  |  |                          |         es_level_max: #@5xl10#             fact_vad: #@6h#"
+    "#@Fdl7# |  |  |  |  |                          |             thrs_abs: #@6xl10#         fact_asd_fil: #@8h#"
+    "#@Fdl7# |  |  |  |  |                          |         fact_asd_mut: #@9xl10#"
+   //COND/
+    "#@Fdl7#  AEC_REQ                                                        aec_control: #@1h#"
+   End header */
+//ID/
+#define TRL1_MMI_AEC_REQ 154
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          aec_control;
+  UWORD16          cont_filter;
+  UWORD16          granularity_att;
+  UWORD16          coef_smooth;
+  UWORD16          es_level_max;
+  UWORD16          fact_vad;
+  UWORD16          thrs_abs;
+  UWORD16          fact_asd_fil;
+  UWORD16          fact_asd_mut;
+}
+T_TR_MMI_AEC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_AEC_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | AEC_CON                  |"
+   //COND/
+    "#@Fdl7#  AEC_CON"
+   End header */
+//ID/
+#define TRL1_MMI_AEC_CON 155
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_AEC_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_AUDIO_FIR_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | AUDIO_FIR_REQ            |           update_fir: #@4=1:DL|=2:UL|=3:DL+UL|l10#             fir_loop: #@3=0:NO|=1:Yes|~|#"
+    "        |  |  |  |  |                          |   fir_ul_coefficient: #@1xl10#   fir_dl_coefficient: #@2x#"
+   //COND/
+    "#@Fdl7#  AUDIO_FIR_REQ                                                  #@4=1:DL|=2:UL|=3:DL+UL|#"
+   End header */
+//ID/
+#define TRL1_MMI_AUDIO_FIR_REQ 156
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fir_ul_coefficient;
+  UWORD32          fir_dl_coefficient;
+  BOOL             fir_loop;
+  UWORD8           update_fir;
+}
+T_TR_MMI_AUDIO_FIR_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_AUDIO_FIR_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | AUDIO_FIR_CON            |"
+   //COND/
+    "#@Fdl7#  AUDIO_FIR_CON"
+   End header */
+//ID/
+#define TRL1_MMI_AUDIO_FIR_CON 157
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_AUDIO_FIR_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_AUDIO_MODE_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | AUDIO_MODE_REQ           |           audio_mode: #@1=0:GSM only|=1:BT cordless mode|=2:BT headset mode|#"
+   //COND/
+    "#@Fdl7#  AUDIO_MODE_REQ                                                 #@1=0:GSM only|=1:BT cordless mode|=2:BT headset mode|#"
+   End header */
+//ID/
+#define TRL1_MMI_AUDIO_MODE_REQ 158
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          audio_mode;
+}
+T_TR_MMI_AUDIO_MODE_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_AUDIO_MODE_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | AUDIO_MODE_CON           |"
+   //COND/
+    "#@Fdl7#  AUDIO_MODE_CON"
+   End header */
+//ID/
+#define TRL1_MMI_AUDIO_MODE_CON 159
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_AUDIO_MODE_CON;
+
+////////////////
+// Debug info //
+////////////////
+
+// L1S debug
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ PM EQUAL 0
+   //ERROR/ PM,@8=1
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  | *** |           PM = 0 #@8=1:(begin)|=0:(end)|l7# |           tpu_offset: #@1dl10#        tpu_offset_hw: #@2d#"
+    "        |  |  |  |  |                          |              d_debug: #@3dl10#           debug_time: #@4d#"
+    "        |  |  |  |  |                          |             adc_mode: #@5dl10#                 task: #@6t#"
+    "        |  |  |  |  |                          |           no_pm_task: #@7t#"
+   //COND/
+    "#@Fdl7#                                                  PM=0 #@8=0:(end)|=1:(begin)|#"
+   End header */
+//ID/
+#define TRL1_PM_EQUAL_0 160
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD32          tpu_offset_hw;
+  UWORD16          d_debug;
+  UWORD16          debug_time;
+  UWORD16          adc_mode;
+  UWORD8           task;
+  UWORD8           no_pm_task;
+  BOOL             error;
+}
+T_TR_PM_EQUAL_0;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MCU DSP COM mismatch
+   //ERROR/ COM,@7=1
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  | *** | MCU/DSP Mismatch #@7=1:(begin)|=0:(end)|l7# |           tpu_offset: #@1dl10#        tpu_offset_hw: #@2d#"
+    "        |  |  |  |  |                          |              d_debug: #@3dl10#           debug_time: #@4d#"
+    "        |  |  |  |  |                          |             adc_mode: #@5dl10#                 task: #@6t#"
+   //COND/
+    "#@Fdl7#                                                  COM #@7=0:(end)|=1:(begin)|#"
+   End header */
+//ID/
+#define TRL1_MCU_DSP_MISMATCH 161
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD32          tpu_offset_hw;
+  UWORD16          d_debug;
+  UWORD16          debug_time;
+  UWORD16          adc_mode;
+  UWORD8           task;
+  BOOL             error;
+}
+T_TR_MCU_DSP_MISMATCH;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1S ABORT
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  O  |                    ABORT |           tpu_offset: #@1dl10#        tpu_offset_hw: #@2d#"
+    "        |  |  |  |  |                          |              d_debug: #@3dl10#           debug_time: #@4d#"
+    "        |  |  |  |  |                          |             adc_mode: #@5dl10#                 task: #@6t#"
+   //COND/
+    "#@Fdl7#                          L1S ABORT"
+   End header */
+//ID/
+#define TRL1_L1S_ABORT 162
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          tpu_offset;
+  UWORD32          tpu_offset_hw;
+  UWORD16          d_debug;
+  UWORD16          debug_time;
+  UWORD16          adc_mode;
+  UWORD8           task;
+}
+T_TR_L1S_ABORT;
+
+// DSP error
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ D_ERROR_STATUS
+   //ERROR/ DSP,@2!0
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  | ***  D_ERROR_STATUS #@2=0:(end)|!0:(begin)|l7# |           debug_time: #@1dl10#       d_error_status: #@2x#"
+    "        |  |  |  |  |                          |              d_debug: #@3d#"
+   //COND/
+    "#@Fdl7#                                                  D_ERROR_STATUS #@2=0:(end)|!0:(begin)|#"
+   End header */
+//ID/
+#define TRL1_D_ERROR_STATUS 163
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          debug_time;
+  UWORD16          d_error_status;
+  UWORD16          d_debug;
+}
+T_TR_D_ERROR_STATUS;
+
+// DSP trace
+
+/***********************************************************************************************************/
+/* Special trace: display is implemented in the trace decoder
+ */
+#define TRL1_DSP_DEBUG_HEADER 164
+
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          debug_time;
+  UWORD16          patch_version;
+  UWORD16          trace_level;
+}
+T_TR_DSP_DEBUG_HEADER;
+
+/***********************************************************************************************************/
+/* Special trace: display is implemented in the trace decoder
+ */
+#define TRL1_DSP_DEBUG_BUFFER 165
+
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          size;
+  UWORD16          content[1];
+}
+T_TR_DSP_DEBUG_BUFFER;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ RLC_UL_PARAM
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |<....|  | RLC_UL                   |            a_pu_gprs: #@1xl10#            a_du_gprs: #@2x#"
+    "        |  |  |  |  |                          |                   fn: #@3dl10#        assignment_id: #@4d#"
+    "        |  |  |  |  |                          |                tx_no: #@5dl10#                   ta: #@6d#"
+    "        |  |  |  |  |                          |    fix_alloc_exhaust: #@7=0:No|=1:Yes|l10#"
+   //COND/
+    "#@Fdl7#                          RLC_UL"
+   End header */
+//ID/
+#define TRL1_RLC_UL_PARAM 166
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          a_pu_gprs;
+  UWORD32          a_du_gprs;
+  UWORD32          fn_param;
+  UWORD8           assignment_id;
+  UWORD8           tx_no;
+  UWORD8           ta;
+  BOOL             fix_alloc_exhaust;
+}
+T_TR_RLC_UL_PARAM;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ RLC_DL_PARAM
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |<....|  | RLC_DL                   |                   fn: #@1dl10#  d_rlcmac_rx_no_gprs: #@2x#"
+    "        |  |  |  |  |                          |        assignment_id: #@3dl10#                rx_no: #@4d#"
+    "        |  |  |  |  |                          |      rlc_blocks_sent: #@5dl10#   last_poll_response: #@6bz8#"
+   //COND/
+    "#@Fdl7#                          RLC_DL"
+   End header */
+//ID/
+#define TRL1_RLC_DL_PARAM 167
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          fn_param;
+  UWORD32          d_rlcmac_rx_no_gprs;
+  UWORD8           assignment_id;
+  UWORD8           rx_no;
+  UWORD8           rlc_blocks_sent;
+  UWORD8           last_poll_response;
+}
+T_TR_RLC_DL_PARAM;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ FORBIDDEN_UPLINK
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  | *** |                          | UL block transmitted while forbidden (no TA)"
+   //COND/
+    "#@Fdl7#                                                  TX while no TA"
+   End header */
+//ID/
+#define TRL1_FORBIDDEN_UPLINK 168
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_FORBIDDEN_UPLINK;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ DL_PTCCH
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  |<-|                 DL PTCCH |            crc_error: #@1=0:OK|=1:ERROR|l10#           ordered_ta: #@2d#"
+   //COND/
+    "#@Fdl7#                          DL PTCCH                #@1=1:CRC ERROR|~|#"
+   End header */
+//ID/
+#define TRL1_DL_PTCCH 169
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           crc_error;
+  UWORD8           ordered_ta;
+}
+T_TR_DL_PTCCH;
+
+/***********************************************************************************************************/
+/* Special trace: display is implemented in the trace decoder
+ */
+#define TRL1_CONDENSED_PDTCH 170
+
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           rx_allocation;
+  UWORD8           tx_allocation;
+  UWORD8           blk_status;
+  UWORD8           dl_cs_type;
+  UWORD8           dl_status[4];
+  UWORD8           ul_status[4];
+}
+T_TR_CONDENSED_PDTCH;
+
+///////////////////
+// OML1 messages //
+///////////////////
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ OML1_CLOSE_TCH_LOOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | CLOSE_TCH_LOOP_REQ       |          sub_channel: #@1dl10#        frame_erasure: loop #@2=0:A|=1:B|=2:C|=3:D|=4:E|=5:F|#"
+   //COND/
+    "------------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7#  CLOSE_TCH_LOOP_REQ                                             loop #@2=0:A|=1:B|=2:C|=3:D|=4:E|=5:F|#"
+   End header */
+//ID/
+#define TRL1_OML1_CLOSE_TCH_LOOP_REQ 171
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           sub_channel;
+  UWORD8           frame_erasure;
+}
+T_TR_OML1_CLOSE_TCH_LOOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ OML1_OPEN_TCH_LOOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | OPEN_TCH_LOOP_REQ        |"
+   //COND/
+    "------------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7#  OPEN_TCH_LOOP_REQ"
+   End header */
+//ID/
+#define TRL1_OML1_OPEN_TCH_LOOP_REQ 172
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_OML1_OPEN_TCH_LOOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ OML1_START_DAI_TEST_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | START_DAI_TEST_REQ       |        tested_device: #@1=0:no test|=1:speech decoder|=2:speech encoder|=3:no test|=4:acoustic devices|#"
+   //COND/
+    "------------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7#  START_DAI_TEST_REQ"
+   End header */
+//ID/
+#define TRL1_OML1_START_DAI_TEST_REQ 173
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           tested_device;
+}
+T_TR_OML1_START_DAI_TEST_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ OML1_STOP_DAI_TEST_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "================================================================================================================================================================"
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_DAI_TEST_REQ        |"
+   //COND/
+    "------------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7#  STOP_DAI_TEST_REQ"
+   End header */
+//ID/
+#define TRL1_OML1_STOP_DAI_TEST_REQ 174
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_OML1_STOP_DAI_TEST_REQ;
+
+///////////////////
+// Test messages //
+///////////////////
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ TST_TEST_HW_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | TEST_HW_REQ              |"
+   //COND/
+    "#@Fdl7#  TEST_HW_REQ"
+   End header */
+//ID/
+#define TRL1_TST_TEST_HW_REQ 175
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_TST_TEST_HW_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_TEST_HW_INFO
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |             TEST_HW_INFO |   *******************************************"
+    "        |  |  |  |  |                          |   *   DSP  code version: #@1xr4#h              *"
+    "        |  |  |  |  |                          |   *            checksum: #@2xr4#h              *"
+    "        |  |  |  |  |                          |   *       patch version: #@3xr4#h              *"
+    "        |  |  |  |  |                          |   *   MCU  code version: l1_#@4xr4#_#@5xr4#_#@6xr4#  *"
+    "        |  |  |  |  |                          |   *         d_checksum1: #@7xr4#h              *"
+    "        |  |  |  |  |                          |   *         d_checksum2: #@8xr4#h              *"
+    "        |  |  |  |  |                          |   *******************************************"
+   //COND/
+    ""
+    ""
+    "#@Fdl7#                          TEST_HW_INFO                           DSP #@1x#h #@2x#h #@3x#h"
+    "                                                                        MCU l1_#@4xr4#_#@5xr4#_#@6xr4#"
+   End header */
+//ID/
+#define TRL1_L1_TEST_HW_INFO 176
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          dsp_code_version;
+  UWORD16          dsp_checksum;
+  UWORD16          dsp_patch_version;
+  UWORD16          mcu_alr_version;
+  UWORD16          mcu_gprs_version;
+  UWORD16          mcu_tm_version;
+  UWORD16          d_checksum1;
+  UWORD16          d_checksum2;
+}
+T_TR_L1_TEST_HW_INFO;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ TST_SLEEP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | TST_SLEEP_REQ            |               clocks: #@1bz16#     sleep_mode: #@2=0:Off|=1:small|=2:big|=3:deep|=4:all|#"
+   //COND/
+    "#@Fdl7#  TST_SLEEP_REQ"
+   End header */
+//ID/
+#define TRL1_TST_SLEEP_REQ 177
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          clocks;
+  UWORD8           sleep_mode;
+}
+T_TR_TST_SLEEP_REQ;
+
+//////////////////
+// ADC messages //
+//////////////////
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_ADC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | ADC_REQ                  |"
+   //COND/
+    "#@Fdl7#  ADC_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_ADC_REQ 178
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_ADC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_STOP_ADC_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | STOP_ADC_REQ             |"
+   //COND/
+    "#@Fdl7#  STOP_ADC_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_STOP_ADC_REQ 179
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_STOP_ADC_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_STOP_ADC_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | STOP_ADC_CON             |"
+   //COND/
+    "#@Fdl7#  STOP_ADC_CON"
+   End header */
+//ID/
+#define TRL1_MMI_STOP_ADC_CON 180
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_STOP_ADC_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_AEC_IND
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |<-|  |               L1_AEC_IND |             es_level: #@3h#"
+    "        |  |  |  |  |                          |          far_end_pow: #@1h10#        far_end_noise: #@2h#"
+   //COND/
+    "#@Fdl7#  L1_AEC_IND"
+   End header */
+//ID/
+#define TRL1_L1_AEC_IND 208
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          far_end_pow;
+  UWORD32          far_end_noise;
+  UWORD16          es_level;
+}
+T_TR_L1_AEC_IND;
+
+//////////////
+// CPU load //
+//////////////
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1S CPU peak
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |  O  |                          | CPU #@1dr2# %"
+    "        |  |  |  |  |                          |"
+   //COND/
+    "#@Fdl7#                                                                                L1S CPU #@1d# %"
+   End header */
+//ID/
+#define TRL1_L1S_CPU_PEAK 181
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           max_cpu;
+}
+T_TR_L1S_CPU_PEAK;
+
+////////////////////////////////
+// Trace configuration change //
+////////////////////////////////
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ Trace configuration change
+   //FULL/
+    ""
+    "*********************************************************************************************************************************************************************************"
+    "                                                         trace config: #@1x#"
+    "#@Fdl7#   Trace configuration change                    RTT config: #@2x#"
+    "                                                            RTT event: #@3x#"
+    "*********************************************************************************************************************************************************************************"
+    ""
+   //COND/
+    ""
+    "******************************************************************************************************************"
+    "#@Fdl7#  Trace config change: #@1xl2#  RTT (#@2xl2#) #@3x#"
+    "******************************************************************************************************************"
+    ""
+   End header */
+//ID/
+#define TRL1_TRACE_CONFIG_CHANGE 182
+//STRUCT/
+typedef struct
+{
+  UWORD32        header;
+//--------------------------------------------------
+  UWORD32        trace_config;
+  UWORD32        rtt_cell_enable[8];
+  UWORD32        rtt_event;
+}
+T_TR_TRACE_CONFIG_CHANGE;
+
+/***********************************************************************************************************/
+/* Special trace: display is implemented in the trace decoder
+ */
+#define TRL1_ASCII 183
+
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          size;
+  char             str[1];
+}
+T_TR_ASCII;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ IT_DSP_ERROR
+   //ERROR/ IT
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  | *** |             IT DSP ERROR |"
+   //COND/
+    "#@Fdl7#                                                  IT DSP ERROR"
+   End header */
+//ID/
+#define TRL1_IT_DSP_ERROR 185
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_IT_DSP_ERROR;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ ADC
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  O  |                      ADC |                 type: #@1=0:RX|=1:TX|#"
+   //COND/
+    "#@Fdl7#                          ADC"
+   End header */
+//ID/
+#define TRL1_ADC 186
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           type;
+}
+T_TR_ADC;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ New TOA
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  O  |                  New TOA |            toa_shift: #@1d#"
+   //COND/
+    "#@Fdl7#                          New TOA"
+   End header */
+//ID/
+#define TRL1_NEW_TOA 187
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  WORD16           toa_shift;
+}
+T_TR_NEW_TOA;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ TOA not updated
+   //ERROR/ TOA
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  | *** |          TOA not updated |            toa_shift: #@1d#"
+   //COND/
+    "#@Fdl7#                                                  TOA not updated"
+   End header */
+//ID/
+#define TRL1_TOA_NOT_UPDATED 188
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  WORD16           toa_shift;
+}
+T_TR_TOA_NOT_UPDATED;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ SLEEP
+   //FULL/
+    "        ---#@1dc7#---                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7#      ...                         SLEEP |           type_sleep: #@3=0:No sleep|=1:Big sleep|=2:Deep sleep|l10#          wakeup_type: #@4=0:Undefined|=1:L1S task|=2:OS task|=3:HW timer task|=4:Gauging task|=5:Async interrupt|#"
+    "             ...                               |        why_big_sleep: #@5=0:Undefined|=1:Light on|=2:UART|=3:SIM|=4:Gauging|=5:Sleep mode|=6:DSP traces|=7:Bluetooth|#"
+    "        ---#@2dc7#---                          |"
+   //COND/
+    "#@Fdl7#                          SLEEP"
+   End header */
+//ID/
+#define TRL1_SLEEP 189
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD32          start_fn;
+  UWORD32          end_fn;
+  UWORD8           type_sleep;
+  UWORD8           wakeup_type;
+  UWORD8           big_sleep_type;
+}
+T_TR_SLEEP;
+
+// Wakeup Type for Power management
+//--------------------------------
+#define WAKEUP_FOR_UNDEFINED       0
+#define WAKEUP_FOR_L1_TASK         1
+#define WAKEUP_FOR_OS_TASK         2
+#define WAKEUP_FOR_HW_TIMER_TASK   3
+#define WAKEUP_FOR_GAUGING_TASK    4
+#define WAKEUP_BY_ASYNC_INTERRUPT  5
+#define WAKEUP_ASYNCHRONOUS_ULPD_0           6
+#define WAKEUP_ASYNCHRONOUS_SLEEP_DURATION_0 7
+
+// Big Sleep source for Power management
+//-------------------------------------
+#define BIG_SLEEP_DUE_TO_UNDEFINED  0  // deep sleep is forbiden : cause undefined
+#define BIG_SLEEP_DUE_TO_LIGHT_ON   1  // deep sleep is forbiden by ligth on activitie
+#define BIG_SLEEP_DUE_TO_UART       2  // deep sleep is forbiden by UART activitie
+#define BIG_SLEEP_DUE_TO_SIM        3  // deep sleep is forbiden by SIM activitie
+#define BIG_SLEEP_DUE_TO_GAUGING    4  // deep sleep is forbiden by not enought gauging
+#define BIG_SLEEP_DUE_TO_SLEEP_MODE 5  // deep sleep is forbiden by the sleep mode enabled
+#define BIG_SLEEP_DUE_TO_DSP_TRACES 6  // deep sleep is forbiden by the DSP
+#define BIG_SLEEP_DUE_TO_BLUETOOTH  7  // deep sleep is forbiden by the Bluetooth module
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ Gauging
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |  O  |             #@1=0:Gauging|=1:Reset Gauging|l12# |"
+   //COND/
+    "#@Fdl7#                          #@1=0:Gauging|=1:Reset Gauging|~|#"
+   End header */
+//ID/
+#define TRL1_GAUGING 190
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  BOOL             reset_gauging;
+}
+T_TR_GAUGING;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ Unknown L1S trace
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  X  |        Unknown L1S trace |                   id: #@1d#"
+   //COND/
+    "#@Fdl7#                          #@1=0:Gauging|=1:Reset Gauging|~|#"
+   End header */
+//ID/
+#define TRL1_UNKNOWN_L1S_TRACE 191
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD16          id;
+}
+T_TR_UNKNOWN_L1S_TRACE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY0_E2_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | MELODY0_E2_START_REQ     |           session_id: #@1dl10#             loopback: #@2=0:NO|=1:YES|~|#"
+   //COND/
+    "#@Fdl7#  MELODY0_E2_START_REQ                                           id: #@1d#"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY0_E2_START_REQ 192
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           session_id;
+  BOOL             loopback;
+}
+T_TR_MMI_MELODY0_E2_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY0_E2_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | MELODY0_E2_STOP_REQ      |"
+   //COND/
+    "#@Fdl7#  MELODY0_E2_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY0_E2_STOP_REQ 193
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY0_E2_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY0_E2_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MELODY0_E2_START_CON     |"
+   //COND/
+    "#@Fdl7#  MELODY0_E2_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY0_E2_START_CON 194
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY0_E2_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY0_E2_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MELODY0_E2_STOP_CON      |"
+   //COND/
+    "#@Fdl7#  MELODY0_E2_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY0_E2_STOP_CON 195
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY0_E2_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY1_E2_START_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | MELODY1_E2_START_REQ     |           session_id: #@1dl10#             loopback: #@2=0:NO|=1:YES|~|#"
+   //COND/
+    "#@Fdl7#  MELODY1_E2_START_REQ                                           id: #@1d#"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY1_E2_START_REQ 196
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           session_id;
+  BOOL             loopback;
+}
+T_TR_MMI_MELODY1_E2_START_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY1_E2_STOP_REQ
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |---->|  |  | MELODY1_E2_STOP_REQ      |"
+   //COND/
+    "#@Fdl7#  MELODY1_E2_STOP_REQ"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY1_E2_STOP_REQ 197
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY1_E2_STOP_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY1_E2_START_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MELODY1_E2_START_CON     |"
+   //COND/
+    "#@Fdl7#  MELODY1_E2_START_CON"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY1_E2_START_CON 198
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY1_E2_START_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MMI_MELODY1_E2_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | MELODY1_E2_STOP_CON      |"
+   //COND/
+    "#@Fdl7#  MELODY1_E2_STOP_CON"
+   End header */
+//ID/
+#define TRL1_MMI_MELODY1_E2_STOP_CON 199
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MMI_MELODY1_E2_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_BACK_MELODY_E2_LOAD_INSTRUMENT_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | L1_BACK_MELODY_E2        |            melody_id: #@1dl10#        nb_instrument: #@2d#"
+    "        |  |  |  |  |     _LOAD_INSTRUMENT_REQ |       waves_table_id: #@3dr3#"
+   //COND/
+    "#@Fdl7#  L1_BACK_MELODY_E2_LOAD_INSTRUMENT_REQ"
+   End header */
+//ID/
+#define TRL1_L1_BACK_MELODY_E2_LOAD_INSTRUMENT_REQ 200
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           melody_id;
+  UWORD8           number_of_instrument;
+  UWORD8           waves_table_id[8];
+}
+T_TR_L1_BACK_MELODY_E2_LOAD_INSTRUMENT_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_BACK_MELODY_E2_LOAD_INSTRUMENT_CON
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  | L1_BACK_MELODY_E2        |            melody_id: #@1d#"
+    "        |  |  |  |  |     _LOAD_INSTRUMENT_CON |"
+   //COND/
+    "#@Fdl7#  L1_BACK_MELODY_E2_LOAD_INSTRUMENT_CON"
+   End header */
+//ID/
+#define TRL1_L1_BACK_MELODY_E2_LOAD_INSTRUMENT_CON 201
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           melody_id;
+}
+T_TR_L1_BACK_MELODY_E2_LOAD_INSTRUMENT_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_REQ
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |---->|  |  | L1_BACK_MELODY_E2        |            melody_id: #@1dl10#        nb_instrument: #@2d#"
+    "        |  |  |  |  |   _UNLOAD_INSTRUMENT_REQ |"
+   //COND/
+    "#@Fdl7#  L1_BACK_MELODY_E2_LOAD_INSTRUMENT_REQ"
+   End header */
+//ID/
+#define TRL1_L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_REQ 202
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           melody_id;
+  UWORD8           number_of_instrument;
+}
+T_TR_L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_REQ;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_CON
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |<----|  |  | L1_BACK_MELODY_E2        |            melody_id: #@1d#"
+    "        |  |  |  |  |   _UNLOAD_INSTRUMENT_CON |"
+   //COND/
+    "#@Fdl7#  L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_CON"
+   End header */
+//ID/
+#define TRL1_L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_CON 203
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+//--------------------------------------------------
+  UWORD8           melody_id;
+}
+T_TR_L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_MELODY0_E2_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |   L1_MELODY0_E2_STOP_CON |"
+   //COND/
+    "#@Fdl7#  L1_MELODY0_E2_STOP_CON"
+   End header */
+//ID/
+#define TRL1_L1_MELODY0_E2_STOP_CON 204
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1_MELODY0_E2_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1_MELODY1_E2_STOP_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |<-|  |   L1_MELODY1_E2_STOP_CON |"
+   //COND/
+    "#@Fdl7#  L1_MELODY1_E2_STOP_CON"
+   End header */
+//ID/
+#define TRL1_L1_MELODY1_E2_STOP_CON 205
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1_MELODY1_E2_STOP_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ RECOVERY
+   //ERROR/ REC
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  | *** |      ***RECOVERY***      |"
+   //COND/
+    "#@Fdl7#                                                  RECOVERY"
+   End header */
+//ID/
+#define TRL1_RECOVERY 206
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_RECOVERY;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ PTCCH DISABLE
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |  |  0  |                          | WARNING: PTCCH disabled by L1S (TA_TN doesn't match with allocated resources)"
+   //COND/
+    "#@Fdl7#                          PTCCH disabled by L1S"
+   End header */
+//ID/
+#define TRL1_PTCCH_DISABLE 207
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_PTCCH_DISABLE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ MPHC_STOP_DEDICATED_CON
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |<----|  |  | STOP_DEDICATED_CON       |"
+   //COND/
+    "#@Fdl7#  STOP_DEDICATED_CON"
+   End header */
+//ID/
+#define TRL1_MPHC_STOP_DEDICATED_CON 218
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_MPHC_STOP_DEDICATED_CON;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ CLASSIC
+   //NAME/ L1C_STOP_DEDICATED_DONE
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |     |<-|  | L1C_STOP_DEDICATED_DONE  |"
+   //COND/
+    "#@Fdl7#  L1C_STOP_DEDICATED_DONE"
+   End header */
+//ID/
+#define TRL1_L1C_STOP_DEDICATED_DONE 219
+//STRUCT/
+typedef struct
+{
+  UWORD32          header;
+}
+T_TR_L1C_STOP_DEDICATED_DONE;
+
+
+/***********************************************************************************************************/
+/* L1 RTT                                                                                                  */
+/***********************************************************************************************************/
+
+// Trace structures:
+// -----------------
+// For 32 bit alignment, all structures should be mapped like this:
+//  1- 32-bit words (arrays of 32-bit words included)
+//  2- 16-bit words (arrays of 16-bit words included)
+//  3-  8-bit words (arrays of 8-bit words included)
+//  4- HOLES permitting to obtain a cell size aligned on 32 bits (multiple of 4 b) !!!
+//  5- cell_id (8 bit)
+// This permits to avoid holes between variables and to have a structure independant of
+// alignment
+
+
+//-----------------------------------------------------------------------------------------------------------
+// L1 RTT API function management
+//-----------------------------------------------------------------------------------------------------------
+
+// Dummy functions
+#if (defined RVM_RTT_SWE || (OP_L1_STANDALONE == 1))
+T_RTT_RET rtt_create_dummy (T_RVT_NAME      name[],
+                            T_RTT_USER_ID *rtt_user_id,
+                            T_RTT_MAX_EVT  nb_max_events,
+                            T_RTT_BUF      buf_ptr,
+                            T_RTT_SIZE     buf_size,
+                            void          *callback);
+
+T_RTT_RET rtt_refresh_status_dummy (T_RTT_USER_ID  user_id);
+
+T_RTT_PTR rtt_get_fill_ptr_dummy (T_RTT_USER_ID  user_id,
+                                  T_RTT_SIZE     size);
+
+T_RTT_RET rtt_dump_buffer_dummy (T_RTT_USER_ID  user_id,
+                                 T_RTT_SIZE     dump_size);
+#endif
+
+//-----------------------------------------------------------------------------------------------------------
+// L1 RTT cell definitions
+//-----------------------------------------------------------------------------------------------------------
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ FN
+   //FULL/
+   //COND/
+   End header */
+//ID//
+#define RTTL1_ENABLE_FN 0
+//STRUCT/
+typedef struct
+{
+  UWORD32     fn;
+  UWORD16     hole1;
+  UWORD8      hole2;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_FN;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ DL Burst
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  |<-|                    DL NB |       angle: #@1dl10#  snr: #@2dl10#  pm: #@5d#"
+    "        |  |  |  |  |                          |         afc: #@3dl10# task: #@4tl10# toa: #@6d#"
+    "        |  |  |  |  |                          | input_level: #-@7 / 2f1# dBm"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_DL_BURST 1
+//STRUCT/
+typedef struct
+{
+  WORD16      angle;
+  UWORD16     snr;
+  WORD16      afc;
+  UWORD8      task;
+  UWORD8      pm;
+  UWORD8      toa;
+  UWORD8      input_level;
+  UWORD8      hole;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_DL_BURST;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ UL Normal Burst
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  |->|                    UL NB | task: #@1tl10# ta: #@2dl10# txpwr: #@3d#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_UL_NB 2
+//STRUCT/
+typedef struct
+{
+  UWORD8      task;
+  UWORD8      ta;
+  UWORD8      txpwr;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_UL_NB;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ UL Access Burst
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  |->|                    UL AB | task: #@1tl10# txpwr: #@3d#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_UL_AB 3
+//STRUCT/
+typedef struct
+{
+  UWORD8      task;
+  UWORD8      txpwr;
+  UWORD8      hole;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_UL_AB;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ Full list Meas
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  |<-|                    DL MS | type: #@4=200:Full list|=201:Idle BA list|=202:Dedicated BA list|=203:MS AGC|=204:Cell selection|=205:Transfer cell selection|=206:Beacon monitoring|#"
+    "        |  |  |  |  |                          | radio_freq: #@1dl10# pm: #@2dl10# input_level: #-@3 / 2f1#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_FULL_LIST_MEAS 4
+//STRUCT/
+typedef struct
+{
+  UWORD16     radio_freq;
+  UWORD8      pm;
+  UWORD8      input_level;
+  UWORD8      task;
+  UWORD8      hole1;
+  UWORD8      hole2;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_FULL_LIST_MEAS;
+
+/***********************************************************************************************************/
+/* Could replace valid_flag by 3 x UWORD16 dsp_header */
+
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ DL DCCH
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |<----|  |                  DL DCCH | valid_flag: #@1=0:OK|=1:CRC ERROR|l10# physical_info: #@2=255:NONE|#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_DL_DCCH 5
+//STRUCT/
+typedef struct
+{
+  BOOL        valid_flag;
+  UWORD8      physical_info; // if 255 no physical info else ta
+  UWORD8      hole;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_DL_DCCH;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ DL PTCCH
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  |<-|                 DL PTCCH |  crc: #@1=0:OK|=1:CRC ERROR|l10# ordered_ta: #@2>63:INVALID|#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_DL_PTCCH 6
+//STRUCT/
+typedef struct
+{
+  BOOL        crc;
+  UWORD8      ordered_ta;
+  UWORD8      hole;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_DL_PTCCH;
+
+/***********************************************************************************************************/
+/*  Could add 23 x UWORD8 data */
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ UL DCCH
+   //FULL/
+    "        |  |  |  |  |                          |"
+    "#@Fdl7# |  |---->|  |                  UL DCCH |"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_UL_DCCH 7
+//STRUCT/
+typedef struct
+{
+  UWORD8      hole1;
+  UWORD8      hole2;
+  UWORD8      hole3;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_UL_DCCH;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ UL SACCH
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |---->|  |                 UL SACCH | data_present: #@1=1:Yes|=0:No|~|l10# reported_ta: #@2dl10# reported_txpwr: #@3d#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_UL_SACCH 8
+//STRUCT/
+typedef struct
+{
+  BOOL        data_present;
+  UWORD8      reported_ta;
+  UWORD8      reported_txpwr;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_UL_SACCH;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ DL PDTCH
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |<----|  |                 DL PDTCH |   timeslot: #@5dl10#     crc: #@3=0:OK|>0:CRC ERROR|#"
+    "        |  |  |  |  |                          | mac_header: #@1xl10# cs_type: #@4=2:CS1|=4:CS2|=5:CS3|=6:CS4|~N/A|#"
+    "        |  |  |  |  |                          | tfi_result: #@2=0:No filtering|=1:NO TFI|=2:Addressed to MS|=3:Not addressed to MS|#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_DL_PDTCH 9
+//STRUCT/
+typedef struct
+{
+  UWORD8      mac_header;
+  UWORD8      tfi_result;
+  BOOL        crc;
+  UWORD8      cs_type;
+  UWORD8      timeslot;
+  UWORD8      hole1;
+  UWORD8      hole2;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_DL_PDTCH;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ UL PDTCH
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |---->|  |                 UL PDTCH |  timeslot: #@3dl10# data_allowed: #@2=0:NO|=1:YES|~N/A|#"
+    "        |  |  |  |  |                          |   cs_type: #@1=2:CS1|=3:CS1 POLL|=4:CS2|=5:CS3|=6:CS4|=7:PRACH 8 bit|=8:PRACH 11 bit|~N/A|#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_UL_PDTCH 10
+//STRUCT/
+typedef struct
+{
+  UWORD8      cs_type;
+  BOOL        data_allowed;
+  UWORD8      timeslot;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_UL_PDTCH;
+
+/***********************************************************************************************************/
+
+#define POLL_REJECT       0
+#define TX_ALLOWED_NO_BLK 1
+#define TX_CANCELLED_POLL 2
+#define TX_CANCELLED_USF  3
+
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ MAC-S Status
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  O  |                    MAC-S | #@1=0:Poll rejected|=1:TX allowed and no block given by RLC|=2:TX cancelled for poll|=3:TX cancelled (bad USF)|# on timeslot #@2d#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_MACS_STATUS 11
+//STRUCT/
+typedef struct
+{
+  UWORD8      status;
+  UWORD8      timeslot;
+  UWORD8      hole;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_MACS_STATUS;
+
+/***********************************************************************************************************/
+/* Special trace: display is implemented in the trace decoder
+ */
+#define RTTL1_ENABLE_L1S_TASK_ENABLE 12
+
+typedef struct
+{
+  UWORD32     bitmap1;
+  UWORD32     bitmap2;
+  UWORD8      hole1;
+  UWORD8      hole2;
+  UWORD8      hole3;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_L1S_TASK_ENABLE;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ Neighbor monitoring meas
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  |<-|                    DL MS | type: #@4=200:Full list|=201:Idle BA list|=202:Dedicated BA list|=203:MS AGC|=204:Cell selection|=205:Transfer cell selection|=206:Beacon monitoring|#"
+    "        |  |  |  |  |                          | radio_freq: #@1dl10# pm: #@2dl10# input_level: #-@3 / 2f1#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_MON_MEAS 13
+//STRUCT/
+typedef struct
+{
+  UWORD16     radio_freq;
+  UWORD8      pm;
+  UWORD8      input_level;
+  UWORD8      task;
+  UWORD8      hole1;
+  UWORD8      hole2;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_MON_MEAS;
+
+/***********************************************************************************************************/
+/* Begin header
+   //TYPE/ RTT
+   //NAME/ MFTAB
+   //FULL/
+    "        |  |  |  |  |                          |----------------------------------------------------------------------------------------------------------------"
+    "#@Fdl7# |  |  |  O  |                          | #@1T[MFTAB]#"
+   //COND/
+   End header */
+//ID/
+#define RTTL1_ENABLE_MFTAB 14
+//STRUCT/
+typedef struct
+{
+  UWORD8      func;
+  UWORD8      hole1;
+  UWORD8      hole2;
+//--------------------------------------------------
+  UWORD8      cell_id;
+} T_RTTL1_MFTAB;
+
+/***************************************************/
+/* General structure: must contain all trace cells */
+/***************************************************/
+
+typedef struct
+{
+  // Classic cells
+  T_TR_MPHC_INIT_L1_REQ                         cell1;
+  T_TR_MPHC_INIT_L1_CON                         cell2;
+  T_TR_MPHC_RXLEV_PERIODIC_REQ                  cell3;
+  T_TR_MPHC_NCELL_FB_SB_READ                    cell4;
+  T_TR_MPHC_RA_CON                              cell5;
+  T_TR_MPHC_IMMED_ASSIGN_REQ                    cell6;
+  T_TR_MPHC_CHANNEL_ASSIGN_REQ                  cell7;
+  T_TR_MPHC_RA_REQ                              cell8;
+  T_TR_MPHC_ASYNC_HO_REQ                        cell9;
+  T_TR_MPHC_SYNC_HO_REQ                         cell10;
+  T_TR_L1C_HANDOVER_FINISHED                    cell11;
+  T_TR_L1C_MEAS_DONE                            cell12;
+  T_TR_MPHC_START_CCCH_REQ                      cell13;
+  T_TR_MPHC_NCELL_SB_READ                       cell14;
+  T_TR_MPHC_RXLEV_REQ                           cell15;
+  T_TR_L1C_VALID_MEAS_INFO                      cell16;
+  T_TR_L1C_RXLEV_PERIODIC_DONE                  cell17;
+  T_TR_MPHC_SCELL_NBCCH_REQ                     cell18;
+  T_TR_MPHC_SCELL_EBCCH_REQ                     cell19;
+  T_TR_MPHC_NCELL_BCCH_REQ                      cell20;
+  T_TR_L1C_BCCHN_INFO                           cell21;
+  T_TR_L1C_NP_INFO                              cell22;
+  T_TR_L1C_EP_INFO                              cell23;
+  T_TR_L1C_ALLC_INFO                            cell24;
+  T_TR_L1C_BCCHS_INFO                           cell25;
+  T_TR_L1C_CB_INFO                              cell26;
+  T_TR_MPHC_NETWORK_SYNC_REQ                    cell27;
+  T_TR_MPHC_NETWORK_SYNC_IND                    cell28;
+  T_TR_MPHC_NCELL_SYNC_REQ                      cell29;
+  T_TR_MPHC_NCELL_SYNC_IND                      cell30;
+  T_TR_L1C_SB_INFO                              cell31;
+  T_TR_L1C_SBCONF_INFO                          cell32;
+  T_TR_MPHC_NEW_SCELL_REQ                       cell33;
+  T_TR_L1C_FB_INFO                              cell34;
+  T_TR_MPHC_STOP_NCELL_SYNC_REQ                 cell35;
+  T_TR_MPHC_STOP_NCELL_BCCH_REQ                 cell36;
+  T_TR_MPHC_CONFIG_CBCH_REQ                     cell37;
+  T_TR_MPHC_CBCH_SCHEDULE_REQ                   cell38;
+  T_TR_MPHC_CBCH_INFO_REQ                       cell39;
+  T_TR_MPHC_CBCH_UPDATE_REQ                     cell40;
+  T_TR_MPHC_STOP_CBCH_REQ                       cell41;
+  T_TR_L1C_SACCH_INFO                           cell42;
+  T_TR_MPHC_CHANGE_FREQUENCY                    cell43;
+  T_TR_MPHC_CHANNEL_MODE_MODIFY_REQ             cell44;
+  T_TR_MPHC_SET_CIPHERING_REQ                   cell45;
+  T_TR_MPHC_UPDATE_BA_LIST                      cell46;
+  T_TR_MPHC_NETWORK_LOST_IND                    cell47;
+  T_TR_MPHC_STOP_CCCH_REQ                       cell48;
+  T_TR_MPHC_STOP_SCELL_BCCH_REQ                 cell49;
+  T_TR_MPHC_STOP_CBCH_CON                       cell50;
+  T_TR_MPHC_STOP_RA_REQ                         cell51;
+  T_TR_L1C_RA_DONE                              cell52;
+  T_TR_MPHC_IMMED_ASSIGN_CON                    cell53;
+  T_TR_MPHC_CHANNEL_ASSIGN_CON                  cell54;
+  T_TR_L1C_REDEF_DONE                           cell55;
+  T_TR_MPHC_STOP_DEDICATED_REQ                  cell56;
+  T_TR_MPHC_ASYNC_HO_CON                        cell57;
+  T_TR_MPHC_SYNC_HO_CON                         cell58;
+  T_TR_MPHC_TA_FAIL_IND                         cell59;
+  T_TR_MPHC_HANDOVER_FAIL_REQ                   cell60;
+  T_TR_MPHC_HANDOVER_FAIL_CON                   cell61;
+  T_TR_MPHC_STOP_RXLEV_REQ                      cell62;
+  T_TR_MPHC_STOP_RXLEV_PERIODIC_REQ             cell63;
+  T_TR_MPHP_RA_REQ                              cell64;
+  T_TR_L1P_RA_DONE                              cell65;
+  T_TR_MPHP_POLLING_RESPONSE_REQ                cell66;
+  T_TR_L1P_POLL_DONE                            cell67;
+  T_TR_MPHP_ASSIGNMENT_REQ                      cell68;
+  T_TR_MPHP_REPEAT_UL_FIXED_ALLOC_REQ           cell69;
+  T_TR_L1P_REPEAT_ALLOC_DONE                    cell70;
+  T_TR_L1P_ALLOC_EXHAUST_DONE                   cell71;
+  T_TR_MPHP_SINGLE_BLOCK_REQ                    cell72;
+  T_TR_L1P_SINGLE_BLOCK_CON                     cell73;
+  T_TR_MPHP_PDCH_RELEASE_REQ                    cell74;
+  T_TR_MPHP_TIMING_ADVANCE_REQ                  cell75;
+  T_TR_MPHP_TBF_RELEASE_REQ                     cell76;
+  T_TR_MPHP_START_PCCCH_REQ                     cell77;
+  T_TR_L1P_PBCCHN_INFO                          cell78;
+  T_TR_L1P_PNP_INFO                             cell79;
+  T_TR_L1P_PEP_INFO                             cell80;
+  T_TR_L1P_PALLC_INFO                           cell81;
+  T_TR_L1P_PBCCHS_INFO                          cell82;
+  T_TR_L1P_PACCH_INFO                           cell83;
+  T_TR_MPHP_SCELL_PBCCH_REQ                     cell84;
+  T_TR_MPHP_CR_MEAS_REQ                         cell85;
+  T_TR_L1P_CR_MEAS_DONE                         cell86;
+  T_TR_MPHP_INT_MEAS_REQ                        cell87;
+  T_TR_MPHP_INT_MEAS_IND                        cell88;
+  T_TR_MPHP_TINT_MEAS_IND                       cell89;
+  T_TR_L1P_ITMEAS_IND                           cell90;
+  T_TR_MPHP_NCELL_PBCCH_REQ                     cell91;
+  T_TR_MPHP_UPDATE_PSI_PARAM_REQ                cell92;
+  T_TR_L1P_TBF_RELEASED                         cell93;
+  T_TR_L1P_PDCH_RELEASED                        cell94;
+  T_TR_L1P_TCR_MEAS_DONE                        cell95;
+  T_TR_MPHP_ASSIGNMENT_CON                      cell96;
+  T_TR_MPHP_TCR_MEAS_REQ                        cell97;
+  T_TR_MPHC_STOP_NETWORK_SYNC_REQ               cell98;
+  T_TR_MPHP_NCELL_PBCCH_STOP_REQ                cell99;
+  T_TR_MPHP_STOP_PCCCH_REQ                      cell100;
+  T_TR_MPHP_SCELL_PBCCH_STOP_REQ                cell101;
+  T_TR_MPHP_RA_STOP_REQ                         cell102;
+  T_TR_MPHP_STOP_SINGLE_BLOCK_REQ               cell103;
+  T_TR_L1P_TA_CONFIG_DONE                       cell104;
+  T_TR_MPHP_CR_MEAS_STOP_REQ                    cell105;
+  T_TR_MPHP_TCR_MEAS_STOP_REQ                   cell106;
+  T_TR_MPHP_INT_MEAS_STOP_REQ                   cell107;
+  T_TR_MMI_KEYBEEP_START_REQ                    cell108;
+  T_TR_MMI_KEYBEEP_START_CON                    cell109;
+  T_TR_MMI_KEYBEEP_STOP_REQ                     cell110;
+  T_TR_MMI_KEYBEEP_STOP_CON                     cell111;
+  T_TR_MMI_TONE_START_REQ                       cell112;
+  T_TR_MMI_TONE_START_CON                       cell113;
+  T_TR_MMI_TONE_STOP_REQ                        cell114;
+  T_TR_MMI_TONE_STOP_CON                        cell115;
+  T_TR_MMI_MELODY0_START_REQ                    cell116;
+  T_TR_MMI_MELODY1_START_REQ                    cell117;
+  T_TR_MMI_MELODY0_START_CON                    cell118;
+  T_TR_MMI_MELODY0_STOP_REQ                     cell119;
+  T_TR_MMI_MELODY0_STOP_CON                     cell120;
+  T_TR_MMI_MELODY1_START_CON                    cell121;
+  T_TR_MMI_MELODY1_STOP_REQ                     cell122;
+  T_TR_MMI_MELODY1_STOP_CON                     cell123;
+  T_TR_MMI_VM_PLAY_START_REQ                    cell124;
+  T_TR_MMI_VM_PLAY_START_CON                    cell125;
+  T_TR_MMI_VM_PLAY_STOP_REQ                     cell126;
+  T_TR_MMI_VM_PLAY_STOP_CON                     cell127;
+  T_TR_MMI_VM_RECORD_START_REQ                  cell128;
+  T_TR_MMI_VM_RECORD_START_CON                  cell129;
+  T_TR_MMI_VM_RECORD_STOP_REQ                   cell130;
+  T_TR_MMI_VM_RECORD_STOP_CON                   cell131;
+  T_TR_MMI_SR_ENROLL_START_REQ                  cell132;
+  T_TR_MMI_SR_ENROLL_START_CON                  cell133;
+  T_TR_MMI_SR_ENROLL_STOP_REQ                   cell134;
+  T_TR_MMI_SR_ENROLL_STOP_CON                   cell135;
+  T_TR_MMI_SR_UPDATE_START_REQ                  cell136;
+  T_TR_MMI_SR_UPDATE_STOP_REQ                   cell137;
+  T_TR_MMI_SR_UPDATE_START_CON                  cell138;
+  T_TR_MMI_SR_UPDATE_STOP_CON                   cell139;
+  T_TR_MMI_SR_RECO_START_REQ                    cell140;
+  T_TR_MMI_SR_RECO_STOP_REQ                     cell141;
+  T_TR_MMI_SR_RECO_START_CON                    cell142;
+  T_TR_MMI_SR_RECO_STOP_CON                     cell143;
+  T_TR_MMI_SR_UPDATE_CHECK_START_REQ            cell144;
+  T_TR_MMI_SR_UPDATE_CHECK_STOP_REQ             cell145;
+  T_TR_MMI_SR_UPDATE_CHECK_START_CON            cell146;
+  T_TR_MMI_SR_UPDATE_CHECK_STOP_CON             cell147;
+  T_TR_L1_SRBACK_SAVE_DATA_REQ                  cell148;
+  T_TR_L1_SRBACK_SAVE_DATA_CON                  cell149;
+  T_TR_L1_SRBACK_LOAD_MODEL_REQ                 cell150;
+  T_TR_L1_SRBACK_LOAD_MODEL_CON                 cell151;
+  T_TR_L1_SRBACK_TEMP_SAVE_DATA_REQ             cell152;
+  T_TR_L1_SRBACK_TEMP_SAVE_DATA_CON             cell153;
+  T_TR_MMI_AEC_REQ                              cell154;
+  T_TR_MMI_AEC_CON                              cell155;
+  T_TR_MMI_AUDIO_FIR_REQ                        cell156;
+  T_TR_MMI_AUDIO_FIR_CON                        cell157;
+  T_TR_MMI_AUDIO_MODE_REQ                       cell158;
+  T_TR_MMI_AUDIO_MODE_CON                       cell159;
+  T_TR_PM_EQUAL_0                               cell160;
+  T_TR_MCU_DSP_MISMATCH                         cell161;
+  T_TR_L1S_ABORT                                cell162;
+  T_TR_D_ERROR_STATUS                           cell163;
+  T_TR_DSP_DEBUG_HEADER                         cell164;
+  T_TR_DSP_DEBUG_BUFFER                         cell165;
+  T_TR_RLC_UL_PARAM                             cell166;
+  T_TR_RLC_DL_PARAM                             cell167;
+  T_TR_FORBIDDEN_UPLINK                         cell168;
+  T_TR_DL_PTCCH                                 cell169;
+  T_TR_CONDENSED_PDTCH                          cell170;
+  T_TR_OML1_CLOSE_TCH_LOOP_REQ                  cell171;
+  T_TR_OML1_OPEN_TCH_LOOP_REQ                   cell172;
+  T_TR_OML1_START_DAI_TEST_REQ                  cell173;
+  T_TR_OML1_STOP_DAI_TEST_REQ                   cell174;
+  T_TR_TST_TEST_HW_REQ                          cell175;
+  T_TR_L1_TEST_HW_INFO                          cell176;
+  T_TR_TST_SLEEP_REQ                            cell177;
+  T_TR_MMI_ADC_REQ                              cell178;
+  T_TR_MMI_STOP_ADC_REQ                         cell179;
+  T_TR_MMI_STOP_ADC_CON                         cell180;
+  T_TR_L1S_CPU_PEAK                             cell181;
+  T_TR_TRACE_CONFIG_CHANGE                      cell182;
+  T_TR_ASCII                                    cell183;
+  T_TR_FULL_LIST_REPORT                         cell184;
+  T_TR_IT_DSP_ERROR                             cell185;
+  T_TR_ADC                                      cell186;
+  T_TR_NEW_TOA                                  cell187;
+  T_TR_TOA_NOT_UPDATED                          cell188;
+  T_TR_SLEEP                                    cell189;
+  T_TR_GAUGING                                  cell190;
+  T_TR_UNKNOWN_L1S_TRACE                        cell191;
+  T_TR_MMI_MELODY0_E2_START_REQ                 cell192;
+  T_TR_MMI_MELODY0_E2_STOP_REQ                  cell193;
+  T_TR_MMI_MELODY0_E2_START_CON                 cell194;
+  T_TR_MMI_MELODY0_E2_STOP_CON                  cell195;
+  T_TR_MMI_MELODY1_E2_START_REQ                 cell196;
+  T_TR_MMI_MELODY1_E2_STOP_REQ                  cell197;
+  T_TR_MMI_MELODY1_E2_START_CON                 cell198;
+  T_TR_MMI_MELODY1_E2_STOP_CON                  cell199;
+  T_TR_L1_BACK_MELODY_E2_LOAD_INSTRUMENT_REQ    cell200;
+  T_TR_L1_BACK_MELODY_E2_LOAD_INSTRUMENT_CON    cell201;
+  T_TR_L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_REQ  cell202;
+  T_TR_L1_BACK_MELODY_E2_UNLOAD_INSTRUMENT_CON  cell203;
+  T_TR_L1_MELODY0_E2_STOP_CON                   cell204;
+  T_TR_L1_MELODY1_E2_STOP_CON                   cell205;
+  T_TR_RECOVERY                                 cell206;
+  T_TR_PTCCH_DISABLE                            cell207;
+  T_TR_L1_AEC_IND                               cell208;
+  T_TR_MMI_VM_AMR_PLAY_START_REQ                cell209;
+  T_TR_MMI_VM_AMR_PLAY_START_CON                cell210;
+  T_TR_MMI_VM_AMR_PLAY_STOP_REQ                 cell211;
+  T_TR_MMI_VM_AMR_PLAY_STOP_CON                 cell212;
+  T_TR_MMI_VM_AMR_RECORD_START_REQ              cell213;
+  T_TR_MMI_VM_AMR_RECORD_START_CON              cell214;
+  T_TR_MMI_VM_AMR_RECORD_STOP_REQ               cell215;
+  T_TR_MMI_VM_AMR_RECORD_STOP_CON               cell216;
+  T_TR_MPHC_NCELL_LIST_SYNC_REQ                 cell217;
+  T_TR_MPHC_STOP_DEDICATED_CON                  cell218;
+  T_TR_L1C_STOP_DEDICATED_DONE                  cell219;
+
+  // RTT cells
+  T_RTTL1_FN                                    rttcell1;
+  T_RTTL1_DL_BURST                              rttcell2;
+  T_RTTL1_UL_NB                                 rttcell3;
+  T_RTTL1_UL_AB                                 rttcell4;
+  T_RTTL1_FULL_LIST_MEAS                        rttcell5;
+  T_RTTL1_DL_DCCH                               rttcell6;
+  T_RTTL1_DL_PTCCH                              rttcell7;
+  T_RTTL1_UL_DCCH                               rttcell8;
+  T_RTTL1_UL_SACCH                              rttcell9;
+  T_RTTL1_DL_PDTCH                              rttcell10;
+  T_RTTL1_UL_PDTCH                              rttcell11;
+  T_RTTL1_MACS_STATUS                           rttcell12;
+  T_RTTL1_L1S_TASK_ENABLE                       rttcell13;
+  T_RTTL1_MON_MEAS                              rttcell14;
+  T_RTTL1_MFTAB                                 rttcell15;
+}
+T_TRACE_CELLS;
+
+
+/************************************/
+/* RTT macro definitions            */
+/************************************/
+#include "l1_rtt_macro.h"
+
+#endif
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_types.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_types.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,38 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_TYPES.H
+ *
+ *        Filename l1_types.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+//--------------------------------------
+// Basic DATA types used along L1 code.
+//--------------------------------------
+#if !defined (BOOL_FLAG)
+  #define BOOL_FLAG
+  typedef unsigned char  BOOL;
+#endif
+
+
+#if !defined (NUCLEUS) && !defined CHAR_FLAG
+  #define CHAR_FLAG
+  typedef          char  CHAR;
+#endif
+
+typedef unsigned char  UWORD8;
+typedef signed   char  WORD8;
+
+typedef unsigned short UWORD16;
+typedef          short WORD16;
+
+typedef unsigned long  UWORD32;
+typedef          long  WORD32;
+//--------------------------------------
+
+typedef volatile UWORD16  API;
+typedef volatile WORD16   API_SIGNED;
+
+
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_varex.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_varex.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,56 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software 
+ * L1_VAREX.H
+ *
+ *        Filename l1_varex.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+#ifdef L1_ASYNC_C
+
+#if (LONG_JUMP == 3)
+ #pragma DATA_SECTION(l1s,".l1s_global")
+ #pragma DATA_SECTION(l1s_dsp_com,".l1s_global")
+ #pragma DATA_SECTION(l1a_l1s_com,".l1s_global")
+ #pragma DATA_SECTION(l1s_tpu_com,".l1s_global")
+ #pragma DATA_SECTION(l1_config,".l1s_global")
+#endif
+
+ T_L1S_GLOBAL   l1s;
+ T_L1A_GLOBAL   l1a;
+
+ T_L1A_L1S_COM  l1a_l1s_com;
+ T_L1S_DSP_COM  l1s_dsp_com;
+ T_L1S_TPU_COM  l1s_tpu_com;
+
+ #if (L1_DYN_DSP_DWNLD == 1)    // equivalent to an API_HISR flag
+ T_L1_API_HISR       l1_apihisr;
+ T_L1A_API_HISR_COM l1a_apihisr_com;
+#endif
+
+ // variables for L1 configuration
+ T_L1_CONFIG    l1_config;
+
+#else  // L1_ASYNC_C
+
+ extern T_L1S_GLOBAL   l1s;
+ extern T_L1A_GLOBAL   l1a;
+
+ extern T_L1A_L1S_COM  l1a_l1s_com;
+ extern T_L1S_DSP_COM  l1s_dsp_com;
+ extern T_L1S_TPU_COM  l1s_tpu_com;
+
+ #if (L1_DYN_DSP_DWNLD == 1)    // equivalent to an API_HISR flag
+ extern T_L1_API_HISR      l1_apihisr;
+ extern T_L1A_API_HISR_COM l1a_apihisr_com;
+#endif
+
+ // variables for L1 configuration
+ extern T_L1_CONFIG    l1_config;
+#endif
+
+
+extern const UWORD8 ramBootCode[]; // dummy DSP code for boot.
+  
+
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/L1/include/l1_ver.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/L1/include/l1_ver.h	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,342 @@
+/************* Revision Controle System Header *************
+ *                  GSM Layer 1 software
+ * L1_VER.H
+ *
+ *        Filename l1_ver.h
+ *  Copyright 2003 (C) Texas Instruments  
+ *
+ ************* Revision Controle System Header *************/
+
+/*********************************************************/
+/* Software Version Integrated on Evaluation board 3 / 4 */
+/*********************************************************/
+
+//#define    SOFTWAREVERSION  0x0300L;  // Release Cust 5 0.3
+//#define    SOFTWAREVERSION  0x0301L;  // + LOOPS A,B,C + A5 (SDCCH/TCH) + DTX
+                                        // + FER Rxlev,Facch + new hw switches
+//#define    SOFTWAREVERSION  0x0400L;  // Release Cust 5 0.4
+//#define    SOFTWAREVERSION  0x0401L;  // SAXO version for next Release
+//#define    SOFTWAREVERSION  0x0402L;  // + new stats/traces - a_sch26
+//#define    SOFTWAREVERSION  0x0500L;  // Release Cust 5 0.5 (Idle/Dedic monitoring)
+//#define    SOFTWAREVERSION  0x0610L;  // Release Cust 5 0.61 (POLE50/VEGA2/CBCH)
+//#define    SOFTWAREVERSION  0x0700L;  // ROM Code
+//#define    SOFTWAREVERSION  0x0720L;  // Release Cust5 0.72 (tones + AGC/AFC)
+//#define    SOFTWAREVERSION  0x0721L;  // Rom bug (l1_sync.c) fixed + test msg + DEDICATED MODE
+//#define    SOFTWAREVERSION  0x0800L;  // IDLE MODE cpu optimization
+//#define    SOFTWAREVERSION  0x0801L;  // DAI tests +  PARAM update
+//#define    SOFTWAREVERSION  0x0820L;  // TI_1, TI_3 + TX data buffer size
+//#define    SOFTWAREVERSION  0x0821L;  // TI_1 to TI_14 problem corrected.
+//#define    SOFTWAREVERSION  0x0827L;  // Release: TI_16, TI_18, TI_19, TI_21, TI_22, TI_23, TI_24,
+                                        // CUST5_6, CUST5_7, CUST5_9 corrected.
+//#define    SOFTWAREVERSION  0x0828L;  // Release: CUST5_14, CUST5_15, CUST5_16, TI_20
+//#define    SOFTWAREVERSION  0x0829L;  // Release: TI_28
+//#define    SOFTWAREVERSION  0x0830L;  // TI internal release: TI_17, TI_29, TI_32, TI_34, TI_35, TI_36,
+                                        //                      TI_37, TI_40, TI_41.
+                                        //                      CUST5_21, CUST5_22, CUST5_26, CUST5_28,
+                                        //                      CUST5_29, CUST5_30, CUST5_31, CUST5_33.
+//#define    SOFTWAREVERSION  0x0831L;  // TI internal release: TI_44(a), CUST5_33, CUST5_35, CUST5_41,
+                                        //                      TI_44(b)(c), TI_35, CUST5_37, TI_44(e),
+                                        //                      TI_44(f), CUST5_40, CUST5_44, TI_44(g),
+                                        //                      CUST5_38, CUST5_39, CUST5_43, CUST5_45,
+                                        //                      CUST5_49, CUST5_50, TI_44(i), TI_47,
+                                        //                      TI_44(j1), TI_44(o), TI_43, CUST5_51,
+                                        //                      CUST5_52 problems corrected.
+//#define    SOFTWAREVERSION  0x0850L;  // TI FTA L1 SW integrated in new DB.
+//#define    SOFTWAREVERSION  0x0851L;  // TI FTA L1 SW with field test problems corrected
+                                        // up to TI_59 and CUST5_59.
+//#define    SOFTWAREVERSION  0x0860L;  // Merged FR FTA code (v0.851) and HR code (0.831 based + HR).
+//#define    SOFTWAREVERSION  0x0861L;  // New PM=0/MCU-DSP Mismatch tracing method.
+//#define    SOFTWAREVERSION  0x0870L;  // Merged v0.860 and EFR code v0x1008.
+//#define    SOFTWAREVERSION  0x0871L;  // Merged v0.861 and v0.870. (result contains 0.870
+                                        // functionality + improved
+                                        // tracing capabilities.
+//#define    SOFTWAREVERSION  0x0872L;  // Updated EVA3 diver library to have capabilites
+                                        // to both pooled and Interrupt driven.
+//#define    SOFTWAREVERSION  0x0873L;  // Reviewed TPU drivers. l1_const.h has been split
+                                        // to separate Timing definitions in l1_time.h
+//#define    SOFTWAREVERSION  0x0874L;  // Corrected bad reference made to l1_rf#.h
+                                        // and tpudrv#.h during "Reviewed TPU drivers".
+//#define    SOFTWAREVERSION  0x0875L;  // Removed redondant definition of PRG_TX from
+                                        // l1_time.h. CUST0/RF1-2 use PRG_TX=20.
+//#define    SOFTWAREVERSION  0x0900L;  // Dual Band SW based on L1 generic database (v0.875)
+//#define    SOFTWAREVERSION  0x0901L;  // Added DSP selection capabilities.
+//#define    SOFTWAREVERSION  0x0902L;  // Corrected TI_60, TI_61, TI_65. Corrected miscelaneous
+                                        // debug/trace mistakes.
+//#define    SOFTWAREVERSION  0x0903L;  // Release: CUST5. Include AGC mods based on FTA problems.
+//#define    SOFTWAREVERSION  0x0904L;  // Due to problem in V0.903 release,
+                                        // generation of V0.904 which includes
+                                        // the unexpected missing features of V0.903.
+//#define    SOFTWAREVERSION  0x0905L;  // Version including Triple vocoder feature.
+//#define    SOFTWAREVERSION  0x0906L;  // Added TXPWR MANAGEMENT.
+//#define    SOFTWAREVERSION  0x0907L;  // Added ADC RESULT report msg L1S->L3 mechanism.
+//#define    SOFTWAREVERSION  0x0908L;  // Added POWER MANAGEMENT mechanism.
+//#define    SOFTWAREVERSION  0x0909L;  // DSP = 4 updated in order to deal with Pole112
+//#define    SOFTWAREVERSION  0x0910L;  // CLKMOD2 modified for DSP == 1, patch_file6.c and
+                                        // patch_file5.c updated
+//#define    SOFTWAREVERSION  0x0911L;  // AGC and TOA management update according to TI/C5 code review.
+//#define    SOFTWAREVERSION  0x0912L;  // Corrected PB #6,7,14,17,18,19,20.
+//#define    SOFTWAREVERSION  0x0913L;  // Integated TXPWR for Dual Band, DSP Patch updated, AGC reworked
+                                        // in order in order to cover all bands, corrected PB
+                                        // #2/22,21,23,24,25,26,28,29
+//#define    SOFTWAREVERSION  0x0914L;  // Modified FB search algorithm (FBNEW, FB51)
+                                        // so that FB search aborted
+                                        // once the FB has been found
+//#define    SOFTWAREVERSION  0x0915L;  // Integratd Data Services modifications implemented
+//#define    SOFTWAREVERSION  0x0916L;  // Reworked power management
+//#define    SOFTWAREVERSION  0x0917L;  // A-sample, protocol stack compatibility, 4PM, audio functions
+//#define    SOFTWAREVERSION  0x0918L;  // Voice memo functions
+                                        // Uplink a_du_0 blud bit set by layer
+                                        // for IDS mode.
+//#define    SOFTWAREVERSION  0x1019L;  // Version 10xx indicates L1 standalone 1.5,
+                                        // version 19 -> IDS modifications + TPU drivers for ATL RF
+//#define    SOFTWAREVERSION  0x1020L   // version 20 Porting of eva3drivers1 on HER. SATU compatibility
+                                        // kept.
+                                        // Correction of a commentation bug in SPIOmega_on()
+                                        // Correction of a bug in l1dmacro_init_hw() for IO accesses
+//#define    SOFTWAREVERSION  0x1021L   // SPEECH RECO.
+//#define    SOFTWAREVERSION  0x1318L   // Voice memo functions
+//#define    SOFTWAREVERSION  0x1319L   // version 19 -> IDS modifications + TPU drivers for ATL RF
+//#define    SOFTWAREVERSION  0x1320L   // version 20 Porting of eva3drivers1 on HER. SATU
+                                        // compatibility kept.
+                                        // Correction of a commentation bug in SPIOmega_on()
+                                        // Correction of a bug in l1dmacro_init_hw() for IO accesses
+//#define    SOFTWAREVERSION  0x1321L   // Corrected TI_5, TI_6, TI_8, TI_9, TI_10, TI_11
+//#define    SOFTWAREVERSION  0x1322L   // New Power mnagement algo. (+ Specch reco. NOT TESTED)
+//#define    SOFTWAREVERSION  0x1x23L   // SPEECH RECO corrections
+//#define    SOFTWAREVERSION  0x1x24L   // SPEECH RECO corrections
+                                        // Corrected TI_19
+//#define    SOFTWAREVERSION  0x1325L   // Corrected TI_2, TI_13, TI_16, TI_18
+                                        // Added ULYSSE switch
+//#define    SOFTWAREVERSION  0x1326L   // Update speech recognition interface to MMI
+                                        // Create audio loop and audio filter functions
+//#define    SOFTWAREVERSION  0x1327L   // Corrected TI_44 and TI_67.
+//#define    SOFTWAREVERSION  0x1328L   // Corrected TI_101,TI_121,TI_112,TI_104
+                                        // TI_100,TI_99,TI_134,TI_127,TI_126
+//#define    SOFTWAREVERSION  0x1329L   // Corrects TI_181/182/183/184/185/186/187/193/194
+                                        //          210/212/216/217
+//#define    SOFTWAREVERSION  0x1330L   // Corrected TI_122, TI_124 and TI_125.
+//#define    SOFTWAREVERSION  0x1331L   // Extensions for VoiceMemo and Melodies
+//#define    SOFTWAREVERSION  0x1332L   // Integration of PASCAL RF drivers with new RF structure
+                                        // Integration of new H/W drivers for B-sample and EVA4 board
+                                        // Integration of bootloader for flash
+//#define    SOFTWAREVERSION  0x1333L   // include the old versions:
+                                        // (!!ALRVERSION is no more used!!)
+                                        // ALRVERSION  0x0003L => Corrected TI_14, TI_15, TI_17
+                                        // ALRVERSION  0x0004L => Correction of TI_23,TI_24,
+                                        //                        TI_25,TI_29,TI_30
+                                        // ALRVERSION  0x0005L => Correction of TI_108, TI_133, TI_139
+                                        // ALRVERSION  0x0006L => Correction of TI_160,TI_246, TI_153,
+                                        //                        TI_265, TI_289,TI_283,TI_80
+                                        // ALRVERSION  0x0007L => Correction of BUG_539:
+                                        //                        suppress Vega compatibility
+                                        // ALRVERSION  0x0008L => Correction of TI_188,TI_169,
+                                        //                        TI_225,TI_243, PB659,PB660,PB661,
+                                        //                       PB662,PB679, PB680, PB 681
+                                        //
+                                        // Correction: BUG_569,BUG_557,BUG_566,BUG_584,TI_253,TI_32,
+                                        //             TI_137,BUG_534,BUG_651,TI_253,BUG_534
+//#define    SOFTWAREVERSION  0x1334L   // New trace (TRACE_TYPE 1 and 4), corrected BUG00683
+//#define    SOFTWAREVERSION  0x1335L   // Corrected bug TI_2622, TI_263, TI_264, TI_298, BUG532,
+                                        // BUG531, BUG537, BUG758.
+
+//#define    SOFTWAREVERSION  0x1336L   // Corrected bug BUG583 and the change CHG669.
+//#define    SOFTWAREVERSION  0x1337L   // Corrected TI_266, BUG_657, BUG_686, BUG_698
+//#define    SOFTWAREVERSION  0x1338L   // Corrected BUG_685, BUG_748, CHG_766, REQ_767, REQ_768,
+                                        // REQ_769, BUG_773 (new patch_file17)
+                                        // Integration of TM3
+//#define    SOFTWAREVERSION  0x1339L   // Corrected BUG_759, BUG_760, REQ_822, BUG_829, BUG_832
+                                        // TI_244
+//#define    SOFTWAREVERSION  0x1340L   // adapted to simulator (ALR_SIMUVERSION 0x0002)
+                                        // corrected TI_116
+//#define    SOFTWAREVERSION  0x1341L   // Trace rework step 2: use of a Riviera Tool trace module
+                                        // emulator - Corrected TI_206
+//#define    SOFTWAREVERSION  0x1342L   // Corrected CHG939.
+//#define    SOFTWAREVERSION  0x1343L   // Corrected BUG960, BUG961.
+//#define    SOFTWAREVERSION  0x1344L   // Corrected BUG0878, BUG0880.
+//#define    SOFTWAREVERSION  0x1345L   // Corrected TI_242, TI_198, REQ_870, BUG_881,BUG_887,
+                                        // BUG 693, CHG_856, BUG_932, REQ_934, BUG_962, BUG_973
+//#define    SOFTWAREVERSION  0x1346L   // Test mode version 0400 implementation
+                                        // Update of BUG887
+//#define    SOFTWAREVERSION  0x1347L   // IDS simulation corrections : BUG00654 BUG00655 BUG00656
+//#define    SOFTWAREVERSION  0x1348L   // correction of compilation problem related to IDS trace : BUG_1061
+//#define    SOFTWAREVERSION  0x1349L   // correction of CHG_770, BUG_1013, BUG_1047
+//#define    SOFTWAREVERSION  0x1350L   // This version contains the audio rework described in the S916 spec.
+                                        // Moreover, the following bugs are fixed:
+                                        // CHG00788, BUG00926, BUG00963, CHG00969, BUG01042, BUG01049, BUG0530,
+                                        // BUG00677, BUg00704, REQ00738, BUG00966, CHG01089, TI_209,
+                                        // TI_211, TI_273.TI_274.
+//#define    SOFTWAREVERSION  0x1351L   // Corrected TI_52, TI_208, BUG1012, BUG719, BUG1052, BUG1078
+//#define    SOFTWAREVERSION  0x1352L   // Change due to the customer request:REQ1191.
+                                        // Corrected bug: BUG1194.
+//#define    SOFTWAREVERSION  0x1353L   // Corrected BUG0551, BUG1268, BUG1277, BUG1283, BUG1284, BUG1286,
+                                        // REQ_1371, BUG1376
+//#define    SOFTWAREVERSION  0x1354L   // Corrected BUG1268, BUG1286, BUG1426
+//#define    SOFTWAREVERSION  0x1355L   // Corrected BUG1435
+//#define    SOFTWAREVERSION  0x1356L   // Corrected REQ1422, BUG1491, BUG1433,
+                                        // REQ1538
+//#define    SOFTWAREVERSION  0x1357L   // Corrected REQ1420, CHG1500, REQ1503
+//#define    SOFTWAREVERSION  0x1358L   // Corrected REQ1232, BUG1253, REQ1328, BUG1330, BUG1729
+//#define    SOFTWAREVERSION  0x1359L   // Corrected REQ1431, BUG1520, BUG1223
+//#define    SOFTWAREVERSION  0x1360L   // Corrected BUG1734
+//#define    SOFTWAREVERSION  0x1361L   // Corrected BUG1360,BUG950,REQ849,REQ1627,BUG1738
+//#define    SOFTWAREVERSION  0x1362L   // Corrected CHG1289, BUG1719, BUG1720, REQ1722, CHG1724.
+//#define    SOFTWAREVERSION  0x1363L   // Corrected REQ1552, REQ1612, BUG1650.
+//#define    SOFTWAREVERSION  0x1364L   // Corrected BUG848, BUG1473
+//#define    SOFTWAREVERSION  0x1365L   // Corrected BUG1558
+//#define    SOFTWAREVERSION  0x1366L   // Corrected BUG1791
+//#define    SOFTWAREVERSION  0x1367L   // AMR integration REQ1858
+                                        // Corrected BUG1825, BUG1818, BUG1809,
+                                        // CHG1638, BUG1803,
+//#define    SOFTWAREVERSION  0x1368L   // Closed REQ1917, REQ1919, REQ1920
+//#define    SOFTWAREVERSION  0x1369L   // Closed BUG1952, REQ1953, BUG1954, BUG1955, CHG1956, new DSP code: 34 (AMR)
+//#define    SOFTWAREVERSION  0x1370L   // Closed REQ1209, BUG1813, BUG1814, BUG1815, REQ1816, REQ1817
+                                        // BUG1823, BUG1824, BUG1991, REQ1992
+//#define    SOFTWAREVERSION  0x1371L   // Closed BUG1848,BUG1937,BUG1990
+//#define    SOFTWAREVERSION  0x1372L   // Corrected BUG1837, CHG1943, CHG1944
+//#define    SOFTWAREVERSION  0x1373L   // Corrected CHG2003, BUG2011, BUG2020, BUG2015, BUG2025, update DSP code 34
+//#define    SOFTWAREVERSION  0x1374L   // Corrected CHG2080
+//#define    SOFTWAREVERSION  0x1375L   // Closed CHG02057, REQ02086
+//#define    SOFTWAREVERSION  0x1376L   // Closed REQ02114
+//#define    SOFTWAREVERSION  0x1377L   // Closed BUG1941, REQ1998, BUG2047, BUG2049, BUG2019, BUG2113, BUG2148
+//#define    SOFTWAREVERSION  0x1378L   // Melody E2 REQ2129
+//#define    SOFTWAREVERSION  0x1379L   // Bug2160, BUG2166
+//#define    SOFTWAREVERSION  0x1380L   // BUG2223, BUG2251, BUG2229, BUG2228, BUG2235,
+                                        // REQ2204, BUG2249, BUG2203, CHG2230, BUG2175,
+                                        // BUG2178, BUG2188, BUG2171
+//#define    SOFTWAREVERSION  0x1381L   // REQ2262
+//#define    SOFTWAREVERSION  0x1382L   // BUG2048, BUG2050, BUG2294, BUG2295, BUG2285,
+                                        // REQ2315, REQ2316
+//#define    SOFTWAREVERSION  0x1383L   // Corrected REQ1708, BUG1746, REQ2009, REQ2292, REQ2317
+//#define    SOFTWAREVERSION  0x1384L   //REQ2367,BUG2350,BUG2343,BUG2266,BUG2364,BUG2293,BUG2259
+                                        //BUG2277,BUG2368,BUG2348,BUG2245,REQ2373
+//#define    SOFTWAREVERSION  0x1385L   // Corrected CHG842, BUG2162, BUG2176, BUG2260
+
+//#define    SOFTWAREVERSION  0x1386L   // Corrected BUG2265, BUG2308, BUG2334, BUG2418
+                                        // BUG2282, BUG1967,BUg2423, BUG2424, BUG2425
+//#define    SOFTWAREVERSION  0x1387L   // Corrected REQ2428, REQ2386, CHG2432
+//#define    SOFTWAREVERSION  0x1388L   // Corrected REQ2447
+//#define    SOFTWAREVERSION  0x1389L   // Corrected BUG02486, CHG02487, BUG02488, BUG02492
+//#define    SOFTWAREVERSION  0x1390L   // Corrected REQ02500
+//#define    SOFTWAREVERSION  0x1391L   // Corrected REQ02345, BUG02388, BUG02434, BUG02436, BUG02461, BUG02462,
+                                        //           BUG02526, BUG02547, BUG02548, BUG02549, REQ02551
+//#define    SOFTWAREVERSION  0x1392L   // Corrected REQ02583,
+//#define    SOFTWAREVERSION  0x1393L   // Corrected REQ2381 (L1 Binary Trace)
+//#define    SOFTWAREVERSION  0x1394L   // Corrected REQ2516 (2nd order Tx Temperature Calibration)
+                                        // Corrected BUG1993 (Testmode now functional in standalone mode)
+//#define    SOFTWAREVERSION  0x1395L   // Integration of new AEC (Spec S892, REQ02477)
+                                        // Corrected BUG02279, CHG02349, BUG02370, REQ02401, REQ02412, BUG02435, BUG02473,
+                                        //           BUG02525, CHG02582, BUG02586, BUG02588, BUG02600
+//#define    SOFTWAREVERSION  0x1396L   // Corrected BUG2608
+                                        // Integration of REQ2571, REQ2572, REQ2603
+//#define    SOFTWAREVERSION  0x1397L   // Corrected BUG1843, CHG2136, BUG2453
+//#define    SOFTWAREVERSION  0x1398L   // Integration of Voice Memo AMR
+                                        // CHG02618, CHG02620, CHG02622
+//#define    SOFTWAREVERSION  0x1399L   // REQ2374,BUG2613,REQ2573,BUG2433,BUG2528,BUG2567
+//#define    SOFTWAREVERSION  0x1400L   // BUG2630, BUG2638, REQ2643, new DSP patch files 0x2120 and 0x4120
+//#define    SOFTWAREVERSION  0x1401L   // BUG2493,BUG2539,BUG2587,BUG2472,BUG2540
+//#define    SOFTWAREVERSION  0x1402L   // REQ02736, REQ02740, BUG02733
+//#define    SOFTWAREVERSION  0x1403L   // BUG2674, BUG2695, BUG2713, BUG2714, CHG2715, BUG2724, BUG2731, BUG2734, BUG2744
+//#define    SOFTWAREVERSION  0x1404L   // BUG2542, BUG2615, BUG2687, REQ2748
+//#define    SOFTWAREVERSION  0x1405L   // REQ02685, CHG02760, BUG02761, CHG02763, CHG02764
+//#define    SOFTWAREVERSION  0x1406L   // BUG2563, BUG2663, BUG2703, BUG2719, BUG2750, CHG2773, CHG2774, CHG2775, BUG2776, BUG2777, New DSP patch files 0x2140 and 0x4130
+//#define    SOFTWAREVERSION  0x1407L   // CHG02814, CHG02815, CHG02816, CHG02817, CHG02818,CHG02819, CHG2820, BUG02782, BUG02813
+//#define    SOFTWAREVERSION  0x1408L   // REQ2845, BUG2846
+//#define    SOFTWAREVERSION  0x1409L   // CHG2356, CHG2490, BUG2778, BUG2787, CHG2816, BUG02848, CHG02850, CHG02851
+//#define    SOFTWAREVERSION  0x1410L   // CHG2877, CHG2879, BUG2883, REQ2884, BUG2891, CHG2898
+//#define    SOFTWAREVERSION  0x1411L   // BUG02705, BUG02730, BUG02766, BUG02855
+//#define    SOFTWAREVERSION  0x1412L   // CHG2972, BUG2928, BUG2929, CHG2931, BUG2932, BUG2933, REQ2934, CHG2935, REQ2936, CHG2938
+//#define    SOFTWAREVERSION  0x1413L   // REQ2338, BUG2864, REQ2952, BUG2963, CHG2969, CHG2973, CHG2985, BUG2996, BUG3013
+//#define    SOFTWAREVERSION  0x1414L   // BUG02467, CHG02497, BUG02580, BUG02921, BUG02922, REQ02997, CHG03005, CHG3041, CHG03042
+//#define    SOFTWAREVERSION  0x1415L   // REQ02965: WCP integration
+//#define    SOFTWAREVERSION  0x1416L   // REQ03070, REQ03075, CHG02898
+//#define    SOFTWAREVERSION  0x1417L   // BUG03064, BUG03060, REQ03071, REQ03077, CHG03088, BUG03089, REQ03091
+//#define    SOFTWAREVERSION  0x1418L   // REQ2947, CHG3087, BUG3093, CHG3104
+//#define    SOFTWAREVERSION  0x1419L   // BUG3191, BUG3190, BUG3114, BUG3118, BUG3121, BUG3124, BUG3141, BUG3146, BUG3158, BUG3167, REQ3202, BUG3213, BUG3138, BUG3140, BUG3139
+//#define    SOFTWAREVERSION  0x1420L   // CHG03154, CHG03155, BUG03125, REQ03194, REQ03204, REQ03218, REQ03219, CHG03230, REQ03231
+//#define    SOFTWAREVERSION  0x1421L   // CHG3057, REQ3062, REQ3063, CHG3120, CHG3134, CHG3135, BUG3189, BUG3207, CHG3227, BUG3246, CHG3250, BUG3251
+//#define    SOFTWAREVERSION  0x1422L   // BUG03212, BUG03174, REQ03241, REQ03242, REQ03243, REQ03244, REQ03262, BUG03265, BUG03266
+//#define    SOFTWAREVERSION  0x1423L   // BUG03184, BUG03182, REQ03248
+//#define    SOFTWAREVERSION  0x1424L   // BUG3083, BUG3188, BUG3221, REQ3228, BUG3257, CHG3264, BUG3267, BUG3268, CHG3269, BUG3273, BUG3293, BUG3294, BUG3295, BUG3300
+//#define    SOFTWAREVERSION  0x1425L   // CHG03307
+//#define    SOFTWAREVERSION  0x1426L   // CHG03059, CHG03306, CHG3319, CHG3330, BUG03331, CHG03344, CHG3345, CHG3346, CHG03347, REQ03349, CHG03352
+//#define    SOFTWAREVERSION  0x1427L   // CHG03382, CHG03394, BUG03395, BUG03403, CHG03405, REQ03406
+//#define    SOFTWAREVERSION  0x1428L   // CHG03415, CHG03402, CHG03411, REQ03414, REQ03396, REQ03410, BUG03401, BUG03312, BUG03372.
+//#define    SOFTWAREVERSION  0x1429L   // CHG03417 
+//#define    SOFTWAREVERSION  0x1430L   // CHG03425, BUG03371, REQ03429, REQ03431, CHG03432, CHG03434
+//#define    SOFTWAREVERSION  0x1431L   // CHG2438, BUG2783, BUG3142, BUG3351, BUG3358, BUG3370, BUG3377, BUG3378, BUG3407, BUG3424, CHG3456, BUG3457, CHG3460, BUG3461
+//#define    SOFTWAREVERSION  0x1432L   // CHG3472 
+
+//#define    DEVELPMTVERSION  0x0001L
+//#define    DEVELPMTVERSION  0x0002L  // Corrected TI_4, TI_7, TI_12
+//#define    DEVELPMTVERSION  0x0003L  // Corrected TI_14, TI_15, TI_17
+
+
+/*************************************************************************/
+/* PORTING L1 TO GSM 1.5 Version Integrated on Evaluation board 3 / 4    */
+/*************************************************************************/
+
+//#define    PORT1.5VERSION     0x0001L;  // TI_13, TI_9, TI_11 fixed
+//#define    PORT1.5VERSION     0x0002L;  // Omega PG 2.0 code integration
+//#define    PORT1.5VERSION     0x0003L;  // DSP17, ULYSSE init
+//#define    PORT1.5VERSION     0x0004L;  // Remove RIF TX/RX delay for Omega, correct one
+                                          // string definition in l1_drive.c under DCS1800 compile switch
+//#define    PORT1.5VERSION     0x0005L;  // added Omega 2.0 RF drivers
+//#define    PORT1.5VERSION     0x0006L;  // added switch SPEECH_RECO in l1_defty.h
+//#define    PORT1.5VERSION     0x0007L;  // TI_46, TI_47, TI_48 fixed
+//#define    PORT1.5VERSION     0x0008L;  // added melody generators
+//#define    PORT1.5VERSION     0x0009L;  // fixed ULPD bugs TI_64 & TI_65
+                                          // added SETUP_RF to SETUP_FRAME
+                                          // don't call sleep_mnager if gauging
+//#define    PORT1.5VERSION     0x0010L;  // (fix TI_78,TI_79,TI_92, TI_93,TI_94,TI_95)
+//#define    PORT1.5VERSION     0x0011L;  // fixed bugs : Melody generator (DSP/MCU bugs)
+//#define    PORT1.5VERSION     0x0012L;  // Clean up of spi functions, AFC_ON switch,VDX
+                                          // mute ported for Omega 2.1 and later versions
+//#define    PORT1.5VERSION     0x0013L;  // added Omega 13 Mhz stop/start for deep sleep
+//#define    PORT1.5VERSION     0x0014L;  // Added audio control functions and TXPWR management for Omega
+//#define    PORT1.5VERSION     0x0015L;  // Porting of L1 and drivers for G1, SAMSON
+                                          // Integration of PTOOL S/W
+//#define    PORT1.5VERSION     0x0016L   // SR correction + prepare for DSP background management
+                                          // + DSP patch 0x06E0
+                                          // TI_232, TI_241, TI_247, TI_250
+//#define    PORT1.5VERSION     0x0017L;  // Porting for SLX RF on EVA4 board
+//#define    PORT1.5VERSION     0x0018L   // SR rejection of OOV during Update TI278
+                                          // + Melody Abort rework TI285
+/////////////////////////////////////
+// PORT1.5 version is no more used //
+/////////////////////////////////////
+
+// added for new naming conventions
+//#define PROGRAM_RELEASE_VERSION       0x2112
+//#define PROGRAM_RELEASE_VERSION       0x2118	// release 1446 is for TCS2.1.1.8
+//#define PROGRAM_RELEASE_VERSION       0x2119	// release 1448 is for TCS2.1.1.9
+//#define PROGRAM_RELEASE_VERSION       0x211A	// release 1450 is for TCS2.1.1.10
+//#define PROGRAM_RELEASE_VERSION       0x211C	// release 1451 is for TCS2.1.1.12 -> switching to dynamic download
+#define PROGRAM_RELEASE_VERSION         0x211E	// release 1452 is for TCS2.1.1.14 
+
+/* Internal release numbering */
+//#define INTERNAL_VERSION	      0x1 // First version on ClearCase
+//#define INTERNAL_VERSION	      0x2 // Second subversion on mainline
+//#define INTERNAL_VERSION	      0x3 // Second subversion on mainline
+#define INTERNAL_VERSION	      0x0 // Official release
+
+/* Official external release numbering */
+//#define OFFICIAL_VERSION	      0x1432
+//#define OFFICIAL_VERSION	      0x1433
+//#define OFFICIAL_VERSION	      0x1434
+//#define OFFICIAL_VERSION	      0x1435
+//#define OFFICIAL_VERSION	      0x1436
+//#define OFFICIAL_VERSION	      0x1438
+//#define OFFICIAL_VERSION	      0x1439 
+//#define OFFICIAL_VERSION	      0x1440
+//#define OFFICIAL_VERSION	      0x1441
+//#define OFFICIAL_VERSION	      0x1442
+//#define OFFICIAL_VERSION	      0x1444
+//#define OFFICIAL_VERSION	      0x1445
+//#define OFFICIAL_VERSION	      0x1446
+//#define OFFICIAL_VERSION	      0x1447
+//#define OFFICIAL_VERSION	      0x1448
+//#define OFFICIAL_VERSION	      0x1449
+//#define OFFICIAL_VERSION	      0x1450
+//#define OFFICIAL_VERSION	      0x1451
+//#define OFFICIAL_VERSION	      0x1453
+#define OFFICIAL_VERSION	      0x1454
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/bsp/Makefile
--- a/nuc-fw/bsp/Makefile	Thu Oct 24 02:47:14 2013 +0000
+++ b/nuc-fw/bsp/Makefile	Sun Oct 27 04:43:04 2013 +0000
@@ -6,7 +6,7 @@
 
 IOBJS=	niq32.o
 
-XTOBJS=	armio.o clkm.o inth.o niq.o timer.o timer1.o timer2.o
+XTOBJS=	armio.o clkm.o init_target.o inth.o niq.o timer.o timer1.o timer2.o
 
 XOBJS=	${XTOBJS}
 AOBJS=	${IOBJS}
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/bsp/clkm.h
--- a/nuc-fw/bsp/clkm.h	Thu Oct 24 02:47:14 2013 +0000
+++ b/nuc-fw/bsp/clkm.h	Sun Oct 27 04:43:04 2013 +0000
@@ -107,19 +107,19 @@
   #define DPLL_PLL_DIV      0x0060     // Mask of division factor configuration
   #define DPLL_PLL_MULT     0x0F80     // Mask of multiply factor configuration
 
-  #define DPLL_BYPASS_DIV_1 0x00       // Configuration of bypass mode divided by 1
-  #define DPLL_BYPASS_DIV_2 0x01       // Configuration of bypass mode divided by 2
-  #define DPLL_BYPASS_DIV_4 0x10       // Configuration of bypass mode divided by 4
-  
+  #define DPLL_BYPASS_DIV_1 0x0        // Configuration of bypass mode divided by 1
+  #define DPLL_BYPASS_DIV_2 0x1        // Configuration of bypass mode divided by 2
+  #define DPLL_BYPASS_DIV_4 0x2        // Configuration of bypass mode divided by 4
+
   #define DPLL_BYPASS_DIV_OFFSET 2     // Offset of bypass bits configuration
   #define DPLL_PLL_DIV_OFFSET    5     // Offset of division bits configuration
   #define DPLL_PLL_MULT_OFFSET   7     // Offset of multiply bits configuration
-  
+
   #define DPLL_LOCK_DIV_1   0x0000     // Divide by 1 when DPLL is locked
   #define DPLL_LOCK_DIV_2   0x0001     // Divide by 2 when DPLL is locked
   #define DPLL_LOCK_DIV_3   0x0002     // Divide by 3 when DPLL is locked
   #define DPLL_LOCK_DIV_4   0x0003     // Divide by 4 when DPLL is locked
-  
+
 #else
   #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6)     /* Lead PLL */
   #define CLKM_PLONOFF	0x0001         // PLL enable signal
@@ -260,8 +260,12 @@
 /*
  * NOTE: the version of the CLKM_INITCNTL() macro in the Sotomodem source
  * does |= instead of =.  It remains to be investigated which is more correct.
+ *
+ * For now I'll define the ORing version under a different (and more
+ * descriptive) name: CLKM_CNTL_OR.
  */
 
+#define CLKM_CNTL_OR(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= value)
 
 #if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
   /*---------------------------------------------------------------/
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/bsp/init_target.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/init_target.c	Sun Oct 27 04:43:04 2013 +0000
@@ -0,0 +1,359 @@
+/*
+ * Init_Target() is the first function called from Application_Initialize().
+ * But unfortunately, our TCS211 semi-src has this function in a binary lib.
+ * I was able to find a conditioned-out version in the LoCosto source that
+ * seems to be a fit - so I'm going to massage it a bit to match the sequence
+ * of operations seen in the disassembly of our reference binary.
+ */
+
+#include "../include/config.h"
+#include "../include/sys_types.h"
+
+#include "mem.h"
+#include "clkm.h"
+#include "armio.h"
+#include "timer.h"
+#include "inth.h"
+#include "rhea_arm.h"
+#include "ulpd.h"
+
+/* TPU_FREEZE is defined in l1_const.h */
+#include "../L1/include/l1_confg.h"
+#include "../L1/include/l1_const.h"
+
+void Init_Target(void)
+{
+#if 1 //(PSP_STANDALONE == 0)
+    // RIF/SPI rising edge clock for ULYSSE
+    //--------------------------------------------------
+    #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
+      #if ((CHIPSET >= 3))
+        #if (CHIPSET == 12)
+          F_CONF_RIF_RX_RISING_EDGE;
+          F_CONF_SPI_RX_RISING_EDGE;
+        #elif (CHIPSET == 15)
+	     //do the DRP init here for Locosto
+	     #if (L1_DRP == 1)
+	     //  drp_power_on(); This should be done after the script is downloaded.
+	     #endif
+        #else
+          #if (BOARD==35)
+            *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x2000;
+          #else
+            *((volatile SYS_UWORD16 *) ASIC_CONF) = 0x6000;
+          #endif   /* (BOARD == 35) */
+        #endif
+      #endif
+    #endif   /* ANLG(ANALOG)) */
+
+    #if 0 //(OP_L1_STANDALONE == 1)
+      #if (BOARD == 40) || (BOARD == 41) || \
+            (BOARD == 42) || (BOARD == 43) || (BOARD == 45)
+        // enable 8 Ohm amplifier for audio on D-sample
+        AI_ConfigBitAsOutput (1);
+        AI_SetBit(1);
+      #elif (BOARD == 70) || (BOARD == 71)
+	  //Locosto I-sample or UPP costo board.BOARD
+	  // Initialize the ARMIO bits as per the I-sample spec
+	  // FIXME
+      #endif
+    #endif   /* (OP_L1_STANDALONE == 1) */
+#endif /* PSP_STANDALONE ==0 */
+
+    // Watchdog
+    //--------------------------------------------------
+    TM_DisableWatchdog();    /* Disable Watchdog */
+    #if (CHIPSET == 12) || (CHIPSET == 15)
+      TM_SEC_DisableWatchdog();
+    #endif
+
+    #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
+
+      /*
+       *  Enable/Disable of clock switch off for INTH, TIMER, BRIDGE and DPLL modules
+       */
+      // IRQ, Timer and bridge may SLEEP
+      // In first step, same configuration as SAMSON
+      //--------------------------------------------------
+      #if (CHIPSET == 12)
+        CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_BRIDGE_DIS | CLKM_DPLL_DIS);
+      #elif (CHIPSET == 15)
+CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_TIMER_DIS | CLKM_CPORT_EN | CLKM_BRIDGE_DIS | 0x8000 ); /* CLKM_DPLL_DIS is remove by Ranga*/
+
+      #else
+        CLKM_CNTL_OR(CLKM_IRQ_DIS | CLKM_TIMER_DIS);
+
+        // Select VTCXO input frequency
+        //--------------------------------------------------
+        CLKM_UNUSED_VTCXO_26MHZ;
+
+        // Rita RF uses 26MHz VCXO
+        #if (RF_FAM == 12)
+          CLKM_USE_VTCXO_26MHZ;
+        #endif
+        // Renesas RF uses 26MHz on F-sample but 13MHz on TEB
+        #if (RF_FAM == 43) && (BOARD == 46)
+          CLKM_USE_VTCXO_26MHZ;
+        #endif
+      #endif
+
+      // Control HOM/SAM automatic switching
+      //--------------------------------------------------
+      *((volatile unsigned short *) CLKM_CNTL_CLK) &= ~CLKM_EN_IDLE3_FLG;
+
+      /*
+       * Disassembly of Init_Target() in init.obj in main.lib in the
+       * Leonardo reference version reveals that the code does the
+       * following at this point:
+       */
+      RHEA_INITRHEA(0,0,0xFF);
+      DPLL_INIT_BYPASS_MODE(DPLL_BYPASS_DIV_1);
+      DPLL_INIT_DPLL_CLOCK(DPLL_LOCK_DIV_1, 8);
+      CLKM_InitARMClock(0x00, 2, 0); /* no low freq, no ext clock, div by 1 */
+      /* at this point the original code sets up the memory wait states */
+      /* we'll do it differently */
+      RHEA_INITAPI(0,1);
+      RHEA_INITARM(0,0);
+      DPLL_SET_PLL_ENABLE;
+
+      /*
+       *  Disable and Clear all pending interrupts
+       */
+      #if (CHIPSET == 12) || (CHIPSET == 15)
+        F_INTH_DISABLE_ALL_IT;           // MASK all it
+        F_INTH2_VALID_NEXT(C_INTH_IRQ);  // reset current IT in INTH2 IRQ
+        F_INTH_VALID_NEXT(C_INTH_IRQ);   // reset current IT in INTH IRQ
+        F_INTH_VALID_NEXT(C_INTH_FIQ);   // reset current IT in INTH FIQ
+        F_INTH_RESET_ALL_IT;             // reset all IRQ/FIQ source
+      #else
+        INTH_DISABLEALLIT;
+        INTH_RESETALLIT;
+        INTH_CLEAR;                 /* reset IRQ/FIQ source */
+      #endif
+
+      // INTH
+      //--------------------------------------------------
+      #if (CHIPSET == 12) || (CHIPSET == 15)
+        #if (GSM_IDLE_RAM != 0)
+          f_inth_setup((T_INTH_CONFIG *)a_inth_config_idle_ram);   // setup configuration IT handlers
+        #else
+          f_inth_setup((T_INTH_CONFIG *)a_inth_config);   // setup configuration IT handlers
+        #endif
+      #else
+        IQ_SetupInterrupts();
+      #endif
+
+      // DMA
+      //--------------------------------------------------
+      // channel0 = Arm, channel1 = Lead, channel2 = forced to Arm, channel3=forced to Arm, dma_burst = 0001, priority = same
+      #if 1 //(OP_L1_STANDALONE == 0)
+        DMA_ALLOCDMA(1,0,1,1);  // Channel 1 used by DSP with RIF RX
+      #endif
+
+      /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
+
+    #else
+
+      // RHEA Bridge
+      //--------------------------------------------------
+      // ACCES_FAC_0 = 0, ACCES_FAC_1 = 0 ,TIMEOUT = 0x7F
+      RHEA_INITRHEA(0,0,0x7F);
+
+      #if (CHIPSET == 6)
+        // WS_H = 1 , WS_L = 15
+        RHEA_INITAPI(1,15);          // should be 0x01E1 for 65 Mhz
+      #else
+        // WS_H = 0 , WS_L = 7
+        RHEA_INITAPI(0,7);           // should be 0x0101 for 65 Mhz
+      #endif
+
+      // Write_en_0 = 0 , Write_en_1 = 0
+      RHEA_INITARM(0,0);
+
+      // INTH
+      //--------------------------------------------------
+      INTH_DISABLEALLIT;          // MASK all it
+      INTH_CLEAR;                 // reset IRQ/FIQ source
+      IQ_SetupInterrupts();
+
+      // DMA
+      //--------------------------------------------------
+      // channel0 = Arm, channel1 = Lead, dma_burst = 0001, priority = same
+      DMA_ALLOCDMA(1,0,1,1);      // should be 0x25   (channel 1 = lead)
+
+      #if (CHIPSET == 6)
+        // Memory WS configuration for ULYSS/G1 (26 Mhz) board
+        //-----------------------------------------------------
+        MEM_INIT_CS2(2,MEM_DVS_16,MEM_WRITE_EN,0);
+      #endif
+
+      // CLKM
+      //--------------------------------------------------
+      CLKM_InitARMClock(0x00, 2); /* no low freq, no ext clock, div by 1 */
+
+      #if (CHIPSET == 6)
+        CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS | CLKM_VTCXO_26);
+      #else
+        CLKM_INITCNTL(CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS);
+      #endif
+
+    #endif   /* CHIPSET = 4 or 7 or 8 or 10 or 11 or 12 */
+
+    // Freeze ULPD timer ....
+    //--------------------------------------------------
+    *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_INIT_REG ) = 0;
+    *((volatile SYS_UWORD16 *) ULDP_GSM_TIMER_CTRL_REG ) = TPU_FREEZE;
+
+    // reset INC_SIXTEEN and INC_FRAC
+    //--------------------------------------------------
+    #if 0 //(OP_L1_STANDALONE == 1)
+      l1ctl_pgm_clk32(DEFAULT_HFMHZ_VALUE,DEFAULT_32KHZ_VALUE);
+    #else
+      ULDP_INCSIXTEEN_UPDATE(132);    //32768.29038  =>132, 	32500 => 133
+                                      // 26000 --> 166
+      ULDP_INCFRAC_UPDATE(15840);     //32768.29038  =>15840,	32500 => 21845
+                                      // 26000 --> 43691
+    #endif   /*  OP_L1_STANDALONE */
+
+    // program ULPD WAKE-UP ....
+    //=================================================
+    #if (CHIPSET == 2)
+       *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG)  = SETUP_FRAME;  // 2 frame
+       *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG)  = SETUP_VTCXO;  // 31 periods
+       *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
+       *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG)  = SETUP_CLK13;  // 31 periods
+    #else
+       *((volatile SYS_UWORD16 *)ULDP_SETUP_FRAME_REG)  = SETUP_FRAME;  // 3 frames
+       *((volatile SYS_UWORD16 *)ULDP_SETUP_VTCXO_REG)  = SETUP_VTCXO;  // 0 periods
+       *((volatile SYS_UWORD16 *)ULDP_SETUP_SLICER_REG) = SETUP_SLICER; // 31 periods
+       *((volatile SYS_UWORD16 *)ULDP_SETUP_CLK13_REG)  = SETUP_CLK13;  // 31 periods
+       *((volatile SYS_UWORD16 *)ULPD_SETUP_RF_REG)     = SETUP_RF;     // 31 periods
+    #endif
+
+    #if (CHIPSET == 15)
+      *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SLEEPN)    = SETUP_SLEEPZ;    // 0
+      *((volatile SYS_UWORD16 *)ULPD_DCXO_SETUP_SYSCLKEN)  = SETUP_SYSCLKEN;  // 255 clocks of 32 KHz for 7.8 ms DCXO delay for Locosto
+	  *((volatile SYS_UWORD16 *)0xFFFEF192) = 0x1; //CLRZ
+  	  *((volatile SYS_UWORD16 *)0xFFFEF190) = 0x2; //SLPZ
+	  *((volatile SYS_UWORD16 *)0xFFFEF18E)= 0x2; //SYSCLKEN
+	  *((volatile SYS_UWORD16 *)0xFFFEF186) = 0x2; //CLK13_EN
+	  *((volatile SYS_UWORD16 *)0xFFFEF18A) = 0x2; //DRP_DBB_SYSCLK
+    #endif
+
+    // Set Gauging versus HF (PLL)
+    //=================================================
+    ULDP_GAUGING_SET_HF;                // Enable gauging versus HF
+    ULDP_GAUGING_HF_PLL;                // Gauging versus PLL
+
+    // current supply for quartz oscillation
+    //=================================================
+    #if 0 //(OP_L1_STANDALONE == 1)
+      #if ((CHIPSET != 9) && (CHIPSET != 12) && (CHIPSET !=15)) // programming model changed for Ulysse C035, stay with default value
+        *(volatile SYS_UWORD16 *)QUARTZ_REG  = 0x27;
+      #endif
+    #else
+      #if ((BOARD == 6) || (BOARD == 8) || (BOARD == 9) || (BOARD == 35) || (BOARD == 40) || (BOARD == 41))
+        *((volatile SYS_UWORD16 *)QUARTZ_REG)  = 0x27;
+      #elif (BOARD == 7)
+        *((volatile SYS_UWORD16 *)QUARTZ_REG)  = 0x24;
+      #endif
+    #endif   /* OP_L1_STANDALONE */
+
+    // stop Gauging if any (debug purpose ...)
+    //--------------------------------------------------
+    if ( *((volatile SYS_UWORD16 *) ULDP_GAUGING_CTRL_REG) & ULDP_GAUGING_EN)
+    {
+      volatile int j;
+      ULDP_GAUGING_STOP; /* Stop the gauging */
+      /* wait for gauging it*/
+      // one 32khz period = 401 periods of 13Mhz
+      for (j=1; j<50; j++);
+      while (! (* (volatile SYS_UWORD16 *) ULDP_GAUGING_STATUS_REG) & ULDP_IT_GAUGING);
+    }
+
+    #if 1 //(OP_L1_STANDALONE == 0)
+      AI_ClockEnable ();
+
+      #if (BOARD == 7)
+        // IOs configuration of the B-Sample in order to optimize the power consumption
+        AI_InitIOConfig();
+
+        // Set LPG instead of DSR_MODEM
+        *((volatile SYS_UWORD16 *) ASIC_CONF) |= 0x40;
+        // Reset the PERM_ON bit of LCR_REG
+        *((volatile SYS_UWORD16 *) MEM_LPG) &= ~(0x80);
+      #elif ((BOARD == 8) || (BOARD == 9))
+        // IOs configuration of the C-Sample in order to optimize the power consumption
+        AI_InitIOConfig();
+
+        // set the debug latch to 0x00.
+        *((volatile SYS_UWORD8 *) 0x2800000) = 0x00;
+      #elif ((BOARD == 35) || (BOARD == 46))
+        AI_InitIOConfig();
+        // CSMI INTERFACE
+        // Initialize CSMI clients for GSM control
+        // and Fax/Data services
+          CSMI_Init();
+          GC_Initialize();  // GSM control initialization
+          CU_Initialize();  // Trace initialization
+          CF_Initialize();  // Fax/Data pre-initialization
+      #elif ((BOARD == 40) || (BOARD == 41))
+        // IOs configuration of the D-Sample in order to optimize the power consumption
+        AI_InitIOConfig();
+
+        #ifdef BTEMOBILE
+          // Reset BT chip by toggling the Island's nRESET_OUT signal
+          *((volatile SYS_UWORD16 *) 0xFFFFFD04) |= 0x04;
+          *((volatile SYS_UWORD16 *) 0xFFFFFD04) &= ~(0x4);
+        #endif
+
+	#if 0	// FreeCalypso
+        // set the debug latch to 0x0000.
+ 	    *((volatile SYS_UWORD16 *) 0x2700000) = 0x0000;
+	#endif
+      #elif ((BOARD == 70) || (BOARD == 71))
+	    AI_InitIOConfig();
+	    /* Mark The System configuration According to I-Sample */
+		/* Adding GPIO Mux Setting Here */
+		pin_configuration_all(); // Init Tuned for Power Management
+		/* A22 is Enabled in int.s hence not Here */
+		/* FIXME: PULL_UP Enable and PULL UP Values Need to revisited */
+
+	/* Add code to find out the manufacture id of NOR flash*/
+
+        // Copy ffsdrv_device_id_read() function code to RAM. The only known
+        // way to determine the size of the code is to look either in the
+        // linker-generated map file or in the assember output file.
+        ffsdrv_copy_code_to_ram((UWORD16 *) detect_code,
+                                (UWORD16 *) &ffsdrv_device_id_read,
+                                sizeof(detect_code));
+
+        // Combine bit 0 of the thumb mode function pointer with the address
+        // of the code in RAM. Then call the detect function in RAM.
+        myfp = (pf_t) (((int) &ffsdrv_device_id_read & 1) | (int) detect_code);
+        (*myfp)(0x06000000, &manufact, device_id);
+
+	enable_ps_ram_burst();
+
+	if( 0x7e == device_id[0] )
+	{
+	   enable_flash_burst();
+	   flash_device_id = 0x7E;
+	}
+	else
+	{
+	   enable_flash_burst_mirror();
+   	   flash_device_id = 0;
+	}
+
+	/* FreeCalypso: a bunch of dead code cut out */
+
+      #endif // BOARD
+
+      // Enable HW Timers 1 & 2
+      TM_EnableTimer (1);
+      TM_EnableTimer (2);
+
+    #endif  /* (OP_L1_STANDALONE == 0) */
+
+}
diff -r 17b0511b243c -r 1e41550feec5 nuc-fw/cfgmagic/post-target
--- a/nuc-fw/cfgmagic/post-target	Thu Oct 24 02:47:14 2013 +0000
+++ b/nuc-fw/cfgmagic/post-target	Sun Oct 27 04:43:04 2013 +0000
@@ -44,9 +44,11 @@
 
 case "$DBB_type" in
 	751992*)
+		# This chip is Calypso C035 with DSP version 36 in the ROM
 		CHIPSET=10
+		DSP=36
 		# Thanks to the Sotovik find, we now have authoritative
-		# knowledge that this number is correct.
+		# knowledge that these numbers are correct.
 		;;
 	*)
 		echo "Error: unknown DBB_type=$DBB_type" 1>&2
@@ -54,6 +56,7 @@
 		;;
 esac
 export_to_c	CHIPSET
+export_to_c	DSP
 
 if [ -z "$ABB_type" ]
 then