# HG changeset patch # User Michael Spacefalcon # Date 1383356891 0 # Node ID 2c5160a9d6528f228a91f19212f78c6d63dbb534 # Parent 035672b72f9beae4b602f69dbd2cfe8e9c6e7b93 nuc-fw: switched from nucdemo to Riviera, got some serial output diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/bsp/init_target.c --- a/nuc-fw/bsp/init_target.c Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/bsp/init_target.c Sat Nov 02 01:48:11 2013 +0000 @@ -12,6 +12,7 @@ #include "mem.h" #include "clkm.h" #include "armio.h" +#include "dma.h" #include "timer.h" #include "inth.h" #include "iq.h" diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/finlink/Makefile --- a/nuc-fw/finlink/Makefile Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/finlink/Makefile Sat Nov 02 01:48:11 2013 +0000 @@ -9,11 +9,11 @@ LIBGCC_A= `${CC} -print-file-name=libgcc.a -mthumb-interwork` LIBGCC_T= `${CC} -print-file-name=libgcc.a -mthumb-interwork -mthumb` -LOCAL_LIBS= ../sprintf/libsprintf.a \ +LOCAL_LIBS= ../riviera/librv.a ../sprintf/libsprintf.a \ ../nucleus/libplus.xip.a ../nucleus/libplus.iram.a -INT_PIECES= ../sysglue/sysinit.o -EXT_PIECES= ../nucdemo/demo.o +INT_PIECES= ../bsp/niq32.o +EXT_PIECES= ../bsp/xipcode.o ../serial/xipcode.o ../sysglue/xipcode.o all: ${RAM_TARGET} ramImage: ${RAM_TARGET} diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/finlink/ld-script.src --- a/nuc-fw/finlink/ld-script.src Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/finlink/ld-script.src Sat Nov 02 01:48:11 2013 +0000 @@ -28,6 +28,7 @@ *(xip.text*) xipcode.o(.text*) *libplus.xip.a:(.text*) + *librv.a:(.text*) *libsprintf.a:(.text*) /* let's put the ARM->Thumb veneers in the XIP section */ *(.glue_7) @@ -83,6 +84,7 @@ *(ext.bss*) xipcode.o(.bss* COMMON) *libplus.xip.a:(.bss* COMMON) + *librv.a:(.bss* COMMON) *libsprintf.a:(.bss* COMMON) . = ALIGN(4); } > XRAM diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/nucleus/Makefile --- a/nuc-fw/nucleus/Makefile Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/nucleus/Makefile Sat Nov 02 01:48:11 2013 +0000 @@ -5,15 +5,15 @@ RANLIB= arm-elf-ranlib IOBJS= csc.o erc.o pmc.o pmce.o pmd.o smc.o smce.o smd.o tcc.o tcce.o tcd.o \ - tct.o tmc.o tmd.o tms.o tmse.o tmt.o irqshell.o + tct.o tmc.o tmd.o tms.o tmse.o tmt.o #irqshell.o XTOBJS= dmc.o dmce.o dmd.o dmf.o dmi.o dms.o erd.o eri.o evc.o evce.o evd.o \ evf.o evi.o hic.o hid.o hii.o inc.o ioc.o ioce.o iod.o iof.o ioi.o \ lic.o lid.o mbc.o mbce.o mbd.o mbf.o mbi.o mbs.o mbse.o pic.o pice.o \ pid.o pif.o pii.o pis.o pise.o pmf.o pmi.o quc.o quce.o qud.o quf.o \ qui.o qus.o quse.o rlc.o rld.o smf.o smi.o sms.o smse.o tcf.o tcfe.o \ - tci.o tcs.o tcse.o tmf.o tmi.o \ - sdc.o tmcal.o + tci.o tcs.o tcse.o tmf.o tmi.o +# sdc.o tmcal.o XOBJS= ${XTOBJS} init.o AOBJS= ${IOBJS} init.o diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/nucleus/init.S --- a/nuc-fw/nucleus/init.S Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/nucleus/init.S Sat Nov 02 01:48:11 2013 +0000 @@ -289,8 +289,11 @@ @ default interrupts with Plus IRQs. Then setup the timer @ and begin the system clock. - BL INT_Interrupt_Init @ Install the vector table - BL INT_Timer_Initialize @ Initialize the timer +@ FreeCalypso change: we are now using TI's code structure +@ which handles the interrupts and the timers differently. + +@ BL INT_Interrupt_Init @ Install the vector table +@ BL INT_Timer_Initialize @ Initialize the timer @ Call INC_Initialize with a pointer to the first available memory @ address after the compiler's global data. This memory may be used diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/nucleus/tcc.c --- a/nuc-fw/nucleus/tcc.c Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/nucleus/tcc.c Sat Nov 02 01:48:11 2013 +0000 @@ -2780,7 +2780,12 @@ TCT_Unprotect(); } - +/* + * FreeCalypso: TI's GSM fw architecture does not use Nucleus' + * LISR framework. + */ + +#if 0 /*************************************************************************/ /* */ /* FUNCTION */ @@ -3053,8 +3058,4 @@ return(status); } - - - - - +#endif diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/nucleus/tct.S --- a/nuc-fw/nucleus/tct.S Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/nucleus/tct.S Sat Nov 02 01:48:11 2013 +0000 @@ -2291,8 +2291,11 @@ @ Nested interrupt. Save complete context on the current stack. TCT_Nested_Save: +/* No longer needed in the FreeCalypso version, as we can use r0 instead. */ +#if 0 @ 1. Save another register on the exception stack so we have enough to work with STMDB r13!,{r5} +#endif @ 2. Save the necessary exception registers into r1-r3 MOV r1,r13 @ Put the exception r13 into r1 @@ -2301,49 +2304,59 @@ MRS r3,spsr @ Put the exception spsr into r3 @ 3. Adjust the exception stack pointer for future exceptions - ADD r13,r13,#24 @ r13 will point to enable reg value when done + ADD r13,r13,#20 @ r13 reset to pre-interrupt value @ 4. Switch CPU modes to save context on system stack - MRS r5,CPSR @ Pickup the current CPSR - BIC r5,r5,#MODE_MASK @ Clear the mode bits + MRS r0,CPSR @ Pickup the current CPSR + BIC r0,r0,#MODE_MASK @ Clear the mode bits - ORR r5,r5,#SUP_MODE @ Change to supervisor mode (SVD) + ORR r0,r0,#SUP_MODE @ Change to supervisor mode (SVD) - MSR CPSR,r5 @ Switch modes (IRQ->SVC) + MSR CPSR,r0 @ Switch modes (IRQ->SVC) @ 5. Store the SVC r13 into r5 so the r13 can be saved as is. - MOV r5,r13 +@ FreeCalyspo: using r0 instead + MOV r0,r13 @ 6. Save the exception return address on the stack (r15). - STMDB r5!,{r4} - -@ 7. Save r6-r14 on stack - STMDB r5!,{r6-r14} + STMDB r0!,{r4} + +@ 7. Save r5-r14 on stack (used to be r6-r14) + STMDB r0!,{r5-r14} @ 8. Switch back to using r13 now that the original r13 has been saved. - MOV r13,r5 - + MOV r13,r0 + +/* no longer relevant */ +#if 0 @ 9. Get r5 and exception enable registers off of exception stack and @ save r5 (stored in r4) back to the system stack. LDMIA r1!,{r4-r5} STMDB r13!,{r4} MOV r4,r5 @ Put exception enable value into r4 +#endif @ 10. Get the rest of the registers off the exception stack and @ save them onto the system stack. LDMIA r1!,{r5-r8,r11} @ Get r0-r4 off exception stack STMDB r13!,{r5-r8,r11} @ Put r0-r4 on system stack +/* no longer relevant */ +#if 0 @ 11. Store the exception enable value back on the exception stack. STMDB r1,{r4} +#endif @ 12. Save the SPSR on the system stack (CPSR) STMDB r13!,{r3} +/* TI's approach to interrupt handling does not support re-enabling here */ +#if 0 @ 13. Re-enable interrupts MRS r1,CPSR BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) MSR CPSR,r1 +#endif BX r2 @ Return to calling ISR @ } @@ -2364,8 +2377,11 @@ @ Yes, a thread was interrupted. Save complete context on the @ thread's stack. +/* No longer needed in the FreeCalypso version, as we can use r0 instead. */ +#if 0 @ 1. Save another register on the exception stack so we have enough to work with STMDB r13!,{r5} +#endif @ 2. Save the necessary exception registers into r1-r3 MOV r1,r13 @ Put the exception r13 into r1 @@ -2374,41 +2390,48 @@ MRS r3,spsr @ Put the exception spsr into r3 @ 3. Adjust the exception stack pointer for future exceptions - ADD r13,r13,#24 @ r13 will point to enable reg value when done + ADD r13,r13,#20 @ r13 reset to pre-interrupt value @ 4. Switch CPU modes to save context on system stack - MRS r5,CPSR @ Pickup the current CPSR - BIC r5,r5,#MODE_MASK @ Clear the mode bits + MRS r0,CPSR @ Pickup the current CPSR + BIC r0,r0,#MODE_MASK @ Clear the mode bits - ORR r5,r5,#SUP_MODE @ Change to supervisor mode (SVD) + ORR r0,r0,#SUP_MODE @ Change to supervisor mode (SVD) - MSR CPSR,r5 @ Switch modes (IRQ->SVC) + MSR CPSR,r0 @ Switch modes (IRQ->SVC) @ 5. Store the SVC r13 into r5 so the r13 can be saved as is. - MOV r5,r13 +@ FreeCalyspo: using r0 instead + MOV r0,r13 @ 6. Save the exception return address on the stack (r15). - STMDB r5!,{r4} - -@ 7. Save r6-r14 on stack - STMDB r5!,{r6-r14} + STMDB r0!,{r4} + +@ 7. Save r5-r14 on stack (used to be r6-r14) + STMDB r0!,{r5-r14} @ 8. Switch back to using r13 now that the original r13 has been saved. - MOV r13,r5 - + MOV r13,r0 + +/* no longer relevant */ +#if 0 @ 9. Get r5 and exception enable registers off of exception stack and @ save r5 (stored in r4) back to the system stack. LDMIA r1!,{r4-r5} STMDB r13!,{r4} MOV r4,r5 @ Put exception enable value into r4 +#endif @ 10. Get the rest of the registers off the exception stack and @ save them onto the system stack. LDMIA r1!,{r5-r8,r11} @ Get r0-r4 off exception stack STMDB r13!,{r5-r8,r11} @ Put r0-r4 on system stack +/* no longer relevant */ +#if 0 @ 11. Store the exception enable value back on the exception stack. STMDB r1,{r4} +#endif @ 12. Save the SPSR on the system stack (CPSR) STMDB r13!,{r3} @@ -2433,10 +2456,13 @@ LDR r13,[r1, #0] @ Switch to system stack LDR r10,[r3, #0] @ Setup system stack limit +/* TI's approach to interrupt handling does not support re-enabling here */ +#if 0 @ Re-enable interrupts MRS r1,CPSR BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) MSR CPSR,r1 +#endif @ Return to caller ISR. @@ -2447,13 +2473,13 @@ TCT_Idle_Context_Save: MOV r2,r14 @ Save r14 in r2 - LDR r3,[r13] @ Get exception enable value from stack +@ LDR r3,[r13] @ Get exception enable value from stack ADD r13,r13,#20 @ Adjust exception r13 for future interrupts - STR r3,[r13] @ Put exception enable value back on stack +@ STR r3,[r13] @ Put exception enable value back on stack MRS r1,CPSR @ Pickup current CPSR BIC r1,r1,#MODE_MASK @ Clear the current mode - BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) @ Re-enable interrupts +@ BIC r1,r1,#(IRQ_BIT_OR_FIQ_BIT) @ Re-enable interrupts ORR r1,r1,#SUP_MODE @ Prepare to switch to supervisor @ mode (SVC) @@ -2963,3 +2989,10 @@ B TCT_Schedule @ Return to main scheduling loop @} + +/* FreeCalypso addition, used by riviera/rvf/rvf_task.c: */ + .globl INT_Check_IRQ_Mask +INT_Check_IRQ_Mask: + MRS r0,CPSR + BX lr + diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/sysglue/irqfiq.S --- a/nuc-fw/sysglue/irqfiq.S Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/sysglue/irqfiq.S Sat Nov 02 01:48:11 2013 +0000 @@ -15,7 +15,7 @@ .globl _INT_IRQ _INT_IRQ: - STMDB sp!,{a1-a4} @ Save a1-a4 on temporary IRQ stack + STMDB sp!,{r0-r4} @ used to be a1-a4 /* * Thanks to TI for discovering and documenting this apparent ARM7TDMI bug: @@ -46,7 +46,7 @@ BNE IRQBUG @ then postpone execution of this IRQ /* Bug correction 1st part end --------------- */ - SUB a4,lr,#4 @ Save IRQ's lr (return address) + SUB r4,lr,#4 @ Save IRQ's lr (return address) BL TCT_Interrupt_Context_Save @ Call context save routine BL IQ_IRQ_isr @ Call int. service routine @@ -56,14 +56,14 @@ B TCT_Interrupt_Context_Restore /* BUG correction 2nd part ------------------ */ -IRQBUG: LDMFD sp!,{a1-a4} @ return from interrupt +IRQBUG: LDMFD sp!,{r0-r4} @ return from interrupt SUBS pc,r14,#4 /* BUG correction 2nd part end -------------- */ .globl _INT_FIQ _INT_FIQ: - STMDB sp!,{a1-a4} @ Save a1-a4 on temporary FIQ stack - SUB a4,lr,#4 @ Save FIQ's lr (return address) + STMDB sp!,{r0-r4} @ used to be a1-a4 + SUB r4,lr,#4 @ Save FIQ's lr (return address) BL TCT_Interrupt_Context_Save @ Call context save routine BL IQ_FIQ_isr @ Call the FIQ ISR diff -r 035672b72f9b -r 2c5160a9d652 nuc-fw/sysglue/sysinit.S --- a/nuc-fw/sysglue/sysinit.S Fri Nov 01 22:59:49 2013 +0000 +++ b/nuc-fw/sysglue/sysinit.S Sat Nov 02 01:48:11 2013 +0000 @@ -14,8 +14,8 @@ b . /* IRQ */ b _INT_IRQ -/* no useful FIQ handler yet */ - b . +/* FIQ */ + b _INT_FIQ .section xip.text,"ax",%progbits .code 32 @@ -39,3 +39,13 @@ bl bzero /* we can start Nucleus now! */ b INT_Initialize + +/* + * riviera/support/exception.c references exit() + * The following kludge will allow us to pass the link for the time being + * until we can find a better solution, such as hooking into DAR maybe. + */ + + .globl exit +exit: + b .