# HG changeset patch
# User Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
# Date 1377992603 0
# Node ID 45911ad957fdc8b9c9ce6b05b084843d609350bb
# Parent  f459043fae0cb1c759d07618554a177ef47444c3
nuc-fw: beginning to integrate TI's BSP code

diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/Makefile
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/Makefile	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,24 @@
+CC=	arm-elf-gcc
+CFLAGS=	-O2 -fno-builtin -mthumb-interwork
+ASFLAGS=-mthumb-interwork
+AR=	arm-elf-ar
+RANLIB=	arm-elf-ranlib
+
+IOBJS=	armio.o inth.o
+
+XTOBJS=	clkm.o niq.o
+
+XOBJS=	${XTOBJS}
+AOBJS=	${IOBJS}
+
+HDRS=
+
+all:	${IOBJS} ${XOBJS}
+
+${AOBJS}:	${HDRS}
+
+${XTOBJS}:	%.o : %.c ${HDRS}
+	${CC} ${CFLAGS} -mthumb -c $<
+
+clean:
+	rm -f *.[oa] *errs
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/armio.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/armio.c	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,239 @@
+/*
+ * ARMIO.C 
+ *
+ *
+ * Control diagnostic bits
+ *
+ * Reference : GCS207
+ *
+ */
+
+
+#include "../include/config.h"
+#include "../include/sys_types.h"
+
+#include "mem.h"
+#include "iq.h"
+#include "armio.h"
+
+#if 0
+/* FreeCalypso: abb.h hasn't been integrated yet */
+#include "abb.h"	 // for AI_Power function : to be removed, use ABB_Power_Off in abb.c file instead !!!
+#endif
+
+#if (CHIPSET != 12)
+/*
+ * AI_EnableBit
+ *
+ * Enable ARMIO input/output bit (see CLKM module specification)
+ */
+void AI_EnableBit(int bit)
+{
+  *((volatile SYS_UWORD16 *) CLKM_IO_CNTL) |= (1<<bit); 
+}
+
+/*
+ * AI_DisableBit
+ *
+ * Disable ARMIO input/output bit (see CLKM module specification)
+ */
+void AI_DisableBit(int bit)
+{
+  *((volatile SYS_UWORD16 *) CLKM_IO_CNTL) &= ~(1<<bit); 
+}
+
+#endif /* CHIPSET != 12 */
+
+/*
+ * AI_SetBit
+ *
+ * Switch-on one bit
+ */
+void AI_SetBit(int bit)
+{
+   *((volatile SYS_UWORD16 *) ARMIO_OUT) |= (1<<bit); 
+}
+
+/*
+ * AI_ResetBit
+ *
+ * Switch-off one bit
+ */
+void AI_ResetBit(int bit)
+{
+   *((volatile SYS_UWORD16 *) ARMIO_OUT) &= ~(1<<bit); 
+}
+
+/*
+ * AI_ConfigBitAsOutput
+ *
+ * Set this bit as an output
+ */
+void AI_ConfigBitAsOutput(int bit)
+{
+   *((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) &= ~(1<<bit); 
+}
+
+/*
+ * AI_ConfigBitAsInput
+ *
+ * Set this bit as an input
+ */
+void AI_ConfigBitAsInput(int bit)
+{
+   *((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) |= (1<<bit); 
+}
+
+
+/*
+ * AI_ReadBit
+ *
+ * Read value in register
+ */
+SYS_BOOL AI_ReadBit(int bit)
+{
+   if ((*((volatile SYS_UWORD16 *) ARMIO_IN)) & (1<<bit))
+      return (1);
+   else
+      return (0);
+}
+
+/*
+ * AI_Power
+ *
+ * Switch-on or off the board
+ *
+ * Parameters : SYS_UWORD8 power: 1 to power-on (maintain power)
+ *                                0 to power-off
+ *
+ */
+// #if (!OP_L1_STANDALONE)
+#if 0
+void AI_Power(SYS_UWORD8 power)
+{
+  if (power == 0) 
+  {
+	ABB_Power_Off();
+  }
+}
+#endif
+
+/*
+ * AI_ResetIoConfig
+ *
+ * Reset all default IO configurations
+ *
+ */
+void AI_ResetIoConfig(void)
+{
+   *((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) = 0xFFFF; // all bits are inputs
+#if (CHIPSET != 12)
+   *((volatile SYS_UWORD16 *) CLKM_IO_CNTL) = 0;       // default config
+  #endif /* CHIPSET != 12 */
+}
+
+
+/*
+ * AI_ClockEnable
+ *
+ * Enable ARMIO clock module
+ *
+ */
+void AI_ClockEnable(void)
+{
+   *((volatile SYS_UWORD16 *) ARMIO_CNTL_REG) |= ARMIO_CLOCKEN;    // set to 1 bit 5
+}
+
+/*
+ * The target-specific AI_InitIOConfig() function will need to go here.
+ */
+
+/*
+ * AI_SelectIOForIT
+ *
+ * Select which IO will be used to generate an interrupt.
+ * 'Edge' specifies if interrup must be detected on falling or rising edge.
+ *
+ * Warning: parameters are not checked.
+ */
+ 
+void AI_SelectIOForIT (SYS_UWORD16 Pin, SYS_UWORD16 Edge)
+{
+  #if (CHIPSET == 12)
+    /*
+     *  Update INTERRUPT_LEVEL_REG with Edge configuration on Pin selection
+     */
+    GPIO_INTERRUPT_LEVEL_REG = (Edge & 0x0001) << Pin;
+
+    /*
+     *  Update INTERRUPT_MASK_REG to enable interrupt generation on Pin selection
+     */
+    GPIO_INTERRUPT_MASK_REG = 1 << Pin;
+  #else
+    /*
+     * Bit SET_GPIO_EVENT_MODE (bit 0) is set to enable the GPIO event mode.
+     */
+     
+    *((volatile SYS_UWORD16 *) ARMIO_GPIO_EVENT_MODE) = (Pin << 1) + (Edge << 5) + 1;
+  #endif
+}
+
+#if (CHIPSET != 12)
+/*
+ * AI_CheckITSource
+ *
+ * Check if the interrupt specified by 'Source' is active or not.
+ *
+ * Output: 0: IT is not active
+ *         1: IT is active
+ *
+ * Warning: parameters are not checked.
+ *
+ * Warning: If the keypad and GPIO interrupts may occur the GPIO interrupt
+ *          must be checked first because the GPIO status bit is reset when
+ *          the register is read.
+ */
+ 
+int  AI_CheckITSource (SYS_UWORD16 Source)
+{
+    return (*((volatile SYS_UWORD16 *) ARMIO_KBD_GPIO_INT) & Source ? 1 : 0);
+}
+
+/*
+ * AI_UnmaskIT
+ *
+ * Unmask the IT specified by 'Source' (keyboard or GPIO).
+ *
+ * Warning: parameters are not checked.
+ */
+ 
+void AI_UnmaskIT (SYS_UWORD16 Source)
+{
+    *((volatile SYS_UWORD16 *) ARMIO_KBD_GPIO_MASKIT) &= ~Source;
+}
+
+/*
+ * AI_MaskIT
+ *
+ * Mask the IT specified by 'Source' (keyboard or GPIO).
+ *
+ * Warning: parameters are not checked.
+ */
+ 
+void AI_MaskIT (SYS_UWORD16 Source)
+{
+    *((volatile SYS_UWORD16 *) ARMIO_KBD_GPIO_MASKIT) |= Source;
+}
+#endif /* CHIPSET != 12 */
+
+#if (CHIPSET == 12)
+
+  void AI_MaskIT(SYS_UWORD16 d_io_number) {
+    GPIO_INTERRUPT_MASK_REG |= (1 << d_io_number);
+  } /* f_gpio_mask_it() */
+  
+  void AI_UnmaskIT(SYS_UWORD16 d_io_number) {
+    GPIO_INTERRUPT_MASK_REG &= ~(1 << d_io_number);
+  } /* f_gpio_unmask_it() */
+
+#endif
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/armio.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/armio.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,114 @@
+/*
+ * ARMIO.H  * * Control diagnostic bits * * Reference : GCS207 *
+ *
+ * FreeCalypso note: this version of armio.h originates
+ * from the MV100-0.1.rar find.
+ */
+
+#ifndef _ARM_IO_H_
+#define _ARM_IO_H_
+
+#include "../include/sys_types.h"
+
+
+// Duplicate address with ARMIO_IO_CNTL
+// Need to investigate !!!
+//#define ARMIO_CNTL      (MEM_ARMIO + 0x04) /* I/O control */
+
+#define ARMIO_IN        (MEM_ARMIO + 0x00) /* inputs */
+#define ARMIO_OUT       (MEM_ARMIO + 0x02) /* outputs */
+#define ARMIO_IO_CNTL   (MEM_ARMIO + 0x04) /* I/O control */
+#define ARMIO_CNTL_REG  (MEM_ARMIO + 0x06) /* control ARMIO */
+#define ARMIO_LOAD_TIM  (MEM_ARMIO + 0x08) /* load TIM */
+#if (CHIPSET != 12)
+  #define ARMIO_KBR_IN    (MEM_ARMIO + 0x0A) /* KBR inputs (rows) */
+  #define ARMIO_KBR_OUT   (MEM_ARMIO + 0x0C) /* KBR outputs (columns) */
+#endif
+#define ARMIO_PWM_CNTL  (MEM_ARMIO + 0x0E) /* LIGHT/BUZZER control */
+#define ARMIO_LIGHT     (MEM_ARMIO + 0x10) /* light value */
+#define ARMIO_BUZZER    (MEM_ARMIO + 0x12) /* buzzer value */
+#define ARMIO_CLOCKEN   0x0020
+#if (CHIPSET != 12)
+  #define CLKM_IO_CNTL    MEM_IO_SEL         /* control IO */
+#endif
+
+#if (CHIPSET == 12)
+  #define GPIO_INTERRUPT_LEVEL_REG  * (volatile SYS_UWORD16 *) (MEM_ARMIO + 0x16)
+  #define GPIO_INTERRUPT_MASK_REG   * (volatile SYS_UWORD16 *) (MEM_ARMIO + 0x18)
+#else
+  #define ARMIO_GPIO_EVENT_MODE (MEM_ARMIO + 0x14) /* GPIO event mode */
+  #define ARMIO_KBD_GPIO_INT    (MEM_ARMIO + 0x16) /* Kbd/GPIO IRQ register */
+  #define ARMIO_KBD_GPIO_MASKIT (MEM_ARMIO + 0x18) /* Kbd/GPIO mask IRQ */
+#endif
+
+
+#if (CHIPSET != 12)
+  #define ARMIO_DCD (2) /* IO used for DCD on C-Sample - Output */
+#endif
+#define ARMIO_DTR (3) /* IO used for DTR on C-Sample - Input */
+
+#define ARMIO_FALLING_EDGE (0)
+#define ARMIO_RISING_EDGE  (1)
+
+#if (CHIPSET != 12)
+  #define ARMIO_KEYPDAD_INT (0x0001)
+  #define ARMIO_GPIO_INT    (0x0002)
+
+  #define ARMIO_MASKIT_KBD  (0x0001)
+  #define ARMIO_MASKIT_GPIO (0x0002)
+
+  void AI_EnableBit(int bit);
+  void AI_DisableBit(int bit);
+#endif
+void AI_SetBit(int bit);
+void AI_ResetBit(int bit);
+void AI_ConfigBitAsOutput(int bit);
+void AI_ConfigBitAsInput(int bit);
+SYS_BOOL AI_ReadBit(int bit);
+void AI_SetSimIO3V(SYS_UWORD8 StdOutput);
+void AI_Power(SYS_UWORD8 power);
+void AI_ResetTspIO(void);
+void AI_ResetDbgReg(void);
+void AI_ResetIoConfig(void);
+void AI_InitIOConfig(void);
+void AI_ClockEnable (void);
+
+void AI_SelectIOForIT (SYS_UWORD16 Pin, SYS_UWORD16 Edge);
+#if (CHIPSET != 12)
+  int  AI_CheckITSource (SYS_UWORD16 Source);
+#endif
+void AI_UnmaskIT (SYS_UWORD16 Source);
+void AI_MaskIT (SYS_UWORD16 Source);
+
+#if 0
+
+/*
+ * The following stuff appears to be additions by whatever handset
+ * manufacturer was behind the MV100 code - not TI's reference code.
+ * It looks unclean, so let's try omitting it for FreeCalypso.
+ */
+
+/* glowing, 2004-06-08 import from M188A, defined by Robert.Chen*/
+#define AI_CFGBIT_OUTPUT(bit)	(*((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) &= ~(1<<bit))
+#define AI_CFGBIT_INPUT(bit)	(*((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) |= (1<<bit))
+#define AI_SETBIT(bit)			(*((volatile SYS_UWORD16 *) ARMIO_OUT) |= (1<<bit))
+#define AI_RESETBIT(bit)		(*((volatile SYS_UWORD16 *) ARMIO_OUT) &= ~(1<<bit))
+
+#define GPIO_LEDG				0
+#define GPIO_LEDB				1
+#define GPIO_HALL 				2
+#define GPIO_HEADSET_DETECT 	3
+
+#define GPIO_MIDI_RESET		5
+
+#define GPIO_LCD_RESET			7
+#define GPIO_LCD_DIMM2			8
+#define GPIO_MIDI_IRQ			9
+
+#define GPIO_CAMERA_IRQ		11
+
+#define GPIO_HEADSET_KEY		13
+
+#endif	/* the #if 0 above */
+
+#endif	/* file include guard */
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/clkm.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/clkm.c	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,317 @@
+/******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: clkm.c
+
+   Description    	: Set of functions useful to test the Saturn
+			  CLKM peripheral 
+
+   Project        	: drivers
+
+   Author         	: pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.11
+
+   Date and time	: 10/23/01 14:43:31
+
+   Previous delta 	: 10/23/01 14:43:31
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.c
+
+   Sccs Id  (SID)       : '@(#) clkm.c 1.11 10/23/01 14:43:31 '
+
+
+ 
+*****************************************************************************/
+
+           //############################################################
+           //############################################################
+           //### Be careful: this file must be placed in Flash Memory ###
+           //###     and compiled in 16 bits length intructions       ###
+           //###        (CF. the function wait_ARM_cycles()           ###
+           //############################################################
+           //############################################################
+           
+#include "../include/config.h"
+#include "../include/sys_types.h"
+
+#include "mem.h"
+#include "clkm.h"
+
+static SYS_UWORD32 ratio_wait_loop = 0;
+
+#if (CHIPSET == 12)
+  const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE] = {1, 1.5, 2, 3};
+#endif
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  /*---------------------------------------------------------------/
+  /*  CLKM_InitARMClock()                                         */
+  /*--------------------------------------------------------------*/
+  /* Parameters :  clk_src : 0x00 means DPLL selected             */
+  /*                         0x01 means VTCX0 selected            */
+  /*                         0x03 means CLKIN selected            */
+  /*               clk_xp5 : Enable 1.5 or 2.5 division factor    */
+  /*                         (0 or 1)                             */
+  /*               clk_div : Division factor applied to clock     */
+  /*                         source                               */
+  /*             WARNING : reverse order in comparison to ULYSSE  */
+  /*                                                              */
+  /* Return     : none                                            */
+  /* Functionality :Initialize the ARM Clock frequency            */
+  /*--------------------------------------------------------------*/
+  
+  inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5)
+  {
+    SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK;
+        
+    cntl &= ~(CLKM_CLKIN0 | CLKM_CLKIN_SEL | CLKM_ARM_MCLK_XP5 | CLKM_MCLK_DIV);
+    
+    cntl |= ((clk_src << 1) | (clk_xp5 << 3) | (clk_div << 4));
+    
+    * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl;
+  }
+#else
+  /*---------------------------------------------------------------/
+  /*  CLKM_InitARMClock()						*/
+  /*--------------------------------------------------------------*/
+  /* Parameters :  clk_src : 0x00 means CLKIN selected		*/
+  /*	  	  	   0x01 means 32 K selected		*/
+  /*	 	  	   0x02 means External clock selected	*/
+  /*								*/
+  /* Return     :	none						*/
+  /* Functionality :Initialize the ARM Clock frequency 		*/
+  /*--------------------------------------------------------------*/
+
+  inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div)
+  {
+    SYS_UWORD16 cntl = * (volatile SYS_UWORD16 *) CLKM_ARM_CLK;
+
+    cntl &= ~(CLKM_LOW_FRQ | CLKM_CLKIN_SEL | CLKM_MCLK_DIV);
+
+    cntl |= ((clk_src << 1) | (clk_div << 4));
+
+    * (volatile SYS_UWORD16 *) CLKM_ARM_CLK = cntl;
+  }
+
+#endif
+
+
+/*-------------------------------------------------------*/ 
+/* convert_nanosec_to_cycles()                           */
+/*-------------------------------------------------------*/
+/* parameter: time in 10E-9 seconds                      */
+/* return: Number of cycles for the wait_ARM_cycles()    */
+/*         function                                      */
+/*                                                       */
+/* Description:                                          */
+/* ------------                                          */
+/* convert x nanoseconds in y cycles used by the ASM loop*/
+/* function . Before calling this function, call the     */ 
+/* initialize_wait_loop() function                       */
+/* Called when the HardWare needs time to wait           */
+/*-------------------------------------------------------*/ 
+inline SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time)
+{ 
+  return( time / ratio_wait_loop);  
+}
+
+
+/*-------------------------------------------------------*/
+/* initialize_wait_loop()                                */
+/*-------------------------------------------------------*/
+/*                                                       */
+/* Description:                                          */
+/* ------------                                          */
+/* Init the ratio used to convert time->Cycles according */
+/* to hardware parameters                                */
+/* measurement time for this function (ARM 39Mhz, 3 waits*/
+/* states) = 75 micoseconds                              */
+/*-------------------------------------------------------*/
+
+void initialize_wait_loop(void)
+{
+  #define NBR_CYCLES_IN_LOOP   5   // this value is got from an oscilloscope measurement
+  
+  double src_ratio;
+  double final_ratio;
+
+  SYS_UWORD16 flash_access_size;
+  SYS_UWORD16 flash_wait_state;
+  SYS_UWORD32 nbr;
+  SYS_UWORD32 arm_clock;
+
+  //////////////////////////////////
+  //  compute the ARM clock used  //
+  //////////////////////////////////
+  {
+    SYS_UWORD16 arm_mclk_xp5;
+    SYS_UWORD16 arm_ratio;
+    SYS_UWORD16 clk_src;
+    SYS_UWORD16 clkm_cntl_arm_clk_reg = * (volatile SYS_UWORD16 *) CLKM_CNTL_ARM_CLK;
+
+    #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+      clk_src  = (clkm_cntl_arm_clk_reg & MASK_CLKIN) >> 1;
+      switch (clk_src)
+      {
+        case 0x00: //DPLL selected 
+          // select the DPLL factor
+          if (((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK) != 0)
+          {
+             SYS_UWORD16 dpll_div;
+             SYS_UWORD16 dpll_mul;
+
+             dpll_div=DPLL_READ_DPLL_DIV;
+             dpll_mul=DPLL_READ_DPLL_MUL;
+             src_ratio = (double)(dpll_mul)/(double)(dpll_div+1);              
+          }
+          else // DPLL in bypass mode
+          {
+             SYS_UWORD16 dpll_div = DPLL_BYPASS_DIV;
+             src_ratio= (double)(1)/(double)(dpll_div+1);
+          }
+          break;
+        case 0x01: //VTCX0 selected 
+          src_ratio = 1;
+          break;
+        case 0x03: //CLKIN selected   (external clock)
+          src_ratio = 1;
+          break;
+      }
+      // define the division factor applied to clock source (CLKIN or VTCXO or DPLL)
+      arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4;
+
+      // check if the 1.5 or 2.5 division factor is enabled
+      arm_mclk_xp5  = clkm_cntl_arm_clk_reg & CLKM_ARM_MCLK_XP5;
+
+      if (arm_mclk_xp5 == 0) // division factor enable for ARM clock ?
+      {
+        if (arm_ratio == 0) 
+          arm_ratio =1; 
+      }
+      else
+        arm_ratio = ((arm_ratio>>1) & 0x0001) == 0 ? 1.5 : 2.5;
+
+
+    #else // CHIPSET
+      src_ratio = 1;
+
+      // define the division factor applied to clock source (CLKIN or VTCXO or DPLL)
+      arm_ratio = (clkm_cntl_arm_clk_reg & CLKM_MCLK_DIV) >> 4;
+
+      // check if the 1.5 or 2.5 division factor is enabled
+      arm_mclk_xp5  = clkm_cntl_arm_clk_reg & MASK_ARM_MCLK_1P5;
+
+      if (arm_mclk_xp5 == 1) // division factor enable for ARM clock ?
+        arm_ratio = 1.5;  
+      else
+      {
+        if (arm_ratio == 0)
+          arm_ratio = 4;
+        else 
+          if (arm_ratio == 1 )
+            arm_ratio = 2;
+          else 
+            arm_ratio = 1;
+      }
+
+    #endif // CHIPSET
+
+   final_ratio = (src_ratio / (double) arm_ratio);
+
+  }
+  //////////////////////////////////////////
+  //  compute the Flash wait states used  //
+  //////////////////////////////////////////
+
+  #if (CHIPSET == 12)
+    flash_access_size  =  *((volatile SYS_UWORD16 *) MEM_REG_nCS5);
+  #else
+    flash_access_size  =  *((volatile SYS_UWORD16 *) MEM_REG_nCS0);
+  #endif
+  flash_access_size  = (flash_access_size >> 5) & 0x0003; // 0=>8bits, 1=>16 bits, 2 =>32 bits
+
+  // the loop file is compiled in 16 bits it means
+  //    flash 8  bits => 2 loads for 1 16 bits assembler instruction
+  //    flash 16 bits => 1 loads for 1 16 bits assembler instruction
+  //    flash 32 bits => 1 loads for 1 16 bits assembler instruction (ARM bus 16 bits !!)
+  
+  // !!!!!!!!! be careful: if this file is compile in 32 bits, change these 2 lines here after !!!
+  if (flash_access_size == 0) flash_access_size = 2;
+  else                        flash_access_size = 1;
+
+  #if (CHIPSET == 12)
+    /*
+     *  WARNING - New ARM Memory Interface features are not supported here below (Page Mode, extended WS, Dummy Cycle,...).
+     */
+    flash_wait_state  =  *((volatile SYS_UWORD16 *) MEM_REG_nCS5);
+  #else
+    flash_wait_state  =  *((volatile SYS_UWORD16 *) MEM_REG_nCS0);
+  #endif
+  flash_wait_state &=  0x001F;
+
+  //////////////////////////////////////
+  //  compute the length of the loop  //
+  //////////////////////////////////////
+
+  // Number of flash cycles for the assembler loop
+  nbr = NBR_CYCLES_IN_LOOP;
+
+  // Number of ARM cycles for the assembler loop
+  nbr = nbr * (flash_wait_state + 1) * (flash_access_size);
+
+  // time for the assembler loop (unit nanoseconds: 10E-9)
+  arm_clock = final_ratio * 13; // ARM clock in Mhz 
+  ratio_wait_loop = (SYS_UWORD32)((nbr*1000) / arm_clock);
+}
+
+
+/*-------------------------------------------------------*/ 
+/* wait_ARM_cycles()                                     */
+/*-------------------------------------------------------*/
+/*                                                       */
+/* Description:                                          */
+/* ------------                                          */
+/* Called when the HardWare needs time to wait.          */
+/* this function wait x cycles and is used with the      */
+/* convert_nanosec_to_cycles() & initialize_wait_loop()  */
+/*                                                       */
+/*  Exemple:  wait 10 micro seconds:                     */
+/*  initialize_wait_loop();                              */
+/*  wait_ARM_cycles(convert_nanosec_to_cycles(10000))    */
+/*                                                       */
+/*  minimum time value with cpt_loop = 0  (estimated)    */
+/*  and C-SAMPLE / flash 6,5Mhz  ~  1,5 micro seconds    */
+/*                                                       */
+/*                                                       */
+/* Be careful : in order to respect the rule about the   */
+/* conversion "time => number of cylcles in this loop"   */
+/* (Cf the functions: convert_nanosec_to_cycles() and    */
+/* initialize_wait_loop() ) respect the following rules: */
+/* This function must be placed in Flash Memory and      */
+/* compiled in 16 bits instructions length               */
+/*-------------------------------------------------------*/
+void wait_ARM_cycles(SYS_UWORD32 cpt_loop) 
+{
+  // C code:
+  // while (cpt_loop -- != 0);
+
+  asm(" CMP       A1, #0");                 
+  asm(" BEQ       END_FUNCTION");           
+
+  asm("LOOP_LINE:        ");                
+  asm(" SUB       A1, A1, #1");
+  asm(" CMP       A1, #0");
+  asm(" BNE       LOOP_LINE");
+
+  asm("END_FUNCTION:        ");  
+} 
+
+
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/clkm.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/clkm.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,373 @@
+/******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: clkm.h
+
+   Description    	: Header file for the CLKM module
+
+   Project        	: drivers
+
+   Author         	: pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.10
+
+   Date and time	: 10/23/01 14:34:54
+
+   Previous delta 	: 10/19/01 15:25:25
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_CLOCK/drivers1/common/SCCS/s.clkm.h
+
+   Sccs Id  (SID)       : '@(#) clkm.h 1.10 10/23/01 14:34:54 '
+
+ 
+*****************************************************************************/
+
+#include "../include/config.h"
+#include "../include/sys_types.h"
+
+#define CLKM_ARM_CLK 	MEM_CLKM_ADDR 		/* CLKM ARM CLock Control reg.*/
+#define CLKM_MCLK_EN	0x0001 
+
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+   #define MASK_CLKIN       0x0006
+#endif
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define CLKM_CLKIN0       0x0002            // Mask to select between DPLL and VTCXO or CLKIN
+#else
+  #define CLKM_LOW_FRQ	    0x0002            // Mask to select low frequency input CLK_32K 
+#endif
+#define CLKM_CLKIN_SEL	    0x0004            // Mask to select between VTCXO and CLKIN 
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define CLKM_ARM_MCLK_XP5 0x0008            // Mask to enable the 1.5 or 2.5 division factor
+  #define CLKM_MCLK_DIV     0x0070            // Mask to configure the division factor
+#else
+  #define MASK_ARM_MCLK_1P5 0x0008            // Mask to enable the 1.5 division factor
+  #define CLKM_MCLK_DIV	    0x0030            // Mask to configure the division factor
+#endif
+
+#define CLKM_DEEP_PWR	    0x0f00            // Mask to configure deep power
+#define CLKM_DEEP_SLEEP	    0x1000            // Mask to configure deep sleep
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define CLKM_SEL_DPLL     0x0000            // Selection of DPLL for ARM clock generation
+  #define CLKM_SEL_VTCXO    0x0001            // Selection of VTCXO for ARM clock generation
+  #define CLKM_SEL_CLKIN    0x0003            // Selection of CLKIN for ARM clock generation
+  
+  #define CLKM_ENABLE_XP5   0x0001            // Enable 1.5 or 2.5 division factor
+  #define CLKM_DISABLE_XP5  0x0000            // Disable 1.5 or 2.5 division factor
+  
+  #define CLKM_ARM_MCLK_DIV_OFFSET 4          // Offset of ARM_MCLK_DIV bits in CNTL_ARM_CLK register
+  
+  #define CLKM_ARM_CLK_RESET 0x1081           // Reset value of CNTL_ARM_CLK register
+#endif
+
+#define CLKM_CNTL_ARM_CLK  (MEM_CLKM_ADDR + 0x00)
+#define CLKM_CNTL_CLK	   (MEM_CLKM_ADDR + 2) 	/* CLKM Clock Control reg. */
+
+#define CLKM_IRQ_DIS        0x0001     // IRQ clock is disabled and enabled according to the sleep command
+#define CLKM_BRIDGE_DIS	    0x0002     // BRIDGE clock is disabled and enabled according to the sleep command
+#define CLKM_TIMER_DIS	    0x0004     // TIMER clock is disabled and enabled according to the sleep command
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define CLKM_DPLL_DIS     0x0008     // DPLL is set in IDLE when both DSP and ARM are respectively in IDLE3 and sleep mode
+#else
+  #define CLKM_PLL_SEL	    0x0008     // CLKIN input is connected to the PLL
+#endif
+#define CLKM_CLKOUT_EN	    0x0010     // Enable CLKOUT(2:0) output clocks
+#if (CHIPSET == 4)
+  #define CLKM_EN_IDLE3_FLG 0x0020     // DSP idle flag control the API wait state
+  #define CLKM_VTCXO_26     0x0040     // VTCXO is divided by 2
+#elif (CHIPSET == 6)
+  #define CLKM_VTCXO_26     0x0040     // VTCXO is divided by 2
+#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
+  #define CLKM_EN_IDLE3_FLG 0x0020     // DSP idle flag control the API wait state
+  #define CLKM_VCLKOUT_2    0x0040     // VTCXO is divided by 2
+  #define CLKM_VTCXO_2      0x0080     // Input clock to DPLL is divided by 2
+#endif
+
+#define CLKM_CNTL_RST 	(MEM_CLKM_ADDR + 4) 	/* CLKM Reset Control reg. */
+#define CLKM_LEAD_RST 	0x0002
+#define CLKM_EXT_RST 	0x0004
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define DPLL_LOCK         0x0001     // Mask of DPLL lock status
+  #define DPLL_BYPASS_DIV   0x000C     // Mask of bypass mode configuration
+  #define DPLL_PLL_ENABLE   0x0010     // Enable DPLL
+  #define DPLL_PLL_DIV      0x0060     // Mask of division factor configuration
+  #define DPLL_PLL_MULT     0x0F80     // Mask of multiply factor configuration
+
+  #define DPLL_BYPASS_DIV_1 0x00       // Configuration of bypass mode divided by 1
+  #define DPLL_BYPASS_DIV_2 0x01       // Configuration of bypass mode divided by 2
+  #define DPLL_BYPASS_DIV_4 0x10       // Configuration of bypass mode divided by 4
+  
+  #define DPLL_BYPASS_DIV_OFFSET 2     // Offset of bypass bits configuration
+  #define DPLL_PLL_DIV_OFFSET    5     // Offset of division bits configuration
+  #define DPLL_PLL_MULT_OFFSET   7     // Offset of multiply bits configuration
+  
+  #define DPLL_LOCK_DIV_1   0x0000     // Divide by 1 when DPLL is locked
+  #define DPLL_LOCK_DIV_2   0x0001     // Divide by 2 when DPLL is locked
+  #define DPLL_LOCK_DIV_3   0x0002     // Divide by 3 when DPLL is locked
+  #define DPLL_LOCK_DIV_4   0x0003     // Divide by 4 when DPLL is locked
+  
+#else
+  #define CLKM_LEAD_PLL_CNTL (MEM_CLKM_ADDR + 6)     /* Lead PLL */
+  #define CLKM_PLONOFF	0x0001         // PLL enable signal
+  #define CLKM_PLMUL	0x001e         // Mask of multiply factor configuration
+  #define CLKM_PLLNDIV	0x0020         // PLL or divide mode selection
+  #define CLKM_PLDIV	0x0040         // Mask of multiply factor configuration
+  #define CLKM_LEAD_PLL_CNTL_MSK 0x00ef // Mask of PLL control register
+#endif
+
+#if (CHIPSET == 12)
+  #define CLKM_CNTL_CLK_DSP (MEM_CLKM_ADDR + 0x8A) 	/* CLKM CNTL_CLK_REG register */
+  
+  #define CLKM_NB_DSP_DIV_VALUE   4
+  
+  #define CLKM_DSP_DIV_1    0x00
+  #define CLKM_DSP_DIV_1_5  0x01
+  #define CLKM_DSP_DIV_2    0x02
+  #define CLKM_DSP_DIV_3    0x03
+  
+  #define CLKM_DSP_DIV_MASK 0x0003
+  
+  extern const double dsp_div_value[CLKM_NB_DSP_DIV_VALUE];
+  
+  /*---------------------------------------------------------------/
+  /*  CLKM_DSP_DIV_FACTOR()						*/
+  /*--------------------------------------------------------------*/
+  /* Parameters : none						*/
+  /* Return     :	none						*/
+  /* Functionality : Set the DSP division factor			*/
+  /*--------------------------------------------------------------*/
+
+  #define CLKM_DSP_DIV_FACTOR(d_dsp_div) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP = d_dsp_div)
+
+
+  /*---------------------------------------------------------------/
+  /*  CLKM_READ_DSP_DIV()						*/
+  /*--------------------------------------------------------------*/
+  /* Parameters : none						*/
+  /* Return     :	none						*/
+  /* Functionality : Read DSP division factor			*/
+  /*--------------------------------------------------------------*/
+
+  #define CLKM_READ_DSP_DIV               ((* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK_DSP) & CLKM_DSP_DIV_MASK)
+  
+  #define CLKM_GET_DSP_DIV_VALUE          dsp_div_value[CLKM_READ_DSP_DIV]
+
+#endif
+
+
+/*---------------------------------------------------------------/
+/*  CLKM_SETLEADRESET()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Set the LEAD reset signal			*/
+/*--------------------------------------------------------------*/
+
+#define CLKM_SETLEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_LEAD_RST)
+
+/*---------------------------------------------------------------/
+/*  CLKM_RELEASELEADRESET()					*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Release the LEAD reset signal		*/
+/*--------------------------------------------------------------*/
+
+#define CLKM_RELEASELEADRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_LEAD_RST)
+
+/*---------------------------------------------------------------/
+/*  CLKM_SETEXTRESET()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Set the external reset signal		*/
+/*--------------------------------------------------------------*/
+
+#define CLKM_SETEXTRESET ( * (volatile SYS_UWORD16 *) CLKM_CNTL_RST |= CLKM_EXT_RST)
+
+/*---------------------------------------------------------------/
+/*  CLKM_CLEAREXTRESET()					*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Clear the external reset signal		*/
+/*--------------------------------------------------------------*/
+
+#define CLKM_CLEAREXTRESET (* (volatile SYS_UWORD16 *) CLKM_CNTL_RST &= ~CLKM_EXT_RST)
+
+
+/*---------------------------------------------------------------/
+/*  CLKM_POWERDOWNARM()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Power down the ARM mcu			*/
+/*--------------------------------------------------------------*/
+#define  CLKM_POWERDOWNARM (* (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_MCLK_EN)
+
+/*---------------------------------------------------------------/
+/*  CLKM_SET1P5()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Set ARM_MCLK_1P5 bit				*/
+/*--------------------------------------------------------------*/
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define CLKM_SETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= CLKM_ARM_MCLK_XP5)
+#else
+  #define CLKM_SET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK |= 0x0008)
+#endif
+
+/*---------------------------------------------------------------/
+/*  CLKM_RESET1P5()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Reset ARM_MCLK_1P5 bit			*/
+/*--------------------------------------------------------------*/
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define CLKM_RESETXP5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= ~CLKM_ARM_MCLK_XP5)
+#else
+  #define CLKM_RESET1P5 ( * (volatile SYS_UWORD16 *) CLKM_ARM_CLK &= 0xfff7)
+#endif
+
+/*---------------------------------------------------------------/
+/*  CLKM_INITCNTL()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : value to write in the CNTL register		*/
+/* Return     :	none						*/
+/* Functionality :Initialize the CLKM Control Clock register	*/
+/*--------------------------------------------------------------*/
+
+#define CLKM_INITCNTL(value) (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK = value)
+
+
+#if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11) && (CHIPSET != 12))
+  /*---------------------------------------------------------------/
+  /*  CLKM_INITLEADPLL()						*/
+  /*--------------------------------------------------------------*/
+  /* Parameters : value to write in the CNTL_PLL LEAD register	*/
+  /* Return     :	none						*/
+  /* Functionality :Initialize LEAD PLL control register		*/
+  /*--------------------------------------------------------------*/
+
+  #define CLKM_INITLEADPLL(value) (* (volatile SYS_UWORD16 *) CLKM_LEAD_PLL_CNTL = value)
+#endif
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  /*---------------------------------------------------------------/
+  /*  CLKM_DPLL_SWITH_OFF_MODE_CONFIG()                           */
+  /*--------------------------------------------------------------*/
+  /* Parameters : None                                            */
+  /* Return     : none                                            */
+  /* Functionality : Configure DPLL switch off mode               */
+  /*--------------------------------------------------------------*/
+
+  #define CLKM_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= \
+             (CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
+             
+  /*---------------------------------------------------------------/
+  /*  CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG()                     */
+  /*--------------------------------------------------------------*/
+  /* Parameters : None                                            */
+  /* Return     : none                                            */
+  /* Functionality : Reset configuration of DPLL switch off mode  */
+  /*--------------------------------------------------------------*/
+             
+  #define CLKM_RESET_DPLL_SWITH_OFF_MODE_CONFIG (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &=\
+            ~(CLKM_DPLL_DIS | CLKM_IRQ_DIS | CLKM_BRIDGE_DIS | CLKM_TIMER_DIS))
+
+  /*---------------------------------------------------------------/
+  /*  CLKM_FORCE_API_HOM_IN_IDLE3()                               */
+  /*--------------------------------------------------------------*/
+  /* Parameters : None                                            */
+  /* Return     : none                                            */
+  /* Functionality : SAM/HOM wait-state register force to HOM when*/
+  /*                 DSP is in IDLE3 mode                         */
+  /*--------------------------------------------------------------*/
+
+  #define CLKM_FORCE_API_HOM_IN_IDLE3 (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_EN_IDLE3_FLG))
+
+  #if (CHIPSET == 4)
+    /*---------------------------------------------------------------/
+    /*  CLKM_USE_VTCXO_26MHZ()                                      */
+    /*--------------------------------------------------------------*/
+    /* Parameters : None                                            */
+    /* Return     : none                                            */
+    /* Functionality : Divide by 2 the clock used by the peripheral */
+    /*                 when using external VTCXO at 26 MHz instead  */
+    /*                 of 13MHz                                     */
+    /*--------------------------------------------------------------*/
+
+    #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_26))
+
+    /*---------------------------------------------------------------/
+    /*  CLKM_UNUSED_VTCXO_26MHZ()                                   */
+    /*--------------------------------------------------------------*/
+    /* Parameters : None                                            */
+    /* Return     : none                                            */
+    /* Functionality : Use VTCXO=13MHz                              */
+    /*--------------------------------------------------------------*/
+
+    #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VTCXO_26))
+  #elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
+    /*---------------------------------------------------------------/
+    /*  CLKM_UNUSED_VTCXO_26MHZ()                                   */
+    /*--------------------------------------------------------------*/
+    /* Parameters : None                                            */
+    /* Return     : none                                            */
+    /* Functionality : Use VTCXO=13MHz                              */
+    /*--------------------------------------------------------------*/
+
+    #define CLKM_USE_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK |= (CLKM_VTCXO_2))
+
+    #define CLKM_UNUSED_VTCXO_26MHZ (* (volatile SYS_UWORD16 *) CLKM_CNTL_CLK &= ~(CLKM_VCLKOUT_2 | CLKM_VTCXO_2))
+  #endif
+
+
+  #define DPLL_SET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR |= DPLL_PLL_ENABLE)
+  #define DPLL_RESET_PLL_ENABLE (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR &= ~DPLL_PLL_ENABLE)
+  
+  #define DPLL_INIT_BYPASS_MODE(d_bypass_mode) { \
+        *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~DPLL_BYPASS_DIV; \
+        *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_bypass_mode << DPLL_BYPASS_DIV_OFFSET); \
+       }
+    
+  #define DPLL_INIT_DPLL_CLOCK(d_pll_div, d_pll_mult) { \
+        *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) &= ~(DPLL_PLL_DIV | DPLL_PLL_MULT); \
+        *((volatile SYS_UWORD16 *) MEM_DPLL_ADDR) |= (d_pll_div << DPLL_PLL_DIV_OFFSET) |\
+                                                        (d_pll_mult << DPLL_PLL_MULT_OFFSET); \
+       }
+
+  #define DPLL_READ_DPLL_DIV ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_DIV) >> DPLL_PLL_DIV_OFFSET)
+  #define DPLL_READ_DPLL_MUL ( ((* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_PLL_MULT)>> DPLL_PLL_MULT_OFFSET)
+  #define DPLL_READ_DPLL_LOCK ( (* (volatile SYS_UWORD16 *) MEM_DPLL_ADDR) & DPLL_LOCK)
+
+
+#endif
+
+/* ----- Prototypes ----- */
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div, SYS_UWORD16 clk_xp5);
+#else
+  inline void CLKM_InitARMClock(SYS_UWORD16 clk_src, SYS_UWORD16 clk_div);
+#endif
+
+void wait_ARM_cycles(SYS_UWORD32 cpt_loop);
+void initialize_wait_loop(void);
+inline SYS_UWORD32 convert_nanosec_to_cycles(SYS_UWORD32 time);
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/dma.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/dma.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,200 @@
+/******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: dma.h
+
+   Description    	: DMA 
+
+   Project        	: drivers
+
+   Author         	: pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.6
+
+   Date and time	: 01/30/01 10:22:23
+
+   Previous delta 	: 12/08/00 11:22:15
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.dma.h
+
+   Sccs Id  (SID)       : '@(#) dma.h 1.6 01/30/01 10:22:23 '
+
+ 
+*****************************************************************************/
+
+#include "../include/config.h"
+ 
+/**** DMA configuration register ****/
+
+#if (CHIPSET == 12)
+
+  #define DMA_GCR   (MEM_DMA_ADDR + 0x0400)
+  #define DMA_CAR   (MEM_DMA_ADDR + 0x0404)
+  #define DMA_SCR   (MEM_DMA_ADDR + 0x0406)
+  #define DMA_AR    (MEM_DMA_ADDR + 0x040A)
+
+  #define DMA_CONFIG { \
+      * (volatile unsigned short *) DMA_GCR = 0x0000; /* Force Autogating off */ \
+      * (volatile unsigned short *) DMA_CAR |= 0x0001; /* Channel 0 allocated to DSP */ \
+      * (volatile unsigned short *) DMA_SCR &= ~0x0001; /* Channel 0 is not secure */ \
+      * (volatile unsigned short *) DMA_AR = 0x001C; /* Reset value */ \
+    }
+
+#else
+
+// CONTROLLER_CONFIG register
+//---------------------------
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA_CONFIG_ADDR	MEM_DMA_ADDR
+#else
+  #define DMA_CONFIG_ADDR		(MEM_DMA_ADDR + 0x20)
+#endif
+#define DMA_CONFIG_BURST   	0x1c	/* length of burst */
+
+// ALLOC_CONFIG register
+//---------------------------
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA_ALLOC_CONFIG_ADDR (MEM_DMA_ADDR + 0x02)
+#endif
+#define DMA_CONFIG_ALLOC1   	0x01	/* allocation for channel 1 */
+#define DMA_CONFIG_ALLOC2   	0x02	/* allocation for channel 2 */
+
+// DMA Channel 1 configuration
+//---------------------------
+
+// DMA1_RAD register
+//---------------------------
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA1_RAD_ADDR		(MEM_DMA_ADDR + 0x10)
+#else
+  #define DMA1_RAD_ADDR		MEM_DMA_ADDR
+#endif
+#define DMA_RHEA_ADDR   	0x07ff	/* rhea start address */
+#define DMA_RHEA_CS	   	0xf800	/* rhea chip select */
+
+// DMA1_RDPTH register
+//---------------------------
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA1_RDPTH_ADDR	(MEM_DMA_ADDR + 0x12)
+#else
+  #define DMA1_RDPTH_ADDR		(MEM_DMA_ADDR + 0x02)
+#endif
+#define DMA_RHEA_LENGTH   	0x07ff	/* rhea buffer length */
+
+// DMA1_AAD register
+//---------------------------
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA1_AAD_ADDR		(MEM_DMA_ADDR + 0x14)
+#else
+  #define DMA1_AAD_ADDR		(MEM_DMA_ADDR + 0x04)
+#endif
+#define DMA_API_ADDR	   	0x0fff	/* API start address */
+
+// DMA1_ALGTH register
+//---------------------------
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA1_ALGTH_ADDR	(MEM_DMA_ADDR + 0x16)
+#else
+  #define DMA1_ALGTH_ADDR		(MEM_DMA_ADDR + 0x06)
+#endif
+#define DMA_API_LENGTH	   	0x0fff	/* API page length */
+
+// DMA1_CTRL register
+//---------------------------
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA1_CTRL_ADDR	(MEM_DMA_ADDR + 0x18)
+#else
+  #define DMA1_CTRL_ADDR		(MEM_DMA_ADDR + 0x08)
+#endif
+#define DMA_CTRL_ENABLE		0x0001	/* DMA enable */
+#define DMA_CTRL_IDLE		0x0002	/* idle */
+#define DMA_CTRL_ONE_SHOT	0x0004 
+#define DMA_CTRL_FIFO_MODE	0x0008 
+#define DMA_CTRL_CUR_PAGE	0x0010	/* current page # */
+#define DMA_CTRL_MAS		0x0020 
+#define DMA_CTRL_START		0x0040	/* DMA start */
+#define DMA_CTRL_IRQ_MODE	0x0080	 
+#define DMA_CTRL_IRQ_STATE	0x0100 
+#define DMA_CTRL_RHEA_ABORT	0x0200 
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA_CTRL_PRIORITY     0x1800  /* Number of additional reading on the bus */
+#endif
+
+// DMA1_CUR_OFFSET_API register
+//---------------------------
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA1_OFFSET_ADDR	(MEM_DMA_ADDR + 0x1A)
+#else
+  #define DMA1_OFFSET_ADDR	(MEM_DMA_ADDR + 0x0A)
+#endif
+
+ 
+// DMA Channel 2 configuration
+//---------------------------
+ 
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define DMA2_RAD_ADDR         (MEM_DMA_ADDR + 0x20)
+  #define DMA2_RDPTH_ADDR       (MEM_DMA_ADDR + 0x22)
+  #define DMA2_AAD_ADDR         (MEM_DMA_ADDR + 0x24)
+  #define DMA2_ALGTH_ADDR       (MEM_DMA_ADDR + 0x26)
+  #define DMA2_CTRL_ADDR        (MEM_DMA_ADDR + 0x28)
+  #define DMA2_OFFSET_ADDR      (MEM_DMA_ADDR + 0x2A)
+#else
+  #define DMA2_RAD_ADDR         (MEM_DMA_ADDR + 0x10)
+  #define DMA2_RDPTH_ADDR		(MEM_DMA_ADDR + 0x12)
+  #define DMA2_AAD_ADDR         (MEM_DMA_ADDR + 0x14)
+  #define DMA2_ALGTH_ADDR		(MEM_DMA_ADDR + 0x16)
+  #define DMA2_CTRL_ADDR        (MEM_DMA_ADDR + 0x18)
+  #define DMA2_OFFSET_ADDR      (MEM_DMA_ADDR + 0x1A)
+#endif
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  // DMA Channel 3 configuration
+  //---------------------------
+
+  #define DMA3_RAD_ADDR     (MEM_DMA_ADDR + 0x30)
+  #define DMA3_RDPTH_ADDR   (MEM_DMA_ADDR + 0x32)
+  #define DMA3_AAD_ADDR     (MEM_DMA_ADDR + 0x34)
+  #define DMA3_ALGTH_ADDR   (MEM_DMA_ADDR + 0x36)
+  #define DMA3_CTRL_ADDR    (MEM_DMA_ADDR + 0x38)
+  #define DMA3_OFFSET_ADDR  (MEM_DMA_ADDR + 0x3A)
+
+  // DMA Channel 4 configuration
+  //---------------------------
+
+  #define DMA4_RAD_ADDR     (MEM_DMA_ADDR + 0x40)
+  #define DMA4_RDPTH_ADDR   (MEM_DMA_ADDR + 0x42)
+  #define DMA4_AAD_ADDR     (MEM_DMA_ADDR + 0x44)
+  #define DMA4_ALGTH_ADDR   (MEM_DMA_ADDR + 0x46)
+  #define DMA4_CTRL_ADDR    (MEM_DMA_ADDR + 0x48)
+  #define DMA4_OFFSET_ADDR  (MEM_DMA_ADDR + 0x4A)
+#endif
+
+/*---------------------------------------------------------------/
+/* DMA_ALLOCDMA()   						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : alloc DMA channel 			*/
+/*--------------------------------------------------------------*/
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  // WARNING :
+  // Only the first two channels can be configured and the last two channels are forced to be controlled by the ARM
+  #define DMA_ALLOCDMA(channel0, channel1, dma_burst,priority) { \
+    * (volatile unsigned short *) DMA_CONFIG_ADDR = (dma_burst << 2) | (priority << 5); \
+    * (volatile unsigned short *) DMA_ALLOC_CONFIG_ADDR = channel0 | (channel1 << 1) | 0x000C; \
+    }
+#else
+  #define DMA_ALLOCDMA(channel0, channel1,dma_burst,priority) (* (volatile unsigned short *) DMA_CONFIG_ADDR = channel0 | channel1 << 1 | dma_burst << 2 | priority << 5)
+#endif
+
+#endif /* CHIPSET != 12 */
+
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/inth.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/inth.c	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,125 @@
+/*******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: inth.c
+
+   Description    	: inth.c saturn interupt handler
+
+   Project        	: drivers
+
+   Author         	: pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.8
+
+   Date and time	: 01/30/01 10:22:26
+
+   Previous delta 	: 12/19/00 14:39:21
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.inth.c
+
+   Sccs Id  (SID)       : '@(#) inth.c 1.8 01/30/01 10:22:26 '
+
+ 
+*****************************************************************************/
+
+#include "../include/config.h"
+#include "../include/sys_types.h"
+
+#include  "mem.h"
+#include  "inth.h"
+
+
+
+
+/*---------------------------------------------------------------/
+/*  INTH_Ack()							*/
+/*--------------------------------------------------------------*/
+/* Parameters : num of it					*/
+/* Return     :	none						*/
+/* Functionality :Acknowledge an interrupt and return the origin*/
+/*	of the interrupt (binary format)			*/
+/*--------------------------------------------------------------*/
+
+SYS_UWORD16 INTH_Ack (int intARM)
+{
+   if (intARM == INTH_IRQ)
+	return((* (volatile SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM);
+   else
+	return((* (volatile SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM);
+}
+	
+/*---------------------------------------------------------------/
+/*  INTH_GetPending()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Return the pending interrupts 		*/
+/*--------------------------------------------------------------*/
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  unsigned long INTH_GetPending (void)
+  {
+    return((unsigned long)((* (volatile SYS_UWORD16 *) INTH_IT_REG1) | 
+           ((* (volatile SYS_UWORD16 *) INTH_IT_REG2) << 16)));
+  }		
+#else
+  unsigned short INTH_GetPending (void)
+  {
+    return(* (volatile SYS_UWORD16 *) INTH_IT_REG);
+  }		
+#endif
+
+/*---------------------------------------------------------------/
+/*  INTH_InitLevel()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : num it,FIQ/IRQ,priority level,edge/level.	*/
+/* Return     :	none						*/
+/* Functionality : Initialize an interrupt			*/
+/*		   - put it on IRQ or FIQ			*/
+/*		   - set its priority level			*/
+/*						 		*/
+/*--------------------------------------------------------------*/
+
+void INTH_InitLevel (int inputInt, int FIQ_nIRQ, int priority, int edge)
+{
+   volatile SYS_UWORD16 *inthLevelReg = (SYS_UWORD16 *) INTH_EXT_REG; 
+
+   inthLevelReg = inthLevelReg + inputInt;
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+   *inthLevelReg = (FIQ_nIRQ | (edge << 1) | (priority << 2));
+#else
+   *inthLevelReg = (FIQ_nIRQ | (priority << 1) | (edge << 5));
+#endif
+}
+
+/*---------------------------------------------------------------/
+/*  INTH_ResetIT()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : reset the inth it register			*/
+/*--------------------------------------------------------------*/
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  unsigned long INTH_ResetIT (void)
+  {
+    * (volatile SYS_UWORD16 *) INTH_IT_REG1 &= 0x0000; 
+    * (volatile SYS_UWORD16 *) INTH_IT_REG2 &= 0x0000; 
+    return((unsigned long)((* (volatile SYS_UWORD16 *) INTH_IT_REG1) | 
+           ((* (volatile SYS_UWORD16 *) INTH_IT_REG2) << 16)));
+  }
+#else
+  unsigned short INTH_ResetIT (void)
+  {
+    * (volatile SYS_UWORD16 *) INTH_IT_REG &= 0x0000; 
+    return(* (volatile SYS_UWORD16 *) INTH_IT_REG);
+  }
+#endif
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/inth.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/inth.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,233 @@
+/*******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: inth.h
+
+   Description    	: Header file for the INTH module
+
+   Project        	: drivers
+
+   Author         	: pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.10
+
+   Date and time	: 01/30/01 10:22:23
+
+   Previous delta 	: 01/22/01 10:32:33
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.inth.h
+
+   Sccs Id  (SID)       : '@(#) inth.h 1.10 01/30/01 10:22:23 '
+
+ 
+*****************************************************************************/
+
+#include "../include/config.h"
+#include "../include/sys_types.h"
+
+/* Adress of the registers */
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9)|| (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define INTH_IT_REG1    MEM_INTH_ADDR 		  /* INTH IT register 1 */
+  #define INTH_IT_REG2    (MEM_INTH_ADDR + 0x02)  /* INTH IT register 2 */
+  #define INTH_MASK_REG1  (MEM_INTH_ADDR + 0x08)  /* INTH mask register 1 */
+  #define INTH_MASK_REG2  (MEM_INTH_ADDR + 0x0a)  /* INTH mask register 2 */
+  #define INTH_B_IRQ_REG  (MEM_INTH_ADDR + 0x10)  /* INTH source binary IRQ reg. */
+  #define INTH_B_FIQ_REG  (MEM_INTH_ADDR + 0x12)  /* INTH source binary FIQ reg. */
+  #define INTH_CTRL_REG   (MEM_INTH_ADDR + 0x14)  /* INTH control register */
+  #define INTH_EXT_REG    (MEM_INTH_ADDR + 0x20)  /* INTH 1st external int. reg. */
+#else
+  #define INTH_IT_REG  	  MEM_INTH_ADDR 		  /* INTH IT register */
+  #define INTH_MASK_REG   (MEM_INTH_ADDR + 0x02)  /* INTH mask register */
+  #define INTH_S_IRQ_REG  (MEM_INTH_ADDR + 0x04)  /* INTH source IRQ register */
+  #define INTH_S_FIQ_REG  (MEM_INTH_ADDR + 0x06)  /* INTH source FIQ register */
+  #define INTH_B_IRQ_REG  (MEM_INTH_ADDR + 0x08)  /* INTH source binary IRQ reg. */
+  #define INTH_B_FIQ_REG  (MEM_INTH_ADDR + 0x0a)  /* INTH source binary FIQ reg. */
+  #define INTH_CTRL_REG   (MEM_INTH_ADDR + 0x0c)  /* INTH control register */
+  #define INTH_EXT_REG    (MEM_INTH_ADDR + 0x0e)  /* INTH 1st external int. reg. */
+#endif
+
+/* Interrupts number */
+
+#define INTH_TIMER	0			/* number of the TIMER int. */
+#define INTH_AIRQ_FIRST	1			/* first external int. number */
+#define INTH_AIRQ_LAST	13			/* last external int. number */
+#define INTH_DMA	14			/* number of the DMA int. */
+#define INTH_LEAD	15			/* number of the LEAD int. */
+
+/* Bit definition of INTH interrupt level registers */
+
+#define INTH_FIQ_NIRQ	0x0001
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define INTH_PRIORITY	  0x007c
+  #define INTH_EDGE_NLVL  0x0002
+#else
+  #define INTH_PRIORITY	0x001e
+  #define INTH_EDGE_NLVL	0x0020
+#endif
+
+
+/* Bit definition of INTH source binary registers */
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define INTH_SRC_NUM	0x001f
+#else
+  #define INTH_SRC_NUM	0x000f
+#endif
+
+
+/* Bit definition of INTH Control Register */
+
+#define INTH_NEW_IRQ_AGR	0x0001
+#define INTH_NEW_FIQ_AGR	0x0002
+
+/* Other useful constants */
+
+#define INTH_IRQ 0
+#define INTH_FIQ 1
+#define INTH_LEVEL 0
+#define INTH_EDGE 1
+
+/*
+ * Macros
+ */
+
+#define INT_MASK(interrupt) (1 << (interrupt - 1))
+#define PENDING_INT(pendingITs, interrupt) (pendingITs & INT_MASK(interrupt))
+
+/*--------------------------------------------------------------*/
+/*  INTH_ENABLEONEIT()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : num of the IT to enable				*/
+/* Return     :	none						*/
+/* Functionality : Unmask one it				*/
+/*--------------------------------------------------------------*/
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define INTH_ENABLEONEIT(it)( \
+    (it < 16) ? (* (volatile unsigned short *) INTH_MASK_REG1 &= ~(1 << it)) : \
+                (* (volatile unsigned short *) INTH_MASK_REG2 &= ~(1 << (it-16))) \
+  )
+#else
+  #define INTH_ENABLEONEIT(it)(* (volatile unsigned short *) INTH_MASK_REG &= ~(1 << it))
+#endif
+
+/*--------------------------------------------------------------*/
+/*  INTH_DISABLEONEIT()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : num of the IT to disable			*/
+/* Return     :	none						*/
+/* Functionality : mask one it					*/
+/*--------------------------------------------------------------*/
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define INTH_DISABLEONEIT(it)( \
+    (it < 16) ? (* (volatile unsigned short *) INTH_MASK_REG1 |= (1 << it)) : \
+                (* (volatile unsigned short *) INTH_MASK_REG2 |= (1 << (it-16))) \
+  )
+#else
+  #define INTH_DISABLEONEIT(it)(* (volatile unsigned short *) INTH_MASK_REG |= (1 << it))
+#endif
+
+/*--------------------------------------------------------------*/
+/*  INTH_ENABLEALLIT()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Enable all it				*/
+/*--------------------------------------------------------------*/
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define INTH_ENABLEALLIT { \
+    * (volatile unsigned short *) INTH_MASK_REG1 = 0x0000; \
+    * (volatile unsigned short *) INTH_MASK_REG2 = 0x0000; \
+  }
+#else
+  #define INTH_ENABLEALLIT ( * (volatile unsigned short *) INTH_MASK_REG = 0x0000)
+#endif
+
+/*--------------------------------------------------------------*/
+/*  INTH_DISABLEALLIT()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality :mask all it					*/
+/*--------------------------------------------------------------*/
+
+#if (CHIPSET == 4)
+  #define INTH_DISABLEALLIT { \
+  * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
+  * (volatile unsigned short *) INTH_MASK_REG2 = 0x000f; \
+  }
+#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
+  #define INTH_DISABLEALLIT { \
+  * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
+  * (volatile unsigned short *) INTH_MASK_REG2 = 0x01ff; \
+  }
+#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
+  #define INTH_DISABLEALLIT { \
+  * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
+  * (volatile unsigned short *) INTH_MASK_REG2 = 0xffff; \
+  }
+#elif (CHIPSET == 12)
+  #define INTH_DISABLEALLIT { \
+  * (volatile unsigned short *) INTH_MASK_REG1 = 0xffff; \
+  * (volatile unsigned short *) INTH_MASK_REG2 = 0xffff; \
+  }
+#else
+  #define INTH_DISABLEALLIT (* (volatile unsigned short *) INTH_MASK_REG = 0xffff)
+#endif
+
+/*--------------------------------------------------------------*/
+/*  INTH_CLEAR()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : value to write                		        */
+/* Return     :	none						*/
+/* Functionality :valid next it					*/
+/*--------------------------------------------------------------*/
+
+#define INTH_CLEAR (* (volatile SYS_UWORD16 *) INTH_CTRL_REG = 0x0003)
+
+
+/*--------------------------------------------------------------*/
+/*  INTH_VALIDNEXT()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : num of the processed it				*/
+/* Return     :	none						*/
+/* Functionality :valid next it					*/
+/*--------------------------------------------------------------*/
+
+#define INTH_VALIDNEXT (intARM)( * (volatile SYS_UWORD16 *) INTH_CTRL_REG |= (1 << intARM))
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  /*--------------------------------------------------------------*/
+  /*  INTH_RESETALLIT()                                           */
+  /*--------------------------------------------------------------*/
+  /* Parameters : None                                            */
+  /* Return     :	none                                          */
+  /* Functionality :Reset the inth it register                    */
+  /*--------------------------------------------------------------*/
+
+  #define INTH_RESETALLIT { \
+   * (volatile unsigned short *) INTH_IT_REG1 &= 0x0000; \
+   * (volatile unsigned short *) INTH_IT_REG2 &= 0x0000; \
+  }  
+#endif
+
+/* Prototypes */
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  unsigned long INTH_GetPending (void);
+  unsigned long INTH_ResetIT (void);
+#else
+  unsigned short INTH_GetPending (void);
+  unsigned short INTH_ResetIT (void);
+#endif
+
+unsigned short INTH_Ack (int);
+void INTH_InitLevel (int, int, int, int);
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/iq.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/iq.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,171 @@
+/******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename         : iq.h
+
+   Description      : Interrupt header
+
+   Project          : drivers
+
+   Author           : pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.13
+
+   Date and time	: 01/30/01 10:22:22
+
+   Previous delta 	: 12/19/00 14:22:53
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.iq.h
+
+   Sccs Id  (SID)       : '@(#) iq.h 1.13 01/30/01 10:22:22 '
+
+ 
+*****************************************************************************/
+
+#include "../include/config.h"
+#include "../include/sys_types.h"
+
+// Hardware driver library build number 
+#define IQ_BUILD      1
+
+#define WS_MASK     0x001F
+                     
+#if (CHIPSET == 4)
+  #define IQ_NUM_INT     20
+#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
+  #define IQ_NUM_INT     25
+#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
+  #define IQ_NUM_INT     21
+#elif (CHIPSET == 12)
+  #define IQ_NUM_INT     32  // 2nd level interrupt handler is not considered here
+#else
+  #define IQ_NUM_INT     16
+#endif
+
+
+#define IRQ 0
+#define FIQ 1
+
+/*
+ * Interrupt bit numbers
+ */
+#define IQ_WATCHDOG             0  
+
+#define IQ_TIM1                 1
+#define IQ_TIM2                 2
+#define IQ_TSP                  3
+#define IQ_FRAME                4
+#define IQ_PAGE                 5
+#define IQ_SIM                  6
+#define IQ_UART_IT              7
+#if (CHIPSET == 12)
+  #define IQ_KEYBOARD           8
+#else
+  #define IQ_ARMIO              8
+#endif
+#define IQ_RTC_TIMER            9
+#define IQ_RTC_ALARM            10
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define IQ_TGSM               19
+#else
+  #define IQ_TGSM               10
+#endif
+#define IQ_ULPD_GAUGING         11
+#define IQ_EXT                  12
+#if (CHIPSET == 12)
+  #define IQ_ARMIO              16
+#else
+  #define IQ_SIM_CD             16
+#endif
+                
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define IQ_UART_IRDA_IT       18
+#endif
+
+#if (CHIPSET == 12)
+  #define IQ_UART_MODEM2_IT     28
+#endif
+#define IQ_ICR                  20
+                
+#if ((CHIPSET == 5) || (CHIPSET == 6))
+  #define IQ_GEA_IT             24
+#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
+  #define IQ_GEA_IT             20
+#endif
+
+/**** JTAG ID   ****/
+#define SATURN    0xB217
+#define HERCRAM   0xB268   	
+#define F731782   0xB2B5   // HERCROM OLD
+#define F731782B  0xB2B5   // HERCROM 1M REV B
+#define F731782A  0xB335   // HERCROM 1M REV A
+#define F731950   0xB334   // HERCROM 2M
+#if (CHIPSET == 4)
+  #define F731787  0xB2AC   // HERCRAM20G
+#endif
+#if ((CHIPSET == 5) || (CHIPSET == 6))
+  #define F741709  0xB393   // HERCROM20G1
+#endif
+#if (CHIPSET == 9)
+  #define F751681 0xB217   // HERCROM200C035
+#endif
+#if (CHIPSET == 12)
+  #define F751997 0xB512   // HERCROM500G2C035
+#endif
+
+
+unsigned IQ_GetBuild(void);
+void IQ_SetupInterrupts(void);
+void IQ_Dummy(void);
+void IQ_TimerHandler(void);     /* Watchdog timer */
+void IQ_TimerHandler1(void);        /* timer 1 */
+void IQ_TimerHandler2(void);        /* timer 2 */
+void IQ_FrameHandler(void);     /* It Handler for TPU Frame IT NUCLEUS TICKS */
+void IQ_IcrHandler32(void);     // 32-bit ICR interrupt handler
+void IQ_SetupInterruptEdge(unsigned short irq_num);
+void IQ_SetupInterruptLevel(unsigned short irq_num);
+void IQ_InitWaitState(unsigned short rom, unsigned short ram, unsigned short spy, unsigned short lcd, unsigned short jtag); 
+void IQ_Unmask(unsigned irqNum);
+void IQ_Mask(unsigned irqNum);
+void IQ_MaskAll(void);
+/*
+ * FreeCalypso change: our starting version had #if/#elif logic
+ * selecting between declaring IQ_KeypadGPIOHandler() or IQ_KeypadHandler()
+ * based on BOARD voodoo numbers.
+ *
+ * Given that the actual Calypso interrupt covers both GPIO and keypad
+ * possibilities, let's always have an IQ_KeypadGPIOHandler() function
+ * and put whatever per-target conditionals are needed inside.
+ */
+  void IQ_KeypadGPIOHandler (void);
+/* end of FC change */
+SYS_UWORD16 IQ_GetJtagId(void);
+SYS_UWORD16 IQ_GetDeviceVersion(void);
+SYS_BOOL IQ_RamBasedLead(void);
+SYS_UWORD16 IQ_GetRevision(void);
+void IQ_Gauging_Handler(void);
+void IQ_External(void);
+void IQ_Rtc_Handler(void);
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  void IQ_RtcA_Handler(void);
+  void IQ_GsmTim_Handler(void);
+#else
+  void IQ_RtcA_GsmTim_Handler(void);
+#endif
+#if ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+//  void IQ_GEA_Handler(void);
+#endif
+
+#if (TI_PROFILER == 1)
+  void IQ_InitLevel( SYS_UWORD16 inputInt, 
+                     SYS_UWORD16 FIQ_nIRQ, 
+                     SYS_UWORD16 priority, 
+                     SYS_UWORD16 edge );
+#endif
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/mem.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/mem.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,264 @@
+/******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: mem.h
+
+   Description    	: Header file for the memory interface module
+
+   Project        	: Drivers
+
+   Author         	: proussel@ti.com  Patrick Roussel.
+
+   Version number	: 1.12
+
+   Date and time	: 01/30/01 10:22:24
+
+   Previous delta 	: 12/19/00 14:24:11
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.mem.h
+
+   Sccs Id  (SID)       : '@(#) mem.h 1.12 01/30/01 10:22:24 '
+ 
+*****************************************************************************/
+
+#include "../include/config.h"
+
+#define MEM_APIC_REG	0xffe00000	/* APIC register address */
+
+#define MEM_STR1_ADDR	0xfffe0000	/* Strobe 1 : address */
+#define MEM_STR1_CS	32		/* Strobe 1 : number of CS */
+#define MEM_STR0_ADDR	0xffff0000	/* Strobe 0 : address */
+#define MEM_STR0_CS	31		/* Strobe 0 : number of CS */
+
+
+#define MEM_STR_LENGTH	2048		/* Strobe : length of a CS space */
+
+#define MEM_UART_IRDA   0xFFFF5000
+#define MEM_UART_MODEM  0xFFFF5800
+#if (CHIPSET == 12)
+  #define MEM_UART_MODEM2  0xFFFFE000
+#endif
+
+#define MEM_RIF         0xFFFF7000
+
+#define MEM_TCIF        0xFFFEA800
+#define MEM_ICR         0xFFFEB000
+
+/**** Generic masks ****/
+#define BIT0            0x00000001L
+#define BIT1            0x00000002L
+#define BIT2            0x00000004L
+#define BIT3            0x00000008L
+#define BIT4            0x00000010L
+#define BIT5            0x00000020L
+#define BIT6            0x00000040L
+#define BIT7            0x00000080L
+#define BIT8            0x00000100L
+#define BIT9            0x00000200L
+#define BIT10           0x00000400L
+#define BIT11           0x00000800L
+#define BIT12           0x00001000L
+#define BIT13           0x00002000L
+#define BIT14           0x00004000L
+#define BIT15           0x00008000L
+#define BIT16           0x00010000L
+
+
+#define MEM_DEV_ID0     0xFFFEF000
+#define MEM_DEV_ID1     0xFFFEF002
+
+
+// Register read and write macros.
+#define READ_REGISTER_ULONG  ( reg )      ( *(volatile unsigned long * const )( reg ) )
+#define WRITE_REGISTER_ULONG ( reg, val ) ( *(volatile unsigned long * const )( reg ) ) = ( val )
+#define READ_REGISTER_USHORT ( reg )      ( *(volatile unsigned short * const)( reg ) )
+#define WRITE_REGISTER_USHORT( reg, val ) ( *(volatile unsigned short * const)( reg ) ) = ( val )
+#define READ_REGISTER_UCHAR  ( reg )      ( *(volatile unsigned char * const )( reg ) )
+#define WRITE_REGISTER_UCHAR ( reg, val ) ( *(volatile unsigned char * const )( reg ) ) = ( val )
+
+
+/**** External memory register ****/
+#define MEM_TIMER_ADDR	0xfffff800	/* TIMER control register */
+#if (CHIPSET == 12)
+  #define MEM_TIMER_SEC_ADDR     0xfffff880  /* TIMER Secure control register */
+#endif
+
+#define MEM_RHEA_CNTL	0xfffff900	/* memory RHEA control register */
+#define MEM_API_CNTL 	0xfffff902	/* memory API control register */
+#define MEM_ARM_RHEA 	0xfffff904	/* memory ARM/RHEA control register */
+#define ENHANCED_RHEA_CNTL 0xfffff906	/* memory ARM/RHEA control register */
+
+#define MEM_INTH_ADDR 	0xfffffa00		/* INTH registers addr. */
+#define MEM_REG_ADDR 	0xfffffb00		/* memory i/f registers addr. */
+#define MEM_REG_nCS0 	(MEM_REG_ADDR + 0) 	/* nCS0 register address */
+#define MEM_REG_nCS1 	(MEM_REG_ADDR + 2) 	/* nCS1 register address */
+#define MEM_REG_nCS2 	(MEM_REG_ADDR + 4) 	/* nCS2 register address */
+#define MEM_REG_nCS3 	(MEM_REG_ADDR + 6) 	/* nCS3 register address */
+
+#if ((CHIPSET == 3) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
+  #define MEM_REG_nCS4 	(MEM_REG_ADDR + 8) 	/* nCS4 register address */
+  #define MEM_REG_nCS5 	(MEM_REG_ADDR + 0xa) 	/* nCS5 register address */
+  #define MEM_REG_nCS6 	(MEM_REG_ADDR + 0xc) 	/* nCS6 register address */
+#elif ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define MEM_REG_nCS4 	(MEM_REG_ADDR + 0xa) 	/* nCS4 register address */
+  #define MEM_REG_nCS6 	(MEM_REG_ADDR + 0xc) 	/* nCS6 register address */
+  #define MEM_REG_nCS7 	(MEM_REG_ADDR + 0x8) 	/* nCS7 register address */
+#elif (CHIPSET == 12)
+  #define MEM_REG_nCS4     (MEM_REG_ADDR + 0x8)  /* nCS4 register address */
+  #define MEM_REG_nCS5     (MEM_REG_ADDR + 0xa)  /* nCS5 register address */
+  #define MEM_REG_DSPMS    (MEM_REG_ADDR + 0x2e) /* DSPMS register address */
+#else
+  #define MEM_REG_nCS4 	(MEM_REG_ADDR + 8) 	  /* nCS4 register address */
+  #define MEM_REG_nCS5 	(MEM_REG_ADDR + 0xa) 	/* nCS5 register address */
+#endif
+
+#define MEM_CTRL_REG	(MEM_REG_ADDR + 0xe) 	/* Control register address */
+
+#if (CHIPSET == 12)
+  #define MEM_DMA_ADDR       0xffffe800            /* DMA controller reg. addr. */
+#else
+  #define MEM_DMA_ADDR 	0xfffffc00		/* DMA controller reg. addr. */
+#endif
+
+#define MEM_CLKM_ADDR 	0xfffffd00		/* CLKM registers addr. */
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET  ==  11) || (CHIPSET  ==  12))
+  #define MEM_DPLL_ADDR   0xffff9800   /* DPLL control register */
+#endif
+
+#if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET  ==  11) || (CHIPSET  ==  12)
+  #define MEM_MPU_ADDR    0xFFFFFF00   /* Base address of MPU module */
+#endif
+
+#define RTC_XIO_START   0xfffe1800
+
+#define ARM_CONF_REG    0xFFFEF006
+
+    #define MEM_SIM         0xFFFE0000
+    #define MEM_TSP         0xFFFE0800
+    #define MEM_TPU_REG     0xFFFE1000
+    #define MEM_TPU_RAM     0xFFFE1400
+    #define MEM_RTC         0xFFFE1800
+    #define MEM_ULPD        0xFFFE2000
+    #define MEM_SPI         0xFFFE3000
+    #define MEM_TIMER1      0xFFFE3800
+    #define MEM_UWIRE       0xFFFE4000
+    #define MEM_ARMIO       0xFFFE4800
+    #define MEM_TIMER2      0xFFFE6800
+    #define MEM_LPG         0xFFFE7800
+    #define MEM_PWL         0xFFFE8000
+    #define MEM_PWT         0xFFFE8800
+    #if (CHIPSET == 12)
+      #define MEM_KEYBOARD  0xFFFEB800
+    #endif
+    #define MEM_JTAGID_PART	0xFFFEF000		/* JTAG ID code register */
+    #define MEM_JTAGID_VER	0xFFFEF002		/* JTAG ID code register */
+#if (CHIPSET != 12)
+    #define MEM_IO_SEL      0xFFFEF00A
+#endif
+
+
+/**** External memory register ****/
+
+#define MEM_REG_WS 	0x001f 		/* number of wait states */
+#define MEM_REG_DVS 0x0060 		/* device size */
+#define MEM_REG_WE 	0x0080 		/* write enable */
+#define MEM_REG_BIG 0x0100 		/* big endian */
+
+#define MEM_DVS_8 	0 		/* device size = 8 bits */
+#define MEM_DVS_16 	1  		/* device size = 16 bits */
+#define MEM_DVS_32 	2		/* device size = 32 bits */
+
+
+#define MEM_WRITE_DIS 	0  		/* write disable */
+#define MEM_WRITE_EN 	1  		/* write enable */
+
+#define MEM_LITTLE 	0  		/* little endian */
+#define MEM_BIG 	1  		/* big endian */
+
+#define MEM_NO_ADAPT 0  		/* no memory adaptation */
+#define MEM_ADAPT 	 1  		/* memory adaptation */
+
+/**** Memory control register ****/
+
+#define MEM_CNTL_0_BIG    0x01          /* Big Endian for strobe 0 */
+#define MEM_CNTL_0_ADAP   0x02          /* size adaptation for strobe 0 */
+#define MEM_CNTL_1_BIG    0x04          /* Big Endian for strobe 1 */
+#define MEM_CNTL_1_ADAP   0x08          /* size adaptation for strobe 1 */
+#define MEM_CNTL_API_BIG  0x10          /* Big Endian for API */
+#define MEM_CNTL_API_ADAP 0x20          /* size adaptation for API */
+#define MEM_CNTL_DBG      0x40          /* debug */
+
+
+#define ARM_CLK_SRC 0x04
+#define ARM_MCLK_DIV 0x30
+#define TPU_CLK_ENABLE 0x400
+
+#if (CHIPSET == 12)
+/**** DSP Memory shared register ****/
+
+#define MEM_DSPMS_0_MB_TO_DSP   ( 0 )
+#define MEM_DSPMS_0_5_MB_TO_DSP ( 1 )
+
+#endif
+
+#if (CHIPSET == 12)
+  #define ASIC_CONF         0xfffef01c
+#else
+  #define ASIC_CONF         0xfffef008
+#endif
+
+// duplicate definition with MEM_ARMIO !!
+//#define ARMIO_ADDR       0xfffe4800
+
+/**** Config registers  ****/
+#if (CHIPSET != 12)
+  #define QUARTZ_REG        0xfffef00c
+#endif
+
+#define MEM_INIT_CS0(d_ws, d_dvs, d_we, d_dc) ( \
+  *((volatile UWORD16 *) MEM_REG_nCS0 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
+
+#define MEM_INIT_CS1(d_ws, d_dvs, d_we, d_dc) ( \
+  *((volatile UWORD16 *) MEM_REG_nCS1 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
+
+#define MEM_INIT_CS2(d_ws, d_dvs, d_we, d_dc) ( \
+  *((volatile UWORD16 *) MEM_REG_nCS2 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
+
+#define MEM_INIT_CS3(d_ws, d_dvs, d_we, d_dc) ( \
+  *((volatile UWORD16 *) MEM_REG_nCS3 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
+
+#define MEM_INIT_CS4(d_ws, d_dvs, d_we, d_dc) ( \
+  *((volatile UWORD16 *) MEM_REG_nCS4 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
+
+#if (CHIPSET == 12)
+  #define MEM_INIT_CS5(d_ws, d_dvs, d_we, d_dc) ( \
+    *((volatile UWORD16 *) MEM_REG_nCS5 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
+#endif
+
+#if ((CHIPSET == 3) || (CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define MEM_INIT_CS6(d_ws, d_dvs, d_we, d_dc) ( \
+    *((volatile UWORD16 *) MEM_REG_nCS6 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
+#endif
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+  #define MEM_INIT_CS7(d_ws, d_dvs, d_we, d_dc) ( \
+    *((volatile UWORD16 *) MEM_REG_nCS7 ) = (d_ws | (d_dvs << 5) | (d_we << 7) | (d_dc << 9)))
+#endif
+
+#if (CHIPSET == 12)
+  #define MEM_INIT_DSPMS(d_share) ( \
+    *((volatile UWORD16 *) MEM_REG_DSPMS ) = (d_share & 0x0003))
+#endif
+
+/********************** Prototypes ************************/
+
+short MEM_InitCtrl(unsigned short Big0, unsigned short Adap0, unsigned short Big1, unsigned short Adap1, 
+		   unsigned short BigAPI, unsigned short AdapAPI, unsigned short debug);
+short MEM_SetCtrlAPI(unsigned short Big, unsigned short Adap);
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/niq.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/niq.c	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,484 @@
+/******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: niq.c
+
+   Description    	: Nucleus IQ initializations
+
+   Project        	: Drivers
+
+   Author         	: proussel@ti.com  Patrick Roussel.
+
+   Version number	: 1.8
+
+   Date and time	: 01/30/01 10:22:21
+
+   Previous delta 	: 12/19/00 14:22:24
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.niq.c
+
+   Sccs Id  (SID)       : '@(#) niq.c 1.8 01/30/01 10:22:21 '
+  *******************************************************************************/
+
+
+#include "../include/config.h"
+#include "../include/sys_types.h"
+
+#include  "mem.h"
+#include  "rhea_arm.h"
+#include  "inth.h"
+#include  "iq.h"
+
+extern SYS_FUNC irqHandlers[IQ_NUM_INT];
+
+/*--------------------------------------------------------------*/
+/*  	IQ_Prty[IQ_NUM_INT]					*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : IRQ priorities 0xFF means interrupt is masked*/
+/*--------------------------------------------------------------*/
+
+#if (CHIPSET == 4)
+  unsigned char IQ_Prty[IQ_NUM_INT] = 
+  {
+  //  AIRQ0  AIRQ1  AIRQ2  AIRQ3  AIRQ4  AIRQ5  AIRQ6 AIRQ7
+      0x01,  0x02,  0x02,  0xFF,  0x00,  0x04,  0x07, 0x02, 
+
+  //  AIRQ8  AIRQ9  AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA   LEAD 
+      0x01,  0x03,  0x03,  0x00,  0x08,  0x05,  0x06, 0x03,
+
+  //  AIRQ16 AIRQ17 AIRQ18 AIRQ19
+      0x07,  0xFF,  0x02,  0x03
+
+  };
+#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
+  unsigned char IQ_Prty[IQ_NUM_INT] = 
+  {
+  //  AIRQ0  AIRQ1  AIRQ2  AIRQ3  AIRQ4  AIRQ5  AIRQ6  AIRQ7
+      0x01,  0x02,  0x02,  0xFF,  0x00,  0x04,  0x07,  0x02, 
+
+  //  AIRQ8  AIRQ9  AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA    LEAD 
+      0x01,  0x03,  0x03,  0x00,  0x08,  0x05,  0x06,  0x03,
+
+  //  AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
+      0x07,  0xFF,  0x02,  0x03,  0x0F,  0xFF,  0xFF,  0xFF,
+
+  //  AIRQ24
+      0xFF
+
+  };
+#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
+  unsigned char IQ_Prty[IQ_NUM_INT] = 
+  {
+  //  AIRQ0  AIRQ1  AIRQ2  AIRQ3  AIRQ4  AIRQ5  AIRQ6 AIRQ7
+      0x01,  0x02,  0x02,  0xFF,  0x00,  0x04,  0x07, 0x02, 
+
+  //  AIRQ8  AIRQ9  AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA   LEAD 
+      0x01,  0x03,  0x03,  0x00,  0x08,  0x05,  0x06, 0x03,
+
+  //  AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20
+      0x07,  0xFF,  0x02,  0x03,  0xFF
+
+  };
+#elif (CHIPSET == 12)
+  unsigned char IQ_Prty[IQ_NUM_INT] = 
+  {
+  //  AIRQ0  AIRQ1  AIRQ2  AIRQ3   AIRQ4   AIRQ5   AIRQ6  AIRQ7
+      0x01,  0x02,  0x02,  0xFF,   0x00,   0x04,   0x07, 0x02, 
+
+  //  AIRQ8  AIRQ9  AIRQ10  AIRQ11  AIRQ12 AIRQ13  DMA   LEAD 
+      0x01,  0x03,  0x03,  0x00,   0x08,   0x05,   0x06, 0x03,
+
+  //  AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
+      0x07,  0xFF,  0x02,  0x03,  0xFF,  0xFF,  0xFF,  0xFF,
+
+  //  AIRQ24 AIRQ25 AIRQ26 AIRQ27 AIRQ28 AIRQ29 AIRQ30 AIRQ31
+      0xFF,  0xFF,  0xFF,  0xFF,  0x02,  0xFF,  0xFF,  0xFF
+
+  };
+#else
+  unsigned char IQ_Prty[IQ_NUM_INT] = 
+  {
+  //  AIRQ0 AIRQ1 AIRQ2  AIRQ3  AIRQ4  AIRQ5  AIRQ6 AIRQ7
+      0x01, 0x02, 0x02,  0xFF,  0x00,  0x04,  0x07, 0x02, 
+      
+  //  AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA   LEAD 
+      0x01, 0x03, 0x03,  0x00,  0x08,  0x05,  0x06, 0x03 
+
+  };
+#endif
+
+/*--------------------------------------------------------------*/
+/*  	IQ_LEVEL[IQ_NUM_INT]					*/
+/*--------------------------------------------------------------*/
+/* Parameters : none			                    			*/
+/* Return     :	none						                    */
+/* Functionality : IRQ sensitivity                              */
+/* 0: falling edge 1: low level (default)                       */
+/*--------------------------------------------------------------*/
+
+#if (CHIPSET == 4)
+  unsigned char IQ_LEVEL[IQ_NUM_INT] = 
+  {
+  //  AIRQ0  AIRQ1  AIRQ2  AIRQ3  AIRQ4  AIRQ5  AIRQ6 AIRQ7
+      0x01,	 0x01,  0x01,  0x01,  0x01,  0x01,  0x01, 0x00, 
+
+  //  AIRQ8  AIRQ9  AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA   LEAD 
+      0x00,  0x01,  0x00,  0x01,  0x01,  0x01,  0x00, 0x01,
+
+  //  AIRQ16 AIRQ17 AIRQ18 AIRQ19
+      0x01,  0x01,  0x00,  0x00
+
+  };
+#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
+  unsigned char IQ_LEVEL[IQ_NUM_INT] = 
+  {
+  //  AIRQ0  AIRQ1  AIRQ2  AIRQ3  AIRQ4  AIRQ5  AIRQ6  AIRQ7
+      0x01,	 0x01,  0x01,  0x01,  0x01,  0x01,  0x01,  0x00, 
+
+  //  AIRQ8  AIRQ9  AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA    LEAD 
+      0x00,  0x01,  0x00,  0x01,  0x01,  0x01,  0x00,  0x01,
+
+  //  AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
+      0x01,  0x01,  0x00,  0x00,  0x01,  0x00,  0x00,  0x00,
+
+  //  AIRQ24
+      0x00
+
+  };
+#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
+  unsigned char IQ_LEVEL[IQ_NUM_INT] = 
+  {
+  //  AIRQ0  AIRQ1  AIRQ2  AIRQ3  AIRQ4  AIRQ5  AIRQ6 AIRQ7
+      0x01,	 0x01,  0x01,  0x01,  0x01,  0x01,  0x01, 0x00, 
+
+  //  AIRQ8  AIRQ9  AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA   LEAD 
+      0x00,  0x01,  0x00,  0x01,  0x01,  0x01,  0x00, 0x01,
+
+  //  AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20
+      0x01,  0x01,  0x00,  0x00,  0x00
+
+  };
+#elif (CHIPSET == 12)
+  unsigned char IQ_LEVEL[IQ_NUM_INT] = 
+  {
+  //  AIRQ0  AIRQ1  AIRQ2  AIRQ3   AIRQ4   AIRQ5   AIRQ6  AIRQ7
+      0x01,	 0x01,  0x01,  0x01,  0x01,  0x01,  0x01, 0x00, 
+
+  //  AIRQ8  AIRQ9  AIRQ10  AIRQ11  AIRQ12 AIRQ13  DMA   LEAD 
+      0x00,  0x01,  0x00,  0x01,  0x01,  0x01,  0x00, 0x01,
+
+  //  AIRQ16 AIRQ17 AIRQ18 AIRQ19 AIRQ20 AIRQ21 AIRQ22 AIRQ23
+      0x01,  0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,
+
+  //  AIRQ24 AIRQ25 AIRQ26 AIRQ27 AIRQ28 AIRQ29 AIRQ30 AIRQ31
+      0x01,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00,  0x00
+
+  };
+#else
+  unsigned char IQ_LEVEL[IQ_NUM_INT] = 
+  {
+  //  AIRQ0 AIRQ1 AIRQ2  AIRQ3  AIRQ4  AIRQ5  AIRQ6 AIRQ7
+      0x01, 0x01, 0x01,  0x01,  0x01,  0x01,  0x01, 0x00, 
+      
+  //  AIRQ8 AIRQ9 AIRQ10 AIRQ11 AIRQ12 AIRQ13 DMA   LEAD 
+      0x00, 0x01, 0x00,  0x01,  0x01,  0x01,  0x00, 0x01 
+
+  };
+#endif
+
+
+/*--------------------------------------------------------------*/
+/*  	IQ_FIQ_nIRQ[IQ_NUM_INT]					                */
+/*--------------------------------------------------------------*/
+/* Parameters : none			                    			*/
+/* Return     :	none						                    */
+/* Functionality : IRQ sensitivity                              */
+/* 0: falling edge 1: low level (default)                       */
+/*--------------------------------------------------------------*/
+
+#if (CHIPSET == 4)
+  unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = 
+  {
+  //  AIRQ0     AIRQ1     AIRQ2     AIRQ3     AIRQ4     AIRQ5     AIRQ6     AIRQ7
+      INTH_IRQ,	INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, 
+
+  //  AIRQ8     AIRQ9     AIRQ10    AIRQ11    AIRQ12    AIRQ13    DMA       LEAD 
+      INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
+
+  //  AIRQ16    AIRQ17    AIRQ18    AIRQ19
+      INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ
+
+  };
+#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 9))
+  unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = 
+  {
+  //  AIRQ0     AIRQ1     AIRQ2     AIRQ3     AIRQ4     AIRQ5     AIRQ6     AIRQ7
+      INTH_IRQ,	INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, 
+
+  //  AIRQ8     AIRQ9     AIRQ10    AIRQ11    AIRQ12    AIRQ13    DMA       LEAD 
+      INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
+
+  //  AIRQ16    AIRQ17    AIRQ18    AIRQ19    AIRQ20    AIRQ21    AIRQ22    AIRQ23
+      INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
+
+  //  AIRQ24
+      INTH_IRQ
+
+  };
+#elif (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)
+  unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = 
+  {
+  //  AIRQ0     AIRQ1     AIRQ2     AIRQ3     AIRQ4     AIRQ5     AIRQ6     AIRQ7
+      INTH_IRQ,	INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, 
+
+  //  AIRQ8     AIRQ9     AIRQ10    AIRQ11    AIRQ12    AIRQ13    DMA       LEAD 
+      INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
+
+  //  AIRQ16    AIRQ17    AIRQ18    AIRQ19    AIRQ20
+      INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ
+
+  };
+#elif (CHIPSET == 12)
+  unsigned char IQ_FIQ_nIRQ[IQ_NUM_INT] = 
+  {
+  //  AIRQ0     AIRQ1     AIRQ2     AIRQ3     AIRQ4     AIRQ5     AIRQ6     AIRQ7
+      INTH_IRQ,	INTH_IRQ, INTH_IRQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, 
+
+  //  AIRQ8     AIRQ9     AIRQ10    AIRQ11    AIRQ12    AIRQ13    DMA       LEAD 
+      INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ,
+
+  //  AIRQ16    AIRQ17    AIRQ18    AIRQ19    AIRQ20    AIRQ21    AIRQ22    AIRQ23
+      INTH_FIQ, INTH_FIQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_FIQ,
+
+  //  AIRQ24    AIRQ25    AIRQ26    AIRQ27    AIRQ28    AIRQ29    AIRQ30    AIRQ31
+      INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ, INTH_IRQ
+
+  };
+#endif
+
+/*--------------------------------------------------------------*/
+/*  	IQ_GetBuild						*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	Return library build number			*/
+/* Functionality : 						*/
+/*--------------------------------------------------------------*/
+
+unsigned IQ_GetBuild(void)
+{
+   return(IQ_BUILD);
+}
+
+
+/*--------------------------------------------------------------*/
+/*  	IQ_SetupInterrupts					*/
+/*--------------------------------------------------------------*/
+/* Parameters : none						*/
+/* Return     :	none						*/
+/* Functionality : Set IRQ interrupt levels and unmask		*/
+/*--------------------------------------------------------------*/
+
+void IQ_SetupInterrupts(void)
+{
+   int i;
+   char prty;
+
+   /* Setup all interrupts to IRQ with different levels */
+   for (i=INTH_TIMER;i<=IQ_NUM_INT;i++ )
+   {
+      prty = IQ_Prty[i];
+      if (prty != 0xFF)
+      {
+        #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+          INTH_InitLevel(i, IQ_FIQ_nIRQ[i], prty, IQ_LEVEL[i]);
+        #else
+          INTH_InitLevel(i, INTH_IRQ, prty, IQ_LEVEL[i]);
+        #endif
+      }     
+   INTH_DISABLEONEIT(i);
+   }
+}
+
+/*--------------------------------------------------------------*/
+/*  	IQ_InitWaitState					*/
+/*--------------------------------------------------------------*/
+/* Parameters :rom,  ram,  spy,  lcd, jtag			*/
+/* Return     :	none						*/
+/* Functionality : Init wait states				*/
+/*--------------------------------------------------------------*/
+
+void IQ_InitWaitState(unsigned short rom, unsigned short ram, unsigned short spy, unsigned short lcd, unsigned short jtag)
+{
+   volatile char ws;
+
+   ws = * (volatile SYS_UWORD16 *)  MEM_REG_nCS0;
+   ws &= ~WS_MASK; 		
+   ws |= rom;
+   * (volatile SYS_UWORD16 *) MEM_REG_nCS0  = ws;
+
+   ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS1;
+   ws &= ~WS_MASK; 		
+   ws |= ram;
+   * (volatile SYS_UWORD16 *) MEM_REG_nCS1 = ws;
+   
+   ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS2;
+   ws &= ~WS_MASK; 		
+   ws |= spy;
+   * (volatile SYS_UWORD16 *) MEM_REG_nCS2  = ws;
+
+   ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS4;
+   ws &= ~WS_MASK; 		
+   ws |= lcd;
+   * (volatile SYS_UWORD16 *) MEM_REG_nCS4  = ws;
+
+#if ((CHIPSET != 4) && (CHIPSET != 7) && (CHIPSET != 8) && (CHIPSET != 10) && (CHIPSET != 11))
+   ws = * (volatile SYS_UWORD16 *) MEM_REG_nCS5;
+   ws &= ~WS_MASK; 		
+   ws |= jtag;
+   * (volatile SYS_UWORD16 *) MEM_REG_nCS5  = ws;
+#endif
+
+}
+
+void IQ_Unmask(unsigned irqNum)
+{
+  INTH_ENABLEONEIT(irqNum); 
+}
+
+void IQ_Mask(unsigned irqNum)
+{
+  INTH_DISABLEONEIT(irqNum); 
+}
+
+void IQ_MaskAll(void)
+{
+  INTH_DISABLEALLIT; 
+}
+
+
+/*
+ * IQ_GetJtagId
+ *
+ * JTAG part identifier 
+ */
+SYS_UWORD16 IQ_GetJtagId(void)
+{
+   unsigned short v;
+   
+   v = *( (volatile unsigned short *) (MEM_JTAGID_PART));
+   return(v);
+}
+
+
+
+ /*
+ * IQ_GetDeviceVersion
+ *
+ * Read from CLKM module
+ */
+SYS_UWORD16 IQ_GetDeviceVersion(void)
+{
+   SYS_UWORD16 v;
+
+   v = *( (volatile SYS_WORD16 *) (MEM_JTAGID_VER));
+   return(v);
+}
+
+
+//// !!!! TO BE REMOVED IN NEXT CONDAT RELEASE >2.55
+ /*
+ * IQ_GetDeviceVersion
+ *
+ * Read from CLKM module
+ */
+SYS_UWORD16 IQ_GetPoleStarVersion(void)
+{
+   SYS_UWORD16 v;
+
+   v = *( (volatile SYS_UWORD16 *) (MEM_JTAGID_VER));
+   return(v);
+}
+
+
+
+/*
+ * IQ_RamBasedLead
+ *
+ * Returns TRUE if the LEAD has RAM and needs to be downloaded
+ *
+ */
+
+SYS_BOOL IQ_RamBasedLead(void)
+{
+   unsigned short id;
+   
+   id  = IQ_GetJtagId();
+   
+#if (CHIPSET != 7)
+   return ((id == SATURN || id == HERCRAM || id == 0xB2AC) ? 1 : 0); 
+#else
+   // Calypso G2 rev. A and Samson share the same JTAG ID
+   return (0);
+#endif
+ }
+
+/*
+ * IQ_Power
+ *
+ * Switch-on or off the board
+ *
+ * Parameters : BOOL power  : 1 to power-on (maintain power)
+ *                            0 to power-off
+ *
+ * See A-Sample board specification
+ */
+void IQ_Power(SYS_UWORD8 power)
+{
+// This is only implemented for the A-Sample
+}
+
+/*
+ * IQ_GetRevision
+ *
+ * Silicon revision - Read from JTAG version code
+ */
+SYS_UWORD16 IQ_GetRevision(void)
+{
+   unsigned short v;
+   
+   v = *( (volatile unsigned short *) (MEM_JTAGID_VER));
+   return(v);
+}
+
+#if (TI_PROFILER == 1)
+
+/*
+ *  	IQ_InitLevel
+ *
+ * Parameters : interrupt, FIQ_nIRQ, priority, edge
+ * Return     :	none
+ * Functionality : initialize Interrupt Level Registers
+ */
+
+void IQ_InitLevel ( SYS_UWORD16 inputInt, 
+                    SYS_UWORD16 FIQ_nIRQ, 
+                    SYS_UWORD16 priority, 
+                    SYS_UWORD16 edge )
+{
+   volatile SYS_UWORD16 *inthLevelReg = (SYS_UWORD16 *) INTH_EXT_REG; 
+
+   inthLevelReg = inthLevelReg + inputInt;
+
+   *inthLevelReg = (FIQ_nIRQ | (priority << 6) | (edge << 1));
+}
+
+#endif
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/niq32.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/niq32.c	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,610 @@
+/******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: niq32.c
+
+   Description    	: Nucleus IQ initializations
+
+   Project        	: Drivers
+
+   Author         	: proussel@ti.com  Patrick Roussel.
+
+   Version number	: 1.12
+
+   Date and time	: 02/19/01 14:01:50
+
+   Previous delta 	: 12/19/00 14:24:51
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED_ADC/drivers1/common/SCCS/s.niq32.c
+
+   Sccs Id  (SID)       : '@(#) niq32.c 1.12 02/19/01 14:01:50 '
+*******************************************************************************/
+
+#include "l1_sw.cfg"
+
+#if(!OP_L1_STANDALONE)
+  #include "chipset.cfg"
+  #include "debug.cfg"
+  #include "board.cfg"
+  #include "rv_defined_swe.h"    
+  #include "rtc_config.h"
+#endif
+
+#include "sys_types.h"
+#include "serialswitch.h"
+
+#include  "mem.h"
+#include  "inth.h"
+#include  "sim.h"
+#include  "abb_inth.h"	  // for External Interrupt
+
+#define IQ_H
+#include  "iq.h"
+#include  "ulpd.h"
+
+#if (defined RVM_DAR_SWE) && (defined _GSM)
+  extern void dar_watchdog_reset(void);
+#endif
+
+#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (BOARD == 43) || (BOARD == 45))
+#include "armio.h"
+#include "uartfax.h"
+#endif
+
+/* External declaration */
+extern void GAUGING_Handler(void);
+extern void TMT_Timer_Interrupt(void);
+extern void kpd_key_handler(void);
+extern void TP_FrameIntHandler(void);
+
+#if (!OP_L1_STANDALONE)
+  #if (defined RVM_MPM_SWE)
+   extern void MPM_InterruptHandler(void);
+  #endif
+
+  #if (TI_PROFILER == 1)
+    extern void ti_profiler_tdma_action(void);
+  #endif
+
+  extern void RTC_GaugingHandler(void);
+  extern void RTC_ItTimerHandle(void);
+  extern void RTC_ItAlarmHandle(void);
+#endif
+
+
+
+/* Global variables */
+unsigned IQ_TimerCount1;   /* Used to check if timer is incrementing */
+unsigned IQ_TimerCount2;   /* Used to check if timer is incrementing */
+unsigned IQ_TimerCount;    /* Used to check if timer is incrementing */
+unsigned IQ_DummyCount;    /* Used to check if dummy IT */
+unsigned IQ_FrameCount;    /* Used to check if Frame IT TPU*/
+unsigned IQ_GsmTimerCount; /* Used to check if GSM Timer IT */
+
+/* add this two variables for imported 188 functions, Jeffrey, 02/26/04 */
+typedef struct GPIO_HISR_INFO 
+{
+	NU_HISR		hisr;
+	char		hisr_stack[1024];	
+} T_GPIO_HISR_INFOS;
+
+static T_GPIO_HISR_INFOS gpio_hisr_infos = {0};
+int g_interrupt = 0;
+
+extern void Hall_OC_IntHandler( void ) ;
+
+
+/*--------------------------------------------------------------*/
+/*  	irqHandlers                                             */
+/*--------------------------------------------------------------*/
+/* Parameters :none                                             */
+/* Return     :	none                                            */
+/* Functionality :  Table of interrupt handlers                 */
+/* These MUST be 32-bit entries                                 */
+/*--------------------------------------------------------------*/
+
+SYS_FUNC irqHandlers[IQ_NUM_INT] = 
+{
+   IQ_TimerHandler,        /* Watchdog timer */
+   IQ_TimerHandler1,       /* timer 1 */
+   IQ_TimerHandler2,       /* timer 2 */
+   IQ_Dummy,               /* AIRQ 3 */   
+   IQ_FrameHandler,        /* TPU Frame It AIRQ 4 */
+   IQ_Dummy,               /* AIRQ 5 */
+   #if (OP_L1_STANDALONE)
+     IQ_Dummy,
+   #else
+     SIM_IntHandler,         /* AIRQ 6 */
+   #endif
+#if ((CHIPSET == 2) || (CHIPSET == 3))
+   SER_uart_handler,       /* AIRQ 7 */
+   #elif ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+   SER_uart_modem_handler, /* AIRQ 7 */
+#endif
+   #if (CHIPSET == 12)
+     IQ_KeypadHandler,       /* AIRQ 8 */
+   #else
+#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41))
+   IQ_KeypadGPIOHandler,   /* AIRQ 8 */
+#else
+   IQ_KeypadHandler,       /* AIRQ 8 */
+#endif
+   #endif
+   IQ_Rtc_Handler,         /* AIRQ 9 RTC Timer*/
+#if ((CHIPSET == 2) || (CHIPSET == 3))
+   IQ_RtcA_GsmTim_Handler, /* AIRQ 10 RTC ALARM OR ULPD GSM TIMER*/
+   #elif ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+   IQ_RtcA_Handler,        /* AIRQ 10 RTC ALARM */
+#endif
+   IQ_Gauging_Handler,     /* AIRQ 11 ULPD GAUGING */
+   IQ_External,            /* AIRQ 12 */
+   IQ_Dummy,               /* AIRQ 13 */
+   IQ_Dummy,               /* DMA interrupt */
+#if (CHIPSET == 4)
+   IQ_Dummy,               /* LEAD */
+   IQ_Dummy,               /* SIM card-detect fast interrupt */
+   IQ_Dummy,               /* External fast interrupt */
+   SER_uart_irda_handler,  /* UART IrDA interrupt */
+   IQ_GsmTim_Handler       /* ULPD GSM timer */
+#elif ((CHIPSET == 5) || (CHIPSET == 6))
+   IQ_Dummy,               /* LEAD */
+   IQ_Dummy,               /* SIM card-detect fast interrupt */
+   IQ_Dummy,               /* External fast interrupt */
+   SER_uart_irda_handler,  /* UART IrDA interrupt */
+   IQ_GsmTim_Handler,      /* ULPD GSM timer */
+   IQ_Dummy,               /* Not mapped interrupt */
+   IQ_Dummy,               /* Not mapped interrupt */
+   IQ_Dummy,               /* Not mapped interrupt */
+   IQ_Dummy,               /* Not mapped interrupt */
+   IQ_Dummy                /* GEA interrupt */
+#elif ((CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+   IQ_Dummy,               /* LEAD */
+   IQ_Dummy,               /* SIM card-detect fast interrupt */
+   IQ_Dummy,               /* External fast interrupt */
+   SER_uart_irda_handler,  /* UART IrDA interrupt */
+   IQ_GsmTim_Handler,      /* ULPD GSM timer */
+   IQ_Dummy                /* GEA interrupt */
+#elif (CHIPSET == 9)
+   IQ_Dummy,               /* LEAD */
+   IQ_Dummy,               /* SIM card-detect fast interrupt */
+   IQ_Dummy,               /* External fast interrupt */
+   SER_uart_irda_handler,  /* UART IrDA interrupt */
+   IQ_GsmTim_Handler,      /* ULPD GSM timer */
+   IQ_Dummy,               /* Not mapped interrupt */
+   IQ_Dummy,               /* Not mapped interrupt */
+   IQ_Dummy,               /* Not mapped interrupt */
+   IQ_Dummy,               /* Not mapped interrupt */
+   IQ_Dummy                /* Reserved */
+#elif (CHIPSET == 12)
+   IQ_Dummy,               /* IRQ15 - LEAD */
+   IQ_Dummy,               /* IRQ16 - GPIO */
+   IQ_Dummy,               /* IRQ17 - External fast interrupt */
+   SER_uart_irda_handler,  /* IRQ18 - UART IrDA interrupt */
+   IQ_GsmTim_Handler,      /* IRQ19 - ULPD GSM timer */
+   IQ_Dummy,               /* IRQ20 - GEA interrupt */
+   IQ_Dummy,               /* IRQ21 - External general Purpose interrupt IRQ1 */
+   IQ_Dummy,               /* IRQ22 - External general Purpose interrupt IRQ2 */
+   IQ_Dummy,               /* IRQ23 - USIM card insertion/extraction */
+   IQ_Dummy,               /* IRQ24 - USIM */
+   IQ_Dummy,               /* IRQ25 - LCD */
+   IQ_Dummy,               /* IRQ26 - USB */
+   IQ_Dummy,               /* IRQ27 - MMC/SD/Memory Stick */
+   SER_uart_modem2_handler,/* IRQ28 - UART_MODEM2 */
+   IQ_Dummy,               /* IRQ29 - 2nd level interrupt handler */
+   IQ_Dummy,               /* IRQ30 - I2C or uWIRE */
+   IQ_Dummy                /* IRQ31 - NAND FLASH */
+#else
+   IQ_Dummy                /* LEAD */
+#endif
+};   
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  /*--------------------------------------------------------------*/
+  /*  	fiqHandlers                                               */
+  /*--------------------------------------------------------------*/
+  /* Parameters :none                                             */
+  /* Return     :none                                             */
+  /* Functionality :  Table of interrupt handlers                 */
+  /* These MUST be 32-bit entries                                 */
+  /*--------------------------------------------------------------*/
+
+  SYS_FUNC fiqHandlers[IQ_NUM_INT] = 
+  {
+    IQ_Dummy,          /* Watchdog timer */
+    IQ_Dummy,          /* timer 1 */
+    IQ_Dummy,          /* timer 2 */
+    IQ_Dummy,          /* AIRQ 3 */   
+    IQ_Dummy,          /* TPU Frame It AIRQ 4 */
+    IQ_Dummy,          /* AIRQ 5 */
+    IQ_Dummy,          /* AIRQ 6 */
+    IQ_Dummy,          /* AIRQ 7 */
+    IQ_Dummy,          /* AIRQ 8 */
+    IQ_Dummy,          /* AIRQ 9 RTC Timer */
+    IQ_Dummy,          /* AIRQ 10 RTC ALARM */
+    IQ_Dummy,          /* AIRQ 11 ULPD GAUGING */
+    IQ_Dummy,          /* AIRQ 12 */
+    IQ_Dummy,          /* AIRQ 13 Spi Tx Rx interrupt */
+    IQ_Dummy,          /* DMA interrupt */
+    IQ_Dummy,          /* LEAD */
+    #if (CHIPSET == 12)
+      IQ_Dummy,        /* IRQ16 - GPIO */
+    #else
+      #if (OP_L1_STANDALONE)
+        IQ_Dummy,
+      #else
+	  /* glowing, 2004-06-08, replace SIM with Hall according to 188 */
+	  Hall_OC_IntHandler,  /* glowing,2003-12-18, Hall open-close fast interrupt, it replace SIM_CD_IntHandler */
+	  //SIM_CD_IntHandler, /* SIM card-detect fast interrupt */
+    #endif
+    #endif
+    IQ_Dummy,          /* External fast interrupt */
+    IQ_Dummy,          /* UART_IRDA interrupt */
+  #if (CHIPSET == 4)
+    IQ_Dummy           /* ULPD GSM timer */
+  #elif ((CHIPSET == 5) || (CHIPSET == 6))
+    IQ_Dummy,          /* ULPD GSM timer */
+    IQ_Dummy,          /* Not mapped interrupt */
+    IQ_Dummy,          /* Not mapped interrupt */
+    IQ_Dummy,          /* Not mapped interrupt */
+    IQ_Dummy,          /* Not mapped interrupt */
+    IQ_Dummy           /* GEA interrupt */
+  #elif ((CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11))
+    IQ_Dummy,          /* ULPD GSM timer */
+    IQ_Dummy           /* GEA timer */
+  #elif (CHIPSET == 9)
+    IQ_Dummy,        /* ULPD GSM timer */
+    IQ_Dummy,        /* Not mapped interrupt */
+    IQ_Dummy,        /* Not mapped interrupt */
+    IQ_Dummy,        /* Not mapped interrupt */
+    IQ_Dummy,        /* Not mapped interrupt */
+    IQ_Dummy         /* Reserved */
+  #elif (CHIPSET == 12)
+    IQ_Dummy,        /* IRQ19 - ULPD GSM timer */
+    IQ_Dummy,        /* IRQ20 - GEA interrupt */
+    IQ_Dummy,        /* IRQ21 - External general Purpose interrupt IRQ1 */
+    IQ_Dummy,        /* IRQ22 - External general Purpose interrupt IRQ2 */
+    IQ_Dummy,        /* IRQ23 - USIM card insertion/extraction */
+    IQ_Dummy,        /* IRQ24 - USIM */
+    IQ_Dummy,        /* IRQ25 - LCD */
+    IQ_Dummy,        /* IRQ26 - USB */
+    IQ_Dummy,        /* IRQ27 - MMC/SD/Memory Stick */
+    IQ_Dummy,        /* IRQ28 - UART_MODEM2 */
+    IQ_Dummy,        /* IRQ29 - 2nd level interrupt handler */
+    IQ_Dummy,        /* IRQ30 - I2C or uWIRE */
+    IQ_Dummy         /* IRQ31 - NAND FLASH */
+  #endif
+};   
+#endif
+
+/*--------------------------------------------------------------*/
+/*  IQ_Gauging_Handler				                */
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :   Handle unused interrupts 			*/
+/*--------------------------------------------------------------*/
+void IQ_Gauging_Handler(void)
+{
+   GAUGING_Handler();
+#if (!OP_L1_STANDALONE)
+   RTC_GaugingHandler();
+#endif
+} 
+
+
+/*--------------------------------------------------------------*/
+/*  IQ_External							                        */
+/*--------------------------------------------------------------*/
+/* Parameters : none						                    */
+/* Return     :	none						                    */
+/* Functionality : Handle External IRQ mapped on ABB.           */
+/*--------------------------------------------------------------*/
+void IQ_External(void)
+{
+  // Mask external interrupt (12)
+  IQ_Mask(IQ_EXT);
+
+  // The external IRQ is mapped on the ABB interrupt.
+  // The associated HISR ABB_Hisr is activated on reception on the external IRQ.
+  if(Activate_ABB_HISR())
+  {
+     IQ_Unmask(IQ_EXT);
+  }
+}
+
+/*--------------------------------------------------------------*/
+/*  IQ_Dummy							*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :   Handle unused interrupts 			*/
+/*--------------------------------------------------------------*/
+void IQ_Dummy(void)
+{
+    IQ_DummyCount++;
+}   
+
+/*--------------------------------------------------------------*/
+/*  IQ_RTCHandler						*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :    Handle RTC Time interrupts 		*/
+/*--------------------------------------------------------------*/
+
+void IQ_Rtc_Handler(void)
+{
+#if (!OP_L1_STANDALONE)
+  RTC_ItTimerHandle();
+#endif
+}
+
+/*--------------------------------------------------------------*/
+/*  IQ_RtcA_GsmTim_Handler					*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :    Handle RTC ALARM or GAUGING interrupts    */
+/*--------------------------------------------------------------*/
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+void IQ_RtcA_Handler(void)
+{
+  #if (!OP_L1_STANDALONE)
+    /* INTH_DISABLEONEIT(IQ_RTC_ALARM); *//* RTC ALARM IT  */
+    if ( (* (SYS_WORD8 *) RTC_STATUS_REG) & RTC_ALARM )
+      RTC_ItAlarmHandle();
+  #endif
+}
+
+  void IQ_GsmTim_Handler(void)
+  {
+
+    if ( (* (SYS_UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM  )
+    {
+      // it is GSM Timer it.....
+      IQ_GsmTimerCount++;
+    }
+  }
+#else
+void IQ_RtcA_GsmTim_Handler(void)
+{
+  #if (!OP_L1_STANDALONE)
+   if ( (* (SYS_UWORD16 *) ULDP_GSM_TIMER_IT_REG) & ULPD_IT_TIMER_GSM  )
+   {
+     // it is GSM Timer it.....
+     IQ_GsmTimerCount++;
+   }
+   else
+   {
+     /* INTH_DISABLEONEIT(IQ_RTC_ALARM); *//* RTC ALARM IT  */
+     if ( (* (SYS_WORD8 *) RTC_STATUS_REG) & RTC_ALARM )
+        RTC_ItAlarmHandle();
+   }   
+  #endif
+}
+#endif
+
+/*--------------------------------------------------------------*/
+/*  IQ_TimerHandler						*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :    Handle Timer interrupts 			*/
+/*--------------------------------------------------------------*/
+ void IQ_TimerHandler(void)
+{
+   IQ_TimerCount++;
+   TMT_Timer_Interrupt();
+   #if (defined RVM_DAR_SWE) && (defined _GSM)
+     dar_watchdog_reset();
+   #endif
+}
+ 
+/*--------------------------------------------------------------*/
+/*  IQ_FramerHandler						*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :    Handle Timer interrupts 			*/
+/*--------------------------------------------------------------*/
+ void IQ_FrameHandler(void)
+{
+   IQ_FrameCount++;
+   TMT_Timer_Interrupt();
+   TP_FrameIntHandler();
+   #if (!OP_L1_STANDALONE)
+     #if (TI_PROFILER == 1)
+       // TDMA treatment for profiling buffer
+       ti_profiler_tdma_action();
+     #endif
+   #endif
+}
+
+/*--------------------------------------------------------------*/
+/*  IQ_TimerHandler1						*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :    Handle Timer 1 interrupts 			*/
+/*--------------------------------------------------------------*/
+void IQ_TimerHandler1(void)
+{
+  IQ_TimerCount1++;  
+}
+ 
+/*--------------------------------------------------------------*/
+/*  IQ_TimerHandler2						*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :    Handle Timer 2 interrupts 			*/
+/*--------------------------------------------------------------*/
+ void IQ_TimerHandler2(void)
+{
+  IQ_TimerCount2++;  
+ }
+
+/*--------------------------------------------------------------*/
+/*  IQ_IRQ_isr							*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :    HHandle IRQ interrupts  			*/
+/*--------------------------------------------------------------*/
+void IQ_IRQ_isr(void)
+{
+  irqHandlers[((* (SYS_UWORD16 *) INTH_B_IRQ_REG) & INTH_SRC_NUM)]();  /* ACK IT */
+  * (SYS_UWORD16 *) INTH_CTRL_REG |= (1 << INTH_IRQ);	/* valid next IRQ */
+}
+
+/*--------------------------------------------------------------*/
+/*  IQ_FIQ_isr							*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :   Handle FIQ interrupts  			*/
+/*--------------------------------------------------------------*/
+void IQ_FIQ_isr(void)
+{
+  #if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+    fiqHandlers[((* (SYS_UWORD16 *) INTH_B_FIQ_REG) & INTH_SRC_NUM)]();  /* ACK IT */
+  #endif
+    * (SYS_UWORD16 *) INTH_CTRL_REG |= (1 << INTH_FIQ);	/* valid next FIQ */
+}   
+
+#if ((BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41))
+
+/*--------------------------------------------------------------*/
+/*  IQ_KeypadGPIOHandler                                        */
+/*--------------------------------------------------------------*/
+/* Parameters    : none                                             */
+/* Return        : none                                            */
+/* Functionality : Handle keypad and GPIO interrupts          */
+/*--------------------------------------------------------------*/
+void IQ_KeypadGPIOHandler(void)
+{
+ #if (!OP_L1_STANDALONE)
+    /*
+     * GPIO interrupt must be checked before the keypad interrupt. The GPIO
+     * status bit is reset when the register is read.
+     */
+     
+	     g_interrupt = 80;
+    if (AI_CheckITSource (ARMIO_GPIO_INT)) {
+    #if 0
+    #ifdef RVM_MPM_SWE
+      /* check if the SWE has been started */
+      MPM_InterruptHandler ();
+    #else
+      UAF_DTRInterruptHandler ();
+    #endif
+    #endif
+	  /* Jeffrey, 02/26/04, add this line from 188 */
+	  gpio_handler();
+	}
+
+    if (AI_CheckITSource (ARMIO_KEYPDAD_INT))
+      kpd_key_handler ();
+ #endif
+}   
+
+/**
+ * function: gpio_handler  hall
+ */
+void gpio_handler(void)
+{
+	/* 2003/11/01 Robert.Chen for melody interrupt from GPIO1*/
+	/* modify from */
+	
+	/*
+	   AI_MaskIT(2);
+	 */
+	 
+	/* to */
+	AI_MaskIT(2);
+	/* end Robert.Chen */
+
+    /* Activate HISR to process the key event */
+      NU_Activate_HISR(&gpio_hisr_infos.hisr);
+	}
+
+/* 2003/11/01 Robert.Chen  Melody HISR entry */
+void MI_Melody_Hisr(void)
+{
+	MaDevDrv_IntHandler();
+	AI_UnmaskIT(0x02);
+}
+
+/**
+ * function: kpd_initialize_keypad_hardware
+ */
+void Gpio_hisr_initialize(void)
+{
+   int i;
+   
+	/* 2003/11/01 Robert.Chen, modify for Melody HISR */
+	/* modify from */
+   #if 0
+   /* HISR creation */
+   NU_Create_HISR(&gpio_hisr_infos.hisr,
+                  "GPIO_HISR",                  
+                  gpio_hisr_entry,
+                  2,
+                  gpio_hisr_infos.hisr_stack,
+                  sizeof(gpio_hisr_infos.hisr_stack));
+
+	AI_UnmaskIT(0x02);
+	
+   	i = HallOnOff();
+	
+	if(i){
+		AI_SelectIOForIT (2, 0);//ARMIO_FALLING_EDGE
+	}
+	else{
+
+		AI_SelectIOForIT (2, 1);//ARMIO_RISING_EDGE
+	}	
+	#endif
+	/* to */
+	NU_Create_HISR(&gpio_hisr_infos.hisr,
+                  "GPIO_HISR",                  
+                  MI_Melody_Hisr,
+                  2,
+                  gpio_hisr_infos.hisr_stack,
+                  sizeof(gpio_hisr_infos.hisr_stack));
+	
+	AI_EnableBit(5); /* MCSI_TXD as GPIO9 */
+	AI_ConfigBitAsInput(9); /* GPIO9 as input pin for YMU765 ~IRQ */		
+	AI_SelectIOForIT (9, 0); /* GPIO9 as input, falling edge triggered */
+	AI_UnmaskIT(0x02);		 /* enable GPIO IRQ */
+	
+	/* end modify, Robert.Chen */
+}
+/* end of imported functins, Jeffrey, 02/26/04 */
+/* ---------------------------------------------*/
+
+#elif ((BOARD == 43) || (BOARD == 45))
+
+/*--------------------------------------------------------------*/
+/*  IQ_KeypadHandler							*/
+/*--------------------------------------------------------------*/
+/* Parameters :none						*/
+/* Return     :	none						*/
+/* Functionality :   Handle keypad interrupts  			*/
+/*--------------------------------------------------------------*/
+void IQ_KeypadHandler(void)
+{
+ #if (!OP_L1_STANDALONE)
+     kpd_key_handler ();
+ #endif
+}   
+	
+#endif
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/rhea_arm.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/rhea_arm.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,100 @@
+/******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename       	: rhea_arm.h
+
+   Description    	: Header file for the ARM RHEA interface
+
+   Project        	: drivers
+
+   Author         	: pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.5
+
+   Date and time	: 01/30/01 10:22:28
+
+   Previous delta 	: 12/08/00 11:38:10
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/RELEASE_GPRS/drivers1/common/SCCS/s.rhea_arm.h
+
+   Sccs Id  (SID)       : '@(#) rhea_arm.h 1.5 01/30/01 10:22:28 '
+
+ 
+*****************************************************************************/
+
+#include "../include/config.h"
+
+/**** RHEA control register ****/
+
+#define RHEA_CNTL_FACT_0   0x000f	/* Division factor for strobe 0 */
+#define RHEA_CNTL_FACT_1   0x00f0	/* Division factor for strobe 1 */
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define RHEA_CNTL_TIMEOUT  0xff00 	/* RHEA bus access timeout */
+#else
+  #define RHEA_CNTL_TIMEOUT  0xfe00 	/* RHEA bus access timeout */
+#endif
+
+/**** API control register ****/
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define RHEA_API_WS_H   0x001f		/* API wait states when DSP is in HOM mode */
+  #define RHEA_API_WS_S   0x03e0		/* API wait states when DSP in in SAM mode */
+#else
+  #define RHEA_API_WS_H   0x001f		/* API wait states for High clkout */
+  #define RHEA_API_WS_L   0x02e0		/* API wait states for Low clkout */
+#endif
+
+/**** ARM RHEA control register ****/
+
+#define RHEA_ARM_WEN_0   0x0001		/* Write enable for strobe 0 */
+#define RHEA_ARM_WEN_1   0x0002		/* Write enable for strobe 1 */
+
+/*---------------------------------------------------------------/
+/*  RHEA_INITRHEA()						*/
+/*--------------------------------------------------------------*/
+/* Parameters :Fac0 acces factor strb0, Fac1 acces factor strb1	*/
+/*		timeout max time periph stall the processor	*/
+/* Return     :	none						*/
+/* Functionality :Initialize the RHEA control register		*/
+/*--------------------------------------------------------------*/
+
+#if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define RHEA_INITRHEA(Fac0,Fac1,TimeOut) (* (unsigned short *) MEM_RHEA_CNTL = (Fac0 | Fac1 << 4 | TimeOut << 8))
+#else
+  #define RHEA_INITRHEA(Fac0,Fac1,TimeOut) (* (unsigned short *) MEM_RHEA_CNTL = (Fac0 | Fac1 << 4 | TimeOut << 9))
+#endif
+
+/*---------------------------------------------------------------/
+/*  RHEA_INITAPI()						*/
+/*--------------------------------------------------------------*/
+/* Parameters :wsH wait states when freq high, wsL wait states	*/
+/*		when freq low					*/
+/* Return     :	none						*/
+/* Functionality :Initialize the API control register		*/
+/*--------------------------------------------------------------*/
+
+#define RHEA_INITAPI(wsH, wsL) (* (SYS_UWORD16 *) MEM_API_CNTL = ((wsH) | (wsL) << 5))
+
+/*---------------------------------------------------------------/
+/*  RHEA_INITARM()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : Wen0 write enable domain strb0			*/
+/*		Wen1 write enable domain strb1			*/
+/* Return     :	none						*/
+/* Functionality :Initialize the ARM RHEA control register	*/
+/*--------------------------------------------------------------*/
+
+#define RHEA_INITARM(Wen0,Wen1) (* (SYS_UWORD16 *) MEM_ARM_RHEA = ((Wen0) | (Wen1) << 1))
+ 
+/* ----- Prototypes ----- */
+
+short RHEA_GetRHEA(unsigned short *Fac0, unsigned short *Fac1, unsigned short *TimeOut);
+short RHEA_GetAPI(unsigned short *wsL, unsigned short *wsH);
+short RHEA_GetARM(unsigned short *Wen0, unsigned short *Wen1);
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/sim.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/sim.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,422 @@
+/*
+ * SIM.H
+ *
+ * Pole Star SIM
+ *
+ * Target : ARM
+ *
+ * Copyright (c) Texas Instruments 1995-1997
+ *
+ */
+
+/*
+ * Device addresses - GCS000 (Gemini / Polestar)
+ *                    HER207 (Hercules)
+ */ 
+
+#include "../include/config.h"
+#include "../include/sys_types.h"
+#include "../nucleus/nucleus.h"
+
+/* Flags activation section */
+/* #define SIM_RETRY			by default : NOT ACTIVE */
+/* #define SIM_DEBUG_TRACE		by default : NOT ACTIVE */
+
+
+#define SIM_CMD         (MEM_SIM + 0x00)
+#define SIM_STAT        (MEM_SIM + 0x02)
+#define SIM_CONF1       (MEM_SIM + 0x04)
+#define SIM_CONF2       (MEM_SIM + 0x06)
+#define SIM_IT          (MEM_SIM + 0x08)
+#define SIM_DRX         (MEM_SIM + 0x0A)
+#define SIM_DTX         (MEM_SIM + 0x0C)
+#define SIM_MASK        (MEM_SIM + 0x0E)
+
+
+
+/*
+ * Bit definitions 
+ */ 
+// control regidter
+#define SIM_CMD_CRST          0x0001
+#define SIM_CMD_SWRST         0x0002
+#define SIM_CMD_STOP          0x0004
+#define SIM_CMD_START         0x0008
+#define SIM_CMD_CLKEN         0x0010	
+
+// status register
+#define SIM_STAT_CD           0x0001   // card present
+#define SIM_STAT_TXPAR        0x0002   // transmit parity status
+#define SIM_STAT_FFULL        0x0004   // fifo full
+#define SIM_STAT_FEMPTY       0x0008   // fifo empty
+
+// configuration register
+#define SIM_CONF1_CHKPAR      0x0001   // enable receipt check parity
+#define SIM_CONF1_CONV        0x0002   // coding convention
+#define SIM_CONF1_TXRX        0x0004   // SIO line direction
+#define SIM_CONF1_SCLKEN      0x0008   // enable SIM clock
+#define SIM_CONF1_RSVD        0x0010   // reserved
+#define SIM_CONF1_SCLKDIV	  0x0020   // SIM clock frquency
+#define SIM_CONF1_SCLKLEV	  0x0040   // SIM clock idle level
+#define SIM_CONF1_ETU	      0x0080   // ETU period
+#define SIM_CONF1_BYPASS      0x0100   // bypass hardware timers
+#define SIM_CONF1_SVCCLEV     0x0200
+#define SIM_CONF1_SRSTLEV     0x0400
+#define SIM_CONF1_SIOLOW      0x8000   //force SIO to low level	 
+
+// interrupt status register
+#define SIM_IT_NATR           0x0001   // No answer to reset
+#define SIM_IT_WT             0x0002
+#define SIM_IT_ITOV           0x0004   
+#define SIM_IT_ITTX           0x0008   // Transmit
+#define SIM_IT_ITRX           0x0010   // Receipt
+
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  #define SIM_IT_CD             0x0001   // Card insertion/extraction
+#else
+  #define SIM_IT_CD             0x0020   // Card insertion/extraction
+#endif
+
+// interrupt mask register
+#define SIM_MASK_NATR         0x0001   // No answer to reset
+#define SIM_MASK_WT           0x0002
+#define SIM_MASK_OV           0x0004
+#define SIM_MASK_TX           0x0008   // Transmit
+#define SIM_MASK_RX           0x0010   // Receipt
+#define SIM_MASK_CD           0x0020   // Card insertion/extraction	
+
+// receveid byte register
+#define SIM_DRX_STATRXPAR     0x0100   // received byte parity status
+
+// SIM return code OK
+#define SIM_OK                  0
+
+// SIM return error codes
+#define SIM_ERR_NOCARD          1
+#define SIM_ERR_NOINT           2
+#define SIM_ERR_NATR            3
+#define SIM_ERR_READ            4
+#define SIM_ERR_XMIT            5
+#define SIM_ERR_OVF             6
+#define SIM_ERR_LEN             7
+#define SIM_ERR_CARDREJECT      8
+#define SIM_ERR_WAIT            9
+#define SIM_ERR_ABNORMAL_CASE1 10
+#define SIM_ERR_ABNORMAL_CASE2 11
+#define SIM_ERR_BUFF_OVERFL    12
+
+// begin of JYT modifications
+#define SIM_ERR_HARDWARE_FAIL  13
+// end of JYT modifications
+#define SIM_ERR_RETRY_FAILURE  14
+
+#define SIM_SLEEP_NONE         0	// No SIM available 
+#define SIM_SLEEP_DESACT       1	// The Driver is NOT currently in sleep mode (clock is off)
+#define SIM_SLEEP_ACT          2	// The Driver is currently in sleep mode (clock is on)
+#define SIM_SLEEP_NOT_ALLOWED  3	// The Driver cannot stop the clock :
+									// The card don't want or the interface is not able
+									// to do it.
+#define SIM_SLEEP_WAITING_TIME 500 //represent 2.3s of period before entering in sleep mode
+
+#define SIM_CLK_STOP_MASK		0x0D	// Clock Stop mask defined by ETSI 11.11 
+#define SIM_CLK_STOP_NOT_ALLWD	0x00	// see ETSI 11.11 : Clock Stop never allowed
+#define SIM_CLK_STOP_ALLWD		0x01	// see ETSI 11.11 : No prefered level
+#define SIM_CLK_STOP_HIGH		0x04	// see ETSI 11.11 : High level only
+#define SIM_CLK_STOP_LOW		0x08	// see ETSI 11.11 : Low level only
+
+#if(ANALOG == 1)
+  //OMEGA specific definitions
+  #define MODE5V_OMEGA         0x06 // used in SIM_SwitchVolt
+  #define MODE_INIT_OMEGA_3V   0x05 // used in SIM_StartVolt
+  #define MODE_INIT_OMEGA_5V   0x07 // unused !!!!
+  #define MODE3V_OMEGA         0x01 // unused !!!!
+  #define MODE_DIS_SIMLDOEN    0xDF // used in SIM_PowerOff
+  #define MODE_DIS_SIMEN       0xFD // used in SIM_PowerOff
+  #define MODE_ENA_SIMLDOEN    0x20 // used in SIM_ManualStart
+  #define MODE_ENA_SIMEN       0x02 // used in SIM_ManualStart
+#elif(ANALOG == 2)
+   //IOTA specific definitions
+   #define MODE1_8V_IOTA        0x00 
+   #define MODE_INIT_IOTA_3V    0x03
+   #define MODE_INIT_IOTA_1_8V  0x02 
+   #define MODE3V_IOTA          0x01
+   #define MODE_DIS_SIMLDOEN    0xFC // SIMSEL + Regulator RSIMEN
+   #define MODE_DIS_SIMEN       0xF7
+   #define MODE_ENA_SIMLDOEN    0x03 // SIMSEL + Regulator RSIMEN
+   #define MODE_ENA_SIMEN       0x08
+#elif(ANALOG == 3)
+   //SYREN specific definitions
+   #define MODE1_8V_SYREN        0x00 
+   #define MODE_INIT_SYREN_3V    0x03
+   #define MODE_INIT_SYREN_1_8V  0x02 
+   #define MODE3V_SYREN          0x01
+   #define MODE_DIS_SIMLDOEN     0x1FC // SIMSEL + Regulator RSIMEN
+   #define MODE_DIS_SIMEN        0x1F7
+   #define MODE_ENA_SIMLDOEN     0x03 // SIMSEL + Regulator RSIMEN
+   #define MODE_ENA_SIMEN        0x08
+#endif
+
+// define type of interface if not defined
+// 5V only ME         SIM_TYPE = 0
+// 3V technology ME   SIM_TYPE = 1
+// 3V only ME         SIM_TYPE = 2
+// 1.8V technology ME SIM_TYPE = 3 // JYT, 29/01/02, from new specs IOTA
+// 1.8V Only ME       SIM_TYPE = 4 // JYT, 29/01/02, from new specs IOTA
+
+#define SIM_TYPE_5V    0
+#define SIM_TYPE_3_5V  1
+#define SIM_TYPE_3V    2
+#define SIM_TYPE_1_8_3V 3
+#define SIM_TYPE_1_8V   4
+
+//default configuration
+#ifndef SIM_TYPE
+#if((ANALOG == 2) || (ANALOG == 3))
+// Until now (20/03/2003), it is impossible to test IOTA or SYREN with 1.8V Sim Card,
+// so SIM drv is configured in 3V only with IOTA.and SYREN
+// When 1.8V Sim Card will be delivered and tested on IOTA and SYREN, then Sim driver will pass 
+// to : #define SIM_TYPE       SIM_TYPE_1_8_3V   
+#define SIM_TYPE       SIM_TYPE_3V   
+#else
+#define SIM_TYPE       SIM_TYPE_3_5V   
+#endif
+#endif
+
+// begin of modifications of JYT
+
+#if((ANALOG == 2) || (ANALOG == 3))
+#define SIM_MASK_INFO_VOLT    0x70  
+#else
+#define SIM_MASK_INFO_VOLT    0x10
+#endif
+
+#define SIM_1_8V              0x30
+#define SIM_3V                0x10  
+#define SIM_5V                0x00
+
+// end of modifications of JYT
+
+// Max size of Answer to Reset (GSM11.11 5.7.1)
+#define MAX_ATR_SIZE          33
+
+// GSM Instruction Class (GSM 11.11 SIM spec)
+#define GSM_CLASS  0xA0
+
+// SIM Instruction Codes
+#define SIM_SELECT              0xA4    
+#define SIM_STATUS              0xF2    
+#define SIM_READ_BINARY         0xB0    
+#define SIM_UPDATE_BINARY       0xD6    
+#define SIM_READ_RECORD         0xB2    
+#define SIM_UPDATE_RECORD       0xDC    
+#define SIM_SEEK                0xA2    
+#define SIM_INCREASE            0x32    
+#define SIM_VERIFY_CHV          0x20    
+#define SIM_CHANGE_CHV          0x24    
+#define SIM_DISABLE_CHV         0x26    
+#define SIM_ENABLE_CHV          0x28    
+#define SIM_UNBLOCK_CHV         0x2C    
+#define SIM_INVALIDATE          0x04    
+#define SIM_REHABILITATE        0x44    
+#define SIM_RUN_GSM_ALGO        0x88    
+#define SIM_GET_RESPONSE        0xC0 
+#define SIM_TERMINAL_PROFILE   	0x10
+#define SIM_FETCH   			0x12
+#define SIM_TERMINAL_RESPONSE   0x14
+#define SIM_ENVELOPE   			0xC2
+
+
+
+// SIM file identifiers
+#define MF                 0x3F00
+#define EF_ICCID           0x2FE2
+#define DF_GSM             0x7F20
+#define DF_DCS1800         0x7F21
+#define EF_LP              0x6F05
+#define EF_IMSI            0x6F07
+#define EF_KC              0x6F20
+#define EF_PLMNSEL         0x6F30
+#define EF_HPLMN           0x6F31
+#define EF_ACMAX           0x6F37
+#define EF_SST             0x6F38
+#define EF_ACM             0x6F39
+#define EF_PUCT            0x6F41
+#define EF_CBMI            0x6F45
+#define EF_BCCH            0x6F74
+#define EF_ACC             0x6F78
+#define EF_FPLMN           0x6F7B
+#define EF_LOCI            0x6F7E
+#define EF_AD              0x6FAD
+#define EF_PHASE           0x6FAE
+#define DF_TELECOM         0x7F10
+#define EF_ADN             0x6F3A
+#define EF_FDN             0x6F3B
+#define EF_SMS             0x6F3C
+#define EF_CCP             0x6F3D
+#define EF_MSISDN          0x6F40
+#define EF_SMSP            0x6F42
+#define EF_SMSS            0x6F43
+#define EF_LND             0x6F44
+#define EF_EXT1            0x6F4A
+#define EF_EXT2            0x6F4B
+#define EF_ECC             0x6FB7
+
+
+#define MASK_INS           0xFE
+#define MASK_CMD           0x11
+#define MASK_RST           0x10  
+
+
+// Buffer sizes
+#define RSIMBUFSIZE  256
+#define RSIZESW1SW2  2 
+#define XSIMBUFSIZE  256
+
+// Structures
+typedef struct
+{
+   volatile unsigned short cmd;
+   volatile unsigned short stat;
+   volatile unsigned short conf1;
+   volatile unsigned short conf2;
+   volatile unsigned short it;
+   volatile unsigned short rx;
+   volatile unsigned short tx;
+   volatile unsigned short maskit;
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+   volatile unsigned short it_cd;
+#endif
+} SIM_CONTROLLER;  
+
+
+typedef struct
+{
+    SIM_CONTROLLER      *c;
+    SYS_UWORD8          *xIn;            // xmit input pointer
+    SYS_UWORD8          *xOut;           // xmit output pointer
+    unsigned            errorSIM;          // code return in case of error detectd
+    unsigned short      conf1; // image of the configuration register - avoids read/mod/write cycles	
+    volatile unsigned short txParityErr;
+    unsigned short		rxParityErr;	// if 0 no parity error on receipt, 1 if...
+    SYS_UWORD8          Freq_Algo;              //use to determine which sim clk freq to choose for running GSM algo
+    SYS_UWORD8          PTS_Try;                //use to calculate how many PTS try were already done
+    SYS_UWORD8          FileC;                  //value of File Characteristic
+    SYS_UWORD16         etu9600;
+    SYS_UWORD16         etu400;
+    SYS_UWORD16         startclock;             //744 clock cycle translated in ETU
+    SYS_UWORD16         stopclock;              //1860 clock cycle translated in ETU
+    SYS_UWORD8          moderx;                  //inform that we are in receive mode
+                                        // 0 : mode of normal reception without procedure
+                                        // 1 : mode of wait for acknowledge during reception of char
+                                        // 2 : mode of reception of data by bloc
+                                        // 3 : mode of reception of data char by char (proc char)
+                                        // 4 : mode of reception of data char by char (data)                                       
+                                        // 5 : mode of reception of procedure char SW1/SW2
+                                        // 6 : mode of wait for acknowledge char after transmission of char
+    SYS_UWORD16       expected_data;          //number of expected char in receive mode proc char
+    SYS_UWORD8        ack;                    //acknowledge char
+    SYS_UWORD8        null_received;          //indicates if a NULL char was received
+    SYS_UWORD8        hw_mask;		          //mask used because of pole112 hw prb
+
+    SYS_UWORD8        rbuf[RSIMBUFSIZE];
+    SYS_UWORD8        rx_index;                   // receive index on rbuf buffer
+
+    SYS_UWORD8        xbuf[XSIMBUFSIZE];
+    SYS_UWORD8        rSW12[RSIZESW1SW2];          //buffer to store SW1 and SW2
+    SYS_UWORD8        SWcount;                     //static counter
+
+    void (*InsertFunc)(void);
+    void (*RemoveFunc)(void);
+}
+SIM_PORT;
+
+typedef struct
+{
+    SYS_UWORD8    Inverse;
+    SYS_UWORD8    AtrSize;
+    SYS_UWORD8    AtrData[MAX_ATR_SIZE];
+} SIM_CARD;
+
+
+/*
+ * Prototypes
+ */ 
+void        SIM_IntHandler(void);
+#if ((CHIPSET == 4) || (CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
+  void SIM_CD_IntHandler(void);
+#endif
+void        SIM_WriteBuffer(SIM_PORT *p, SYS_UWORD16 offset, SYS_UWORD16 n);
+SYS_UWORD16 SIM_Command(SIM_PORT *p, SYS_UWORD16 n, SYS_UWORD8 *rP, SYS_UWORD8 *lP);
+SYS_UWORD16 SIM_Dummy(void);
+void        SIM_InitLog(void);
+
+void        SIM_Init(void (Insert(void)), void (Remove(void)));
+void        SIM_Initialize(void);
+SYS_UWORD16 SIM_Register(void (Insert(void)), void (Remove(void)));
+SYS_UWORD16 SIM_Reset(SIM_CARD *c);
+
+SYS_UWORD16 SIM_Select(SYS_UWORD16 id, SYS_UWORD8 *dat, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_Status(SYS_UWORD8 *dat, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_ReadBinary(SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD8 len, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_UpdateBinary(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD16 offset, SYS_UWORD8 len, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_ReadRecord(SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD8 len, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_UpdateRecord(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 recNum, SYS_UWORD8 len, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_Seek(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 mode, SYS_UWORD8 len, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_Increase(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 *size);
+
+// Authentication
+SYS_UWORD16 SIM_VerifyCHV(SYS_UWORD8 *result, SYS_UWORD8 *chv, SYS_UWORD8 chvType, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_ChangeCHV(SYS_UWORD8 *result,SYS_UWORD8 *oldChv, SYS_UWORD8 *newChv, SYS_UWORD8 chvType, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_DisableCHV(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_EnableCHV(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_UnblockCHV(SYS_UWORD8 *result, SYS_UWORD8 *unblockChv, SYS_UWORD8 *newChv, SYS_UWORD8 chvType, SYS_UWORD8 *size);
+
+SYS_UWORD16 SIM_Invalidate(SYS_UWORD8 *rP, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_Rehabilitate(SYS_UWORD8 *rP, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_RunGSMAlgo(SYS_UWORD8 *result, SYS_UWORD8 *rand, SYS_UWORD8 *size);
+SYS_UWORD16 SIM_GetResponse(SYS_UWORD8 *dat, SYS_UWORD8 len, SYS_UWORD8 *size);
+
+SYS_UWORD16 SIM_TxParityErrors();
+
+SYS_UWORD16 SIM_TerminalProfile(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 len, SYS_UWORD8 *rcvSize);
+SYS_UWORD16 SIM_Fetch(SYS_UWORD8 *result, SYS_UWORD8 len, SYS_UWORD8 *rcvSize);
+SYS_UWORD16 SIM_TerminalResponse(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 len, SYS_UWORD8 *rcvSize);
+SYS_UWORD16 SIM_Envelope(SYS_UWORD8 *result, SYS_UWORD8 *dat, SYS_UWORD8 len, SYS_UWORD8 *rcvSize);
+
+
+SYS_UWORD16  SIM_WaitReception(SIM_PORT *p);
+void         SIM_PowerOff(void);
+void         SIM_Interpret_FileCharacteristics(SIM_PORT *p);
+SYS_UWORD16  SIM_PTSprocedure(SIM_CARD *cP, SIM_PORT *p);
+void         SIM_WARMReset (SIM_PORT *p);
+void	     SIM_SleepMode_In(SYS_UWORD32 param);
+void	     SIM_SleepMode_Out(SIM_PORT *p);
+SYS_UWORD8 	 SIM_GetFileCharacteristics(SIM_PORT *p);
+SYS_UWORD16  SIM_ATRdynamictreatement (SIM_PORT *p, SIM_CARD *c);
+SYS_UWORD16  SIM_Waitforchars (SIM_PORT *p, SYS_UWORD16 max_wait);
+void         SIM_Calcetu (SIM_PORT *p);
+SYS_UWORD8   SIM_Translate_atr_char (SYS_UWORD8 input, SIM_CARD *cP);
+
+
+SYS_UWORD8   SIM_StartVolt (void);
+SYS_UWORD8   SIM_SwitchVolt (void);
+
+SYS_UWORD16  SIM_ManualStart (SIM_PORT *p);
+SYS_UWORD8   SIM_Memcpy(SYS_UWORD8 *Buff_target, SYS_UWORD8 Buff_source[], SYS_UWORD8 len);
+SYS_BOOL     SIM_SleepStatus(void);
+
+/*
+ * Global variables
+ */ 
+#ifdef SIM_C
+#define SI_GLOBAL 
+#else
+#define SI_GLOBAL extern
+#endif
+
+
+SI_GLOBAL SIM_PORT   Sim[1]; 
+SI_GLOBAL NU_TIMER   SIM_timer;  
+SI_GLOBAL STATUS     status_os_sim;
+SI_GLOBAL SYS_UWORD8 SIM_sleep_status;
+
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/timer.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/timer.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,91 @@
+/*******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+   Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                  
+                                                           
+   Filename         : timer.h
+
+   Description      : timer.c header
+
+   Project          : drivers
+
+   Author           : pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number   : 1.3
+
+   Date and time    : 07/23/98 16:25:53
+   Previous delta   : 07/23/98 16:25:52
+
+   SCCS file        : /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release1.5/mod/emu/EMU_MCMP/eva3_drivers/source/SCCS/s.timer.h
+
+   Sccs Id  (SID)       : '@(#) timer.h 1.3 07/23/98 16:25:53 '
+
+ 
+*****************************************************************************/
+
+#include "../include/sys_types.h"
+
+#define TIMER_CNTL_REG  MEM_TIMER_ADDR      /* watchdog Control Timer register */
+ 
+#define TIMER_ST        0x0080       
+#define TIMER_AR        0x0100       
+#define TIMER_PTV       0x0e00   
+#define	TIMER_CNTL_MASK	0x0f80	 
+#define	TIMER_MODE_MASK	0x80ff	 
+
+
+#define TIMER_LOAD_REG  (MEM_TIMER_ADDR + 0x02)   /* Timer load register */ 
+#define TIMER_READ_REG  (MEM_TIMER_ADDR + 0x02)   /* Timer read register */ 
+
+
+#define TIMER_MODE_REG  (MEM_TIMER_ADDR + 0x04)   /* Timer mode register */ 
+#define TIMER_WDOG      0x8000          /* watch dog */
+
+#define START_STOP      1           /*to start or stop a timer */
+#define AR              0x0002       
+#define PTV             0x001c 
+#define TIMER_CLK_EN    0x0020
+
+
+#define TIMER1_CNTL         (MEM_TIMER1 + 0x00)
+#define TIMER1_LOAD_TIM     (MEM_TIMER1 + 0x02)
+#define TIMER1_READ_TIM     (MEM_TIMER1 + 0x04)
+#define TIMER2_CNTL         (MEM_TIMER2 + 0x00)
+#define TIMER2_LOAD_TIM     (MEM_TIMER2 + 0x02)
+#define TIMER2_READ_TIM     (MEM_TIMER2 + 0x04)
+
+
+/*---------------------------------------------------------------/
+/*   TIMER_START_STOP ()						*/
+/*--------------------------------------------------------------*/
+/* Parameters : start or stop command	 			*/
+/* Return     :	none						*/
+/* Functionality : Start or Stop the timer  			*/
+/*--------------------------------------------------------------*/
+#define TIMER_START_STOP(startStop) ((startStop) ? ((* (volatile SYS_UWORD16 *) TIMER_CNTL_REG) |=  TIMER_ST) : \
+((* (volatile SYS_UWORD16 *) TIMER_CNTL_REG) &= ~TIMER_ST))
+
+
+/* Prototype of the functions */
+
+void        TM_ResetTimer (SYS_UWORD16 timerNum, SYS_UWORD16 countValue,
+                           SYS_UWORD16 autoReload, SYS_UWORD16 clockScale);
+void        TM_StopTimer (int timerNum);
+void        TM_StartTimer (int timerNum);
+SYS_UWORD16      TM_ReadTimer (int timerNum);
+
+void        TM_DisableWatchdog(void);
+void        TM_EnableWatchdog(void);
+void        TM_ResetWatchdog(SYS_UWORD16 cnt);
+void        TM_EnableTimer (int timerNum);
+void        TM_DisableTimer (int timerNum);
+
+SYS_UWORD16 TIMER_Read (unsigned short);
+inline unsigned short TIMER_WriteValue (SYS_UWORD16);
+inline unsigned short TIMER_ReadValue (void);
+
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/timer1.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/timer1.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,75 @@
+/*******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+  Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                 
+                                                           
+   Filename       	: timer1.h
+
+   Description    	:TIMER1 
+
+   Project        	: drivers
+
+   Author         	: pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.7
+
+   Date and time	: 02/15/01 15:47:06
+
+   Previous delta 	: 02/15/01 15:47:06
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED/drivers1/common/SCCS/s.timer1.h
+
+   Sccs Id  (SID)       : '@(#) timer1.h 1.7 02/15/01 15:47:06 '
+
+ 
+*****************************************************************************/
+
+#include "../include/sys_types.h"
+
+/**** DIONE TIMERs configuration register ****/
+
+#define D_TIMER_ADDR        0xfffe3800
+
+#define D_TIMER_CNTL_MASK	0x001f
+
+#define CNTL_D_TIMER_OFFSET	0x0000
+#define LOAD_D_TIMER_OFFSET	0x0002
+#define READ_D_TIMER_OFFSET	0x0004
+
+#define D_TIMER_CNTL		(D_TIMER_ADDR+CNTL_D_TIMER_OFFSET)
+#define D_TIMER_LOAD		(D_TIMER_ADDR+LOAD_D_TIMER_OFFSET)
+#define D_TIMER_READ		(D_TIMER_ADDR+READ_D_TIMER_OFFSET)
+
+#define D_TIMER_ST		0x0001		/* bit 0 */
+#define D_TIMER_AR		0x0002		/* bit 1 */
+#define D_TIMER_PTV		0x001c		/* bits 4:2 */
+#define D_TIMER_CLK_EN		0x0020		/* bit 5  */
+#define D_TIMER_RUN		0x0021		/* bit 5 ,0 */
+
+#define LOAD_TIM		0xffff		/* bits 15:0 */
+
+
+
+
+
+/* ----- Prototypes ----- */
+SYS_UWORD16 Dtimer1_Get_cntlreg(void);
+
+void Dtimer1_AR(SYS_UWORD16 Ar);
+
+void Dtimer1_PTV(SYS_UWORD16 Ptv);
+
+void Dtimer1_Clken(SYS_UWORD16 En);
+
+void  Dtimer1_Start (SYS_UWORD16 startStop);
+
+void Dtimer1_Init_cntl (SYS_UWORD16 St, SYS_UWORD16 Reload, SYS_UWORD16 clockScale, SYS_UWORD16 clkon);
+
+SYS_UWORD16 Dtimer1_WriteValue (SYS_UWORD16 value);
+
+SYS_UWORD16 Dtimer1_ReadValue (void);
diff -r f459043fae0c -r 45911ad957fd nuc-fw/bsp/timer2.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/timer2.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,76 @@
+/*******************************************************************************
+            TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION           
+                                                                             
+  Property of Texas Instruments -- For  Unrestricted  Internal  Use  Only 
+   Unauthorized reproduction and/or distribution is strictly prohibited.  This 
+   product  is  protected  under  copyright  law  and  trade  secret law as an 
+   unpublished work.  Created 1987, (C) Copyright 1997 Texas Instruments.  All 
+   rights reserved.                                                            
+                 
+                                                           
+   Filename       	: timer2.h
+
+   Description    	:TIMER1 
+
+   Project        	: drivers
+
+   Author         	: pmonteil@tif.ti.com  Patrice Monteil.
+
+   Version number	: 1.4
+
+   Date and time	: 02/15/01 15:47:05
+
+   Previous delta 	: 02/15/01 15:47:05
+
+   SCCS file      	: /db/gsm_asp/db_ht96/dsp_0/gsw/rel_0/mcu_l1/release_gprs/mod/emu_p/EMU_P_FRED/drivers1/common/SCCS/s.timer2.h
+
+   Sccs Id  (SID)       : '@(#) timer2.h 1.4 02/15/01 15:47:05 '
+
+
+ 
+*****************************************************************************/
+
+#include "../include/sys_types.h"
+
+/**** DIONE TIMERs configuration register ****/
+
+#define D_TIMER_ADDR        0xfffe6800
+
+#define D_TIMER_CNTL_MASK	0x001f
+
+#define CNTL_D_TIMER_OFFSET	0x0000
+#define LOAD_D_TIMER_OFFSET	0x0002
+#define READ_D_TIMER_OFFSET	0x0004
+
+#define D_TIMER_CNTL		(D_TIMER_ADDR+CNTL_D_TIMER_OFFSET)
+#define D_TIMER_LOAD		(D_TIMER_ADDR+LOAD_D_TIMER_OFFSET)
+#define D_TIMER_READ		(D_TIMER_ADDR+READ_D_TIMER_OFFSET)
+
+#define D_TIMER_ST		0x0001		/* bit 0 */
+#define D_TIMER_AR		0x0002		/* bit 1 */
+#define D_TIMER_PTV		0x001c		/* bits 4:2 */
+#define D_TIMER_CLK_EN		0x0020		/* bit 5  */
+#define D_TIMER_RUN		0x0021		/* bit 5 ,0 */
+
+#define LOAD_TIM		0xffff		/* bits 15:0 */
+
+
+
+
+
+/* ----- Prototypes ----- */
+SYS_UWORD16 Dtimer2_Get_cntlreg(void);
+
+void Dtimer2_AR(SYS_UWORD16 Ar);
+
+void Dtimer2_PTV(SYS_UWORD16 Ptv);
+
+void Dtimer2_Clken(SYS_UWORD16 En);
+
+void  Dtimer2_Start (SYS_UWORD16 startStop);
+
+void Dtimer2_Init_cntl (SYS_UWORD16 St, SYS_UWORD16 Reload, SYS_UWORD16 clockScale, SYS_UWORD16 clkon);
+
+SYS_UWORD16 Dtimer2_WriteValue (SYS_UWORD16 value);
+
+SYS_UWORD16 Dtimer2_ReadValue (void);
diff -r f459043fae0c -r 45911ad957fd nuc-fw/cfgmagic/post-target
--- a/nuc-fw/cfgmagic/post-target	Sun Aug 25 21:20:20 2013 +0000
+++ b/nuc-fw/cfgmagic/post-target	Sat Aug 31 23:43:23 2013 +0000
@@ -65,17 +65,17 @@
 
 case "$ABB_type" in
 	Iota*)
-		ANLG_FAM=2
+		ANALOG=2
 		;;
 	Syren*)
-		ANLG_FAM=3
+		ANALOG=3
 		;;
 	*)
 		echo "Error: unknown ABB_type=$ABB_type" 1>&2
 		exit 1
 		;;
 esac
-export_to_c	ANLG_FAM
+export_to_c	ANALOG
 
 # Ensure that device_class is set - various feature configurations
 # will certainly depend on it.
diff -r f459043fae0c -r 45911ad957fd nuc-fw/include/sys_types.h
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/include/sys_types.h	Sat Aug 31 23:43:23 2013 +0000
@@ -0,0 +1,28 @@
+/**********************************************************
+ *        GSM/GPRS TI S/W software 
+ *
+ *        Filename sys_types.h
+ *
+ *
+ *	Redefine the types for the TI GSM/GPRS system software
+ *
+ **********************************************************/
+
+#ifndef __SYS_TYPES_H__
+#define __SYS_TYPES_H__
+
+typedef unsigned char  SYS_BOOL;
+
+typedef unsigned char  SYS_UWORD8;
+typedef signed   char  SYS_WORD8;
+
+typedef unsigned short SYS_UWORD16;
+typedef          short SYS_WORD16;
+
+typedef unsigned long  SYS_UWORD32;
+typedef          long  SYS_WORD32;
+
+
+typedef void           (*SYS_FUNC)(void);		/* pointer to a function */
+
+#endif /* __SYS_TYPES_H__ */
\ No newline at end of file