# HG changeset patch
# User Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
# Date 1383293003 0
# Node ID 8b0793c67f9f19a494fcf85d30a921480f939c5f
# Parent  7d7950d7f924b583766bdd96000bd31a80bf9454
nuc-fw: final preparations for the big transition

diff -r 7d7950d7f924 -r 8b0793c67f9f nuc-fw/bsp/Makefile
--- a/nuc-fw/bsp/Makefile	Fri Nov 01 06:13:58 2013 +0000
+++ b/nuc-fw/bsp/Makefile	Fri Nov 01 08:03:23 2013 +0000
@@ -7,8 +7,8 @@
 
 XTOBJS=	armio.o clkm.o init_target.o inth.o niq.o timer.o timer1.o timer2.o
 
-XOBJS=	${XTOBJS}
-AOBJS=	${IOBJS}
+XOBJS=	${XTOBJS} oldint.o
+AOBJS=	${IOBJS} oldint.o
 
 HDRS=	armio.h clkm.h dma.h inth.h iq.h mem.h rhea_arm.h sim.h timer.h \
 	timer1.h timer2.h ulpd.h
diff -r 7d7950d7f924 -r 8b0793c67f9f nuc-fw/bsp/init_target.c
--- a/nuc-fw/bsp/init_target.c	Fri Nov 01 06:13:58 2013 +0000
+++ b/nuc-fw/bsp/init_target.c	Fri Nov 01 08:03:23 2013 +0000
@@ -67,6 +67,8 @@
       TM_SEC_DisableWatchdog();
     #endif
 
+    freecalypso_disable_bootrom_pll();
+
     #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15))
 
       /*
diff -r 7d7950d7f924 -r 8b0793c67f9f nuc-fw/bsp/oldint.S
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/bsp/oldint.S	Fri Nov 01 08:03:23 2013 +0000
@@ -0,0 +1,70 @@
+/*
+ * This module contains that part of TI's int.s (INT_Initialize) code
+ * which does some entry-point initialization of a few Calypso registers.
+ * The important part for us is getting rid of whatever PLL setup
+ * may have been done by the BootROM-based process that got us loaded
+ * and running - we need to do that before we can do our own setup.
+ */
+
+	.code 32
+	.text
+
+#define	CNTL_ARM_CLK_REG	0xFFFFFD00  // CNTL_ARM_CLK register address
+#define	DPLL_CNTRL_REG		0xFFFF9800  // DPLL control register address
+#define	EXTRA_CONTROL_REG	0xFFFFFB10  // Extra Control register CONF addr
+#define	MPU_CTL_REG		0xFFFFFF08  // MPU_CTL register address
+
+#define	CNTL_ARM_CLK_RST	0x1081      // Init of CNTL_ARM_CLK register
+
+                                            // Use DPLL, Divide by 1
+#define	DPLL_CONTROL_RST	0x2002      // Configure DPLL in default state
+#define	DISABLE_DU_MASK		0x0800      // Mask to Disable the DU module
+#define	ENABLE_DU_MASK		0xF7FF      // Mask to Enable the DU module
+#define	MPU_CTL_RST		0x0000      // Reset value of MPU_CTL register
+					    // - All protections disabled
+
+	.globl	freecalypso_disable_bootrom_pll
+freecalypso_disable_bootrom_pll:
+@
+@  Configure DPLL register with reset value
+@
+       ldr     r1,=DPLL_CNTRL_REG    @ Load address of DPLL register in R1
+       ldrh    r2,=DPLL_CONTROL_RST  @ Load DPLL reset value in R2
+       strh    r2,[r1]               @ Store DPLL reset value in DPLL register
+
+@
+@  Wait that DPLL goes in BYPASS mode
+@
+Wait_DPLL_Bypass:
+       ldr     r2,[r1]               @ Load DPLL register
+       and     r2,r2,#1              @ Perform a mask on bit 0
+       cmp     r2,#1                 @ Compare DPLL lock bit
+       beq     Wait_DPLL_Bypass      @ Wait Bypass mode (i.e. bit[0]='0')
+
+@
+@  Configure CNTL_ARM_CLK register with reset value: DPLL is used to
+@  generate ARM clock with division factor of 1.
+@
+       ldr     r1,=CNTL_ARM_CLK_REG  @ Load address of CNTL_ARM_CLK register in R1
+       ldrh    r2,=CNTL_ARM_CLK_RST  @ Load CNTL_ARM_CLK reset value in R2
+       strh    r2,[r1]               @ Store CNTL_ARM_CLK reset value in CNTL_ARM_CLK register
+
+@
+@  Disable/Enable the DU module by setting/resetting bit 11 to '1'/'0'
+@
+       ldr     r1,=EXTRA_CONTROL_REG @ Load address of Extra Control register CONF
+@      ldrh    r2,=DISABLE_DU_MASK   @ Load mask to write in Extra Control register CONF
+       ldrh    r2,=ENABLE_DU_MASK    @ Load mask to write in Extra Control register CONF
+       ldrh    r0,[r1]               @ Load Extra Control register CONF in r0
+@      orr     r0,r0,r2              @ Disable DU module
+       and     r0,r0,r2              @ Enable DU module
+       strh    r0,[r1]               @ Store configuration in Extra Control register CONF
+
+@
+@  Disable all MPU protections
+@
+       ldr     r1,=MPU_CTL_REG       @ Load address of MPU_CTL register
+       ldrh    r2,=MPU_CTL_RST       @ Load reset value of MPU_CTL register
+       strh    r2,[r1]               @ Store reset value of MPU_CTL register
+
+	bx	lr
diff -r 7d7950d7f924 -r 8b0793c67f9f nuc-fw/sysglue/Makefile
--- a/nuc-fw/sysglue/Makefile	Fri Nov 01 06:13:58 2013 +0000
+++ b/nuc-fw/sysglue/Makefile	Fri Nov 01 08:03:23 2013 +0000
@@ -1,9 +1,14 @@
 CC=	arm-elf-gcc
+CFLAGS=	-Os -fno-builtin -mthumb-interwork -mthumb
 ASFLAGS=-mthumb-interwork
+LD=	arm-elf-ld
 
-OBJS=	irqfiq.o sysinit.o
+OBJS=	appinit.o irqfiq.o sysinit.o
 
-all:	${OBJS}
+all:	xipcode.o
+
+xipcode.o:	${OBJS}
+	${LD} -r -o $@ ${OBJS}
 
 clean:
 	rm -f *.[oa] *errs
diff -r 7d7950d7f924 -r 8b0793c67f9f nuc-fw/sysglue/appinit.c
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/nuc-fw/sysglue/appinit.c	Fri Nov 01 08:03:23 2013 +0000
@@ -0,0 +1,36 @@
+/*
+ * This module contains our Application_Initialize() function,
+ * based on the disassembly of the binary object version in the
+ * Leonardo semi-src.
+ */
+
+#include "../include/config.h"
+
+Application_Initialize()
+{
+	Init_Target();
+	/*
+	 * The original version calls Init_Drivers() at this point,
+	 * but that function is nothing more than a short sequence
+	 * of calls to other functions, so I've inlined it.
+	 */
+#if 0
+	ABB_Sem_Create();
+	ffs_main_init();
+#endif
+	rvf_init();
+	rvm_init();
+	create_tasks();
+#if 0
+	SIM_Initialize();
+#endif
+	/* end of Init_Drivers() */
+#if CONFIG_GSM
+	Cust_Init_Layer1();
+#endif
+	Init_Serial_Flows();
+#if CONFIG_GSM
+	StartFrame();
+#endif
+	Init_Unmask_IT();
+}