# HG changeset patch
# User Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
# Date 1406911593 0
# Node ID de635895e0bef4431a977760da35b391935ecf72
# Parent  25a7fe25864c08a2bcff8506b8a0a6aa96168f90
gsm-fw/L1/include/*.h: s/ANLG_FAM/ANALOG/ in LoCosto-based version

diff -r 25a7fe25864c -r de635895e0be gsm-fw/L1/anlg-subst.ed
--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gsm-fw/L1/anlg-subst.ed	Fri Aug 01 16:46:33 2014 +0000
@@ -0,0 +1,2 @@
+1,$s/\<ANLG_FAM\>/ANALOG/g
+w
diff -r 25a7fe25864c -r de635895e0be gsm-fw/L1/include/l1_confg.h
--- a/gsm-fw/L1/include/l1_confg.h	Fri Aug 01 16:38:35 2014 +0000
+++ b/gsm-fw/L1/include/l1_confg.h	Fri Aug 01 16:46:33 2014 +0000
@@ -614,13 +614,13 @@
   //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
   //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
 
-  #if    (ANLG_FAM == 1)  // OMEGA / NAUSICA
+  #if    (ANALOG == 1)  // OMEGA / NAUSICA
     #define C_DSP_SW_WORK_AROUND 0x0006
 
-  #elif  (ANLG_FAM == 2)  // IOTA
+  #elif  (ANALOG == 2)  // IOTA
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANLG_FAM == 3)  // SYREN
+  #elif  (ANALOG == 3)  // SYREN
     #define C_DSP_SW_WORK_AROUND 0x000E
 
   #endif
@@ -712,13 +712,13 @@
   //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
   //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
   //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
-  #if    (ANLG_FAM == 1)  // OMEGA / NAUSICA
+  #if    (ANALOG == 1)  // OMEGA / NAUSICA
     #define C_DSP_SW_WORK_AROUND 0x0006
 
-  #elif  (ANLG_FAM == 2)  // IOTA
+  #elif  (ANALOG == 2)  // IOTA
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANLG_FAM == 3)  // SYREN
+  #elif  (ANALOG == 3)  // SYREN
     #define C_DSP_SW_WORK_AROUND 0x000E
 
   #endif
@@ -820,13 +820,13 @@
   //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
   //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
   //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
-  #if    (ANLG_FAM == 1)  // OMEGA / NAUSICA
+  #if    (ANALOG == 1)  // OMEGA / NAUSICA
     #define C_DSP_SW_WORK_AROUND 0x0006
 
-  #elif  (ANLG_FAM == 2)  // IOTA
+  #elif  (ANALOG == 2)  // IOTA
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANLG_FAM == 3)  // SYREN
+  #elif  (ANALOG == 3)  // SYREN
     #define C_DSP_SW_WORK_AROUND 0x000E
 
   #endif
@@ -933,16 +933,16 @@
   //  bit1 - DMA reset on critical DMA still running cases, refer to REQ01260.
   //  bit2 - Solve Read/Write BULDATA pointers Omega & Nausica issue, refer to BUG00650.
   //  bit3 - Solve IBUFPTRx reset IOTA issue, refer to BUG01911.
-  #if    (ANLG_FAM == 1)  // OMEGA / NAUSICA
+  #if    (ANALOG == 1)  // OMEGA / NAUSICA
     #define C_DSP_SW_WORK_AROUND 0x0006
 
-  #elif  (ANLG_FAM == 2)  // IOTA
+  #elif  (ANALOG == 2)  // IOTA
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANLG_FAM == 3)  // SYREN
+  #elif  (ANALOG == 3)  // SYREN
     #define C_DSP_SW_WORK_AROUND 0x000E
 
-  #elif  (ANLG_FAM == 11)  // TRITON
+  #elif  (ANALOG == 11)  // TRITON
     #define C_DSP_SW_WORK_AROUND 0x000E
 
   #endif
diff -r 25a7fe25864c -r de635895e0be gsm-fw/L1/include/l1_const.h
--- a/gsm-fw/L1/include/l1_const.h	Fri Aug 01 16:38:35 2014 +0000
+++ b/gsm-fw/L1/include/l1_const.h	Fri Aug 01 16:46:33 2014 +0000
@@ -1581,7 +1581,7 @@
 
 // "d_ctrl_abb" bits positions for conditionnal loading of abb registers.
 #define B_RAMP                   0
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
   #define B_BULRAMPDEL             3 // Note: this name is changed
   #define B_BULRAMPDEL2            2 // Note: this name is changed
   #define B_BULRAMPDEL_BIS         9
diff -r 25a7fe25864c -r de635895e0be gsm-fw/L1/include/l1_ctl.h
--- a/gsm-fw/L1/include/l1_ctl.h	Fri Aug 01 16:38:35 2014 +0000
+++ b/gsm-fw/L1/include/l1_ctl.h	Fri Aug 01 16:46:33 2014 +0000
@@ -86,7 +86,7 @@
   #define  ALGO_AFC_KALMAN_PREDICTOR 3 // Kalman filter + rgap predictor
 #endif
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
    // clipping related to AFC DAC linearity range
   #define  C_max_step        32000   //   4000 * 2**3
   #define  C_min_step       -32000   //  -4000 * 2**3
diff -r 25a7fe25864c -r de635895e0be gsm-fw/L1/include/l1_defty.h
--- a/gsm-fw/L1/include/l1_defty.h	Fri Aug 01 16:38:35 2014 +0000
+++ b/gsm-fw/L1/include/l1_defty.h	Fri Aug 01 16:46:33 2014 +0000
@@ -498,7 +498,7 @@
                              //        bit [12.13] -> b_tch_loop,     tch loops A/B/C.
   API hole;               // 0x080A (10) unused hole.
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
   API d_ctrl_abb;         // 0x080B (11) Bit field indicating the analog baseband register to send.
                              //        bit [0]     -> b_ramp: the ramp information(a_ramp[]) is located in NDB
                              //        bit [1.2]   -> unused
@@ -1396,9 +1396,9 @@
     API d_dai_onoff;
     API d_auxdac;
 
-  #if (ANLG_FAM == 1)
+  #if (ANALOG == 1)
     API d_vbctrl;
-  #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+  #elif ((ANALOG == 2) || (ANALOG == 3))
     API d_vbctrl1;
   #endif
 
@@ -1504,7 +1504,7 @@
     API d_gea_mode_ovly;
     API a_gea_kc_ovly[4];
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
     // SYREN specific registers
     API d_vbpop;
     API d_vau_delay_init;
@@ -1513,7 +1513,7 @@
     API d_vaus_vol;
     API d_vaud_pll;
     API d_togbr2;
-#elif ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+#elif ((ANALOG == 1) || (ANALOG == 2))
     API d_hole3_ndb[7];
 #endif
 
@@ -1863,9 +1863,9 @@
     API d_dai_onoff;
     API d_auxdac;
 
-  #if (ANLG_FAM == 1)
+  #if (ANALOG == 1)
     API d_vbctrl;
-  #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+  #elif ((ANALOG == 2) || (ANALOG == 3))
     API d_vbctrl1;
   #endif
 
@@ -2124,7 +2124,7 @@
                             //   bit [2]     -> b_dtx.
 
   // OMEGA...........................(MCU -> DSP).
-  #if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+  #if ((ANALOG == 1) || (ANALOG == 2))
     API a_ramp[16];
     #if (MELODY_E1)
       API d_melo_osc_used;
@@ -2182,9 +2182,9 @@
     API d_dai_onoff;
     API d_auxdac;
 
-    #if (ANLG_FAM == 1)
+    #if (ANALOG == 1)
       API d_vbctrl;
-    #elif (ANLG_FAM == 2)
+    #elif (ANALOG == 2)
       API d_vbctrl1;
     #endif
 
@@ -2354,7 +2354,7 @@
 
   // OMEGA...........................(MCU -> DSP).
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+#if ((ANALOG == 1) || (ANALOG == 2))
   API a_ramp[16];
   #if (MELODY_E1)
     API d_melo_osc_used;
@@ -2410,9 +2410,9 @@
   API d_bulqoff;
   API d_dai_onoff;
   API d_auxdac;
-  #if (ANLG_FAM == 1)
+  #if (ANALOG == 1)
     API d_vbctrl;
-  #elif (ANLG_FAM == 2)
+  #elif (ANALOG == 2)
     API d_vbctrl1;
   #endif
   API d_bbctrl;
@@ -3593,7 +3593,7 @@
   T_L1S_AUDIO_ONOFF_MANAGER audio_on_off_ctl;
 #endif
 
-#if (ANLG_FAM == 11)
+#if (ANALOG == 11)
 UWORD8 abb_write_done;
 #endif
 UWORD8 tcr_prog_done;
@@ -4165,7 +4165,7 @@
     BOOL     dco_enabled;
   #endif
 
-  #if (ANLG_FAM == 1)
+  #if (ANALOG == 1)
     UWORD16 debug1;
     UWORD16 afcctladd;
     UWORD16 vbuctrl;
@@ -4179,7 +4179,7 @@
     UWORD16 vbctrl;
     UWORD16 apcdel1;
   #endif
-  #if (ANLG_FAM == 2)
+  #if (ANALOG == 2)
     UWORD16 debug1;
     UWORD16 afcctladd;
     UWORD16 vbuctrl;
@@ -4196,7 +4196,7 @@
     UWORD16 apcdel1;
     UWORD16 apcdel2;
   #endif
-  #if (ANLG_FAM == 3)
+  #if (ANALOG == 3)
     UWORD16 debug1;
     UWORD16 afcctladd;
     UWORD16 vbuctrl;
@@ -4219,7 +4219,7 @@
     UWORD16 vaus_vol;
     UWORD16 vaud_pll;
   #endif
-  #if (ANLG_FAM == 11)
+  #if (ANALOG == 11)
     UWORD8 vulgain;
     UWORD8 vdlgain;
     UWORD8 sidetone;
diff -r 25a7fe25864c -r de635895e0be gsm-fw/L1/include/l1_proto.h
--- a/gsm-fw/L1/include/l1_proto.h	Fri Aug 01 16:38:35 2014 +0000
+++ b/gsm-fw/L1/include/l1_proto.h	Fri Aug 01 16:46:33 2014 +0000
@@ -150,7 +150,7 @@
 /* prototypes of L1_FUNC functions    */
 /**************************************/
 void            dsp_power_on                (void);
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
    void         l1_abb_power_on              (void);
 #endif
 void            tpu_init                    (void);
@@ -656,7 +656,7 @@
 WORD8 l1ctl_encode_delta1  (UWORD16 radio_freq);
 WORD8 l1ctl_encode_delta2  (UWORD16 radio_freq);
 void Cust_get_ramp_tab     (API *a_ramp, UWORD8 txpwr_ramp_up, UWORD8 txpwr_ramp_down, UWORD16 radio_freq);
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (RF_FAM == 61))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (RF_FAM == 61))
   UWORD16 Cust_get_pwr_data(UWORD8 txpwr, UWORD16 radio_freq
   										  #if(REL99 && FF_PRF)
   										  ,UWORD8 number_uplink_timeslot
diff -r 25a7fe25864c -r de635895e0be gsm-fw/L1/include/l1_time.h
--- a/gsm-fw/L1/include/l1_time.h	Fri Aug 01 16:38:35 2014 +0000
+++ b/gsm-fw/L1/include/l1_time.h	Fri Aug 01 16:46:33 2014 +0000
@@ -170,7 +170,7 @@
 #if (CODE_VERSION==SIMULATION)
   #define TULSET_DURATION    ( 16L )                                                 // Uplink power on setup time
   #define BULRUDEL_DURATION  ( 2L )
-  #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3) || (ANLG_FAM == 11))
+  #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG == 11))
      // 16 qbits are added because the Calibration time is reduced of 4 GSM bit
      // due to a slow APC ramp of OMEGA (Cf. START_TX_NB)
      #define UL_VEGA_DELAY      ( TULSET_DURATION + BULRUDEL_DURATION +16L )         // = 18qbits, TX Vega delay