FreeCalypso > hg > freecalypso-sw

changeset 152:26472940e5b0

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l1_rf<N>.h headers preened
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Sun, 17 Nov 2013 04:59:55 +0000
parents d0de2d0a426d
children 65efffcb28dc
files gsm-fw/L1/cust0/l1_rf10.h gsm-fw/L1/cust0/l1_rf12.h gsm-fw/L1/cust0/l1_rf2.h gsm-fw/L1/cust0/l1_rf35.h gsm-fw/L1/cust0/l1_rf8.h gsm-fw/bsp/abb+spi/abb.c
diffstat 6 files changed, 74 insertions(+), 74 deletions(-) [+]
line wrap: on
line diff
--- a/gsm-fw/L1/cust0/l1_rf10.h	Sun Nov 17 04:50:45 2013 +0000
+++ b/gsm-fw/L1/cust0/l1_rf10.h	Sun Nov 17 04:59:55 2013 +0000
@@ -73,7 +73,7 @@
 /* Fixed TXPWR value when GSM management is disabled. */
 /******************************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
 //  #define FIXED_TXPWR       ((0xFC<<6) | AUXAPC | FALSE)            // TXPWR=10, value=252
 //  #define FIXED_TXPWR       ((0x65<<6) | AUXAPC | FALSE)  
   #define FIXED_TXPWR       ((0x74<<6) | AUXAPC | FALSE)            // TXPWR=15
@@ -86,22 +86,22 @@
 #define  UL_DELAY_1RF     5                                         // time spent in the first  uplink RF block
 #define  UL_DELAY_2RF     0                                         // time spent in the second uplink RF block
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   #define  UL_ABB_DELAY   6                                         // modulator input to output delay
 #endif
 
-#if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 2) || (ANALOG == 3))
   #define  UL_ABB_DELAY   3                                         // modulator input to output delay
 #endif
 
 /************************************/
 /* TX Propagation delay...          */
 /************************************/
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   #define  PRG_TX       (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY)       // = 40
 #endif
 
-#if (ANLG_FAM == 2) || (ANLG_FAM == 3)
+#if (ANALOG == 2) || (ANALOG == 3)
   #define  PRG_TX       (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY + 2)   // = 42
 #endif
 
@@ -109,13 +109,13 @@
 /* Initial value for APC DELAY      */
 /************************************/
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
 //#define APCDEL_DOWN     (32 - GUARD_BITS*4)                       // minimum value: 2
   #define APCDEL_DOWN      2                                        // minimum value: 2
   #define APCDEL_UP       (6+5)                                     // minimum value: 6
 #endif
 
-#if (ANLG_FAM == 2) || (ANLG_FAM == 3)
+#if (ANALOG == 2) || (ANALOG == 3)
 //#define APCDEL_DOWN     (32 - GUARD_BITS*4)                       // minimum value: 2
   #define APCDEL_DOWN     (2+0)                                     // minimum value: 2
   #define APCDEL_UP       (6+8)                                     // minimum value: 6
@@ -136,7 +136,7 @@
 /* Baseband registers               */
 /************************************/
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
 
   // Omega registers values will be programmed at 1st DSP communication interrupt
 
@@ -156,7 +156,7 @@
   #define  C_BBCTRL         ((0x181 << 6) | BBCTRL    | TRUE)       // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
 #endif
 
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
 
   // IOTA registers values will be programmed at 1st DSP communication interrupt
 
@@ -181,7 +181,7 @@
   #define  C_BULGCAL        ((0x000 << 6) | BULGCAL   | TRUE )      // IAG=0 dB, QAG=0 dB
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
 
   // SYREN registers values will be programmed at 1st DSP communication interrupt
 
@@ -305,7 +305,7 @@
 /************************************/
 /*       Ramp definitions           */
 /************************************/
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
   typedef struct
   {
     UWORD8  ramp_up     [16];                                       // Ramp-up profile
@@ -556,18 +556,18 @@
 /* ABB (Omega) Initialization       */
 /************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+#if ((ANALOG == 1) || (ANALOG == 2))
   #define ABB_TABLE_SIZE  16
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
   #define ABB_TABLE_SIZE  22
 #endif
 
 // Note that this translation is probably not needed at all. But until L1 is
 // (maybe) changed to simply initialize the ABB from a table of words, we
 // use this to make things more easy-readable.
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -583,7 +583,7 @@
   };
 #endif
 
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -602,7 +602,7 @@
   };
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
--- a/gsm-fw/L1/cust0/l1_rf12.h	Sun Nov 17 04:50:45 2013 +0000
+++ b/gsm-fw/L1/cust0/l1_rf12.h	Sun Nov 17 04:59:55 2013 +0000
@@ -82,7 +82,7 @@
 /* Fixed TXPWR value when GSM management is disabled. */
 /******************************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
 //  #define FIXED_TXPWR       ((0xFC<<6) | AUXAPC | FALSE)  // TXPWR=10, value=252
 //#define FIXED_TXPWR         ((0x65<<6) | AUXAPC | FALSE)  
   #define FIXED_TXPWR       ((0x74<<6) | AUXAPC | FALSE)  // TXPWR=15
@@ -95,30 +95,30 @@
 #define  DL_DELAY_RF      1   // time spent in the Downlink global RF chain by the modulated signal 
 #define  UL_DELAY_1RF     7   // time spent in the first  uplink RF block
 #define  UL_DELAY_2RF     0   // time spent in the second uplink RF block
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   #define  UL_ABB_DELAY   3   // modulator input to output delay
 #endif
-#if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 2) || (ANALOG == 3))
   #define  UL_ABB_DELAY   3   // modulator input to output delay
 #endif
 
 /************************************/
 /* TX Propagation delay...          */
 /************************************/
- #if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+ #if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
   #define  PRG_TX       (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY)   // = 40
 #endif
 
 /************************************/
 /* Initial value for APC DELAY      */
 /************************************/
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
 //#define APCDEL_DOWN     (32 - GUARD_BITS*4)          // minimum value: 2
   #define APCDEL_DOWN      2                           // minimum value: 2
   #define APCDEL_UP       (6+5)                        // minimum value: 6
 #endif
 
-#if (ANLG_FAM == 2) || (ANLG_FAM == 3)
+#if (ANALOG == 2) || (ANALOG == 3)
 //#define APCDEL_DOWN     (32 - GUARD_BITS*4)          // minimum value: 2
   #define APCDEL_DOWN     (2+0)                        // minimum value: 2
   #define APCDEL_UP       (6+3+1)                      // minimum value: 6
@@ -138,7 +138,7 @@
 /************************************/
 /* Baseband registers               */
 /************************************/
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
    // Omega registers values will be programmed at 1st DSP communication interrupt 
   #define  C_DEBUG1           0x0001                            // Enable f_tx delay of 400000 cyc DEBUG 
   #define  C_AFCCTLADD      ((0x000 << 6) | AFCCTLADD | TRUE)   // Value at reset
@@ -157,7 +157,7 @@
   #define  C_BBCTRL         ((0x181 << 6) | BBCTRL    | TRUE)   // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
 #endif
 
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
 
   // IOTA registers values will be programmed at 1st DSP communication interrupt
 
@@ -195,7 +195,7 @@
   #define  C_BULGCAL        ((0x000 << 6) | BULGCAL   | TRUE) // IAG=0 dB, QAG=0 dB 
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
 
   // SYREN registers values will be programmed at 1st DSP communication interrupt
 
@@ -332,7 +332,7 @@
 /************************************/
 /*       Ramp definitions           */
 /************************************/
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
   typedef struct
   {
     UWORD8  ramp_up     [16];  // Ramp-up profile
@@ -570,9 +570,9 @@
 /* ABB (Omega) Initialization       */
 /************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
-#define ABB_TABLE_SIZE 16
-#elif (ANLG_FAM == 3)
+#if ((ANALOG == 1) || (ANALOG == 2))
+  #define ABB_TABLE_SIZE 16
+#elif (ANALOG == 3)
   #define ABB_TABLE_SIZE 22
 #endif
 
@@ -580,7 +580,7 @@
 // (maybe) changed to simply initialize the ABB from a table of words, we
 // use this to make things more easy-readable.
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -594,7 +594,7 @@
     ABB_VBCTRL,
     ABB_APCDEL1
   };
-#elif (ANLG_FAM == 2)
+#elif (ANALOG == 2)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -611,7 +611,7 @@
     ABB_APCDEL1,
     ABB_APCDEL2
   };
-#elif (ANLG_FAM == 3)
+#elif (ANALOG == 3)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
--- a/gsm-fw/L1/cust0/l1_rf2.h	Sun Nov 17 04:50:45 2013 +0000
+++ b/gsm-fw/L1/cust0/l1_rf2.h	Sun Nov 17 04:59:55 2013 +0000
@@ -33,7 +33,7 @@
 /* TXPWR configuration...           */
 /************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
   #define FIXED_TXPWR       ((0x1FF << 6) | AUXAPC | FALSE)            // TXPWR=15
 //  #define FIXED_TXPWR       ((0xFF << 6) | AUXAPC | FALSE)
 #endif
@@ -42,7 +42,7 @@
 /* TX Propagation delay...          */
 /************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
 //  #define  PRG_TX                ( 52L ) 
   #define  PRG_TX                ( 8L) 
 #endif
@@ -63,7 +63,7 @@
                                               // !! minimum Value : 1 Frame due to the fact there is no
                                               // hisr() in the first wake-up frame !!!!
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   /************************************/
   /* Omega power on...                */
   /************************************/
@@ -84,7 +84,7 @@
   #define  C_APCDEL1        ((0x000 << 6) | APCDEL1   | FALSE) 
 #endif
 
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
   /************************************/
   /* Iota power on...                 */
   /************************************/
@@ -108,7 +108,7 @@
   #define  C_APCDEL2        ((0x000 << 6) | APCDEL2   | TRUE )
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
   // SYREN registers values will be programmed at 1st DSP communication interrupt
   #define  C_DEBUG1          (0x0000                  | FALSE)      // Enable f_tx delay of 400000 cyc DEBUG 
   #define  C_AFCCTLADD      ((0x000 << 6) | AFCCTLADD | TRUE )      // Value at reset
@@ -212,7 +212,7 @@
 /*       Ramp definitions           */
 /************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
   typedef struct
   {
     UWORD8  ramp_up     [16];  // Ramp-up profile
@@ -460,18 +460,18 @@
 /************************************/
 /* ABB (Omega) Initialization       */
 /************************************/
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+#if ((ANALOG == 1) || (ANALOG == 2))
   #define ABB_TABLE_SIZE 16
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
   #define ABB_TABLE_SIZE 22
 #endif
 
 // Note that this translation is probably not needed at all. But until L1 is
 // (maybe) changed to simply initialize the ABB from a table of words, we
 // use this to make things more easy-readable.
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -485,7 +485,7 @@
     ABB_VBCTRL,
     ABB_APCDEL1
   };
-#elif (ANLG_FAM == 2)
+#elif (ANALOG == 2)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -502,7 +502,7 @@
     ABB_APCDEL1,
     ABB_APCDEL2
   };
-#elif (ANLG_FAM == 3)
+#elif (ANALOG == 3)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
--- a/gsm-fw/L1/cust0/l1_rf35.h	Sun Nov 17 04:50:45 2013 +0000
+++ b/gsm-fw/L1/cust0/l1_rf35.h	Sun Nov 17 04:59:55 2013 +0000
@@ -27,7 +27,7 @@
 /* TXPWR configuration...                             */
 /* Fixed TXPWR value when GSM management is disabled. */
 /******************************************************/
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+#if ((ANALOG == 1) || (ANALOG == 2))
 //  #define FIXED_TXPWR       0x3f12  // TXPWR=10, value=252
 //  #define FIXED_TXPWR       0x0a12  // TXPWR=15, value=40
   #define FIXED_TXPWR       0x1a12  // TXPWR=15, EVA4, CRTP1
@@ -40,29 +40,29 @@
 #define  DL_DELAY_RF      1   // time spent in the Downlink global RF chain by the modulated signal 
 #define  UL_DELAY_1RF     5   // time spent in the first  uplink RF block
 #define  UL_DELAY_2RF     0   // time spent in the second uplink RF block
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   #define  UL_ABB_DELAY   6   // modulator input to output delay
 #endif
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
   #define  UL_ABB_DELAY   3   // modulator input to output delay
 #endif
 
 /************************************/
 /* TX Propagation delay...          */
 /************************************/
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+#if ((ANALOG == 1) || (ANALOG == 2))
   #define  PRG_TX       (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY)   // = 40 + NB_MARGIN
 #endif
 
 /************************************/
 /* Initial value for APC DELAY      */
 /************************************/
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
 //#define APCDEL_DOWN     (32 - GUARD_BITS*4)          // minimum value: 2
   #define APCDEL_DOWN      2                           // minimum value: 2
   #define APCDEL_UP       (6+5)                        // minimum value: 6
 #endif
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
 //#define APCDEL_DOWN     (32 - GUARD_BITS*4)          // minimum value: 2
   #define APCDEL_DOWN      2                           // minimum value: 2
   #define APCDEL_UP       (6+2)                        // minimum value: 6
@@ -82,7 +82,7 @@
 /************************************/
 /* Baseband registers               */
 /************************************/
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   // Omega registers values will be programmed at 1st DSP communication interrupt
   #define  C_DEBUG1          0x0000          // Enable f_tx delay of 400000 cyc DEBUG 
   #define  C_AFCCTLADD       0x002a | TRUE   // Value at reset
@@ -99,7 +99,7 @@
   #define  C_APCDEL1         (((APCDEL_DOWN-2)<<11) | ((APCDEL_UP-6)<<6) | 0x0004) 
   #define  C_BBCTRL          0x604c | TRUE   // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
 #endif
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
   // IOTA registers values will be programmed at 1st DSP communication interrupt
   #define  C_DEBUG1          0x0001          // Enable f_tx delay of 400000 cyc DEBUG 
   #define  C_AFCCTLADD       0x002a | TRUE   // Value at reset
@@ -192,7 +192,7 @@
 /************************************/
 /*       Ramp definitions           */
 /************************************/
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+#if ((ANALOG == 1) || (ANALOG == 2))
   typedef struct
   {
     UWORD8  ramp_up     [16];  // Ramp-up profile
@@ -440,7 +440,7 @@
 // Note that this translation is probably not needed at all. But until L1 is
 // (maybe) changed to simply initialize the ABB from a table of words, we
 // use this to make things more easy-readable.
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
 enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -454,7 +454,7 @@
     ABB_VBCTRL,
     ABB_APCDEL1
 };
-#elif (ANLG_FAM == 2)
+#elif (ANALOG == 2)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
--- a/gsm-fw/L1/cust0/l1_rf8.h	Sun Nov 17 04:50:45 2013 +0000
+++ b/gsm-fw/L1/cust0/l1_rf8.h	Sun Nov 17 04:59:55 2013 +0000
@@ -31,7 +31,7 @@
 /* Fixed TXPWR value when GSM management is disabled. */
 /******************************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
 //  #define FIXED_TXPWR       ((0xFC << 6) | AUXAPC | FALSE)            // TXPWR=10, value=252
 //  #define FIXED_TXPWR       ((0x28 << 6) | AUXAPC | FALSE)  
   #define FIXED_TXPWR       ((0x68 << 6) | AUXAPC | FALSE)            // TXPWR=15
@@ -46,11 +46,11 @@
 #define  UL_DELAY_1RF     5   // time spent in the first  uplink RF block
 #define  UL_DELAY_2RF     0   // time spent in the second uplink RF block
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   #define  UL_ABB_DELAY   0   // modulator input to output delay, theoretical value is 6, needs to be checked
 #endif
 
-#if ((ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 2) || (ANALOG == 3))
   #define  UL_ABB_DELAY   3   // modulator input to output delay
 #endif
 
@@ -58,7 +58,7 @@
 /* TX Propagation delay...          */
 /************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
   #define  PRG_TX       (DL_DELAY_RF + UL_DELAY_2RF + (GUARD_BITS*4) + UL_DELAY_1RF + UL_ABB_DELAY)   // = 40
 #endif
 
@@ -66,13 +66,13 @@
 /* Initial value for APC DELAY      */
 /************************************/
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
 //#define APCDEL_DOWN     (32 - GUARD_BITS*4)          // minimum value: 2
   #define APCDEL_DOWN      2                           // minimum value: 2
   #define APCDEL_UP       (6+5)                        // minimum value: 6
 #endif
 
-#if (ANLG_FAM == 2) || (ANLG_FAM == 3)
+#if (ANALOG == 2) || (ANALOG == 3)
 //#define APCDEL_DOWN     (32 - GUARD_BITS*4)          // minimum value: 2
   #define APCDEL_DOWN     (2+0)                           // minimum value: 2
   #define APCDEL_UP       (6+2)                        // minimum value: 6
@@ -94,7 +94,7 @@
 /* Baseband registers               */
 /************************************/
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   // Omega registers values will be programmed at 1st DSP communication interrupt
   #define  C_DEBUG1          (0x0000                  | FALSE)      // Enable f_tx delay of 400000 cyc DEBUG 
   #define  C_AFCCTLADD      ((0x000 << 6) | AFCCTLADD | TRUE )      // Value at reset
@@ -112,7 +112,7 @@
   #define  C_BBCTRL         ((0x181 << 6) | BBCTRL    | TRUE)       // OUTLEV1=OUTLEV1=SELVMID1=SELVMID0=1 for B-sample 'modified'
 #endif
 
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
   // IOTA registers values will be programmed at 1st DSP communication interrupt
   #define  C_DEBUG1          (0x0000                  | TRUE )      // Enable f_tx delay of 400000 cyc DEBUG 
   #define  C_AFCCTLADD      ((0x000 << 6) | AFCCTLADD | TRUE )      // Value at reset
@@ -135,7 +135,7 @@
   #define  C_BULGCAL        ((0x000 << 6) | BULGCAL   | TRUE )      // IAG=0 dB, QAG=0 dB
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
   // SYREN registers values will be programmed at 1st DSP communication interrupt
   #define  C_DEBUG1          (0x0000                  | TRUE )      // Enable f_tx delay of 400000 cyc DEBUG 
   #define  C_AFCCTLADD      ((0x000 << 6) | AFCCTLADD | TRUE )      // Value at reset
@@ -247,7 +247,7 @@
 /*       Ramp definitions           */
 /************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
   typedef struct
   {
     UWORD8  ramp_up     [16];  // Ramp-up profile
@@ -498,11 +498,11 @@
 /* ABB (Omega) Initialization       */
 /************************************/
 
-#if ((ANLG_FAM == 1) || (ANLG_FAM == 2))
+#if ((ANALOG == 1) || (ANALOG == 2))
   #define ABB_TABLE_SIZE 16
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
   #define ABB_TABLE_SIZE 22
 #endif
 
@@ -510,7 +510,7 @@
 // (maybe) changed to simply initialize the ABB from a table of words, we
 // use this to make things more easy-readable.
 
-#if (ANLG_FAM == 1)
+#if (ANALOG == 1)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -526,7 +526,7 @@
   };
 #endif
 
-#if (ANLG_FAM == 2)
+#if (ANALOG == 2)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
@@ -545,7 +545,7 @@
   };
 #endif
 
-#if (ANLG_FAM == 3)
+#if (ANALOG == 3)
   enum ABB_REGISTERS {
     ABB_AFCCTLADD = 0,
     ABB_VBUCTRL,
--- a/gsm-fw/bsp/abb+spi/abb.c	Sun Nov 17 04:50:45 2013 +0000
+++ b/gsm-fw/bsp/abb+spi/abb.c	Sun Nov 17 04:59:55 2013 +0000
@@ -48,24 +48,24 @@
 #endif
 
 #if (RF_FAM == 35)
-  #include "l1_rf35.h"
+  #include "../../L1/cust0/l1_rf35.h"
 #endif
 
 #if (RF_FAM == 12)
   #include "tpudrv12.h" 
-  #include "l1_rf12.h"
+  #include "../../L1/cust0/l1_rf12.h"
 #endif
 
 #if (RF_FAM == 10)
-  #include "l1_rf10.h"
+  #include "../../L1/cust0/l1_rf10.h"
 #endif
 
 #if (RF_FAM == 8)
-  #include "l1_rf8.h"
+  #include "../../L1/cust0/l1_rf8.h"
 #endif
 
 #if (RF_FAM == 2)
-  #include "l1_rf2.h"
+  #include "../../L1/cust0/l1_rf2.h"
 #endif
 
 #if (ABB_SEMAPHORE_PROTECTION)