--- a/nuc-fw/bsp/armio.c	Sat Oct 19 18:59:34 2013 +0000
+++ b/nuc-fw/bsp/armio.c	Sun Oct 20 07:04:15 2013 +0000
@@ -129,7 +129,7 @@
    *((volatile SYS_UWORD16 *) ARMIO_IO_CNTL) = 0xFFFF; // all bits are inputs
 #if (CHIPSET != 12)
    *((volatile SYS_UWORD16 *) CLKM_IO_CNTL) = 0;       // default config
-  #endif /* CHIPSET != 12 */
+#endif /* CHIPSET != 12 */
 }
 
 
@@ -145,9 +145,114 @@
 }
 
 /*
- * The target-specific AI_InitIOConfig() function will need to go here.
+ * The AI_InitIOConfig() function is target-specific.
  */
 
+#ifdef CONFIG_TARGET_GTAMODEM
+/* version for the Openmoko GTA0x GSM modem */
+void AI_InitIOConfig(void)
+{
+  // reset the IOs config
+  AI_ResetIoConfig();
+
+  /*
+   * The GTA0x Calypso block is a stripped-down version of the Leonardo,
+   * reduced to the absolute minimum that is needed for a slave modem.
+   * Almost all of the unused interface pins are left unconnected, only
+   * a few are pulled externally to GND or VIO.
+   *
+   * We handle the unused pins the way TI's code does: configure then
+   * as GPIOs, then as outputs driving a fixed value (high for GPIOs 8+,
+   * low for 0-7).
+   */
+
+  /* I'll be brave and turn the unused TSPDI input into a GPIO4 output */
+  AI_EnableBit(0);
+  /* Don't want to do that for the IO5 pin though, as it's wired to SIM_IO
+   * through a resistor like on the Leonardo. */
+  AI_DisableBit(1);
+  /*
+   * The following 2 lines are straight from the Leonardo source: enable
+   * GPIO6 and GPIO8.  GPIO6 takes the place of an ancient VEGA3(?) compat
+   * pin, and GPIO8 takes the place of MCUEN1 which no Leonardo-based
+   * design seems to use.
+   *
+   * Note that GPIO7 is not enabled in this version, so that pin retains
+   * its meaning as nRESET_OUT - but it's an unused output, rather than
+   * a floating input, so we are fine.
+   */
+  AI_EnableBit(2);
+  AI_EnableBit(4);
+
+  /*
+   * The GTA0x modem has no Calypso-interfaced Bluetooth, nor any other
+   * use for MCSI, aka the DSP backdoor interface.  So we turn these 4 pins
+   * into GPIOs driving high output state like TI's code does in the
+   * sans-BT configuration.
+   */
+  AI_EnableBit(5);
+  AI_EnableBit(6);
+  AI_EnableBit(7);
+  AI_EnableBit(8);
+
+  /* ditto for MCUEN2 turned GPIO 13 */
+  AI_EnableBit(9);
+
+  // ARMIO_OUT register configuration :
+  // set IOs 8,9,10,11,12 and 13 as high
+  // set IOs 0 to 7 as low
+  // Falcon's note: the BP->AP interrupt line gets set low as desired
+  *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x3F00;
+    
+  // ARMIO_CNTL_REG register configuration :
+  // set IOs 0,1,6,8,9,10,11,12 and 13 as outputs.
+  // Falcon's addition: set 2, 3 and 4 as outputs too,
+  // as they are no-connects on the board.
+
+  AI_ConfigBitAsOutput(0);
+  AI_ConfigBitAsOutput(1);
+  AI_ConfigBitAsOutput(2);
+  AI_ConfigBitAsOutput(3);
+  AI_ConfigBitAsOutput(4);
+  AI_ConfigBitAsOutput(6);
+  AI_ConfigBitAsOutput(8);
+  AI_ConfigBitAsOutput(9);
+  AI_ConfigBitAsOutput(10);
+  AI_ConfigBitAsOutput(11);
+  AI_ConfigBitAsOutput(12);
+  AI_ConfigBitAsOutput(13);
+}
+#endif
+
+#ifdef CONFIG_TARGET_PIRELLI
+/* version for Pirelli DP-L10 */
+void AI_InitIOConfig(void)
+{
+  // reset the IOs config
+  AI_ResetIoConfig();
+
+  /*
+   * In the case of the Pirelli, our understanding of the hardware
+   * is severely crippled by the lack of schematics and the difficulty of
+   * reverse engineering from steve-m's PCB layer grind-down scans.
+   *
+   * The folllowing ARMIO configuration has been copied from OsmocomBB.
+   */
+  AI_EnableBit(0);
+  AI_EnableBit(1);
+  AI_EnableBit(2);
+  AI_EnableBit(3);
+  AI_EnableBit(4);
+  AI_EnableBit(9);
+  /* GPIO out all zeros */
+  *((volatile SYS_UWORD16 *) ARMIO_OUT) = 0x0000;
+  /* setup outputs like OsmocomBB does */
+  AI_ConfigBitAsOutput(1);
+  AI_ConfigBitAsOutput(4);
+  AI_ConfigBitAsOutput(7);
+}
+#endif
+
 /*
  * AI_SelectIOForIT
  *