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changeset 554:3a0ce0ea4035

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gsm-fw/L1/tpudrv/tpudrv.h: Leonardo version replaced with LoCosto-based one; l1dmacro_rx_nb() and l1dmacro_rx_cont() prototypes fixed not to include the csf_filter_choice parameter in the Calypso configuration
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Mon, 04 Aug 2014 04:57:24 +0000
parents e4feac5bc3ea
children 44d30f013ee5
files gsm-fw/L1/tpudrv/tpudrv.h
diffstat 1 files changed, 118 insertions(+), 43 deletions(-) [+]
line wrap: on
line diff
--- a/gsm-fw/L1/tpudrv/tpudrv.h	Mon Aug 04 00:07:21 2014 +0000
+++ b/gsm-fw/L1/tpudrv/tpudrv.h	Mon Aug 04 04:57:24 2014 +0000
@@ -1,19 +1,19 @@
 /************* Revision Controle System Header *************
- *                  GSM Layer 1 software 
+ *                  GSM Layer 1 software
  *
  *        Filename tpudrv.h
- *  Copyright 2003 (C) Texas Instruments  
+ *  Copyright 2003 (C) Texas Instruments
  *
  ************* Revision Controle System Header *************/
 
 /*
  * Device addresses - GCS000
- */ 
-// GSM 1.5 : TPU / TSP addresses 
+ */
+// GSM 1.5 : TPU / TSP addresses
 //-------------------------------------
 
 #if ((CHIPSET ==2) || (CHIPSET == 3) || (CHIPSET == 4))
-  #define TPU_ADDR      0xFFFE0000l            // Hercule / Ulysse / Samson
+  #define TPU_ADDR      0xFFFE0000L  //omaps00090550          // Hercule / Ulysse / Samson
 
   #define TPU_RAM       (TPU_ADDR + 0x1400)
 
@@ -22,20 +22,31 @@
   #define TPU_TIM       (TPU_ADDR + 0x2000)
 
 #elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7)  || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12))
-  #define TPU_ADDR      0xFFFF0000l            // Strobe 1 address
+  #define TPU_ADDR      0xFFFF0000L            // Strobe 1 address //omaps00090550
 
-  #define TPU_RAM       0xFFFF9000l            // TPU RAM
+  #define TPU_RAM       0xFFFF9000L            // TPU RAM //omaps00090550
 
   #define TPU_REG       (TPU_ADDR + 0x1000)    // TPU register
-  #define TSP_REG       0xFFFE0800l            // TSP register
-  #define TPU_TIM       0xFFFE2000l            // ULPD register
+  #define TSP_REG       0xFFFE0800L            // TSP register  //omaps00090550
+  #define TPU_TIM       0xFFFE2000L            // ULPD register  //omaps00090550
+
+#elif (CHIPSET == 15)
+  #define TPU_ADDR      0xFFFFF000L            // Strobe 1 address //omaps00090550
+
+  #define TPU_RAM       0xFFFF9000L            // TPU RAM   //omaps00090550
+
+  #define TPU_REG       (TPU_ADDR)             // TPU register
+
+  // TSP should be removed for Locosto. Leaving it as such as the TPU drivers are not yet ported.
+  #define TSP_REG       0xFFFE0800L            // TSP register   //omaps00090550
+  #define TPU_TIM       0xFFFE2000L            // ULPD register   //omaps00090550
 
 #endif
 
 
 /*
  * Macros for defining TPU instructions
- */ 
+ */
 #define TPU_SLEEP             0
 #define TPU_MOVE(addr,data)   (0x8000 | ((data)<<5) | (addr))
 #define TPU_AT(time)          (0x2000 | (((time + 5000) % 5000)))
@@ -48,12 +59,12 @@
 
 /*
  * TSP registers - defined in GCS004 - Time Serial Port
- */ 
+ */
 /*
  *  in TPU address space
  */
 // GSM 1.5 : TSP_TX_REG_1/2/3/4 instead of TSP_TX_U/M/L
-//           added TSP_SPI_SET1/2/3 to ctrl up to 5 periph. 
+//           added TSP_SPI_SET1/2/3 to ctrl up to 5 periph.
 //-----------------------------------------------------
   #define TSP_CTRL1       0x00
   #define TSP_CTRL2       0x01
@@ -65,7 +76,7 @@
   #define TSP_ACTX        0x07
   #define TSP_GAUGING_EN  0x11
   #define TSP_SPI_SET1    0x09
-  #define TSP_SPI_SET2    0x0A 
+  #define TSP_SPI_SET2    0x0A
   #define TSP_SPI_SET3    0x0B
   #define TPU_IT_DSP_PG   0x10
   #define TSP_GAUGING_EN  0x11
@@ -74,17 +85,13 @@
  *  in ARM address space - defined in HYP004
  */
   #define TSP_RX_LSB   (TSP_REG + 0x00)
-
   #define TSP_RX_MSB   (TSP_REG + 0x02)
-
   #define TSP_TX_LSB   (TSP_REG + 0x0c)
-
   #define TSP_TX_MSB   (TSP_REG + 0x0a)
 
-
 /*
  * TSP registers bit definitions
- */ 
+ */
   #define TC1_DEVICE0   0x00
   #define TC1_DEVICE1   0x20
   #define TC1_DEVICE2   0x40
@@ -105,7 +112,7 @@
 
 /*
  * TPU registers - defined in HYP002
- */ 
+ */
 // GSM 1.5 : TPU reg are 16-bit access
 //---------------------------------------
 #define TPU_CTRL          (TPU_REG + 0x00)
@@ -117,14 +124,14 @@
 
 
 
- 
+
 
 /*
  * TPU control register bits
- */ 
+ */
 // GSM 1.5 : TPU bits changed
 //---------------------------------------
-#define TPU_CTRL_RESET     0x0001 
+#define TPU_CTRL_RESET     0x0001
 #define TSP_CTRL_RESET     0x0080
 #define TPU_CTRL_T_PAGE    0x0002
 #define TPU_CTRL_T_ENBL    0x0004
@@ -132,33 +139,33 @@
 #define TPU_CTRL_SPI_RST   0x0080
 #define TPU_CTRL_WAIT      0x0200
 #define TPU_CTRL_CLK_EN    0x0400
-#if (CHIPSET == 7)  || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)
+#if (CHIPSET == 7)  || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) || (CHIPSET == 15)
   #define TPU_CTRL_FULL_WRITE 0x0800
 #endif
 
 
 
 
-/* 
+/*
  * TPU interrupt control register bits
  */
 
 
 /* WARNING BUG IN HYPERION. */
-/* READING TPU_INT_CRTL, TPU_INT_ITP_M BIT CONTENTS AFFECTS THE TPU_INT_ITD_M VALUE. */ 
+/* READING TPU_INT_CRTL, TPU_INT_ITP_M BIT CONTENTS AFFECTS THE TPU_INT_ITD_M VALUE. */
 
 #define TPU_INT_ITF_M      0x0001
-#define TPU_INT_ITP_M      0x0002         
+#define TPU_INT_ITP_M      0x0002
 #define TPU_INT_ITD_M      0x0004
 #define TPU_INT_ITD_F      0x0008        // WARNING THIS BIT DOES NOT EXIST IN HYPERION
 
-#define INT_FRAME   4       /* TPU frame interrupt */   
-#define INT_PAGE    5       /* TPU page interrupt */        
-#define INT_TSP 3       /* TSP interrupt */ 
+#define INT_FRAME   4       /* TPU frame interrupt */
+#define INT_PAGE    5       /* TPU page interrupt */
+#define INT_TSP 3       /* TSP interrupt */
 
 
 
-#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3))
+#if ((ANALOG == 1) || (ANALOG == 2) || (ANALOG == 3) || (ANALOG==11))
     // BB signals connected to serial link1
     #define BULON    0x80     // bit6
     #define BULCAL   0x40     // bit5
@@ -169,8 +176,16 @@
     #define STARTADC 0x02     // bit0
 #endif
 
+#if (RF_FAM == 61)
+/*	#define START_ADC 0x01     // TSPact 8  omaps00090550*/
+    // TSPACT
+    #define REG_SPI_ACT_U   0x07
+    #define REG_SPI_ACT_L   0x06
 
-/* 
+#endif
+#define TPU_CTRL_TPU_IDLE 0x0100
+
+/*
  * GSM RF programming times in quarter bits
  */
 /**************************************************************************/
@@ -189,37 +204,99 @@
 //------------
 void l1dmacro_reset_hw        (UWORD32 servingCellOffset);
 void l1dmacro_init_hw         (void);
-void l1dmacro_init_hw_light   (void);
-void l1dmacro_idle            (void);                       
+void l1dmacro_idle            (void);
 void l1dmacro_rx_synth        (SYS_UWORD16  radio_freq);
 void l1dmacro_tx_synth        (SYS_UWORD16  radio_freq);
+
+
+#if (RF_FAM == 61)
+void l1dmacro_agc             (SYS_UWORD16  radio_freq, WORD8 gain, UWORD8 lna, UWORD8 if_ctl);
+#endif
+#if (RF_FAM != 61)
 void l1dmacro_agc             (SYS_UWORD16  radio_freq, WORD8 gain, UWORD8 lna);
+#endif
+
 void l1dmacro_afc             (SYS_UWORD16 afc_value, UWORD8 win_id);
+#if (L1_MADC_ON == 1)
+#if (RF_FAM == 61)
+void l1dmacro_rx_ms           (SYS_UWORD16 radio_freq,UWORD8 adc_active);
+void l1dmacro_rx_fb           (SYS_UWORD16 radio_freq,UWORD8 adc_active);
+void l1dmacro_rx_fb26         (SYS_UWORD16 radio_freq,UWORD8 adc_active);
+#endif
+#else
 void l1dmacro_rx_ms           (SYS_UWORD16 radio_freq);
 void l1dmacro_rx_fb           (SYS_UWORD16 radio_freq);
 void l1dmacro_rx_fb26         (SYS_UWORD16 radio_freq);
-void l1dmacro_offset          (UWORD32     offset_value, 
+#endif
+
+void l1dmacro_offset          (UWORD32     offset_value,
                                WORD32      relative_time);
 void l1dmacro_synchro         (UWORD32 when, UWORD32 value);
+#if (L1_MADC_ON == 1)
+#if (RF_FAM == 61)
+void l1dmacro_rx_sb           (SYS_UWORD16 radio_freq,UWORD8 adc_active);
+void l1dmacro_rx_nb           (SYS_UWORD16 radio_freq,UWORD8 adc_active, UWORD8 csf_filter_choice
+#if (NEW_SNR_THRESHOLD == 1)
+                                  ,UWORD8 saic_flag
+#endif /* NEW_SNR_THRESHOLD*/
+    );
+#endif /* RF_FAM == 61*/
+#else /* L1_MADC_ON == 1*/
 void l1dmacro_rx_sb           (SYS_UWORD16 radio_freq);
+#if (RF_FAM == 61)
+void l1dmacro_rx_nb           (SYS_UWORD16 radio_freq,  UWORD8 csf_filter_choice);
+#else
 void l1dmacro_rx_nb           (SYS_UWORD16 radio_freq);
+#endif	// RF_FAM
+#endif	// L1_MADC_ON
+
 void l1dmacro_tx_nb           (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
 void l1dmacro_tx_ra           (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active);
-void l1dmacro_adc_read_tx     (UWORD32 when);
+
+#if (L1_MADC_ON == 1)
+#if (RF_FAM == 61)
+	void l1dmacro_adc_read_tx     (UWORD32 when, UWORD8 tx_up_state);
+#endif
+#endif
+#if (RF_FAM != 61)
+	void l1dmacro_adc_read_tx     (UWORD32 when);
+#endif
+
 void l1dmacro_adc_read_rx     (void);
+
+#if (CODE_VERSION != SIMULATION)
+#if (L1_MADC_ON ==1)
+void l1dmacro_adc_read_rx_cs_mode0(void);
+#endif
+#endif
+
+
 void l1dmacro_set_frame_it    (void);
-
-void l1pdmacro_it_dsp_gen(WORD16 time);
+void l1dmacro_init_hw_light   (void);
 
 #if TESTMODE
+#if (L1_MADC_ON == 1)
+#if (RF_FAM == 61)
+void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr,UWORD8 adc_active, UWORD8 csf_filter_choice
+#if (NEW_SNR_THRESHOLD == 1)
+                                  ,UWORD8 saic_flag
+#endif /* NEW_SNR_THRESHOLD*/
+    );
+#endif /* RF_FAM == 1*/
+#else /* L1_MADC_ON == 1*/
+#if (RF_RAM == 61)
+  void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr,  UWORD8 csf_filter_choice);
+#else
   void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
+#endif /* RF_FAM */
+#endif /* L1_MADC_ON */
   void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr);
   void l1dmacro_stop_cont (void);
-#endif
+#endif /* TESTMODE */
 
 /*
  * TPU prototypes
- */ 
+ */
 void TP_PageIntHandler  (void);
 void TP_FrameIntHandler (void);
 void TP_PageIntHandler  (void);
@@ -234,14 +311,12 @@
 
 /*
  * TPUDRV global variables
- */ 
+ */
 #ifdef TPUDRV_C
-#define TP_GLOBAL 
+#define TP_GLOBAL
 #else
 #define TP_GLOBAL extern
 #endif
 
 TP_GLOBAL volatile UWORD32 TP_PageInt;
 TP_GLOBAL volatile UWORD32 TP_FrameInt;
-
-