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changeset 939:62ca61292b77

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gsm-fw: Intel single bank flash driver (Compal) compiles and links
author Mychaela Falconia <falcon@ivan.Harhan.ORG>
date Sat, 31 Oct 2015 23:21:40 +0000
parents 1db4da08b9b4
children 0fb9b7f2ef87
files gsm-fw/finlink/Makefile gsm-fw/services/ffs/Makefile gsm-fw/services/ffs/intelsbdrv.c
diffstat 3 files changed, 36 insertions(+), 117 deletions(-) [+]
line wrap: on
line diff
--- a/gsm-fw/finlink/Makefile	Sat Oct 31 23:02:20 2015 +0000
+++ b/gsm-fw/finlink/Makefile	Sat Oct 31 23:21:40 2015 +0000
@@ -41,6 +41,9 @@
 INT_PIECES=	../bsp/iramcode.o
 EXT_PIECES=	../bsp/xipcode.o ../serial/xipcode.o ../sysglue/xipcode.o \
 		../services/ffs/xipcode.o ../services/dar/xipcode.o
+ifeq (${FLASH_IS_INTEL_ONEBANK},1)
+INT_PIECES+=	../services/ffs/intelsbdrv.o
+endif
 ifeq (${CONFIG_INCLUDE_GPF},1)
 EXT_PIECES+=	../gpf/conf/xipcode.o
 endif
--- a/gsm-fw/services/ffs/Makefile	Sat Oct 31 23:02:20 2015 +0000
+++ b/gsm-fw/services/ffs/Makefile	Sat Oct 31 23:21:40 2015 +0000
@@ -1,16 +1,24 @@
 CC=	arm-elf-gcc
-CFLAGS=	-O2 -fno-builtin -mthumb-interwork -mthumb
+CFLAGS=	-O2 -fno-builtin -mthumb-interwork
 LD=	arm-elf-ld
 
+sinclude ../../include/config.mk
+
 OBJS=	cfgffs.o core.o drv.o ffs_env.o ffs_target.o ffstrace.o fsck.o rand.o \
 	reclaim.o task.o tmffs.o
 
 HDRS=	core.h drv.h ffs.h ffs_api.h ffs_env.h ffs_pool_size.h ffstrace.h \
 	intctl.h ramffs.h task.h tmffs.h
 
-all:	xipcode.o
+TARGETS=xipcode.o
+ifeq (${FLASH_IS_INTEL_ONEBANK},1)
+TARGETS+=intelsbdrv.o
+endif
 
-${OBJS}:	${HDRS}
+all:	${TARGETS}
+
+${OBJS}:	%.o : %.c ${HDRS}
+	${CC} ${CFLAGS} -mthumb -c $<
 
 ffs_target.c:	ffs.c mktarget.pl
 	./mktarget.pl
@@ -18,5 +26,8 @@
 xipcode.o:	${OBJS}
 	${LD} -r -o $@ ${OBJS}
 
+intelsbdrv.o:	intelsbdrv.c ${HDRS}
+	${CC} ${CFLAGS} -c intelsbdrv.c
+
 clean:
 	rm -f *.[oa] *errs ffs_target.c
--- a/gsm-fw/services/ffs/intelsbdrv.c	Sat Oct 31 23:02:20 2015 +0000
+++ b/gsm-fw/services/ffs/intelsbdrv.c	Sat Oct 31 23:21:40 2015 +0000
@@ -8,14 +8,11 @@
  *
  ******************************************************************************/
 
-#include "ffs.cfg"
-
-#include "ffs/ffs.h"
-#include "ffs/board/drv.h"
-#include "ffs/board/ffstrace.h"
-
-
-#define INTEL_UNLOCK_SLOW 1
+#include "../../include/config.h"
+#include "ffs.h"
+#include "drv.h"
+#include "ffstrace.h"
+#include "intctl.h"
 
 
 #undef  tlw
@@ -28,12 +25,6 @@
 #define FLASH_READ(addr)        (*(volatile uint16 *) (addr))
 #define FLASH_WRITE(addr, data) (*(volatile uint16 *) (addr)) = data
 
-asm("        .label _ffsdrv_ram_intel_begin");
-asm("        .def   _ffsdrv_ram_intel_begin");
-
-uint32 intel_int_disable(void);
-void intel_int_enable(uint32 tmp);
-
 /******************************************************************************
  * INTEL Single Bank Driver Functions
  ******************************************************************************/
@@ -43,40 +34,17 @@
 // it does not cause any problems.
 int ffsdrv_ram_intel_sb_init(void)
 {
-    uint32 cpsr, i;
-    volatile char *addr;
-	uint16 status;
+    uint32 i;
+    volatile uint16 *addr;
 
     for (i = 0; i < dev.numblocks; i++)
     {
-        addr = block2addr(i);
-      
-        *addr = 0x50; // Intel Clear Status Register
-        *addr = 0xFF; // Intel read array
+        addr = (volatile uint16 *) block2addr(i);
 
         *addr = 0x60; // Intel Config Setup
         *addr = 0xD0; // Intel Unlock Block
 
-		// Wait for unlock to finish
-		do {
-            status = FLASH_READ(addr);
-        } while (!(status & INTEL_STATE_MACHINE_DONE));
-
-		*addr = 0x70; // Intel Read Status Register
-		status = FLASH_READ(addr);
-		
-		// Is there an erase suspended?
-		if ((status & 0x40) != 0) {
-			*addr = 0xD0; // Intel erase resume
-
-			*addr = 0x70; // Intel Read Status Register
-			// wait for erase to finish
-			do {
-				status = FLASH_READ(addr);
-			} while (!(status & INTEL_STATE_MACHINE_DONE));
-		}
-
-        *addr = 0xFF; // Intel Read Array
+	*addr = 0xFF; // Intel Read Array
     }
 
     return 0;
@@ -93,7 +61,7 @@
         return;
     }
 
-    cpsr = intel_int_disable();
+    cpsr = int_disable();
     tlw(led_on(LED_WRITE));
 
 #if (INTEL_UNLOCK_SLOW == 1)
@@ -108,20 +76,20 @@
         ;
     *addr = 0xFF; // Intel read array
     tlw(led_off(LED_WRITE));
-    intel_int_enable(cpsr);
+    int_enable(cpsr);
 }
 
 void ffsdrv_ram_intel_sb_erase(uint8 block)
 {
-    volatile char *addr;
+    volatile uint16 *addr;
     uint32 cpsr;
     uint16 poll;
 
     ttw(ttr(TTrDrvEra, "e(%d)" NL, block));
 
-    addr = block2addr(block);
+    addr = (volatile uint16 *) block2addr(block);
 
-    cpsr = intel_int_disable();
+    cpsr = int_disable();
     tlw(led_on(LED_ERASE));
 
 #if (INTEL_UNLOCK_SLOW == 1)
@@ -132,7 +100,7 @@
     *addr = 0x50; // Intel Clear Status Register
     *addr = 0x20; // Intel Erase Setup
     *addr = 0xD0; // Intel Erase Confirm
-	*addr = 0x70; // Intel Read Status Register
+    *addr = 0x70; // Intel Read Status Register
 
     // Wait for erase to finish.
     while ((*addr & 0x80) == 0) {
@@ -160,11 +128,11 @@
             *addr = 0xFF; // Intel read array
 
             tlw(led_off(LED_ERASE_SUSPEND));
-            intel_int_enable(cpsr);
+            int_enable(cpsr);
 
             // Other interrupts and tasks run now...
 
-            cpsr = intel_int_disable();
+            cpsr = int_disable();
             tlw(led_on(LED_ERASE_SUSPEND));
 
             *addr = 0xD0; // Intel erase resume
@@ -172,7 +140,7 @@
 // changed the specification of the W30 flash! (See "1.8 Volt Intel®
 // Wireless Flash Memory with 3 Volt I/O 28F6408W30, 28F640W30, 28F320W30
 // Specification Update")
-			*addr = 0x70; // Intel Read Status Register
+	    *addr = 0x70; // Intel Read Status Register
 
             tlw(led_off(LED_ERASE_SUSPEND));
         }
@@ -181,68 +149,5 @@
 
     tlw(led_on(LED_ERASE));
     tlw(led_off(LED_ERASE));
-    intel_int_enable(cpsr);
-}
-
-// TODO: remove below function, not in use anymore.
-void ffsdrv_ram_intel_erase(uint8 block) 
-{
-    uint32 cpsr;
-    uint16 status;
-
-    ttw(ttr(TTrDrvErase, "e(%d)" NL, block));
-    tlw(led_on(LED_ERASE));
-
-    dev.addr = (uint16 *) block2addr(block);
-
-    cpsr = intel_int_disable();
-    dev.state = DEV_ERASE;
-
-    *dev.addr = 0x60; // Intel Config setup
-    *dev.addr = 0xD0; // Intel Unlock block
-
-    *dev.addr = 0x50; // Intel clear status register (not really necessary)
-    *dev.addr = 0x20; // Intel erase setup
-    *dev.addr = 0xD0; // Intel erase confirm
-
-    intel_int_enable(cpsr);
-
-    while ((*dev.addr & 0x80) == 0)
-        ;
-
-    *dev.addr = 0xFF; // Intel read array
-    dev.state = DEV_READ;
-    tlw(led_off(LED_WRITE));
+    int_enable(cpsr);
 }
-
-
-/******************************************************************************
- * Interrupt Enable/Disable
- ******************************************************************************/
-
-uint32 intel_int_disable(void)
-{
-    asm("        .state16");
-    asm("        mov       A1, #0xC0");
-    asm("        ldr       A2, tct_intel_disable");
-    asm("        bx        A2      ");
-
-    asm("tct_intel_disable 	.field     _TCT_Control_Interrupts+0,32");
-    asm("	                .global	   _TCT_Control_Interrupts");
-}
-
-void intel_int_enable(uint32 cpsr)
-{
-    asm("        .state16");
-    asm("        ldr       A2, tct_intel_enable");
-    asm("        bx        A2      ");
-
-    asm("tct_intel_enable 	.field     _TCT_Control_Interrupts+0,32");
-    asm("	                .global	   _TCT_Control_Interrupts");
-}
-
-// Even though we have this end label, we cannot determine the number of
-// constant/PC-relative data following the code!
-asm("        .state32");
-asm("        .label _ffsdrv_ram_intel_end");
-asm("        .def   _ffsdrv_ram_intel_end");