FreeCalypso > hg > freecalypso-sw
changeset 148:63750f70796d
gsm-fw/bsp/abb+spi: initial import from the Leonardo TCS211 version
| author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
|---|---|
| date | Sat, 16 Nov 2013 19:03:37 +0000 |
| parents | 4ac657b95f52 |
| children | 971e84124a6f |
| files | gsm-fw/bsp/abb+spi/abb.c gsm-fw/bsp/abb+spi/abb.h gsm-fw/bsp/abb+spi/abb_core_inth.c gsm-fw/bsp/abb+spi/abb_core_inth.h gsm-fw/bsp/abb+spi/abb_inline.h gsm-fw/bsp/abb+spi/abb_inth.c gsm-fw/bsp/abb+spi/abb_inth.h gsm-fw/bsp/abb+spi/spi_api.c gsm-fw/bsp/abb+spi/spi_api.h gsm-fw/bsp/abb+spi/spi_drv.c gsm-fw/bsp/abb+spi/spi_drv.h gsm-fw/bsp/abb+spi/spi_env.c gsm-fw/bsp/abb+spi/spi_env.h gsm-fw/bsp/abb+spi/spi_pool_size.h gsm-fw/bsp/abb+spi/spi_process.c gsm-fw/bsp/abb+spi/spi_process.h gsm-fw/bsp/abb+spi/spi_task.c gsm-fw/bsp/abb+spi/spi_task.h |
| diffstat | 18 files changed, 4130 insertions(+), 0 deletions(-) [+] |
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--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/abb.c Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,1163 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : abb.c */ +/* */ +/* Description : Functions to drive the ABB device. */ +/* The Serial Port Interface is used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0. */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.3 */ +/* */ +/* Date and time : 08/22/03 */ +/* */ +/* Previous delta : Creation */ +/* */ +/**********************************************************************************/ + +#include "l1sw.cfg" + +#include "chipset.cfg" +#include "board.cfg" +#include "rf.cfg" +#include "swconfig.cfg" +#include "sys.cfg" +#include "abb.h" +#include "l1_macro.h" +#include "l1_confg.h" +#include "clkm/clkm.h" // for wait_ARM_cycles function +#include "abb_inline.h" +#include "ulpd/ulpd.h" // for FRAME_STOP definition +#include "nucleus.h" // for NUCLEUS functions and types +#include "l1_types.h" + +#if (OP_L1_STANDALONE == 0) + #include "main/sys_types.h" + #include "rv/general.h" + #include "buzzer/buzzer.h" // for BZ_KeyBeep_OFF function +#else + #include "sys_types.h" +#endif + +#if (VCXO_ALGO == 1) + #include "l1_ctl.h" +#endif + +#if (RF_FAM == 35) + #include "l1_rf35.h" +#endif + +#if (RF_FAM == 12) + #include "tpudrv12.h" + #include "l1_rf12.h" +#endif + +#if (RF_FAM == 10) + #include "l1_rf10.h" +#endif + +#if (RF_FAM == 8) + #include "l1_rf8.h" +#endif + +#if (RF_FAM == 2) + #include "l1_rf2.h" +#endif + +#if (ABB_SEMAPHORE_PROTECTION) + +static NU_SEMAPHORE abb_sem; + +/*-----------------------------------------------------------------------*/ +/* ABB_Sem_Create() */ +/* */ +/* This function creates the Nucleus semaphore to protect ABB accesses */ +/* against preemption. */ +/* No check on the result. */ +/* */ +/*-----------------------------------------------------------------------*/ +void ABB_Sem_Create(void) +{ + // create a semaphore with an initial count of 1 and with FIFO type suspension. + NU_Create_Semaphore(&abb_sem, "ABB_SEM", 1, NU_FIFO); +} + +#endif // ABB_SEMAPHORE_PROTECTION + +/*-----------------------------------------------------------------------*/ +/* ABB_Wait_IBIC_Access() */ +/* */ +/* This function waits for the first IBIC access. */ +/* */ +/*-----------------------------------------------------------------------*/ +void ABB_Wait_IBIC_Access(void) +{ + #if (ANLG_FAM ==1) + // Wait 6 OSCAS cycles (100 KHz) for first IBIC access + // (i.e wait 60us + 10% security marge = 66us) + wait_ARM_cycles(convert_nanosec_to_cycles(66000)); + #elif ((ANLG_FAM ==2) || (ANLG_FAM == 3)) + // Wait 6 x 32 KHz clock cycles for first IBIC access + // (i.e wait 187us + 10% security marge = 210us) + wait_ARM_cycles(convert_nanosec_to_cycles(210000)); + #endif +} + + + +/*-----------------------------------------------------------------------*/ +/* ABB_Write_Register_on_page() */ +/* */ +/* This function manages all the spi serial transfer to write to an */ +/* ABB register on a specified page. */ +/* */ +/*-----------------------------------------------------------------------*/ +void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value) +{ + volatile SYS_UWORD16 status; + + // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_WR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) + + // check if the semaphore has been correctly created and try to obtain it. + // if the semaphore cannot be obtained, the task is suspended and then resumed + // as soon as the semaphore is released. + if(&abb_sem != 0) + { + NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // set the ABB page for register access + ABB_SetPage(page); + + // Write value in reg_id + ABB_WriteRegister(reg_id, value); + + // set the ABB page for register access at page 0 + ABB_SetPage(PAGE0); + + #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) + // release the semaphore only if it has correctly been created. + if(&abb_sem != 0) + { + NU_Release_Semaphore(&abb_sem); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + + +/*-----------------------------------------------------------------------*/ +/* ABB_Read_Register_on_page() */ +/* */ +/* This function manages all the spi serial transfer to read one */ +/* ABB register on a specified page. */ +/* */ +/* Returns the real data value of the register. */ +/* */ +/*-----------------------------------------------------------------------*/ +SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id) +{ + volatile SYS_UWORD16 status; + SYS_UWORD16 reg_val; + + // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_RDWR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) + + // check if the semaphore has been correctly created and try to obtain it. + // if the semaphore cannot be obtained, the task is suspended and then resumed + // as soon as the semaphore is released. + if(&abb_sem != 0) + { + NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); + } + #endif // ABB_SEMAPHORE_PROTECTION + + /* set the ABB page for register access */ + ABB_SetPage(page); + + /* Read selected ABB register */ + reg_val = ABB_ReadRegister(reg_id); + + /* set the ABB page for register access at page 0 */ + ABB_SetPage(PAGE0); + + #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) + // release the semaphore only if it has correctly been created. + if(&abb_sem != 0) + { + NU_Release_Semaphore(&abb_sem); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif + + return (reg_val); // Return result +} + +/*------------------------------------------------------------------------*/ +/* ABB_free_13M() */ +/* */ +/* This function sets the 13M clock working in ABB. A wait loop */ +/* is required to allow first slow access to ABB clock register. */ +/* */ +/* WARNING !! : this function must not be protected by semaphore !! */ +/* */ +/*------------------------------------------------------------------------*/ +void ABB_free_13M(void) +{ + volatile SYS_UWORD16 status; + + // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_WR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + ABB_SetPage(PAGE0); + + // This transmission frees the CLK13 in ABB. + ABB_WriteRegister(TOGBR2, 0x08); + + // Wait for first IBIC access + ABB_Wait_IBIC_Access(); + + // SW Workaround : This transmission has to be done twice. + ABB_WriteRegister(TOGBR2, 0x08); + + // Wait for first IBIC access + ABB_Wait_IBIC_Access(); + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + + + +/*------------------------------------------------------------------------*/ +/* ABB_stop_13M() */ +/* */ +/* This function stops the 13M clock in ABB. */ +/* */ +/*------------------------------------------------------------------------*/ +void ABB_stop_13M(void) +{ + volatile SYS_UWORD16 status; + + // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_WR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + ABB_SetPage(PAGE0); + + // Set ACTIVMCLK = 0. + ABB_WriteRegister(TOGBR2, 0x04); + + // Wait for first IBIC access + ABB_Wait_IBIC_Access(); + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + + + +/*------------------------------------------------------------------------*/ +/* ABB_Read_Status() */ +/* */ +/* This function reads and returns the value of VRPCSTS ABB register. */ +/* */ +/*------------------------------------------------------------------------*/ +SYS_UWORD16 ABB_Read_Status(void) +{ + volatile SYS_UWORD16 status; + SYS_UWORD16 reg_val; + + // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_WR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) + + // check if the semaphore has been correctly created and try to obtain it. + // if the semaphore cannot be obtained, the task is suspended and then resumed + // as soon as the semaphore is released. + if(&abb_sem != 0) + { + NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); + } + #endif // ABB_SEMAPHORE_PROTECTION + + ABB_SetPage(PAGE0); + + #if (ANLG_FAM == 1) || (ANLG_FAM == 2) + ABB_SetPage(PAGE0); + reg_val = ABB_ReadRegister(VRPCSTS); + #elif (ANLG_FAM == 3) + ABB_SetPage(PAGE1); + reg_val = ABB_ReadRegister(VRPCCFG); + #endif + + #if ((ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) + // release the semaphore only if it has correctly been created. + if(&abb_sem != 0) + { + NU_Release_Semaphore(&abb_sem); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif + + return (reg_val); +} + +/*------------------------------------------------------------------------*/ +/* ABB_on() */ +/* */ +/* This function configures ABB registers to work in ON condition */ +/* */ +/*------------------------------------------------------------------------*/ +void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag) +{ + volatile SYS_UWORD16 status; + #if ((ANLG_FAM ==2) || (ANLG_FAM == 3)) + SYS_UWORD32 reg; + #endif + + // a possible cause of the recovery is that ABB is on Oscas => switch from Oscas to CLK13 + if (bRecoveryFlag) + { + // RESTITUTE 13MHZ CLOCK TO ABB + //--------------------------------------------------- + ABB_free_13M(); + + // RESTITUTE 13MHZ CLOCK TO ABB AGAIN (C.F. BUG1719) + //--------------------------------------------------- + ABB_free_13M(); + } + + // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_RDWR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + #if (ABB_SEMAPHORE_PROTECTION == 3) + + // check if the semaphore has been correctly created and try to obtain it. + // if the semaphore cannot be obtained, the task is suspended and then resumed + // as soon as the semaphore is released. + if(&abb_sem != 0) + { + NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); + } + #endif // ABB_SEMAPHORE_PROTECTION + + ABB_SetPage(PAGE0); + + // This transmission disables MADC,AFC,VDL,VUL modules. + ABB_WriteRegister(TOGBR1, 0x0155); + + #if (ANLG_FAM == 1) + // This transmission disables Band gap fast mode Enable BB charge. + ABB_WriteRegister(VRPCCTL2, 0x1fc); + + /* *********** DC/DC enabling selection ************************************************************** */ + // This transmission changes the register page in OMEGA for usp to pg1. + ABB_SetPage(PAGE1); + + /* Insert here accesses to modify DC/DC parameters. Default is a switching frequency of 240 Khz */ + { + SYS_UWORD8 vrpcctrl3_data; + + #if (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) + vrpcctrl3_data = 0x007d; // core voltage 1.4V for C035 + #else + vrpcctrl3_data = 0x00bd; // core voltage 1.8V for C05 + #endif + + if(modules & DCDC) // check if the DCDC is enabled + { + vrpcctrl3_data |= 0x0002; // set DCDCEN + } + + // This access disables the DCDC. + ABB_WriteRegister(VRPCCTRL3, vrpcctrl3_data); + } + + /* ************************ SELECTION OF TEST MODE FOR ABB **************************************** */ + /* This test configuration allows visibility on BULENA,BULON,BDLON,BDLENA on test pins */ + /* ***************************************************************************************************/ + #if (BOARD==6)&& (ANLG_FAM==1) //BUG01967 to remove access to TAPCTRL (EVA4 board and Nausica) + // This transmission enables Omega test register. + ABB_WriteRegister(TAPCTRL, 0x01); + + // This transmission select Omega test instruction. + ABB_WriteRegister(TAPREG, TSPTEST1); + + // This transmission disables Omega test register. + ABB_WriteRegister(TAPCTRL, 0x00); + #endif + /* *************************************************************************************************** */ + + if (!bRecoveryFlag) // Check recovery status from L1, prevent G23 SIM issue + { + // This transmission changes SIM power supply to 3 volts. + ABB_WriteRegister(VRPCCTRL1, 0x45); + } + + ABB_SetPage(PAGE0); + + // This transmission enables selected OMEGA modules. + ABB_WriteRegister(TOGBR1, (modules & ~DCDC) >> 6); + + if(modules & MADC) // check if the ADC is enabled + { + // This transmission connects the resistive divider to MB and BB. + ABB_WriteRegister(BCICTL1, 0x0005); + } + #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) + // Restore the ABB checks and debouncing if start on TESTRESETZ + + // This transmission changes the register page in the ABB for usp to pg1. + ABB_SetPage(PAGE1); + + // This transmission sets the AFCCK to CKIN/2. + ABB_WriteRegister(AFCCTLADD, 0x01); + + // This transmission enables the tapreg. + ABB_WriteRegister(TAPCTRL, 0x01); + + // This transmission enables access to page 2. + ABB_WriteRegister(TAPREG, 0x01b); + + // This transmission changes the register page in the ABB for usp to pg2. + ABB_SetPage(PAGE2); + + #if (ANLG_FAM == 2) + // Restore push button environment + ABB_WriteRegister(0x3C, 0x07); + + #elif (ANLG_FAM == 3) + + // Restore push button environment + ABB_WriteRegister(0x3C, 0xBF); + + /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG1_0 *******************************/ + #if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE + ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register + #endif + // This transmission enables access to page 0. + ABB_SetPage(PAGE0); + + // reset bit MSKINT1 , if set by TESTRESET + reg=ABB_ReadRegister(VRPCSTS) & 0xffe; + + ABB_WriteRegister(VRPCSTS, reg); + + ABB_SetPage(PAGE2); + + // Restore default for BG behavior in sleep mode + ABB_WriteRegister(VRPCAUX, 0xBF); + + // Restore default for deboucing length + ABB_WriteRegister(VRPCLDO, 0x00F); + + // Restore default for INT1 generation, wait time in switch on, checks in switch on + ABB_WriteRegister(VRPCABBTST, 0x0002); + + #endif + + // This transmission changes the register page in the ABB for usp to pg1. + ABB_SetPage(PAGE1); + + // This transmission sets tapinst to id code. + ABB_WriteRegister(TAPREG, 0x0001); + + // This transmission disables TAPREG access. + ABB_WriteRegister(TAPCTRL, 0x00); + + // enable BB battery charge BCICONF register, enable test mode to track BDLEN and BULEN windows + // This transmission enables BB charge and BB bridge connection for BB measurements. + ABB_WriteRegister(BCICONF, 0x060); + + /* ************************ SELECTION OF BBCFG CONFIG FOR ABB 3 PG2_0 *******************************/ + #if (ANLG_FAM == 3) + #if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO + ABB_WriteRegister(BBCFG, C_BBCFG); // Initialize transmit register + #endif + #endif + + /* ************************ SELECTION OF TEST MODE FOR ABB ******************************************/ + /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ + /* ****************************************************************************************************/ + + // This transmission enables the tapreg. + ABB_WriteRegister(TAPCTRL, 0x01); + + // This transmission select ABB test instruction. + ABB_WriteRegister(TAPREG, TSPEN); + + // This transmission changes the register page in ABB for usp to pg0. + ABB_SetPage(PAGE0); + + // This transmission enables selected ABB modules. + ABB_WriteRegister(TOGBR1, modules >> 6); + + // enable MB & BB resistive bridges for measurements + if(modules & MADC) // check if the ADC is enabled + { + // This transmission connects the resistive divider to MB and BB. + ABB_WriteRegister(BCICTL1, 0x0001); + } + + /********* Sleep definition part ******************/ + // This transmission changes the register page in the ABB for usp to pg1. + #if (ANLG_FAM == 2) + ABB_SetPage(PAGE1); + + // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. + reg = ABB_ReadRegister(VRPCCFG) & 0x1e0; + + ABB_WriteRegister(VRPCCFG, (SLPDLY | reg)); + + // update the ABB mask sleep register (regulator disabled in deep sleep), and clear previous mask value. + reg = ABB_ReadRegister(VRPCMSK) & 0x1e0; + ABB_WriteRegister(VRPCMSK, (MASK_SLEEP_MODE | reg)); + #elif (ANLG_FAM == 3) + Syren_Sleep_Config(NORMAL_SLEEP,SLEEP_BG,SLPDLY); + #endif + // This transmission changes the register page in the ABB for usp to pg0. + ABB_SetPage(PAGE0); + #endif + + // SW workaround for initialization of the audio parts of the ABB to avoid white noise + // C.f. BUG1941 + // Set VDLR and VULR bits + // Write TOGBR1 register + // This transmission enables selected ABB modules. + ABB_WriteRegister(TOGBR1, 0x0A); + + // wait for 1 ms + wait_ARM_cycles(convert_nanosec_to_cycles(1000000)); + + // Reset VDLS and VULS bits + // Write TOGBR1 register + // This transmission enables selected ABB modules. + ABB_WriteRegister(TOGBR1, 0x05); + + #if (ABB_SEMAPHORE_PROTECTION == 3) + // release the semaphore only if it has correctly been created. + if(&abb_sem != 0) + { + NU_Release_Semaphore(&abb_sem); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + + + +/*-----------------------------------------------------------------------*/ +/* ABB_Read_ADC() */ +/* */ +/* This function manages all the spi serial transfer to read all the */ +/* ABB ADC conversion channels. */ +/* Stores the result in Buff parameter. */ +/* */ +/*-----------------------------------------------------------------------*/ +void ABB_Read_ADC(SYS_UWORD16 *Buff) +{ + volatile SYS_UWORD16 status; + + // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_RDWR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + #if (ABB_SEMAPHORE_PROTECTION == 3) + + // check if the semaphore has been correctly created and try to obtain it. + // if the semaphore cannot be obtained, the task is suspended and then resumed + // as soon as the semaphore is released. + if(&abb_sem != 0) + { + NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // This transmission changes the register page in the ABB for usp to pg0. + ABB_SetPage(PAGE0); + + /* Read all ABB ADC registers */ + *Buff++ = ABB_ReadRegister(VBATREG); + *Buff++ = ABB_ReadRegister(VCHGREG); + *Buff++ = ABB_ReadRegister(ICHGREG); + *Buff++ = ABB_ReadRegister(VBKPREG); + *Buff++ = ABB_ReadRegister(ADIN1REG); + *Buff++ = ABB_ReadRegister(ADIN2REG); + *Buff++ = ABB_ReadRegister(ADIN3REG); + + #if (ANLG_FAM ==1) + *Buff++ = ABB_ReadRegister(ADIN4XREG); + *Buff++ = ABB_ReadRegister(ADIN5YREG); + #elif (ANLG_FAM ==2) + *Buff++ = ABB_ReadRegister(ADIN4REG); + #elif (ANLG_FAM == 3) + *Buff++ = ABB_ReadRegister(ADIN4REG); + *Buff++ = ABB_ReadRegister(ADIN5REG); + #endif // ANLG_FAM + + #if (ABB_SEMAPHORE_PROTECTION == 3) + // release the semaphore only if it has correctly been created. + if(&abb_sem != 0) + { + NU_Release_Semaphore(&abb_sem); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + + + +/*-----------------------------------------------------------------------*/ +/* ABB_Conf_ADC() */ +/* */ +/* This function manages all the spi serial transfer to: */ +/* - select the ABB ADC channels to be converted */ +/* - enable/disable EOC interrupt */ +/* */ +/*-----------------------------------------------------------------------*/ +void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal) +{ + volatile SYS_UWORD16 status; + SYS_UWORD16 reg_val; + + // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_RDWR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + #if (ABB_SEMAPHORE_PROTECTION == 3) + + // check if the semaphore has been correctly created and try to obtain it. + // if the semaphore cannot be obtained, the task is suspended and then resumed + // as soon as the semaphore is released. + if(&abb_sem != 0) + { + NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // This transmission changes the register page in the ABB for usp to pg0. + ABB_SetPage(PAGE0); + + /* select ADC channels to be converted */ + #if (ANLG_FAM == 1) + ABB_WriteRegister(MADCCTRL1, Channels); + #elif ((ANLG_FAM == 2) || (ANLG_FAM == 3)) + ABB_WriteRegister(MADCCTRL, Channels); + #endif + + reg_val = ABB_ReadRegister(ITMASK); + + // This transmission configure the End Of Conversion IT without modifying other bits in the same register. + if(ItVal == EOC_INTENA) + ABB_WriteRegister(ITMASK, reg_val & EOC_INTENA); + else if(ItVal == EOC_INTMASK) + ABB_WriteRegister(ITMASK, reg_val | EOC_INTMASK); + + #if (ABB_SEMAPHORE_PROTECTION == 3) + // release the semaphore only if it has correctly been created. + if(&abb_sem != 0) + { + NU_Release_Semaphore(&abb_sem); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + + + + +/*------------------------------------------------------------------------*/ +/* ABB_sleep() */ +/* */ +/* This function disables the DCDC and returns to PAGE 0. It stops then */ +/* the 13MHz clock in ABB. A wait loop s required to allow */ +/* first slow access to ABB clock register. */ +/* */ +/* WARNING !! : this function must not be protected by semaphore !! */ +/* */ +/* Returns AFC value. */ +/* */ +/*------------------------------------------------------------------------*/ +SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) +{ + volatile SYS_UWORD16 status; + SYS_UWORD32 afcout_index; + volatile SYS_UWORD16 nb_it; + SYS_UWORD16 reg_val; + + // table for AFC allowed values during Sleep mode. First 5th elements + // are related to positive AFC values, last 5th to negative ones. + SYS_UWORD32 Afcout_T[10]= {0x0f,0x1f,0x3f,0x7f,0xff,0x00,0x01,0x03,0x07,0x0f}; + + // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_RDWR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + // COMPUTATION AND PROGRAMMING OF AFC VALUE + //--------------------------------------------------- + if(afc & 0x1000) + afcout_index = ((afc + 512)>>10) + 1; + else + afcout_index = (afc + 512)>>10; + + if (sleep_performed == FRAME_STOP) // Big sleep + { + #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) + //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP //////////////////////////// + #endif + + } + else // Deep sleep + { + #if(ANLG_FAM == 1) + // SELECTION OF AFC TEST MODE FOR OMEGA + //--------------------------------------------------- + // This test configuration allows access on the AFCOUT register + ABB_SetPage(PAGE1); + + // This transmission enables OMEGA test register. + ABB_WriteRegister(TAPCTRL, 0x01); + + // This transmission selects OMEGA test instruction. + ABB_WriteRegister(TAPREG, AFCTEST); + + // Set AFCOUT to 0. + ABB_WriteRegister(AFCOUT, 0x00 >> 6); + + ABB_SetPage(PAGE0); + + #elif (ANLG_FAM == 2) + // This configuration allows access on the AFCOUT register + ABB_SetPage(PAGE1); + + // Read AFCCTLADD value and enable USP access to AFCOUT register + reg_val = (ABB_ReadRegister(AFCCTLADD) | 0x04); + + ABB_WriteRegister(AFCCTLADD, reg_val); + + // Set AFCOUT to 0. + ABB_WriteRegister(AFCOUT, 0x00); + + // Read BCICONF value and cut the measurement bridge of BB cut the BB charge. + reg_val = ABB_ReadRegister(BCICONF) & 0x039f; + + ABB_WriteRegister(BCICONF, reg_val); + + // Disable the ABB test mode + ABB_WriteRegister(TAPCTRL, 0x00); + + ABB_SetPage(PAGE0); + + // Read BCICTL1 value and cut the measurement bridge of MB. + reg_val = ABB_ReadRegister(BCICTL1) & 0x03fe; + + ABB_WriteRegister(BCICTL1, reg_val); + #endif + + #if (ANLG_FAM == 3) // Nothing to be done as MB and BB measurement bridges are automatically disconnected + // in Syren during sleep mode. BB charge stays enabled + ABB_SetPage(PAGE1); // Initialize transmit reg_num. This transmission + // change the register page in IOTA for usp to pg1 + + ABB_WriteRegister(TAPCTRL, 0x00); // Disable Syren test mode + + ABB_SetPage(PAGE0); + #endif + + // switch off MADC, AFC, AUXDAC, VOICE. + ABB_WriteRegister(TOGBR1, 0x155); + + // Switch off Analog supply LDO + //----------------------------- + #if (ANLG_FAM == 1) + ABB_SetPage(PAGE1); + + // Read VRPCCTL3 register value and switch off VR3. + reg_val = ABB_ReadRegister(VRPCCTRL3) & 0x3df; + + ABB_WriteRegister(VRPCCTRL3, reg_val); + + #elif (ANLG_FAM == 2) + // Read VRPCSTS register value and extract status of meaningfull inputs. + reg_val = ABB_ReadRegister(VRPCSTS) & 0x0070; + + if (reg_val == 0x30) + { + // start the SLPDLY counter in order to switch the ABB in sleep mode. This transmission sets IOTA sleep bit. + ABB_WriteRegister(VRPCDEV, 0x02); + } + + // Dummy transmission to clean of ABB bus. This transmission accesses IOTA address 0 in "read". + ABB_WriteRegister(0x0000 | 0x0001, 0x0000); + + #elif (ANLG_FAM == 3) + // In Syren there is no need to check for VRPCCFG as wake up prioritys are changed + // start the SLPDLY counter in order to switch the ABB in sleep mode + ABB_WriteRegister(VRPCDEV,0x02); // Initialize transmit reg_num. This transmission + // set Syren sleep bit +/* + // Dummy transmission to clean of ABB bus. This transmission accesses SYREN address 0 in "read". + ABB_WriteRegister(0x0000 | 0x0001, 0x0000); +*/ + #endif + + // Switch to low frequency clock + ABB_stop_13M(); + } + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif + +#if (OP_L1_STANDALONE == 1) + #if (CHIPSET == 12) + // GPIO_InitAllPull(ALL_ONE); // enable all GPIO internal pull + // workaround to set APLL_DIV_CLK( internal PU) at high level + // by default APLL_DIV_CLK is low pulling 80uA on VRIO +// *(SYS_UWORD16*) (0xFFFFFD90)= 0x01;//CNTL_APLL_DIV_CLK -> APLL_CLK_DIV != 0 +// *(SYS_UWORD16*) (0xFFFEF030)= 0x10;// DPLL mode + #endif +#endif + return(Afcout_T[afcout_index]); +} + + +/*------------------------------------------------------------------------*/ +/* ABB_wakeup() */ +/* */ +/* This function sets the 13MHz clock working in ABB. A wait loop */ +/* is required to allow first slow access to ABB clock register. */ +/* Then it re-enables DCDC and returns to PAGE 0. */ +/* */ +/* WARNING !! : this function must not be protected by semaphore !! */ +/* */ +/*------------------------------------------------------------------------*/ +void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc) +{ + volatile SYS_UWORD16 status; + SYS_UWORD16 reg_val; + + // Start spi clock, mask IT for RD and WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_RDWR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + if (sleep_performed == FRAME_STOP) // Big sleep + { + #if ((ANLG_FAM == 2) || (ANLG_FAM == 3)) + //////////// ADD HERE IOTA or SYREN CONFIGURATION FOR BIG SLEEP WAKEUP //////////////////////////// + #endif + } + else // Deep sleep + { + #if (OP_L1_STANDALONE == 1) + #if (CHIPSET == 12) + // restore context from + // workaround to set APLL_DIV_CLK( internal PU) at high level + // by default APLL_DIV_CLK is low pulling 80uA on VRIO +// *(SYS_UWORD16*) (0xFFFFFD90)= 0x00;//CNTL_APLL_DIV_CLK -> APLL_DIV_CLK != 0 +// *(SYS_UWORD16*) (0xFFFEF030)= 0x00;// DPLL mode + #endif + #endif + + // Restitutes 13MHZ Clock to ABB + ABB_free_13M(); + + // Switch ON Analog supply LDO + #if (ANLG_FAM == 1) + ABB_SetPage(PAGE1); + + // Read VRPCCTL3 register value and switch on VR3. + reg_val = ABB_ReadRegister(VRPCCTRL3) | 0x020; + + ABB_WriteRegister(VRPCCTRL3, reg_val); + ABB_SetPage(PAGE0); + #endif + + // This transmission switches on MADC, AFC. + ABB_WriteRegister(TOGBR1, 0x280); + + // This transmission sets the AUXAFC2. + ABB_WriteRegister(AUXAFC2, ((afc>>10) & 0x7)); + + // This transmission sets the AUXAFC1. + ABB_WriteRegister(AUXAFC1, (afc & 0x3ff)); + + #if (ANLG_FAM == 1) + // Remove AFC test mode + ABB_SetPage(PAGE1); + + // This transmission select Omega test instruction. + ABB_WriteRegister(TAPREG, TSPTEST1); + + // Disable test mode selection + // This transmission disables Omega test register. + ABB_WriteRegister(TAPCTRL, 0x00 >> 6); + + ABB_SetPage(PAGE0); + + #elif (ANLG_FAM == 2) + ABB_SetPage(PAGE1); + + // Read AFCCTLADD register value and disable USP access to AFCOUT register. + reg_val = ABB_ReadRegister(AFCCTLADD) & ~0x04; + + ABB_WriteRegister(AFCCTLADD, reg_val); + + // Read BCICONF register value and enable BB measurement bridge enable BB charge. + reg_val = ABB_ReadRegister(BCICONF) | 0x0060; + + ABB_WriteRegister(BCICONF, reg_val); + + + /* *************************************************************************************************** */ + // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. + reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; + ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); + + // Enable the ABB test mode + ABB_WriteRegister(TAPCTRL, 0x01); + ABB_WriteRegister(TAPREG, TSPEN); + ABB_SetPage(PAGE0); + + // Read BCICTL1 register value and enable MB measurement bridge and cut the measurement bridge of MB. + reg_val = ABB_ReadRegister(BCICTL1) | 0x0001; + + ABB_WriteRegister(BCICTL1, reg_val); + #endif + + #if (ANLG_FAM == 3) + + ABB_SetPage(PAGE1); + + /* *************************************************************************************************** */ + // update the Delay needed by the ABB before going in deep sleep, and clear previous delay value. + reg_val = ABB_ReadRegister(VRPCCFG) & 0x1e0; + ABB_WriteRegister(VRPCCFG, (SLPDLY | reg_val)); + + /* ************************ SELECTION OF TEST MODE FOR ABB=3 *****************************************/ + /* This test configuration allows visibility on test pins TAPCTRL has not to be reset */ + /* ****************************************************************************************************/ + + ABB_WriteRegister(TAPCTRL, 0x01); // Initialize the transmit register + // This transmission enables IOTA test register + + ABB_WriteRegister(TAPREG, TSPEN); + // This transmission select IOTA test instruction + // This transmission select IOTA test instruction + /**************************************************************************************************** */ + + ABB_SetPage(PAGE0); // Initialize transmit reg_num. This transmission + #endif + } + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + +/*------------------------------------------------------------------------*/ +/* ABB_wa_VRPC() */ +/* */ +/* This function initializes the VRPCCTRL1 or VRPCSIM register */ +/* according to the ABB used. */ +/* */ +/*------------------------------------------------------------------------*/ +void ABB_wa_VRPC(SYS_UWORD16 value) +{ + volatile SYS_UWORD16 status; + + // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_WR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) + + // check if the semaphore has been correctly created and try to obtain it. + // if the semaphore cannot be obtained, the task is suspended and then resumed + // as soon as the semaphore is released. + if(&abb_sem != 0) + { + NU_Obtain_Semaphore(&abb_sem, NU_SUSPEND); + } + #endif // ABB_SEMAPHORE_PROTECTION + + ABB_SetPage(PAGE1); + + #if (ANLG_FAM == 1) + // This transmission initializes the VRPCCTL1 register. + ABB_WriteRegister(VRPCCTRL1, value); + + #elif (ANLG_FAM == 2) + // This transmission initializes the VRPCSIM register. + ABB_WriteRegister(VRPCSIM, value); + + #elif (ANLG_FAM == 3) + // This transmission initializes the VRPCSIMR register. + ABB_WriteRegister(VRPCSIMR, value); + + #endif + + ABB_SetPage(PAGE0); + + #if ((ABB_SEMAPHORE_PROTECTION == 1) || (ABB_SEMAPHORE_PROTECTION == 2) || (ABB_SEMAPHORE_PROTECTION == 3)) + // release the semaphore only if it has correctly been created. + if(&abb_sem != 0) + { + NU_Release_Semaphore(&abb_sem); + } + #endif // ABB_SEMAPHORE_PROTECTION + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + + +/*-----------------------------------------------------------------------*/ +/* ABB_Write_Uplink_Data() */ +/* */ +/* This function uses the SPI to write to ABB uplink buffer. */ +/* */ +/*-----------------------------------------------------------------------*/ +void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data) +{ + SYS_UWORD8 i; + volatile SYS_UWORD16 status; + + // Start spi clock, mask IT for WR and read SPI_REG_STATUS to reset the RE and WE flags. + SPI_Ready_for_WR + status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS; + + // Select Page 0 for TOGBR2 + ABB_SetPage(PAGE0); + + // Initialize pointer of burst buffer 1 : IBUFPTR is bit 10 of TOGBR2 + ABB_WriteRegister(TOGBR2, 0x10); + + // Clear, assuming that it works like IBUFPTR of Vega + ABB_WriteRegister(TOGBR2, 0x0); + + // Write the ramp data + for (i=0;i<16;i++) + ABB_WriteRegister(BULDATA1_2, TM_ul_data[i]>>6); + + // Stop the SPI clock + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + +//////////////////////// IDEV-INLO integration of sleep mode for Syren /////////////////////////////////////// + +#if (ANLG_FAM == 3) + + // Syren Sleep configuration function -------------------------- + void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay) + { + volatile SYS_UWORD16 status,sl_ldo_stat; + + ABB_SetPage(PAGE1); // Initialize transmit register. This transmission + // change the register page in ABB for usp to pg1 + + ABB_WriteRegister(VRPCCFG, sleep_delay); // write delay value + + sl_ldo_stat = ((sleep_type<<9|bg_select<<8) & 0x0374); + + ABB_WriteRegister(VRPCMSKSLP, sl_ldo_stat); // write sleep ldo configuration + + ABB_SetPage(PAGE0); // Initialize transmit register. This transmission + // change the register page in ABB for usp to pg0 + } +#endif + + +#if (OP_L1_STANDALONE == 0) +/*-----------------------------------------------------------------------*/ +/* ABB_Power_Off() */ +/* */ +/* This function uses the SPI to switch off the ABB. */ +/* */ +/*-----------------------------------------------------------------------*/ +void ABB_Power_Off(void) +{ + // Wait until all necessary actions are performed (write in FFS, etc...) to power-off the board (empirical value - 30 ticks). + NU_Sleep (30); + + // Wait also until <ON/OFF> key is released. + // This is needed to avoid, if the power key is pressed for a long time, to switch + // ON-switch OFF the mobile, until the power key is released. + #if((ANLG_FAM == 1) || (ANLG_FAM == 2)) + while ((ABB_Read_Status() & ONREFLT) == PWR_OFF_KEY_PRESSED) { + #elif(ANLG_FAM == 3) + while ((ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND) == PWR_OFF_KEY_PRESSED) { + #endif + + NU_Sleep (1); } + + BZ_KeyBeep_OFF(); + + #if(ANLG_FAM == 1) + ABB_Write_Register_on_page(PAGE0, VRPCCTL2, 0x00EE); + #elif((ANLG_FAM == 2) || (ANLG_FAM == 3)) + ABB_Write_Register_on_page(PAGE0, VRPCDEV, 0x0001); + #endif +} +#endif + + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/abb.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,686 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : abb.h */ +/* */ +/* Description : Analog BaseBand registers and bits definition. */ +/* Functions to drive the ABB device. */ +/* The Serial Port Interface is used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0. */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.3 */ +/* */ +/* Date and time : 08/22/03 */ +/* */ +/* Previous delta : Creation */ +/* */ +/**********************************************************************************/ + +#ifndef __ABB_H__ +#define __ABB_H__ + +#include "l1sw.cfg" + +#if (OP_L1_STANDALONE == 0) + #include "main/sys_types.h" +#else + #include "sys_types.h" +#endif + + +#ifndef _WINDOWS + + +#include "chipset.cfg" + + + + +/*------------------------------------*/ +/* SYREN PG Definition */ +/*------------------------------------*/ + +#if (ANLG_FAM == 3) // SYREN + #define S_PG_10 1 + #define S_PG_20 2 +#endif // (ANLG_FAM == 3) + + + +// DEFINITIONS FOR OMEGA/NAUSICA +#if (ANLG_FAM == 1) + // ABB PAGE + #define PAGE0 0x0001 + #define PAGE1 0x0002 + + // ABB REGISTERS + //=== PAGE 0 ======= + #define PAGEREG (1 << 1) + #define APCDEL1 (2 << 1) + #define BULDATA1_2 (3 << 1) + #define TOGBR1 (4 << 1) + #define TOGBR2 (5 << 1) + #define VBDCTRL (6 << 1) + #define AUXAFC1 (7 << 1) + #define AUXAFC2 (8 << 1) + #define AUXAPC (9 << 1) + #define APCRAM (10 << 1) + #define APCOFF (11 << 1) + #define AUXDAC (12 << 1) + #define MADCCTRL1 (13 << 1) + #define MADCCTRL2 (14 << 1) + #define VBATREG (15 << 1) + #define VCHGREG (16 << 1) + #define ICHGREG (17 << 1) + #define VBKPREG (18 << 1) + #define ADIN1REG (19 << 1) + #define ADIN2REG (20 << 1) + #define ADIN3REG (21 << 1) + #define ADIN4XREG (22 << 1) + #define ADIN5YREG (23 << 1) + #define MADCSTAT (24 << 1) + #define CHGREG (25 << 1) + #define ITMASK (26 << 1) + #define ITSTATREG (27 << 1) + #define BCICTL1 (28 << 1) + #define BCICTL2 (29 << 1) + #define VRPCCTL2 (30 << 1) + #define VRPCSTS (31 << 1) + + //=== PAGE 1 ======= + #define PAGEREG (1 << 1) + #define BULIOFF (2 << 1) + #define BULQOFF (3 << 1) + #define BULQDAC (4 << 1) + #define BULIDAC (5 << 1) + #define BBCTRL (6 << 1) + #define VBUCTRL (7 << 1) + #define VBCTRL (8 << 1) + #define PWDNRG (9 << 1) + #define TSC_TIMER (10 << 1) + #define VRPCCTRL3 (11 << 1) + #define APCOUT (12 << 1) + #define VRPCBGT (18 << 1) + #define TAPCTRL (19 << 1) + #define TAPREG (20 << 1) + #define AFCCTLADD (21 << 1) + #define AFCOUT (22 << 1) + #define VRPCCTRL1 (23 << 1) + #define VRPCCTRL4 (24 << 1) + #define APCDEL2 (26 << 1) + #define ITSTATREG (27 << 1) + + // Registers bit definitions + // ABB device bits definition of register VBCTRL + #define VDLAUX 0x001 + #define VDLEAR 0x002 + #define VBUZ 0x004 + #define VULSWITCH 0x008 + #define MICBIAS 0x010 + #define VALOOP 0x020 + #define VCLKMODE 0x040 + #define VSYNC 0x080 + #define VBDFAUXG 0x100 + #define VFBYP 0x200 + + // ABB device bits definition of register VBUCTRL + #define DXEN 0x200 + + // ABB device bits definition of register VRPCSTS + #define ONBSTS 0x01 // ON Button push flag + #define ONRSTS 0x02 // Remote ON flag + #define ITWSTS 0x04 // Wake-up IT flag + #define CHGSTS 0x08 // Charger plug flag + #define ONREFLT 0x10 // ON Button current state + #define ORMRFLT 0x20 // Remote ON current state + #define CHGPRES 0x40 // Charger plug current state + + // ABB device bits definition of register ITSTATREG + #define REMOT_IT_STS 0x02 + #define PUSHOFF_IT_STS 0x04 + #define CHARGER_IT_STS 0x08 + #define ADCEND_IT_STS 0x20 + + // On Nausica, if the PWR key is pressed, the bit is set, and cleared when released + #define PWR_OFF_KEY_PRESSED (ONREFLT) + + // ABB ADC Interrupts + #define EOC_INTENA 0x03DF + #define EOC_INTMASK 0x0020 + + // ABB ADC CHANNELS + #define VBATCV 0x0001 + #define VCHGCV 0x0002 + #define ICHGCV 0x0004 + #define VBKPCV 0x0008 + #define ADIN1CV 0x0010 + #define ADIN2CV 0x0020 + #define ADIN3CV 0x0040 + #define vADIN4XCV 0x0080 + #define ADIN5XCV 0x0100 + #define ALL 0x01FF + #define NONE 0x0000 + + // ABB MODULES + #define MADC 0x8000 + #define AFC 0x2000 + #define ADAC 0x0800 + #define DCDC 0x0080 + #define ALLOFF 0x0000 + + // Definitions of OMEGA test modes for baseband windows + #define TSPTEST1 0x001d + #define TSPTEST2 0x001e + #define AFCTEST 0x0010 + #define AFCNORM 0x0000 + + +// DEFINITIONS FOR IOTA +#elif (ANLG_FAM == 2) + // ABB PAGE + #define PAGE0 0x0001 + #define PAGE1 0x0002 + #define PAGE2 0x0010 + + // ABB REGISTERS + //=== PAGE 0 ======= + #define PAGEREG (1 << 1) + #define APCDEL1 (2 << 1) + #define BULDATA1_2 (3 << 1) + #define TOGBR1 (4 << 1) + #define TOGBR2 (5 << 1) + #define VBDCTRL (6 << 1) + #define AUXAFC1 (7 << 1) + #define AUXAFC2 (8 << 1) + #define AUXAPC (9 << 1) + #define APCRAM (10 << 1) + #define APCOFF (11 << 1) + #define AUXDAC (12 << 1) + #define MADCCTRL (13 << 1) + #define VBATREG (15 << 1) + #define VCHGREG (16 << 1) + #define ICHGREG (17 << 1) + #define VBKPREG (18 << 1) + #define ADIN1REG (19 << 1) + #define ADIN2REG (20 << 1) + #define ADIN3REG (21 << 1) + #define ADIN4REG (22 << 1) + #define MADCSTAT (24 << 1) + #define CHGREG (25 << 1) + #define ITMASK (26 << 1) + #define ITSTATREG (27 << 1) + #define BCICTL1 (28 << 1) + #define BCICTL2 (29 << 1) + #define VRPCDEV (30 << 1) + #define VRPCSTS (31 << 1) + + //=== PAGE 1 ======= + #define PAGEREG (1 << 1) + #define BULIOFF (2 << 1) + #define BULQOFF (3 << 1) + #define BULQDAC (4 << 1) + #define BULIDAC (5 << 1) + #define BBCTRL (6 << 1) + #define VBUCTRL (7 << 1) + #define VBCTRL1 (8 << 1) + #define PWDNRG (9 << 1) + #define VBPOP (10 << 1) + #define VBCTRL2 (11 << 1) + #define APCOUT (12 << 1) + #define BCICONF (13 << 1) + #define BULGCAL (14 << 1) + #define TAPCTRL (19 << 1) + #define TAPREG (20 << 1) + #define AFCCTLADD (21 << 1) + #define AFCOUT (22 << 1) + #define VRPCSIM (23 << 1) + #define AUXLED (24 << 1) + #define APCDEL2 (26 << 1) + #define ITSTATREG (27 << 1) + #define VRPCMSKABB (29 << 1) + #define VRPCCFG (30 << 1) + #define VRPCMSK (31 << 1) + + // Registers bit definitions + // ABB device bits definition of register VBCTRL1 + #define VDLAUX 0x001 + #define VDLEAR 0x002 + #define VBUZ 0x004 + #define VULSWITCH 0x008 + #define MICBIAS 0x010 + #define VALOOP 0x020 + #define VCLKMODE 0x040 + #define VSYNC 0x080 + #define VBDFAUXG 0x100 + #define VFBYP 0x200 + + // ABB device bits definition of register VBCTRL2 + #define MICBIASEL 0x001 + #define VDLHSO 0x002 + #define MICNAUX 0x004 + + // ABB device bits definition of register VBUCTRL + #define DXEN 0x200 + + // ABB device bits definition of register VBPOP + #define HSODIS 0x001 + #define HSOCHG 0x002 + #define HSOAUTO 0x004 + #define EARDIS 0x008 + #define EARCHG 0x010 + #define EARAUTO 0x020 + #define AUXDIS 0x040 + #define AUXCHG 0x080 + #define AUXAUTO 0x100 + + // ABB device bits definition of register VRPCSTS + #define ONBSTS 0x01 // ON Button push flag + #define ONRSTS 0x02 // Remote ON flag + #define ITWSTS 0x04 // Wake-up IT flag + #define CHGSTS 0x08 // Charger plug flag + #define ONREFLT 0x10 // ON Button current state + #define ORMRFLT 0x20 // Remote ON current state + #define CHGPRES 0x40 // Charger plug current state + + // ABB device bits definition of register ITSTATREG + #define REMOT_IT_STS 0x02 + #define PUSHOFF_IT_STS 0x04 + #define CHARGER_IT_STS 0x08 + #define ADCEND_IT_STS 0x20 + + // On Iota, the bit is set when the key is released and set when the key is pressed + #define PWR_OFF_KEY_PRESSED (0) + + // ABB ADC Interrupts + #define EOC_INTENA 0x03DF + #define EOC_INTMASK 0x0020 + + // ABB ADC CHANNELS + #define VBATCV 0x0001 + #define VCHGCV 0x0002 + #define ICHGCV 0x0004 + #define VBKPCV 0x0008 + #define ADIN1CV 0x0010 + #define ADIN2CV 0x0020 + #define ADIN3CV 0x0040 + #define ADIN4CV 0x0080 + #define ALL 0x00FF + #define NONE 0x0000 + + // ABB MODULES + #define MADC 0x8000 + #define AFC 0x2000 + #define ADAC 0x0800 + #define DCDC 0x0080 + #define ALLOFF 0x0000 + + // Definitions of IOTA test modes + #define TSPTEST1 0x001d + #define TSPTEST2 0x001e + #define AFCTEST 0x0010 + #define AFCNORM 0x0000 + + // Definition for IOTA test modes + #define TSPEN 0x001a + #define MADCTEST 0x0012 + #define TSPADC 0x0015 + #define TSPUP 0x0017 + #define TSPDN 0x0018 + + // Definition for IOTA Power Management + + //The duration of the SLPDLY counter must be greater than the process execution time: + //DBB deep sleep routine included the IT check = DBB sleep routine and IT check + //+ the seven 32Khz clock cycle interval needed to ABB in order to make effective the sleep abort write access in VRPCDEV ++ // register -> 7*T32Khz = = ABB IBIC propagation delay + //+ 150us of short asynchronous wake-up time (approximately 4*T32Khz) = ULPD short sleep where Syren/IOTA aborts sleep and + // write DEVSLEEP = 0 + + + + + #define SLPDLY 0x001F // delay to set IOTA in sleep mode (unit: 20*T32Khz) + #define MASK_SLEEP_MODE 0x0000 // set the regulators in low consumption in sleep mode + + +// DEFINITIONS FOR SYREN +#elif (ANLG_FAM == 3) + + // ABB PAGE + #define PAGE0 0x0001 + #define PAGE1 0x0002 + #define PAGE2 0x0010 + + // ABB REGISTERS + //=== PAGE 0 ======= + #define PAGEREG (1 << 1) + #define APCDEL1 (2 << 1) + #define BULDATA1_2 (3 << 1) + #define TOGBR1 (4 << 1) + #define TOGBR2 (5 << 1) + #define VBDCTRL (6 << 1) + #define AUXAFC1 (7 << 1) + #define AUXAFC2 (8 << 1) + #define AUXAPC (9 << 1) + #define APCRAM (10 << 1) + #define APCOFF (11 << 1) + #define AUXDAC (12 << 1) + #define MADCCTRL (13 << 1) + #define CHGIREG (14 << 1) + #define VBATREG (15 << 1) + #define VCHGREG (16 << 1) + #define ICHGREG (17 << 1) + #define VBKPREG (18 << 1) + #define ADIN1REG (19 << 1) + #define ADIN2REG (20 << 1) + #define ADIN3REG (21 << 1) + #define ADIN4REG (22 << 1) + #define ADIN5REG (23 << 1) + #define MADCSTAT (24 << 1) + #define CHGVREG (25 << 1) + #define ITMASK (26 << 1) + #define ITSTATREG (27 << 1) + #define BCICTL1 (28 << 1) + #define BCICTL2 (29 << 1) + #define VRPCDEV (30 << 1) + #define VRPCSTS (31 << 1) + + //=== PAGE 1 ======= + #define PAGEREG (1 << 1) + #define BULIOFF (2 << 1) + #define BULQOFF (3 << 1) + #define BULQDAC (4 << 1) + #define BULIDAC (5 << 1) + #define BBCTRL (6 << 1) + #define VBUCTRL (7 << 1) + #define VBCTRL1 (8 << 1) + #define PWDNRG (9 << 1) + #define VBPOP (10 << 1) + #define VBCTRL2 (11 << 1) + #define APCOUT (12 << 1) + #define BCICONF (13 << 1) + #define BULGCAL (14 << 1) + #define VAUDCTRL (15 << 1) + #define VAUSCTRL (16 << 1) + #define VAUOCTRL (17 << 1) + #define VAUDPLL (18 << 1) + #define TAPCTRL (19 << 1) + #define TAPREG (20 << 1) + #define AFCCTLADD (21 << 1) + #define AFCOUT (22 << 1) + #define VRPCSIMR (23 << 1) + #define BCIWDOG (24 << 1) + #define NONE8 (25 << 1) + #define APCDEL2 (26 << 1) + #define ITSTATREG (27 << 1) + +#if (ANLG_PG == S_PG_20) // SYREN PG2.0 ON EVACONSO + #define BBCFG (28 << 1) +#else + #define NONE9 (28 << 1) +#endif + + #define VRPCMSKOFF (29 << 1) + #define VRPCCFG (30 << 1) + #define VRPCMSKSLP (31 << 1) + + //=== PAGE 2 ======= + +#if (ANLG_PG == S_PG_10) // SYREN PG1.0 ON ESAMPLE + #define BBCFG (5 << 1) +#endif + + #define VRPCABBTST (25 << 1) + #define VRPCAUX (30 << 1) + #define VRPCLDO (31 << 1) + +/* INSERT HERE OTHER DEVICES REGISTERS */ + + + // Registers bit definitions + /*** SYREN internal control bits ***/ + + /** For reg. VBCTRL1 **/ + #define VULSWITCH 0x008 + #define MICBIAS 0x010 + #define VALOOP 0x020 + #define VCLKMODE 0x040 + #define VSYNC 0x080 + #define VBDFAUXG 0x100 + #define VFBYP 0x200 + + /** For reg. VBCTRL2 **/ + #define HSMICSEL 0x001 + #define MICBIASEL 0x004 + #define SPKG 0x008 + #define HSOVMID 0x010 + #define HSDIF 0x020 + + /** For reg. VBUCTRL **/ + #define DXEN 0x200 + + /** For reg. VBPOP **/ + #define HSODIS 0x001 + #define HSOCHG 0x002 + #define HSOAUTO 0x004 + #define EARDIS 0x008 + #define EARCHG 0x010 + #define EARAUTO 0x020 + #define AUXFDIS 0x040 + #define AUXAUTO 0x080 + #define AUXFBYP 0x200 + + // ABB device bits definition of register VRPCCFG + #define PWOND 0x20 // ON Button current state + #define CHGPRES 0x40 + + // ABB device bits definition of register ITSTATREG + #define REMOT_IT_STS 0x02 + #define PUSHOFF_IT_STS 0x04 + #define CHARGER_IT_STS 0x08 + #define ADCEND_IT_STS 0x20 + + // ABB device bits definition of register VRPCSTS + #define ITWSTS 0x10 // Wake-up IT flag + #define PWONBSTS 0x20 // ON Button push flag + #define CHGSTS 0x40 // Charger plug flag + #define RPSTS 0x100 // Remote ON flag + + // ABB ADC Interrupts + #define EOC_INTENA 0x03DF + #define EOC_INTMASK 0x0020 + + // ABB ADC CHANNELS (reg. MADCCTRL) + #define VBATCV 0x0001 + #define VCHGCV 0x0002 + #define ICHGCV 0x0004 + #define VBKPCV 0x0008 + #define ADIN1CV 0x0010 + #define ADIN2CV 0x0020 + #define ADIN3CV 0x0040 + #define ADIN4CV 0x0080 + #define ADIN5CV 0x0100 + #define ALL 0x01FF + #define NONE 0x0000 + + // ABB MODULES + #define MADC 0x8000 + #define AFC 0x2000 + #define ADAC 0x0800 + #define DCDC 0x0080 + #define ALLOFF 0x0000 + + // Definitions of SYREN test modes + #define TSPTEST1 0x001d + #define TSPTEST2 0x001e + #define AFCTEST 0x0010 + #define AFCNORM 0x0000 + + #define TSPEN 0x001a + #define MADCTEST 0x0012 + #define TSPADC 0x0015 + #define TSPUP 0x0017 + #define TSPDN 0x0018 + + // Definition for SYREN Power Management + + //The duration of the SLPDLY counter must be greater than the process execution time: + //DBB deep sleep routine included the IT check = DBB sleep routine and IT check + //+ the seven 32Khz clock cycle interval needed to ABB in order to make effective the sleep abort write access in VRPCDEV ++ // register -> 7*T32Khz = = ABB IBIC propagation delay + //+ 150us of short asynchronous wake-up time (approximately 4*T32Khz) = ULPD short sleep where Syren/IOTA aborts sleep and + // write DEVSLEEP = 0 + + #define SLPDLY 0x001F // delay to set SYREN in sleep mode (unit: 20*T32Khz) + #define MASK_SLEEP_MODE 0x0000 // set the regulators in low consumption in sleep mode + + #define LOCORE_SLEEP 0x01 + #define NORMAL_SLEEP 0x00 + + #define MAIN_BG 0x01, + #define SLEEP_BG 0x00 + +#endif // ANLG_FAM == 1,2,3 + + +// Define the level of semaphore protection for all accesses to the ABB +// 0 for no protection +// 1 for protection low +// 2 for protection medium +// 3 for protection high +#if (OP_L1_STANDALONE == 1) +#define ABB_SEMAPHORE_PROTECTION (0) +#else +#define ABB_SEMAPHORE_PROTECTION (1) +#endif + + + +// PROTOTYPES +#if (ABB_SEMAPHORE_PROTECTION) + void ABB_Sem_Create(void); +#endif +void ABB_Wait_IBIC_Access(void); +void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD16 value); +SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id); +void ABB_free_13M(void); +void ABB_stop_13M(void); +SYS_UWORD16 ABB_Read_Status(void); +void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal); +void ABB_Read_ADC(SYS_UWORD16 *Buff); +void ABB_on(SYS_UWORD16 modules, SYS_UWORD8 bRecoveryFlag); +SYS_UWORD32 ABB_sleep(SYS_UWORD8 sleep_performed, SYS_WORD16 afc); +void ABB_wakeup(SYS_UWORD8 sleep_performed, SYS_WORD16 afc); +void ABB_wa_VRPC(SYS_UWORD16 value); +void ABB_Write_Uplink_Data(SYS_UWORD16 *TM_ul_data); +#if (OP_L1_STANDALONE == 0) +void ABB_Power_Off(void); +#endif +#if (ANLG_FAM ==3) + void Syren_Sleep_Config(SYS_UWORD16 sleep_type,SYS_UWORD16 bg_select, SYS_UWORD16 sleep_delay); +#endif + +#else // _WINDOWS +// DEFINITIONS FOR IOTA + // ABB PAGE + #define PAGE0 0x0001 + #define PAGE1 0x0002 + #define PAGE2 0x0010 + + // ABB REGISTERS + //=== PAGE 0 ======= + #define PAGEREG (1 << 1) + #define APCDEL1 (2 << 1) + #define BULDATA1_2 (3 << 1) + #define TOGBR1 (4 << 1) + #define TOGBR2 (5 << 1) + #define VBDCTRL (6 << 1) + #define AUXAFC1 (7 << 1) + #define AUXAFC2 (8 << 1) + #define AUXAPC (9 << 1) + #define APCRAM (10 << 1) + #define APCOFF (11 << 1) + #define AUXDAC (12 << 1) + #define MADCCTRL (13 << 1) + #define VBATREG (15 << 1) + #define VCHGREG (16 << 1) + #define ICHGREG (17 << 1) + #define VBKPREG (18 << 1) + #define ADIN1REG (19 << 1) + #define ADIN2REG (20 << 1) + #define ADIN3REG (21 << 1) + #define ADIN4REG (22 << 1) + #define MADCSTAT (24 << 1) + #define CHGREG (25 << 1) + #define ITMASK (26 << 1) + #define ITSTATREG (27 << 1) + #define BCICTL1 (28 << 1) + #define BCICTL2 (29 << 1) + #define VRPCDEV (30 << 1) + #define VRPCSTS (31 << 1) + + //=== PAGE 1 ======= + #define PAGEREG (1 << 1) + #define BULIOFF (2 << 1) + #define BULQOFF (3 << 1) + #define BULQDAC (4 << 1) + #define BULIDAC (5 << 1) + #define BBCTRL (6 << 1) + #define VBUCTRL (7 << 1) + #define VBCTRL1 (8 << 1) + #define PWDNRG (9 << 1) + #define VBPOP (10 << 1) + #define VBCTRL2 (11 << 1) + #define APCOUT (12 << 1) + #define BCICONF (13 << 1) + #define BULGCAL (14 << 1) + #define TAPCTRL (19 << 1) + #define TAPREG (20 << 1) + #define AFCCTLADD (21 << 1) + #define AFCOUT (22 << 1) + #define VRPCSIM (23 << 1) + #define AUXLED (24 << 1) + #define APCDEL2 (26 << 1) + #define ITSTATREG (27 << 1) + #define VRPCMSKABB (29 << 1) + #define VRPCCFG (30 << 1) + #define VRPCMSK (31 << 1) + + // ABB device bits definition of register VBUCTRL + #define DXEN 0x200 + + // ABB device bits definition of register VRPCSTS + #define ONBSTS 0x01 // ON Button push flag + #define ONRSTS 0x02 // Remote ON flag + #define ITWSTS 0x04 // Wake-up IT flag + #define CHGSTS 0x08 // Charger plug flag + #define ONREFLT 0x10 // ON Button current state + #define ORMRFLT 0x20 // Remote ON current state + #define CHGPRES 0x40 // Charger plug current state + + // ABB device bits definition of register ITSTATREG + #define REMOT_IT_STS 0x02 + #define PUSHOFF_IT_STS 0x04 + #define CHARGER_IT_STS 0x08 + #define ADCEND_IT_STS 0x20 + + +// PROTOTYPES +void ABB_Write_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id, SYS_UWORD32 value); +SYS_UWORD16 ABB_Read_Register_on_page(SYS_UWORD16 page, SYS_UWORD16 reg_id); +SYS_UWORD16 ABB_Read_Status(void); +void ABB_Conf_ADC(SYS_UWORD16 Channels, SYS_UWORD16 ItVal); +void ABB_Read_ADC(SYS_UWORD16 *Buff); + +#endif // _WINDOWS + +#endif // __ABB_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/abb_core_inth.c Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,223 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : abb_core_inth.c */ +/* */ +/* Description : Functions to manage the ABB device interrupt. */ +/* The Serial Port Interface is used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0, and ABB interrupt is mapped as external IT. */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.2 */ +/* */ +/* Date and time : 07/02/03 */ +/* */ +/* Previous delta : Creation */ +/* */ +/**********************************************************************************/ +/* */ +/* 17/12/03 */ +/* The original abb_inth.c has been splitted between the actual abb_inth.c */ +/* located in drv_apps directory and abb_inth_core.c located in drv_core */ +/* directory. */ +/* */ +/**********************************************************************************/ + +#include "l1sw.cfg" +#include "chipset.cfg" +#include "swconfig.cfg" +#include "sys.cfg" + +#include "l1_macro.h" +#include "l1_confg.h" +#include <string.h> +#include "abb/abb_core_inth.h" +#include "nucleus.h" + +#if (OP_L1_STANDALONE == 0) + #include "rv/rv_defined_swe.h" // for RVM_PWR_SWE +#endif + +#if (OP_L1_STANDALONE == 1) + #include "l1_types.h" +#endif + +#if (CHIPSET == 12) + #include "sys_inth.h" +#else + #include "inth/iq.h" +#endif + +#include "cust_os.h" +#include "l1_signa.h" +#include "abb/abb.h" + +#if(OP_L1_STANDALONE == 0) + #include "rvm/rvm_use_id_list.h" // for SPI_USE_ID + #include "spi/spi_env.h" + #include "spi/spi_process.h" // for ABB_EXT_IRQ_EVT + #include "power/power.h" +#endif /* (OP_L1_STANDALONE == 0) */ + + + +// Size of the HISR stack associated to the ABB interrupt +#define ABB_HISR_STACK_SIZE (512) + +static NU_HISR ABB_Hisr; +static char ABB_HisrStack[ABB_HISR_STACK_SIZE]; + + + +/*-----------------------------------------------------------------------*/ +/* Create_ABB_HISR() */ +/* */ +/* This function is called from Layer1 during initialization process */ +/* to create the HISR associated to the ABB External Interrupt. */ +/* */ +/*-----------------------------------------------------------------------*/ +void Create_ABB_HISR(void) +{ + // Fill the entire stack with the pattern 0xFE + memset (ABB_HisrStack, 0xFE, sizeof(ABB_HisrStack)); + + // Create the HISR which is called when an ABB interrupt is received. + NU_Create_HISR(&ABB_Hisr, "EXT_HISR", EXT_HisrEntry, 2, ABB_HisrStack, sizeof(ABB_HisrStack)); // lowest prty +} + + + + +/*-----------------------------------------------------------------------*/ +/* Activate_ABB_HISR() */ +/* */ +/* This function is called from the interrupt handler to activate */ +/* the HISR associated to the ABB External Interrupt. */ +/* */ +/*-----------------------------------------------------------------------*/ +SYS_BOOL Activate_ABB_HISR(void) +{ + if(NU_SUCCESS != NU_Activate_HISR(&ABB_Hisr)) + { + return 1; + } + return 0; +} + + + +/*-----------------------------------------------------------------------*/ +/* EXT_HisrEntry() */ +/* */ +/* This function is called when an ABB interrupt (external interrupt) */ +/* is received. */ +/* In a "L1_STANDALONE" environment, this IT is related to ADC. */ +/* In a complete system, this IT can have several causes. In that case, */ +/* it sends a message to the SPI task, to handle the IT in calling a */ +/* callback function. */ +/* */ +/*-----------------------------------------------------------------------*/ +void EXT_HisrEntry(void) +{ +#if (OP_L1_STANDALONE == 1) + // New code in order to test the ADC with the L1 standalone + UWORD16 data ; + xSignalHeaderRec *adc_msg; + + // Call to the low-level driver function to read the interrupt status register. + data = ABB_Read_Register_on_page(PAGE1, ITSTATREG); + + if(data & ADCEND_IT_STS) // end of ADC + { + adc_msg = os_alloc_sig(sizeof(T_CST_ADC_RESULT)); + if(adc_msg != NU_NULL) + { + adc_msg->SignalCode = CST_ADC_RESULT; + ABB_Read_ADC(&((T_CST_ADC_RESULT *)(adc_msg->SigP))->adc_result[0]); + os_send_sig(adc_msg, RRM1_QUEUE); + } + } + + #if (CHIPSET == 12) + // Unmask ABB ext interrupt + F_INTH_ENABLE_ONE_IT(C_INTH_ABB_IRQ_IT); + #else + // Unmask external (ABB) interrupt + IQ_Unmask(IQ_EXT); + #endif +#endif + +#if (OP_L1_STANDALONE == 0) + T_RV_HDR *msgPtr; + + if(SPI_GBL_INFO_PTR != NULL) + { + if(SPI_GBL_INFO_PTR->SpiTaskReady != FALSE) + { + if(rvf_get_buf (SPI_GBL_INFO_PTR->prim_id, sizeof (T_RV_HDR),(void **) &msgPtr) == RVF_RED) + { + rvf_send_trace ("SPI ERROR: ABB IQ External not possible. Reason: Not enough memory", + 66, + NULL_PARAM, + RV_TRACE_LEVEL_ERROR, + SPI_USE_ID); + + /* Unmask External interrupt */ + #if (CHIPSET == 12) + // Unmask ABB ext interrupt + F_INTH_ENABLE_ONE_IT(C_INTH_ABB_IRQ_IT); + #else + // Unmask external (ABB) interrupt + IQ_Unmask(IQ_EXT); + #endif + } + else // enough memory => normal processing : a message is sent to the SPI task. + { + msgPtr->msg_id = ABB_EXT_IRQ_EVT; + msgPtr->dest_addr_id = SPI_GBL_INFO_PTR->addr_id; + msgPtr->callback_func = (CALLBACK_FUNC) spi_abb_read_int_reg_callback; + + rvf_send_msg (SPI_GBL_INFO_PTR->addr_id, msgPtr); + } + } + else // SpiTaskReady is false + { + rvf_send_trace("ABB IQ External not possible. Reason: SPI Task not ready",56, NULL_PARAM, + RV_TRACE_LEVEL_ERROR, SPI_USE_ID); + + /* Unmask External interrupt */ + #if (CHIPSET == 12) + // Unmask ABB ext interrupt + F_INTH_ENABLE_ONE_IT(C_INTH_ABB_IRQ_IT); + #else + // Unmask external (ABB) interrupt + IQ_Unmask(IQ_EXT); + #endif + } + } + else // SPI_GBL_INFO_PTR = NULL + { + rvf_send_trace("ABB IQ External ERROR. Reason: SPI task not started",51, NULL_PARAM, + RV_TRACE_LEVEL_ERROR, SPI_USE_ID); + + /* Unmask External interrupt */ + #if (CHIPSET == 12) + // Unmask ABB ext interrupt + F_INTH_ENABLE_ONE_IT(C_INTH_ABB_IRQ_IT); + #else + // Unmask external (ABB) interrupt + IQ_Unmask(IQ_EXT); + #endif + } +#endif +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/abb_core_inth.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,81 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : abb_core_inth.h */ +/* */ +/* Description : Functions to manage the ABB device interrupt. */ +/* The Serial Port Interface is used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0, and ABB interrupt is mapped as external IT. */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.0 */ +/* */ +/* Date and time : Jan 2003 */ +/* */ +/* Previous delta : Creation */ +/* */ +/**********************************************************************************/ +/* */ +/* 17/12/03 */ +/* The original abb_inth.h has been splitted between the actual abb_inth.h */ +/* located in drv_apps directory and abb_inth_core.h located in drv_core */ +/* directory. */ +/* */ +/**********************************************************************************/ + +#ifndef __ABB_CORE_INTH_H__ +#define __ABB_CORE_INTH_H__ + + #include "l1sw.cfg" + + #if (OP_L1_STANDALONE == 0) + #include "main/sys_types.h" + #else + #include "sys_types.h" + #endif + + #ifndef _WINDOWS + + #include "chipset.cfg" + + // Structure definition for ADC READING RESULT REPORTS + // Define the maximum number of measures performed by the MADC module + #if ((ANLG_FAM == 1) || (ANLG_FAM == 3)) + #define MADC_NUMBER_OF_MEAS (9) + #endif + #if (ANLG_FAM == 2) + #define MADC_NUMBER_OF_MEAS (8) + #endif + + typedef struct + { + SYS_UWORD16 adc_result[MADC_NUMBER_OF_MEAS]; + } T_CST_ADC_RESULT; + + #else // _WINDOWS + + #define MADC_NUMBER_OF_MEAS (8) + + #endif // _WINDOWS + + + // PROTOTYPES + #ifndef _WINDOWS + void Create_ABB_HISR(void); + SYS_BOOL Activate_ABB_HISR(void); + #endif // _WINDOWS + + void EXT_HisrEntry(void); + + +#endif // __ABB_CORE_INTH_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/abb_inline.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,131 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : abb_inline.h */ +/* */ +/* Description : inline functions to drive the ABB device. */ +/* The Serial Port Interface is used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0. */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.0 */ +/* */ +/* Date and time : Dec 2002 */ +/* */ +/* Previous delta : Creation */ +/* */ +/**********************************************************************************/ + +#ifndef __ABB_INLINE_H__ +#define __ABB_INLINE_H__ + +#include "l1sw.cfg" + +#if (OP_L1_STANDALONE == 0) + #include "main/sys_types.h" +#else + #include "sys_types.h" +#endif + +#include "spi/spi_drv.h" + +// MACROS +#define ABB_WRITE_REG(reg, data) { \ + SPI_WRITE_TX_MSB((data << 6) | reg) \ + SPI_START_WRITE } + +#define ABB_READ_REG(reg) { \ + SPI_WRITE_TX_MSB(reg | 1) \ + SPI_START_READ } + + +#define ABB_SET_PAGE(page) ABB_WRITE_REG(PAGEREG, page) + +#define SEVEN_CYCLES_13M_NS 539 + +// INLINE FUNCTIONS +/*-----------------------------------------------------------------------*/ +/* ABB_SetPage() */ +/* */ +/* This function sets the right page in the ABB register PAGEREG. */ +/* */ +/*-----------------------------------------------------------------------*/ +static inline void ABB_SetPage(SYS_UWORD16 page) +{ + volatile SYS_UWORD16 status; + + ABB_SET_PAGE(page); + while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & WE_ST) == 0); + + // if IBIC is already processing another request (from the BSP) + // the USP request is delayed by 3 clock cycles + // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case + wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS)); +} + + +/*-----------------------------------------------------------------------*/ +/* ABB_WriteRegister() */ +/* */ +/* This function writes "data" in the ABB register "abb_reg". */ +/* */ +/*-----------------------------------------------------------------------*/ +static inline void ABB_WriteRegister(SYS_UWORD16 abb_reg, SYS_UWORD16 data) +{ + volatile SYS_UWORD16 status; + + ABB_WRITE_REG(abb_reg, data); + while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & WE_ST) == 0); + + // if IBIC is already processing another request (from the BSP) + // the USP request is delayed by 3 clock cycles + // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case + wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS)); + +} + + +/*-----------------------------------------------------------------------*/ +/* ABB_ReadRegister() */ +/* */ +/* This function reads the ABB register "abb_reg" and returns */ +/* the real register value. */ +/* */ +/*-----------------------------------------------------------------------*/ +static inline SYS_UWORD16 ABB_ReadRegister(SYS_UWORD16 abb_reg) +{ + volatile SYS_UWORD16 status; + + // First part of read access to the ABB register + ABB_READ_REG(abb_reg); + while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & RE_ST) == 0); + + // if IBIC is already processing another request (from the BSP) + // the USP request is delayed by 3 clock cycles + // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case + wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS)); + + // Second part of read access to the ABB register + ABB_READ_REG(abb_reg); + while(((status = * (volatile SYS_UWORD16 *) SPI_REG_STATUS) & RE_ST) == 0); + + // if IBIC is already processing another request (from the BSP) + // the USP request is delayed by 3 clock cycles + // which gives a total of 7 clock cycles ( = 539 ns at 13 MHz) in the worst case + wait_ARM_cycles(convert_nanosec_to_cycles(SEVEN_CYCLES_13M_NS)); + + return ((SPI_ReadRX_LSB() >> 6) & 0x3ff); +} + + +#endif // __ABB_INLINE_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/abb_inth.c Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,274 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : abb_inth.c */ +/* */ +/* Description : Functions to manage the ABB device interrupt. */ +/* The Serial Port Interface is used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0, and ABB interrupt is mapped as external IT. */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.2 */ +/* */ +/* Date and time : 07/02/03 */ +/* */ +/* Previous delta : Creation */ +/* */ +/**********************************************************************************/ +/* */ +/* 17/12/03 */ +/* The original abb_inth.c has been splitted between the actual abb_inth.c */ +/* located in drv_apps directory and abb_inth_core.c located in drv_core */ +/* directory. */ +/* */ +/**********************************************************************************/ + +#include "l1sw.cfg" +#include "chipset.cfg" +#include "swconfig.cfg" +#include "sys.cfg" + + +#include "l1_macro.h" +#include "l1_confg.h" +#include <string.h> +#include "abb/abb_inth.h" +#include "nucleus.h" + +#include "rv/rv_defined_swe.h" // for RVM_PWR_SWE + +#if (CHIPSET == 12) + #include "sys_inth.h" +#else + #include "inth/iq.h" +#endif + +#include "cust_os.h" +#include "l1_signa.h" +#include "abb/abb.h" + +#if defined (OP_WCP) + #include "ffs/ffs.h" + #include "ffs/board/ffspcm.h" +#endif + +#include "rvm/rvm_use_id_list.h" // for SPI_USE_ID +#include "spi/spi_env.h" +#include "spi/spi_process.h" // for ABB_EXT_IRQ_EVT +#include "kpd/kpd_power_api.h" // for kpd_power_key_pressed() +#include "power/power.h" + + +#ifdef RVM_LCC_SWE + #include "lcc/lcc_api.h" + #include "lcc/lcc_cfg_i.h" + #include "lcc/lcc.h" + #include "lcc/lcc_env.h" +#endif +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_read_int_reg_callback */ +/* */ +/* Purpose: Callback function */ +/* Called when an external interrupt has occured and the */ +/* ABB interrupt register has been read. */ +/* */ +/********************************************************************************/ +void spi_abb_read_int_reg_callback(SYS_UWORD16 *read_value) +{ + SYS_UWORD16 loop_count; + SYS_UWORD16 status_value; + xSignalHeaderRec *adc_msg; + volatile SYS_UWORD8 i; + +#ifdef RVM_LCC_SWE + struct pwr_adc_ind_s *addr; + extern T_PWR_CTRL_BLOCK *pwr_ctrl; +#endif + + + // check all the possible causes of the ABB IT + if (*read_value & PUSHOFF_IT_STS) + { + /* Push Button from ON to OFF */ + if (SPI_GBL_INFO_PTR->is_gsm_on == TRUE) + { + NU_Sleep(SHORT_OFF_KEY_PRESSED); + + // WCP Patch + #if (OP_WCP == 1) + // Backup of GSM FFS is remotely handled by MPU-S + // we trigger the backup upon each ON->OFF transition + ffs_backup (); + #else + /* Since this callback function is called from the SPI task + it can't be interrupted by another task + so we can directly access the SPI through the low-level driver */ + + #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) + status_value = (ABB_Read_Status() & ONREFLT); + #elif (ANLG_FAM == 3) + status_value = (ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND); + #endif + + if (status_value == PWR_OFF_KEY_PRESSED) + { + /* Inform keypad that key ON/OFF has been pressed */ + kpd_power_key_pressed(); + + loop_count = 0; + /* Wait loop for Power-OFF */ + while ((loop_count < OFF_LOOP_COUNT) && + (status_value == PWR_OFF_KEY_PRESSED)) + { + NU_Sleep(SHORT_OFF_KEY_PRESSED); + #if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) + status_value = (ABB_Read_Status() & ONREFLT); + #elif (ANLG_FAM == 3) + status_value = (ABB_Read_Register_on_page(PAGE1, VRPCCFG) & PWOND); + #endif + loop_count++; + } + + if (status_value == PWR_OFF_KEY_PRESSED) /* Power-OFF request detected */ + { + rvf_send_trace("IQ EXT: Power Off request",25, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + + Power_OFF_Button(); + } + } + #endif //WCP + } + else /* GSM OFF */ + { + rvf_send_trace("IQ EXT: Power On request",24, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + + Power_ON_Button(); + } + } + + else if (*read_value & REMOT_IT_STS) + { + rvf_send_trace("IQ EXT: Power Off remote request",32, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + + /* 'Remote Power' from ON to OFF */ + Power_OFF_Remote(); + } + + else if (*read_value & ADCEND_IT_STS) + { + rvf_send_trace("IQ EXT: ADC End",15, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + + /* ADC end of conversion */ + ABB_Read_ADC(&SPI_GBL_INFO_PTR->adc_result[0]); + adc_msg = os_alloc_sig(sizeof(T_CST_ADC_RESULT)); + if(adc_msg != NULL) + { + adc_msg->SignalCode = CST_ADC_RESULT; + + for(i=0;i<MADC_NUMBER_OF_MEAS;i++) + { + ((T_CST_ADC_RESULT *)(adc_msg->SigP))->adc_result[i] = SPI_GBL_INFO_PTR->adc_result[i]; + } + os_send_sig(adc_msg, RRM1_QUEUE); +#ifdef RVM_LCC_SWE + // Send ADC measurement to PWR (LCC) task + // NOTE that memory is allocated externally in the PWR task + if (rvf_get_buf(pwr_ctrl->prim_id, sizeof(struct pwr_adc_ind_s), (void *)&addr) == RVF_RED) { + rvf_send_trace("rvf_get_buf failed",18, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, LCC_USE_ID); + /* Unmask External interrupt */ + IQ_Unmask(IQ_EXT); +// rvf_dump_mem(); + return; + } + addr->header.msg_id = PWR_ADC_IND; + addr->header.src_addr_id = SPI_GBL_INFO_PTR->addr_id; + addr->header.dest_addr_id = pwr_ctrl->addr_id; + addr->header.callback_func = NULL; + // FIXME: memcpy from SPI_GBL_INFO_PTR->adc_result - make sure it has not been de-allocated + memcpy(addr->data, SPI_GBL_INFO_PTR->adc_result, 8*2); + addr->data[9] = ABB_Read_Status();; // Read & assign ITSTATREG status so we save the polling in PWR task!! + if (rvf_send_msg(pwr_ctrl->addr_id, addr) != RV_OK) { + rvf_send_trace("SPI FATAL: Send failed!",23, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, LCC_USE_ID); + } +#endif + } + } + +#if (defined(RVM_PWR_SWE) || defined(RVM_LCC_SWE)) + else if (*read_value & CHARGER_IT_STS) + { + /* Charger plug IN or OUT */ +#if ((ANLG_FAM == 1) || (ANLG_FAM == 2)) + status_value = ABB_Read_Status(); +#elif (ANLG_FAM == 3) + status_value = ABB_Read_Register_on_page(PAGE1, VRPCCFG); +#endif + if (status_value & CHGPRES) + { + rvf_send_trace("IQ EXT: Charger Plug",20, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); +#ifdef RVM_PWR_SWE + PWR_Charger_Plug(); /* charger plugged IN */ +#endif +#ifdef RVM_LCC_SWE + // Forward charger plug indication to PWR (LCC) task + // NOTE that memory is allocated externally in the PWR task + if (rvf_get_buf(pwr_ctrl->prim_id, sizeof(struct pwr_req_s), (void *)&addr) == RVF_RED) { + rvf_send_trace("rvf_get_buf failed#1",20, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, LCC_USE_ID); + rvf_dump_mem(); + } + addr->header.msg_id = PWR_CHARGER_PLUGGED_IND; + addr->header.src_addr_id = SPI_GBL_INFO_PTR->addr_id; + addr->header.dest_addr_id = pwr_ctrl->addr_id; + addr->header.callback_func = NULL; + if (rvf_send_msg(pwr_ctrl->addr_id, addr) != RV_OK) { + rvf_send_trace("SPI FATAL: Send failed!",23, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, LCC_USE_ID); + } +#endif + } + else + { + rvf_send_trace("IQ EXT: Charger Unplug",22, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + +#ifdef RVM_PWR_SWE + PWR_Charger_Unplug(); /* charger plugged OUT */ +#endif +#ifdef RVM_LCC_SWE + // Forward charger unplug indication to PWR (LCC) task + // NOTE that memory is allocated externally in the PWR task + if (rvf_get_buf(pwr_ctrl->prim_id, sizeof(struct pwr_req_s), (void *)&addr) == RVF_RED) { + rvf_send_trace("rvf_get_buf failed#2",20, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, LCC_USE_ID); + rvf_dump_mem(); + } + addr->header.msg_id = PWR_CHARGER_UNPLUGGED_IND; + addr->header.src_addr_id = SPI_GBL_INFO_PTR->addr_id; + addr->header.dest_addr_id = pwr_ctrl->addr_id; + addr->header.callback_func = NULL; + if (rvf_send_msg(pwr_ctrl->addr_id, addr) != RV_OK) { + rvf_send_trace("SPI FATAL: Send failed!",23, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, LCC_USE_ID); + } +#endif + } + } + +#endif /* RVM_PWR_SWE || RVM_LCC_SWE */ + + /* Unmask External interrupt */ + #if (CHIPSET == 12) + // Unmask ABB ext interrupt + F_INTH_ENABLE_ONE_IT(C_INTH_ABB_IRQ_IT); + #else + // Unmask external (ABB) interrupt + IQ_Unmask(IQ_EXT); + #endif +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/abb_inth.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,63 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : abb_inth.h */ +/* */ +/* Description : Functions to manage the ABB device interrupt. */ +/* The Serial Port Interface is used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0, and ABB interrupt is mapped as external IT. */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.0 */ +/* */ +/* Date and time : Jan 2003 */ +/* */ +/* Previous delta : Creation */ +/* */ +/**********************************************************************************/ +/* */ +/* 17/12/03 */ +/* The original abb_inth.h has been splitted between the actual abb_inth.h */ +/* located in drv_apps directory and abb_inth_core.h located in drv_core */ +/* directory. */ +/* abb_core_inth.h must be included in abb_inth.h. */ +/* */ +/**********************************************************************************/ + +#ifndef __ABB_INTH_H__ +#define __ABB_INTH_H__ + + #include "main/sys_types.h" + #include "abb/abb_core_inth.h" + + #ifndef _WINDOWS + + #include "l1sw.cfg" + #include "chipset.cfg" + + /****************************************************************/ + /* Power ON/OFF key definition. */ + /****************************************************************/ + // If <ON/OFF> key is pressed more than 20 TDMAs, it's a Hook-ON + #define SHORT_OFF_KEY_PRESSED (20) + + // If <ON/OFF> key is pressed more than 160 TDMAs, it's a Hook-ON AND then Power-OFF + #define OFF_LOOP_COUNT (8) + #define LONG_OFF_KEY_PRESSED (OFF_LOOP_COUNT * SHORT_OFF_KEY_PRESSED) + + #endif // _WINDOWS + + // PROTOTYPES + void spi_abb_read_int_reg_callback(SYS_UWORD16 *read_value); + +#endif // __ABB_INTH_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_api.c Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,227 @@ +/********************************************************************************* +* +* File Name: spi_api.c +* +* Bridge functions used to send events to the SPI task +* +* (C) Texas Instruments, all rights reserved +* +* Version number: 0.1 Date: 25-September-2000 +* +* History: 0.1 - Created by Candice Bazanegue +* +* Author: +* +*********************************************************************************/ + +#include "rvf/rvf_api.h" +#include "spi/spi_api.h" +#include "spi/spi_env.h" +#include "spi/spi_process.h" +#include "rvm/rvm_use_id_list.h" + + + +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_read */ +/* */ +/********************************************************************************/ +T_RV_RET spi_abb_read(UINT16 page, UINT16 address, CALLBACK_FUNC_U16 CallBack) +{ + T_SPI_READ *msgPtr; + + /* check if the driver has been started */ + if (SPI_GBL_INFO_PTR == NULL) + { + rvf_send_trace("ABB read not possible. Reason: SPI task not started",51, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + return (RVM_NOT_READY); + } + + if(SPI_GBL_INFO_PTR->SpiTaskReady == FALSE) + { + rvf_send_trace("ABB read not possible. Reason: SPI Task not ready",49, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + return (RVM_NOT_READY); + } + + rvf_send_trace("SPI_ABB_READ",12, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + + if (rvf_get_buf (SPI_GBL_INFO_PTR->prim_id, sizeof (T_SPI_READ),(void **) &msgPtr) == RVF_RED) + { + rvf_send_trace ("SPI ERROR: ABB read not possible. Reason: Not enough memory", + 59, + NULL_PARAM, + RV_TRACE_LEVEL_ERROR, + SPI_USE_ID); + + return (RV_MEMORY_ERR); + } + + (msgPtr->os_hdr).msg_id = SPI_ABB_READ_EVT; + (msgPtr->os_hdr).dest_addr_id = SPI_GBL_INFO_PTR->addr_id; + (msgPtr->os_hdr).callback_func = (CALLBACK_FUNC) CallBack; + msgPtr->page = page; + msgPtr->address = address; + + rvf_send_msg (SPI_GBL_INFO_PTR->addr_id, + msgPtr); + + return (RV_OK); +} + + + + +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_write */ +/* */ +/********************************************************************************/ +T_RV_RET spi_abb_write(UINT16 page, UINT16 address, UINT16 data) +{ + T_SPI_WRITE *msgPtr; + + /* check if the driver has been started */ + if (SPI_GBL_INFO_PTR == NULL) + { + rvf_send_trace("ABB write not possible. Reason: SPI task not started",52, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + return (RVM_NOT_READY); + } + + if(SPI_GBL_INFO_PTR->SpiTaskReady == FALSE) + { + rvf_send_trace("ABB write not possible. Reason: SPI Task not ready",50, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + return (RVM_NOT_READY); + } + + if (rvf_get_buf (SPI_GBL_INFO_PTR->prim_id, sizeof (T_SPI_WRITE),(void **) &msgPtr) == RVF_RED) + { + rvf_send_trace ("SPI ERROR: ABB write not possible. Reason: Not enough memory", + 60, + NULL_PARAM, + RV_TRACE_LEVEL_ERROR, + SPI_USE_ID); + + return (RV_MEMORY_ERR); + } + + (msgPtr->os_hdr).msg_id = SPI_ABB_WRITE_EVT; + (msgPtr->os_hdr).dest_addr_id = SPI_GBL_INFO_PTR->addr_id; + (msgPtr->os_hdr).callback_func = NULL; + msgPtr->page = page; + msgPtr->address = address; + msgPtr->data = data; + + rvf_send_msg (SPI_GBL_INFO_PTR->addr_id, msgPtr); + + return (RV_OK); +} + + + + +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_conf_ADC */ +/* */ +/********************************************************************************/ +T_RV_RET spi_abb_conf_ADC(UINT16 channels, UINT16 itval) +{ + T_SPI_ABB_CONF_ADC *msgPtr; + + /* check if the driver has been started */ + if (SPI_GBL_INFO_PTR == NULL) + { + rvf_send_trace("ABB conf ADC not possible. Reason: SPI task not started",55, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + return (RVM_NOT_READY); + } + + if(SPI_GBL_INFO_PTR->SpiTaskReady == FALSE) + { + rvf_send_trace("ABB conf ADC not possible. Reason: SPI Task not ready",53, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + return (RVM_NOT_READY); + } + + rvf_send_trace("SPI_ABB_CONF_ADC",16, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + + if (rvf_get_buf (SPI_GBL_INFO_PTR->prim_id, sizeof (T_SPI_ABB_CONF_ADC),(void **) &msgPtr) == RVF_RED) + { + rvf_send_trace ("SPI ERROR: ABB conf ADC not possible. Reason: Not enough memory", + 63, + NULL_PARAM, + RV_TRACE_LEVEL_ERROR, + SPI_USE_ID); + + return (RV_MEMORY_ERR); + } + + (msgPtr->os_hdr).msg_id = SPI_ABB_CONF_ADC_EVT; + (msgPtr->os_hdr).dest_addr_id = SPI_GBL_INFO_PTR->addr_id; + (msgPtr->os_hdr).callback_func = NULL; + msgPtr->channels = channels; + msgPtr->itval = itval; + + rvf_send_msg (SPI_GBL_INFO_PTR->addr_id, msgPtr); + + return (RV_OK); +} + + + +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_read_ADC */ +/* */ +/********************************************************************************/ +T_RV_RET spi_abb_read_ADC(UINT16 *Buff, CALLBACK_FUNC_NO_PARAM CallBack) +{ + T_SPI_ABB_READ_ADC *msgPtr; + + /* check if the driver has been started */ + if (SPI_GBL_INFO_PTR == NULL) + { + rvf_send_trace("ABB read ADC not possible. Reason: SPI task not started",55, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + return (RVM_NOT_READY); + } + + if(SPI_GBL_INFO_PTR->SpiTaskReady == FALSE) + { + rvf_send_trace("ABB conf ADC not possible. Reason: SPI Task not ready",53, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + return (RVM_NOT_READY); + } + + rvf_send_trace("SPI_ABB_READ_ADC",16, NULL_PARAM, + RV_TRACE_LEVEL_WARNING, SPI_USE_ID); + + if (rvf_get_buf (SPI_GBL_INFO_PTR->prim_id, sizeof (T_SPI_ABB_READ_ADC),(void **) &msgPtr) == RVF_RED) + { + rvf_send_trace ("SPI ERROR: ABB read ADC not possible. Reason: Not enough memory", + 63, + NULL_PARAM, + RV_TRACE_LEVEL_ERROR, + SPI_USE_ID); + + return (RV_MEMORY_ERR); + } + + (msgPtr->os_hdr).msg_id = SPI_ABB_READ_ADC_EVT; + (msgPtr->os_hdr).dest_addr_id = SPI_GBL_INFO_PTR->addr_id; + (msgPtr->os_hdr).callback_func = NULL; + msgPtr->Buff = Buff; + msgPtr->callback_func = CallBack; + + rvf_send_msg (SPI_GBL_INFO_PTR->addr_id, msgPtr); + + return (RV_OK); +} +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_api.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,178 @@ +/****************************************************************************/ +/* */ +/* File Name: spi_api.h */ +/* */ +/* Purpose: This file contains data structures and functions prototypes */ +/* used to send events to the SPI SWE. */ +/* */ +/* Version 0.1 */ +/* */ +/* Date Modification */ +/* ------------------------------------ */ +/* 20/08/2000 Create */ +/* */ +/* Author */ +/* */ +/* (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved*/ +/****************************************************************************/ +#ifndef __SPI_API_H_ +#define __SPI_API_H_ + + +#include "rv/rv_general.h" +#include "abb/abb.h" + +#ifdef __cplusplus +extern "C" +{ +#endif + + +/* the message offset must differ for each SWE in order to have unique msg_id in the system */ +#define SPI_MESSAGES_OFFSET (0x34 << 10) + + +/* define a first msg id */ +#define SPI_MESSAGE_1 (SPI_MESSAGES_OFFSET | 0x0001) + + +typedef void (*CALLBACK_FUNC_NO_PARAM)(void); +typedef void (*CALLBACK_FUNC_U16)(UINT16 *); + + + +/*****************************************/ +/* structures of messages send to SPI */ +/*****************************************/ + +typedef struct +{ T_RV_HDR os_hdr; + UINT16 page; + UINT16 address; + UINT16 data; +} T_SPI_WRITE; + + +typedef struct +{ T_RV_HDR os_hdr; + UINT16 page; + UINT16 address; +} T_SPI_READ; + + +typedef struct +{ T_RV_HDR os_hdr; + UINT16 channels; + UINT16 itval; +} T_SPI_ABB_CONF_ADC; + + +typedef struct +{ T_RV_HDR os_hdr; + UINT16 *Buff; + CALLBACK_FUNC_NO_PARAM callback_func; +} T_SPI_ABB_READ_ADC; + + + +#ifdef __cplusplus +} +#endif + + +/* Prototypes */ + +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_write */ +/* */ +/* Purpose: This function is used to send to the SPI mailbox a */ +/* WRITE REGISTER rqst msg. */ +/* */ +/* Input Parameters: */ +/* - page : ABB Page where to read the register. */ +/* - address : address of the ABB register to read. */ +/* - data : data to write in the ABB register */ +/* */ +/* Return : */ +/* - RVM_NOT_READY : the SPI task is not ready */ +/* - RV_MEMORY_ERR : the SPI task has not enough memory */ +/* - RV_OK : normal processing */ +/* */ +/* Note: */ +/* None. */ +/* */ +/********************************************************************************/ +T_RV_RET spi_abb_write(UINT16 page, UINT16 address, UINT16 data); + +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_read */ +/* */ +/* Purpose: This function is used to send a READ REGISTER rqst msg */ +/* to the SPI mailbox. */ +/* */ +/* Input Parameters: */ +/* - page : ABB Page where to read the register. */ +/* - address : address of the ABB register to read. */ +/* - CallBack : callback function called by the spi task */ +/* at the end of the read process. */ +/* */ +/* Return : */ +/* - RVM_NOT_READY : the SPI task is not ready */ +/* - RV_MEMORY_ERR : the SPI task has not enough memory */ +/* - RV_OK : normal processing */ +/* */ +/* Note: */ +/* None. */ +/* */ +/********************************************************************************/ +T_RV_RET spi_abb_read(UINT16 page, UINT16 address, CALLBACK_FUNC_U16 CallBack); + +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_conf_ADC */ +/* */ +/* Purpose: This function is used to send to the SPI mailbox a rqst msg */ +/* for configuring ABB MADC for conversions. */ +/* */ +/* Input Parameters: */ +/* - channels : ABB channels to be converted. */ +/* - itval : configure the End Of Conversion IT. */ +/* */ +/* Return : */ +/* - RVM_NOT_READY : the SPI task is not ready */ +/* - RV_MEMORY_ERR : the SPI task has not enough memory */ +/* - RV_OK : normal processing */ +/* */ +/* Note: */ +/* None. */ +/* */ +/********************************************************************************/ +T_RV_RET spi_abb_conf_ADC(UINT16 channels, UINT16 itval); + +/********************************************************************************/ +/* */ +/* Function Name: spi_abb_read_ADC */ +/* */ +/* Purpose: This function is used to send to the SPI mailbox a rqst msg */ +/* for reading the ABB ADC results. */ +/* */ +/* Input Parameters: */ +/* - Buff : pointer to the buffer filled with ADC results. */ +/* - CallBack : callback function called by the spi task */ +/* at the end of the read process. */ +/* */ +/* Return : */ +/* - RVM_NOT_READY : the SPI task is not ready */ +/* - RV_MEMORY_ERR : the SPI task has not enough memory */ +/* - RV_OK : normal processing */ +/* */ +/* Note: */ +/* None. */ +/* */ +/********************************************************************************/ +T_RV_RET spi_abb_read_ADC(UINT16 *Buff, CALLBACK_FUNC_NO_PARAM CallBack); + +#endif /* __SPI_API_H_ */ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_drv.c Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,79 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : spi_drv.c */ +/* */ +/* Description : Functions to drive the SPI module. */ +/* The Serial Port Interface is a bidirectional 3 lines */ +/* interface dedicated to the transfer of data to and */ +/* from up to 5 external devices offering a 3 lines */ +/* serial interface. */ +/* In this project, it is only used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0. */ +/* */ +/* This interface is specified to be compatible with */ +/* the UMA1018M Philips, the FUJITSU MB15F02, the */ +/* SIEMENS PMB2306T synthesizers and the TI ABB. */ +/* */ +/* This serial port is based on a looped shift-register */ +/* thus allowing both transmit (PISO) and receive (SIPO) */ +/* modes. */ +/* */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.45 */ +/* */ +/* Date and time : 07/01/03 */ +/* */ +/* Previous delta : Rework */ +/* */ +/**********************************************************************************/ + +#include "spi/spi_drv.h" + + + +/*-----------------------------------------------------------------------*/ +/* SPI_InitDev() */ +/* */ +/* This function initializes the SPI registers for an external device */ +/* connected to the serial port. */ +/* */ +/*-----------------------------------------------------------------------*/ +void SPI_InitDev(T_SPI_DEV *Device) +{ + unsigned short Param,Gate,Shiftval; + unsigned short Mask = 0x7bde; + + /* Clock enable, mask ITs and pre scale setting */ + * (volatile SYS_UWORD16 *) SPI_REG_SET1 = (SPI_CLK_ON | Device->PrescVal | SPI_IT_MASK_0 | SPI_IT_MASK_1); + + /* Building the parameter for REG_SET2 initialization */ + Shiftval = Device->DevId >> 7; + Param = (Device->ClkEdge | Device->TspEnLevel | Device->TspEnForm)<<Shiftval ; + Gate = Mask<<Shiftval; + + * (volatile SYS_UWORD16 *) SPI_REG_SET2 = (* (volatile SYS_UWORD16 *) SPI_REG_SET2 & Gate) | Param; + + + /* Configuring CTRL_REG : this writting erases the previous one */ + * (volatile SYS_UWORD16 *) SPI_REG_CTRL = (Device->DataTrLength | Device->DevId); + + /* Stop the SPI clock */ + #ifdef SPI_CLK_LOW_POWER + SPI_CLK_DISABLE + #endif +} + + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_drv.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,283 @@ +/**********************************************************************************/ +/* TEXAS INSTRUMENTS INCORPORATED PROPRIETARY INFORMATION */ +/* */ +/* Property of Texas Instruments -- For Unrestricted Internal Use Only */ +/* Unauthorized reproduction and/or distribution is strictly prohibited. This */ +/* product is protected under copyright law and trade secret law as an */ +/* unpublished work. Created 1987, (C) Copyright 1997 Texas Instruments. All */ +/* rights reserved. */ +/* */ +/* */ +/* Filename : spi_drv.h */ +/* */ +/* Description : SPI registers and bits definitions. */ +/* Functions and macros to drive the SPI module. */ +/* The Serial Port Interface is a bidirectional 3 lines */ +/* interface dedicated to the transfer of data to and */ +/* from up to 5 external devices offering a 3 lines */ +/* serial interface. */ +/* In this project, it is only used to connect the TI */ +/* Analog BaseBand (ABB). */ +/* It is assumed that the ABB is connected as the SPI */ +/* device 0. */ +/* */ +/* This interface is specified to be compatible with */ +/* the UMA1018M Philips, the FUJITSU MB15F02, the */ +/* SIEMENS PMB2306T synthesizers and the TI ABB. */ +/* */ +/* This serial port is based on a looped shift-register */ +/* thus allowing both transmit (PISO) and receive (SIPO) */ +/* modes. */ +/* */ +/* */ +/* Author : Pascal PUEL */ +/* */ +/* Version number : 1.28 */ +/* */ +/* Date and time : 07/01/03 */ +/* */ +/* Previous delta : Rework */ +/* */ +/**********************************************************************************/ + +#ifndef __SPI_DRV_H__ +#define __SPI_DRV_H__ + +#include "l1sw.cfg" +#include "chipset.cfg" + +#include "memif/mem.h" +#if (OP_L1_STANDALONE == 0) + #include "main/sys_types.h" +#else + #include "sys_types.h" +#endif + +// SPI module registers definition +#define SPI_REG_SET1 (MEM_SPI + 0x00) +#define SPI_REG_SET2 (MEM_SPI + 0x02) +#define SPI_REG_CTRL (MEM_SPI + 0x04) +#define SPI_REG_STATUS (MEM_SPI + 0x06) +#define SPI_REG_TX_LSB (MEM_SPI + 0x08) +#define SPI_REG_TX_MSB (MEM_SPI + 0x0A) +#define SPI_REG_RX_LSB (MEM_SPI + 0x0C) +#define SPI_REG_RX_MSB (MEM_SPI + 0x0E) + + +// SPI module bits definition of register SPI_REG_SET1 +#define SPI_CLK_OFF 0x0000 // default value +#define SPI_CLK_ON 0x0001 +#define SPI_CLOCK_DIV_1 0x0000 // default value +#define SPI_CLOCK_DIV_2 0x0002 +#define SPI_CLOCK_DIV_4 0x0004 +#define SPI_CLOCK_DIV_8 0x0006 +#define SPI_CLOCK_DIV_16 0x0008 +#if (CHIPSET == 12) +#define SPI_CLOCK_DIV_32 0x000A +#define SPI_CLOCK_DIV_64 0x000C +#define SPI_CLOCK_DIV_128 0x000E +#endif +#define SPI_IT_MASK_0 0x0010 // default value +#define SPI_IT_DEMASK_0 0x0000 +#define SPI_IT_MASK_1 0x0020 // default value +#define SPI_IT_DEMASK_1 0x0000 + + +// SPI module bits definition of register SPI_REG_SET2 +#define SPI_CLK_EDG_FALL 0x0000 // default value for device 0 +#define SPI_CLK_EDG_RISE 0x0001 +#define SPI_CLK_EDG_FALL_1 0x0000 // default value for device 1 +#define SPI_CLK_EDG_RISE_1 0x0002 +#define SPI_CLK_EDG_FALL_2 0x0000 // default value for device 2 +#define SPI_CLK_EDG_RISE_2 0x0004 +#define SPI_CLK_EDG_FALL_3 0x0000 // default value for device 3 +#define SPI_CLK_EDG_RISE_3 0x0008 +#define SPI_CLK_EDG_FALL_4 0x0000 // default value for device 4 +#define SPI_CLK_EDG_RISE_4 0x0010 +#define SPI_NTSPEN_NEG_LEV 0x0000 // default value for device 0 +#define SPI_NTSPEN_POS_LEV 0x0020 +#define SPI_NTSPEN_NEG_LEV_1 0x0000 // default value for device 1 +#define SPI_NTSPEN_POS_LEV_1 0x0040 +#define SPI_NTSPEN_NEG_LEV_2 0x0000 // default value for device 2 +#define SPI_NTSPEN_POS_LEV_2 0x0080 +#define SPI_NTSPEN_NEG_LEV_3 0x0000 // default value for device 3 +#define SPI_NTSPEN_POS_LEV_3 0x0100 +#define SPI_NTSPEN_NEG_LEV_4 0x0000 // default value for device 4 +#define SPI_NTSPEN_POS_LEV_4 0x0200 +#define SPI_NTSPEN_LEV_TRIG 0x0000 // default value for device 0 +#define SPI_NTSPEN_EDG_TRIG 0x0400 +#define SPI_NTSPEN_LEV_TRIG_1 0x0000 // default value for device 1 +#define SPI_NTSPEN_EDG_TRIG_1 0x0800 +#define SPI_NTSPEN_LEV_TRIG_2 0x0000 // default value for device 2 +#define SPI_NTSPEN_EDG_TRIG_2 0x1000 +#define SPI_NTSPEN_LEV_TRIG_3 0x0000 // default value for device 3 +#define SPI_NTSPEN_EDG_TRIG_3 0x2000 +#define SPI_NTSPEN_LEV_TRIG_4 0x0000 // default value for device 4 +#define SPI_NTSPEN_EDG_TRIG_4 0x4000 + + +// SPI module bits definition of register SPI_REG_CTRL +#define SPI_RDWR_DEACTIV 0x0000 // default value +#define SPI_RDWR_ACTIV 0x0001 +#define SPI_WR_DEACTIV 0x0000 // default value +#define SPI_WR_ACTIV 0x0002 +#define SPI_WNB_0 0x0000 // default value +#define SPI_WNB_1 0x0004 +#define SPI_WNB_2 0x0008 +#define SPI_WNB_3 0x000c +#define SPI_WNB_4 0x0010 +#define SPI_WNB_5 0x0014 +#define SPI_WNB_6 0x0018 +#define SPI_WNB_7 0x001c +#define SPI_WNB_8 0x0020 +#define SPI_WNB_9 0x0024 +#define SPI_WNB_10 0x0028 +#define SPI_WNB_11 0x002c +#define SPI_WNB_12 0x0030 +#define SPI_WNB_13 0x0034 +#define SPI_WNB_14 0x0038 +#define SPI_WNB_15 0x003c +#define SPI_WNB_16 0x0040 +#define SPI_WNB_17 0x0044 +#define SPI_WNB_18 0x0048 +#define SPI_WNB_19 0x004c +#define SPI_WNB_20 0x0050 +#define SPI_WNB_21 0x0054 +#define SPI_WNB_22 0x0058 +#define SPI_WNB_23 0x005c +#define SPI_WNB_24 0x0060 +#define SPI_WNB_25 0x0064 +#define SPI_WNB_26 0x0068 +#define SPI_WNB_27 0x006c +#define SPI_WNB_28 0x0070 +#define SPI_WNB_29 0x0074 +#define SPI_WNB_30 0x0078 +#define SPI_WNB_31 0x007c + + +// SPI possible device IDs +#define SPI_DEV0 0x0000 +#define SPI_DEV1 0x0080 +#define SPI_DEV2 0x0100 +#define SPI_DEV3 0x0180 +#define SPI_DEV4 0x0200 + +// ABB should be mapped as device 0 +#define ABB SPI_DEV0 + + +// SPI module bits definition of register SPI_REG_STATUS +#define RE_ST 0x0001 // bit 0 +#define WE_ST 0x0002 // bit 1 + + +/* The ARM emulator requires the spi clock always ON to be able to access */ +/* spi registers through a window.*/ +/* But it's better to stop the SPI clock in the GSM application to reduce the power consumption. */ +/* Validate the next line to reduce power consumption */ +//#define SPI_CLK_LOW_POWER + + + +// STRUCTURES +typedef struct +{ + SYS_UWORD16 PrescVal; + SYS_UWORD16 DataTrLength; + SYS_UWORD16 DevAddLength; + SYS_UWORD16 DevId; + SYS_UWORD16 ClkEdge; + SYS_UWORD16 TspEnLevel; + SYS_UWORD16 TspEnForm; +}T_SPI_DEV; // T_SPI_DEV is used to define an SPI device + + +// MACROS +#define SPI_WRITE_TX_LSB(TxLsb) { \ +* (volatile SYS_UWORD16 *) SPI_REG_TX_LSB = TxLsb; } + +#define SPI_WRITE_TX_MSB(TxMsb) { \ +* (volatile SYS_UWORD16 *) SPI_REG_TX_MSB = TxMsb; } + +#define SPI_START_WRITE {* (volatile SYS_UWORD16 *) SPI_REG_CTRL |= SPI_WR_ACTIV; } + +#define SPI_START_READ {* (volatile SYS_UWORD16 *) SPI_REG_CTRL |= SPI_RDWR_ACTIV; } + +#define SPI_CLK_DISABLE { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_CLK_ON; } + +#define SPI_CLK_ENABLE { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_CLK_ON; } + +#define SPI_MaskIT_WR { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_IT_MASK_0; } + +#define SPI_MaskIT_RD { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 |= SPI_IT_MASK_1; } + +#define SPI_Mask_All_IT { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_IT_MASK_0 | SPI_IT_MASK_1); } + +#define SPI_UnmaskIT_WR { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_IT_MASK_0; } + +#define SPI_UnmaskIT_RD { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~SPI_IT_MASK_1; } + +#define SPI_Unmask_All_IT { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 &= ~(SPI_IT_MASK_0 | SPI_IT_MASK_1); } + +#define SPI_Ready_for_WR { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_0); } + +#define SPI_Ready_for_RD { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_1); } + +#define SPI_Ready_for_RDWR { \ +* (volatile SYS_UWORD16 *) SPI_REG_SET1 |= (SPI_CLK_ON | SPI_IT_MASK_0 | SPI_IT_MASK_1); } + + + +// INLINE FUNCTIONS +/*-----------------------------------------------------------------------*/ +/* SPI_ReadRX_LSB() */ +/* */ +/* This function returns the value of SPI_REG_RX_LSB register */ +/* */ +/*-----------------------------------------------------------------------*/ +static inline SYS_UWORD16 SPI_ReadRX_LSB(void) +{ + return * (volatile SYS_UWORD16 *) SPI_REG_RX_LSB; +} + + +/*-----------------------------------------------------------------------*/ +/* SPI_ReadRX_MSB() */ +/* */ +/* This function returns the value of SPI_REG_RX_MSB register */ +/* */ +/*-----------------------------------------------------------------------*/ +static inline SYS_UWORD16 SPI_ReadRX_MSB(void) +{ + return * (volatile SYS_UWORD16 *) SPI_REG_RX_MSB; +} + + + +/*-----------------------------------------------------------------------*/ +/* SPI_ReadStatus() */ +/* */ +/* This function returns the value of SPI_REG_STATUS register */ +/* */ +/*-----------------------------------------------------------------------*/ +static inline SYS_UWORD16 SPI_ReadStatus(void) +{ + return * (volatile SYS_UWORD16 *) SPI_REG_STATUS; +} + + + +// PROTOTYPES +void SPI_InitDev(T_SPI_DEV *Device); + +#endif // __SPI_DRV_H__
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_env.c Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,228 @@ +/****************************************************************************/ +/* */ +/* File Name: spi_env.c */ +/* */ +/* Purpose: This file contains definitions for RV manager related */ +/* functions used to get info, start and stop the SPI SWE. */ +/* */ +/* Version 0.1 */ +/* */ +/* Date Modification */ +/* ------------------------------------ */ +/* 20/08/2000 Create */ +/* */ +/* Author David Lamy-Charrier (dlamy@tif.ti.com) */ +/* */ +/* (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved*/ +/****************************************************************************/ + +#include "spi/spi_env.h" +#include "rv/general.h" +#include "rvm/rvm_gen.h" +#include "rvm/rvm_priorities.h" +#include "rvm/rvm_use_id_list.h" +#include <string.h> + +//extern T_RV_RET spi_core(void); +#include "spi/spi_task.h" + + +/* global pointer to the error function */ +static T_RVM_RETURN (*spi_error_ft)(T_RVM_NAME swe_name, T_RVM_RETURN error_cause, + T_RVM_ERROR_TYPE error_type,T_RVM_STRING error_msg); + +/* Global variables */ +T_SPI_GBL_INFO *SPI_GBL_INFO_PTR = NULL; + + + +/****************************************************************************** +* Function : spi_get_info +* +* Description : This function is called by the RV manager to learn +* spi requirements in terms of memory, SWEs... +* +* Parameters : T_RVM_INFO_SWE * swe_info: pointer to the structure to fill +* containing infos related to the SPI SWE. +* +* Return : T_RVM_RETURN +* +* History : 0.1 (20-August-2000) +* +* +******************************************************************************/ +T_RVM_RETURN spi_get_info(T_RVM_INFO_SWE * infoSWE) +{ + + /* SWE info */ + + infoSWE->swe_type = RVM_SWE_TYPE_4; + infoSWE->type_info.type4.swe_use_id = SPI_USE_ID; + memcpy( infoSWE->type_info.type4.swe_name, "SPI", sizeof("SPI") ); + + infoSWE->type_info.type4.stack_size = SPI_STACK_SIZE; + infoSWE->type_info.type4.priority = RVM_SPI_TASK_PRIORITY; + + + /* memory bank info */ + infoSWE->type_info.type4.nb_mem_bank = 1; + + memcpy ((UINT8 *) infoSWE->type_info.type4.mem_bank[0].bank_name, "SPI_PRIM", 9); + infoSWE->type_info.type4.mem_bank[0].initial_params.size = SPI_MB_PRIM_SIZE; + infoSWE->type_info.type4.mem_bank[0].initial_params.watermark = SPI_MB_PRIM_WATERMARK; + + + /* linked SWE info */ + infoSWE->type_info.type4.nb_linked_swe = 0; + + + /* generic functions */ + infoSWE->type_info.type4.set_info = spi_set_info; + infoSWE->type_info.type4.init = spi_init; + infoSWE->type_info.type4.core = spi_core; + infoSWE->type_info.type4.stop = spi_stop; + infoSWE->type_info.type4.kill = spi_kill; + + /* Set the return path */ + infoSWE->type_info.type4.return_path.callback_func = NULL; + infoSWE->type_info.type4.return_path.addr_id = 0; + + return RV_OK; +} + + +/****************************************************************************** +* Function : spi_set_info +* +* Description : This function is called by the RV manager to inform +* the spi SWE about task_id, mb_id and error function. +* +* Parameters : - T_RVM_TASK_ID taskId: task_id. +* - T_RV_RETURN ReturnPath[], array of return path for linked SWE +* - T_RVF_MB_ID mbId[]: array of memory bank ids. +* - callback function to call in case of unrecoverable error. +* +* Return : T_RVM_RETURN +* +* History : 0.1 (20-August-2000) +* +* +******************************************************************************/ +T_RVM_RETURN spi_set_info( T_RVF_ADDR_ID addr_id, + T_RV_RETURN ReturnPath[], + T_RVF_MB_ID mbId[], + T_RVM_RETURN (*callBackFct)(T_RVM_NAME SWEntName, + T_RVM_RETURN errorCause, + T_RVM_ERROR_TYPE errorType, + T_RVM_STRING errorMsg)) +{ + T_RVF_MB_STATUS mb_status; + UINT16 i; + + rvf_send_trace("SPI : spi_set_info: try to init GLOBAL INFO SPI structure ... ",62, + NULL_PARAM, + RV_TRACE_LEVEL_DEBUG_LOW, + SPI_USE_ID); + + mb_status = rvf_get_buf(mbId[0],sizeof(T_SPI_GBL_INFO),(void **) &SPI_GBL_INFO_PTR); + + if (mb_status == RVF_RED) + { + rvf_send_trace("SPI : spi_set_info: Not enough memory to initiate GLOBAL INFO SPI structure ... ",80, + NULL_PARAM, + RV_TRACE_LEVEL_ERROR, + SPI_USE_ID); + + return (RVM_MEMORY_ERR); + } + + + /* store the pointer to the error function */ + spi_error_ft = callBackFct ; + + SPI_GBL_INFO_PTR->prim_id = mbId[0]; + + /* Store the addr id */ + SPI_GBL_INFO_PTR->addr_id = addr_id; + + for(i=0;i<MADC_NUMBER_OF_MEAS;i++) + { + SPI_GBL_INFO_PTR->adc_result[i] = 0; + } + + SPI_GBL_INFO_PTR->is_gsm_on = FALSE; + + SPI_GBL_INFO_PTR->SpiTaskReady = FALSE; + + /* spi task_id and spi mb_id could be retrieved later + using rvf_get_taskid and rvf_get_mb_id functions */ + + return RV_OK; +} + + +/****************************************************************************** +* Function : spi_init +* +* Description : This function is called by the RV manager to initialize the +* spi SWE before creating the task and calling spi_start. +* +* Parameters : None +* +* Return : T_RVM_RETURN +* +* History : 0.1 (20-August-2000) +* +* +******************************************************************************/ +T_RVM_RETURN spi_init(void) +{ + + return RV_OK; +} + + + +/****************************************************************************** +* Function : spi_stop +* +* Description : This function is called by the RV manager to stop the spi SWE. +* +* Parameters : None +* +* Return : T_RVM_RETURN +* +* History : 0.1 (20-August-2000) +* +* +******************************************************************************/ +T_RVM_RETURN spi_stop(void) +{ + /* other SWEs have not been killed yet, spi can send messages to other SWEs */ + + return RV_OK; +} + + +/****************************************************************************** +* Function : spi_kill +* +* Description : This function is called by the RV manager to kill the spi +* SWE, after the spi_stop function has been called. +* +* Parameters : None +* +* Return : T_RVM_RETURN +* +* History : 0.1 (20-August-2000) +* +* +******************************************************************************/ +T_RVM_RETURN spi_kill (void) +{ + /* free all memory buffer previously allocated */ + return RV_OK; +} + + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_env.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,72 @@ +/*****************************************************************************/ +/* */ +/* File Name: spi_env.h */ +/* */ +/* Purpose: This file contains prototypes for RV manager related */ +/* functions used to get info, start and stop the spi block */ +/* */ +/* Version 0.1 */ +/* */ +/* Date Modification */ +/* ------------------------------------ */ +/* 20/08/2000 Create */ +/* */ +/* Author David Lamy-Charrier (dlamy@tif.ti.com) */ +/* */ +/* (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved */ +/*****************************************************************************/ + +#ifndef __SPI_ENV_H_ +#define __SPI_ENV_H_ + +#include "rvm/rvm_gen.h" +#include "abb/abb_inth.h" // for MADC_NUMBER_OF_MEAS + +#include "spi/spi_pool_size.h" /* Stack & Memory Bank sizes definitions */ + +/* SPI mailbox */ +#define SPI_MAILBOX RVF_TASK_MBOX_0 + + +/* memory bank size and watermark */ +#define SPI_MB_PRIM_SIZE SPI_MB1_SIZE +#define SPI_MB_PRIM_WATERMARK (SPI_MB_PRIM_SIZE - 56) +#define SPI_MB_PRIM_INC_SIZE 0 +#define SPI_MB_PRIM_INC_WATERMARK 0 + + + +typedef struct SPI_GBL_INFO +{ + T_RVF_MB_ID prim_id; + T_RVF_ADDR_ID addr_id; + UINT16 adc_result[MADC_NUMBER_OF_MEAS]; + BOOLEAN is_gsm_on; + BOOLEAN is_adc_on; + BOOLEAN SpiTaskReady; +} T_SPI_GBL_INFO; + + +/* Global variables */ +extern T_SPI_GBL_INFO *SPI_GBL_INFO_PTR; + + +/* generic functions declarations */ +T_RVM_RETURN spi_get_info (T_RVM_INFO_SWE *infoSWE); + +T_RVM_RETURN spi_set_info(T_RVF_ADDR_ID addr_id, + T_RV_RETURN ReturnPath[], + T_RVF_MB_ID mbId[], + T_RVM_RETURN (*callBackFct)(T_RVM_NAME SWEntName, + T_RVM_RETURN errorCause, + T_RVM_ERROR_TYPE errorType, + T_RVM_STRING errorMsg)); + +T_RVM_RETURN spi_init (void); + +T_RVM_RETURN spi_stop (void); + +T_RVM_RETURN spi_kill (void); + +#endif /*__SPI_ENV_H_*/ +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_pool_size.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,35 @@ +/** + * @file spi_pool_size.h + * + * Declarations of: + * - the memory bank sizes and their watermark + * - the SWE stack size + * - the pool size needed (generally the sum of memory bank and stack sizes) + * + * @author Vincent Oberle + * @version 0.1 + */ + +/* + * History: + * + * Date Author Modification + * ------------------------------------------------------------------- + * 07/08/2003 Vincent Oberle Extracted from rvf_pool_size.h + * + * (C) Copyright 2003 by Texas Instruments Incorporated, All Rights Reserved + */ + +#ifndef __SPI_POOL_SIZE_H_ +#define __SPI_POOL_SIZE_H_ + + +/* + * Values used in spi_env.h + */ +#define SPI_STACK_SIZE (1000) +#define SPI_MB1_SIZE (256) +#define SPI_POOL_SIZE (SPI_STACK_SIZE + SPI_MB1_SIZE) + + +#endif /*__SPI_POOL_SIZE_H_*/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_process.c Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,164 @@ +/*****************************************************************************/ +/* */ +/* Name spi_process.c */ +/* */ +/* Function this file contains the spi_process function, used to */ +/* handle messages received in the SPI mailbox, and used to */ +/* access the ABB. It is called by the spi task core. */ +/* */ +/* Version 0.1 */ +/* */ +/* Date Modification */ +/* ------------------------------------ */ +/* 20/08/2000 Create */ +/* */ +/* Author */ +/* */ +/* (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved */ +/*****************************************************************************/ + +#include "rvf/rvf_api.h" +#include "spi/spi_api.h" +#include "rvm/rvm_use_id_list.h" +#include "spi/spi_process.h" +#include "rv/rv_defined_swe.h" // for RVM_PWR_SWE + + + +//#ifndef _WINDOWS +//#include "iq.h" +//#endif + +/******************************************************************************* +** Function spi_process +** +*******************************************************************************/ +UINT8 spi_process(T_RV_HDR * msg_ptr) +{ + UINT16 data ; +// static UINT8 int_nb = 0; + + if(msg_ptr != NULL) + { + switch (msg_ptr->msg_id) + { + case ABB_EXT_IRQ_EVT: + { + /* Call to the low-level driver function : interrupt status register reading */ + data = ABB_Read_Register_on_page(PAGE0, ITSTATREG); + +//#ifndef _WINDOWS + // SW workaround to avoid an ABB interrupt occuring to early after the application start. + // The first ABB interrupt is skipped. + +// if((int_nb == 0) && (data == ADCEND_IT_STS)) +// { +// int_nb++; + + /* Unmask keypad interrupt */ +// IQ_Unmask(IQ_EXT); +// } +// else +// { + + /* Callback function */ +// if(msg_ptr->callback_func != NULL) +// { +// msg_ptr->callback_func(&data); +// } +// } +//#else + + /* Callback function */ + if(msg_ptr->callback_func != NULL) + { + msg_ptr->callback_func(&data); + } +//#endif + + rvf_free_buf ((void *) msg_ptr); + + break; + } + + case SPI_ABB_READ_EVT: + { + rvf_send_trace("SPI_task: SPI_READ_ABB_EVT received", 35, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + + /* Call to the low-level driver function */ + data = ABB_Read_Register_on_page(((T_SPI_READ *)msg_ptr)->page, ((T_SPI_READ *)msg_ptr)->address); + + /* Callback function */ + if(((T_SPI_READ *)msg_ptr)->os_hdr.callback_func != NULL) + { + ((T_SPI_READ *)msg_ptr)->os_hdr.callback_func(&data); + } + + rvf_free_buf ((void *) msg_ptr); + + return 0; + } + + case SPI_ABB_WRITE_EVT: + { + rvf_send_trace("SPI_task: SPI_WRITE_ABB_EVT received", 36, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + + /* Call to the low-level driver function */ + ABB_Write_Register_on_page(((T_SPI_WRITE *)msg_ptr)->page, ((T_SPI_WRITE *)msg_ptr)->address, ((T_SPI_WRITE *)msg_ptr)->data); + + rvf_free_buf ((void *) msg_ptr); + + return 0; + } + + case SPI_ABB_CONF_ADC_EVT: + { + rvf_send_trace("SPI_task: SPI_ABB_CONF_ADC_EVT received", 39, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + + /* Call to the low-level driver function */ + ABB_Conf_ADC(((T_SPI_ABB_CONF_ADC *)msg_ptr)->channels, ((T_SPI_ABB_CONF_ADC *)msg_ptr)->itval); + + rvf_free_buf ((void *) msg_ptr); + + return 0; + } + + case SPI_ABB_READ_ADC_EVT: + { + rvf_send_trace("SPI_task: SPI_ABB_READ_ADC_EVT received", 39, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + + /* Call to the low-level driver function */ + ABB_Read_ADC(((T_SPI_ABB_READ_ADC *)msg_ptr)->Buff); + + /* Callback function */ + if(((T_SPI_ABB_READ_ADC *)msg_ptr)->callback_func != NULL) + { + ((T_SPI_ABB_READ_ADC *)msg_ptr)->callback_func(); + } + + rvf_free_buf ((void *) msg_ptr); + + return 0; + } + + default: + { + /* Unknown message has been received */ + #ifdef RVM_PWR_SWE + rvf_send_trace("SPI_task : Received an unknown or a PWR message",47, NULL_PARAM , + RV_TRACE_LEVEL_DEBUG_HIGH, SPI_USE_ID); + #else + rvf_send_trace("SPI_task : Received an unknown message",38, NULL_PARAM , + RV_TRACE_LEVEL_DEBUG_HIGH, SPI_USE_ID); + + rvf_free_buf ((void *) msg_ptr); + #endif + + return 1; + } + } // end of switch + } // end of if (msg_ptr != NULL) + return 0; +} + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_process.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,39 @@ +/*****************************************************************************/ +/* */ +/* Name spi_process.h */ +/* */ +/* Function this file contains the spi_process function prototype, */ +/* used to handle messages received in the SPI task mailbox. */ +/* */ +/* Version 0.1 */ +/* */ +/* Date Modification */ +/* ------------------------------------ */ +/* */ +/* Author Candice Bazanegue */ +/* */ +/* (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved */ +/*****************************************************************************/ + +#ifndef __SPI_PROCESS_H__ +#define __SPI_PROCESS_H__ + + +#define SPI_ABB_READ_EVT 1 +#define SPI_ABB_WRITE_EVT 2 +#define SPI_ABB_CONF_ADC_EVT 3 +#define SPI_ABB_READ_ADC_EVT 4 +#define ABB_EXT_IRQ_EVT 5 + +/* Prototypes */ + +/******************************************************************************* +** Function spi_process +** +** Description It is called by the spi task core to handle the access to +** the ABB through the SPI in a non-preemptive way. +** +*******************************************************************************/ +UINT8 spi_process(T_RV_HDR * msg_ptr); + +#endif /* __SPI_PROCESS_H__ */ \ No newline at end of file
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_task.c Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,148 @@ +/*****************************************************************************/ +/* */ +/* Name spi_task.c */ +/* */ +/* Function this file contains the main SPI function: spi_core. */ +/* It contains the body of the SPI task. */ +/* It will initialize the SPI and then wait for messages */ +/* or functions calls. */ +/* */ +/* Version 0.1 */ +/* Author Candice Bazanegue */ +/* */ +/* Date Modification */ +/* ------------------------------------ */ +/* 20/08/2000 Create */ +/* 01/09/2003 Modfication */ +/* Author Pascal Puel */ +/* */ +/* (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved */ +/*****************************************************************************/ + +#ifndef _WINDOWS + #include "chipset.cfg" + #if (CHIPSET == 12) + #include "inth/sys_inth.h" + #else + #include "inth/iq.h" // for IQ_Unmask() + #endif + #include "power/power.h" // for Switch_ON() +#endif + +#include "rv/rv_defined_swe.h" // for RVM_PWR_SWE +#include "rvm/rvm_use_id_list.h" +#include "spi/spi_env.h" +#include "spi/spi_process.h" +#include "spi/spi_task.h" + +#ifdef RVM_PWR_SWE + #include "pwr/pwr_liion_cha.h" + #include "pwr/pwr_disch.h" + #include "pwr/pwr_process.h" + #include "pwr/pwr_env.h" +#endif + + + +/******************************************************************************* +** Function spi_core +** +** Description Core of the spi task, which initiliazes the spi SWE and +** waits for messages. +** +*******************************************************************************/ +T_RV_RET spi_core(void) +{ + BOOLEAN error_occured = FALSE; + T_RV_HDR * msg_ptr; + + rvf_send_trace("SPI_task: Initialization", 24, NULL_PARAM, RV_TRACE_LEVEL_DEBUG_LOW, SPI_USE_ID); + SPI_GBL_INFO_PTR->SpiTaskReady = TRUE; + +#ifndef _WINDOWS + /* Unmask External Interrupt once the SPI task is started */ + #if (CHIPSET == 12) + // Unmask ABB ext interrupt + F_INTH_ENABLE_ONE_IT(C_INTH_ABB_IRQ_IT); + #else + // Unmask external (ABB) interrupt + IQ_Unmask(IQ_EXT); + #endif + // Get the switch on cause from ABB. + Set_Switch_ON_Cause(); +#endif + + /* loop to process messages */ + while (error_occured == FALSE) + { + /* Wait for the necessary events (infinite wait for a msg in the mailbox 0). */ + UINT16 received_event = rvf_wait (0xffff, 0); + + /* If an event related to mailbox 0 is received, then */ + if (received_event & RVF_TASK_MBOX_0_EVT_MASK) + { + /* Read the message in the driver mailbox and delegate action..*/ + msg_ptr = (T_RV_HDR *) rvf_read_mbox(SPI_MAILBOX); + + #ifdef RVM_PWR_SWE + if(spi_process(msg_ptr)) + { + pwr_process(msg_ptr); + } + #else + spi_process(msg_ptr); + #endif + } + + #ifdef RVM_PWR_SWE + /* Timers */ + if (received_event & SPI_TIMER0_WAIT_EVENT) + { + pwr_bat_test_timer_process(); + } + + if (received_event & SPI_TIMER1_WAIT_EVENT) + /* timer used to detect the end of the CI charge */ + { + pwr_CI_charge_timer_process(); + } + + if (received_event & SPI_TIMER2_WAIT_EVENT) + /* timer used to detect the end of the CV charge */ + { + pwr_CV_charge_timer_process(); + } + + if (received_event & SPI_TIMER3_WAIT_EVENT) + /* timer used to check the battery discharge level */ + { + pwr_discharge_timer_process(); + } + #endif + } // end of while + return RV_OK; +} + + + +/********************************************************************************** +* Function : spi_adc_on +* +* Description : Put the variable is_adc_on of the T_SPI_GBL_INFO structure to TRUE. +* This variable is used for the battery management. +* This function is called by the CST entity. +* +* Parameters : None +* +* Return : None +* +**********************************************************************************/ +void spi_adc_on (void) +{ + SPI_GBL_INFO_PTR->is_adc_on = TRUE; + + rvf_send_trace("SPI: ADC are on",15, + NULL_PARAM, + RV_TRACE_LEVEL_DEBUG_LOW, + SPI_USE_ID); +}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/bsp/abb+spi/spi_task.h Sat Nov 16 19:03:37 2013 +0000 @@ -0,0 +1,56 @@ +/*****************************************************************************/ +/* */ +/* Name spi_task.h */ +/* */ +/* Function this file contains timers definitions used by spi_core, */ +/* in case the PWR SWE is defined. */ +/* */ +/* Version 0.1 */ +/* Author Candice Bazanegue */ +/* */ +/* Date Modification */ +/* ------------------------------------ */ +/* 20/08/2000 Create */ +/* 01/09/2003 Modfication */ +/* Author Pascal Puel */ +/* */ +/* (C) Copyright 2000 by Texas Instruments Incorporated, All Rights Reserved */ +/*****************************************************************************/ + +#ifndef _SPI_TASK_H_ +#define _SPI_TASK_H_ + +#include "rv/rv_defined_swe.h" // for RVM_PWR_SWE + +#ifdef RVM_PWR_SWE + +#include "pwr/pwr_cust.h" + +#define SPI_TIMER0 (RVF_TIMER_0) +#define SPI_TIMER0_INTERVAL_1 (PWR_BAT_TEST_TIME_1) +#define SPI_TIMER0_INTERVAL_2 (PWR_BAT_TEST_TIME_2) +#define SPI_TIMER0_INTERVAL_3 (PWR_CALIBRATION_TIME_1) +#define SPI_TIMER0_INTERVAL_4 (PWR_CALIBRATION_TIME_2) +#define SPI_TIMER0_WAIT_EVENT (RVF_TIMER_0_EVT_MASK) + +#define SPI_TIMER1 (RVF_TIMER_1) +#define SPI_TIMER1_INTERVAL (PWR_CI_CHECKING_TIME) +#define SPI_TIMER1_WAIT_EVENT (RVF_TIMER_1_EVT_MASK) + +#define SPI_TIMER2 (RVF_TIMER_2) +#define SPI_TIMER2_INTERVAL (PWR_CV_CHECKING_TIME) +#define SPI_TIMER2_WAIT_EVENT (RVF_TIMER_2_EVT_MASK) + +#define SPI_TIMER3 (RVF_TIMER_3) +#define SPI_TIMER3_INTERVAL (PWR_DISCHARGE_CHECKING_TIME_1) +#define SPI_TIMER3_INTERVAL_BIS (PWR_DISCHARGE_CHECKING_TIME_2) +#define SPI_TIMER3_WAIT_EVENT (RVF_TIMER_3_EVT_MASK) + +#endif // RVM_PWR_SWE + + +// Prototypes +void spi_adc_on (void); +T_RV_RET spi_core(void); + +#endif // _SPI_TASK_H_ \ No newline at end of file