FreeCalypso > hg > freecalypso-sw
changeset 153:65efffcb28dc
tpudrv*.h headers imported
| author | Michael Spacefalcon <msokolov@ivan.Harhan.ORG> |
|---|---|
| date | Sun, 17 Nov 2013 05:10:06 +0000 |
| parents | 26472940e5b0 |
| children | 47754cdb6248 |
| files | gsm-fw/L1/tpudrv/tpudrv.h gsm-fw/L1/tpudrv/tpudrv10.h gsm-fw/L1/tpudrv/tpudrv12.h gsm-fw/L1/tpudrv/tpudrv2.h gsm-fw/L1/tpudrv/tpudrv8.h |
| diffstat | 5 files changed, 1408 insertions(+), 0 deletions(-) [+] |
line wrap: on
line diff
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/L1/tpudrv/tpudrv.h Sun Nov 17 05:10:06 2013 +0000 @@ -0,0 +1,247 @@ +/************* Revision Controle System Header ************* + * GSM Layer 1 software + * + * Filename tpudrv.h + * Copyright 2003 (C) Texas Instruments + * + ************* Revision Controle System Header *************/ + +/* + * Device addresses - GCS000 + */ +// GSM 1.5 : TPU / TSP addresses +//------------------------------------- + +#if ((CHIPSET ==2) || (CHIPSET == 3) || (CHIPSET == 4)) + #define TPU_ADDR 0xFFFE0000l // Hercule / Ulysse / Samson + + #define TPU_RAM (TPU_ADDR + 0x1400) + + #define TPU_REG (TPU_ADDR + 0x1000) + #define TSP_REG (TPU_ADDR + 0x0800) + #define TPU_TIM (TPU_ADDR + 0x2000) + +#elif ((CHIPSET == 5) || (CHIPSET == 6) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 9) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12)) + #define TPU_ADDR 0xFFFF0000l // Strobe 1 address + + #define TPU_RAM 0xFFFF9000l // TPU RAM + + #define TPU_REG (TPU_ADDR + 0x1000) // TPU register + #define TSP_REG 0xFFFE0800l // TSP register + #define TPU_TIM 0xFFFE2000l // ULPD register + +#endif + + +/* + * Macros for defining TPU instructions + */ +#define TPU_SLEEP 0 +#define TPU_MOVE(addr,data) (0x8000 | ((data)<<5) | (addr)) +#define TPU_AT(time) (0x2000 | (((time + 5000) % 5000))) +#define TPU_FAT(time) (0x2000 | (time)) // Fast version without modulo +#define TPU_SYNC(time) (0x6000 | (time)) +#define TPU_WAIT(time) (0xA000 | (time)) +#define TPU_OFFSET(time) (0x4000 | (time)) +#define MOD5000(a) (((a) + 5000) % 5000) + + +/* + * TSP registers - defined in GCS004 - Time Serial Port + */ +/* + * in TPU address space + */ +// GSM 1.5 : TSP_TX_REG_1/2/3/4 instead of TSP_TX_U/M/L +// added TSP_SPI_SET1/2/3 to ctrl up to 5 periph. +//----------------------------------------------------- + #define TSP_CTRL1 0x00 + #define TSP_CTRL2 0x01 + #define TSP_TX_REG_1 0x04 + #define TSP_TX_REG_2 0x03 + #define TSP_TX_REG_3 0x02 + #define TSP_TX_REG_4 0x05 + #define TSP_ACT 0x06 + #define TSP_ACTX 0x07 + #define TSP_GAUGING_EN 0x11 + #define TSP_SPI_SET1 0x09 + #define TSP_SPI_SET2 0x0A + #define TSP_SPI_SET3 0x0B + #define TPU_IT_DSP_PG 0x10 + #define TSP_GAUGING_EN 0x11 + +/* + * in ARM address space - defined in HYP004 + */ + #define TSP_RX_LSB (TSP_REG + 0x00) + + #define TSP_RX_MSB (TSP_REG + 0x02) + + #define TSP_TX_LSB (TSP_REG + 0x0c) + + #define TSP_TX_MSB (TSP_REG + 0x0a) + + +/* + * TSP registers bit definitions + */ + #define TC1_DEVICE0 0x00 + #define TC1_DEVICE1 0x20 + #define TC1_DEVICE2 0x40 + #define TC1_DEVICE3 0x60 + #define TC1_DEVICE4 0x80 + #define TC2_RD 0x01 + #define TC2_WR 0x02 + #define TC2_EDGE_TRIG 0x40 + #define TC2_RISING 0x80 + #define TSP_CLK_RISE 0x01 + #define TSP_ENA_POS 0x02 + #define TSP_ENA_EDGE 0x04 + #define GAUGING_START 0x01 + #define GAUGING_STOP 0x00 + #define TSP_ENA_POS_MSB 0x20 + + + +/* + * TPU registers - defined in HYP002 + */ +// GSM 1.5 : TPU reg are 16-bit access +//--------------------------------------- +#define TPU_CTRL (TPU_REG + 0x00) +#define TPU_INT_CTRL (TPU_REG + 0x02) +#define TPU_INT_STAT (TPU_REG + 0x04) +#define TPU_OFFSET_REG (TPU_REG + 0x0C) +#define TPU_SYNCHRO_REG (TPU_REG + 0x0E) +#define TPU_DSP_PG (TPU_REG + 0x20) + + + + + +/* + * TPU control register bits + */ +// GSM 1.5 : TPU bits changed +//--------------------------------------- +#define TPU_CTRL_RESET 0x0001 +#define TSP_CTRL_RESET 0x0080 +#define TPU_CTRL_T_PAGE 0x0002 +#define TPU_CTRL_T_ENBL 0x0004 +#define TPU_CTRL_D_ENBL 0x0010 // WARNING THIS BIT DOES NOT EXIST IN HYPERION +#define TPU_CTRL_SPI_RST 0x0080 +#define TPU_CTRL_WAIT 0x0200 +#define TPU_CTRL_CLK_EN 0x0400 +#if (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11) || (CHIPSET == 12) + #define TPU_CTRL_FULL_WRITE 0x0800 +#endif + + + + +/* + * TPU interrupt control register bits + */ + + +/* WARNING BUG IN HYPERION. */ +/* READING TPU_INT_CRTL, TPU_INT_ITP_M BIT CONTENTS AFFECTS THE TPU_INT_ITD_M VALUE. */ + +#define TPU_INT_ITF_M 0x0001 +#define TPU_INT_ITP_M 0x0002 +#define TPU_INT_ITD_M 0x0004 +#define TPU_INT_ITD_F 0x0008 // WARNING THIS BIT DOES NOT EXIST IN HYPERION + +#define INT_FRAME 4 /* TPU frame interrupt */ +#define INT_PAGE 5 /* TPU page interrupt */ +#define INT_TSP 3 /* TSP interrupt */ + + + +#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) + // BB signals connected to serial link1 + #define BULON 0x80 // bit6 + #define BULCAL 0x40 // bit5 + #define BULENA 0x20 // bit4 + #define BDLON 0x10 // bit3 + #define BDLCAL 0x08 // bit2 + #define BDLENA 0x04 // bit1 + #define STARTADC 0x02 // bit0 +#endif + + +/* + * GSM RF programming times in quarter bits + */ +/**************************************************************************/ +/**************************************************************************/ +/****************************** W A R N I N G !!! *************************/ +/******* This values are fine tuned for LAYER 1 . DO NOT MODIFY !!! *******/ +/****** FOR ANY MODIFICATION , PLEASE CONTACT Texas Instruments Inc. ******/ +/**************************************************************************/ +/**************************************************************************/ + + +/**************************************/ +/* TPU Macros: prototypes functions */ +/**************************************/ +// TPU macros. +//------------ +void l1dmacro_reset_hw (UWORD32 servingCellOffset); +void l1dmacro_init_hw (void); +void l1dmacro_init_hw_light (void); +void l1dmacro_idle (void); +void l1dmacro_rx_synth (SYS_UWORD16 radio_freq); +void l1dmacro_tx_synth (SYS_UWORD16 radio_freq); +void l1dmacro_agc (SYS_UWORD16 radio_freq, WORD8 gain, UWORD8 lna); +void l1dmacro_afc (SYS_UWORD16 afc_value, UWORD8 win_id); +void l1dmacro_rx_ms (SYS_UWORD16 radio_freq); +void l1dmacro_rx_fb (SYS_UWORD16 radio_freq); +void l1dmacro_rx_fb26 (SYS_UWORD16 radio_freq); +void l1dmacro_offset (UWORD32 offset_value, + WORD32 relative_time); +void l1dmacro_synchro (UWORD32 when, UWORD32 value); +void l1dmacro_rx_sb (SYS_UWORD16 radio_freq); +void l1dmacro_rx_nb (SYS_UWORD16 radio_freq); +void l1dmacro_tx_nb (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active); +void l1dmacro_tx_ra (SYS_UWORD16 radio_freq, UWORD8 txpwr, UWORD8 adc_active); +void l1dmacro_adc_read_tx (UWORD32 when); +void l1dmacro_adc_read_rx (void); +void l1dmacro_set_frame_it (void); + +void l1pdmacro_it_dsp_gen(WORD16 time); + +#if TESTMODE + void l1dmacro_rx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr); + void l1dmacro_tx_cont (SYS_UWORD16 radio_freq, UWORD8 txpwr); + void l1dmacro_stop_cont (void); +#endif + +/* + * TPU prototypes + */ +void TP_PageIntHandler (void); +void TP_FrameIntHandler (void); +void TP_PageIntHandler (void); +void TP_FrameIntHandler (void); +void TPU_Reset(SYS_UWORD16 on); +void TSP_Reset(SYS_UWORD16 on); +void TPU_ClkEnable(SYS_UWORD16 on); +void TP_Reset(SYS_UWORD16 on); +void TP_Enable(SYS_UWORD16 on); +BOOL TPU_check_IT_DSP(void); + + +/* + * TPUDRV global variables + */ +#ifdef TPUDRV_C +#define TP_GLOBAL +#else +#define TP_GLOBAL extern +#endif + +TP_GLOBAL volatile UWORD32 TP_PageInt; +TP_GLOBAL volatile UWORD32 TP_FrameInt; + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/L1/tpudrv/tpudrv10.h Sun Nov 17 05:10:06 2013 +0000 @@ -0,0 +1,285 @@ +/****************** Revision Controle System Header *********************** + * GSM Layer 1 software + * Copyright (c) Texas Instruments 1998 + * + * Filename tpudrv10.h + * Copyright 2003 (C) Texas Instruments + * + ****************** Revision Controle System Header ***********************/ + +#define BIT_0 0x000001 +#define BIT_1 0x000002 +#define BIT_2 0x000004 +#define BIT_3 0x000008 +#define BIT_4 0x000010 +#define BIT_5 0x000020 +#define BIT_6 0x000040 +#define BIT_7 0x000080 +#define BIT_8 0x000100 +#define BIT_9 0x000200 +#define BIT_10 0x000400 +#define BIT_11 0x000800 +#define BIT_12 0x001000 +#define BIT_13 0x002000 +#define BIT_14 0x004000 +#define BIT_15 0x008000 +#define BIT_16 0x010000 +#define BIT_17 0x020000 +#define BIT_18 0x040000 +#define BIT_19 0x080000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 + + +//TRF6150 definitions +#define MODE0 0x000000 +#define MODE1 0x000001 +#define MODE2 0x000002 +#define MODE3 0x000003 +#define MODE4 0x000004 +#define MODE5 0x000005 +#define MODE6 0x000006 +#define MODE7 0x000007 + +#define REGUL_ON BIT_3 //MODE0 +#define BG_SPEEDUP BIT_4 //MODE0 +#define RX_ON_CLARA BIT_5 //MODE0 +#define TX_ON_CLARA BIT_6 //MODE0 +#define PA_CTRLR_ON BIT_7 //MODE0 +#define AUX_SYNTH_ON BIT_8 //MODE0 +#define MAIN_SYNTH_OFF 0x000000 //MODE0 +#define MAIN_SYNTH_ON_RX BIT_9 //MODE0 +#define MAIN_SYNTH_ON_TX BIT_10 //MODE0 +#define DCO_COMP_ON BIT_11 //MODE0 +#define DCO_COMP_RUN BIT_12 //MODE0 +#define BAND_SELECT_GSM BIT_13 //MODE0 +#define BAND_SELECT_850 BIT_13 //MODE0 +#define BAND_SELECT_PCS BIT_14 //MODE0 +#define BAND_SELECT_DCS (BIT_14 | BIT_13) + +#define RX_RF_GAIN BIT_15 //MODE0 + +// MODE1 is only for Receiver gain programming (AGC) + +#define AUX_SHDW_ADD(arfcn) ((arfcn >= 822) && (arfcn <= 885)) ? BIT_3 : 0 //MODE2 +#define AUX_SHDW_RCL BIT_4 //MODE2 +#define MAIN_FCU_REG_100 BIT_7 //MODE2 +#define PA_CTRL_I_DIOD BIT_23 //MODE2 + +//MODE3 +#define TEST_MODE BIT_3 //MODE3 +#define HB_OPLL_PRECHARGE BIT_4 //MODE3 + +#define HB_OPLL_CP_CUR_0_125MA 0x000000 //0.125 mA +#define HB_OPLL_CP_CUR_0_25MA BIT_5 //0.25 mA +#define HB_OPLL_CP_CUR_0_5MA BIT_6 //0.5 mA +#define HB_OPLL_CP_CUR_1MA (BIT_6 | BIT_5) //1 mA +#define HB_OPLL_CP_CUR_2MA BIT_7 //2 mA + +#define LB_OPLL_PRECHARGE BIT_8 //MODE3 + +#define LB_OPLL_CP_CUR_0_125MA 0x000000 //0.125 mA +#define LB_OPLL_CP_CUR_0_25MA BIT_9 //0.25 mA +#define LB_OPLL_CP_CUR_0_5MA BIT_10 //0.5 mA +#define LB_OPLL_CP_CUR_1MA (BIT_10 | BIT_9) //1 mA +#define LB_OPLL_CP_CUR_2MA BIT_11 //2 mA + +#define CLK_REF BIT_17 //MODE3 +#define MAIN_VCO_EN BIT_18 //MODE3 +#define AUX_VCO_EN BIT_19 //MODE3 +#define EXT_VCO_CONTROL BIT_20 //MODE3 +#define TEMP_SENSOR_EN BIT_21 //MODE3 + +//MODE4 +#define MAIN_TIMER_RX_49_2US BIT_6 //MODE4 +#define MAIN_TIMER_RX_55_35US ( 8 << 3) //added 30.01.02 +#define MAIN_TIMER_RX_61_5US (10 << 3) +#define MAIN_TIMER_RX_78_9US (13 << 3) +#define MAIN_TIMER_RX_91_9US (15 << 3) +#define MAIN_TIMER_RX_98_4US (16 << 3) +#define MAIN_TIMER_RX_159_9US (26 << 3) //added 21.08 CR + + +#define MAIN_TIMER_TX_49_2US BIT_11 //MODE4 +#define MAIN_TIMER_TX_61_5US (10 << 8) //added 30.01.02 +#define MAIN_TIMER_TX_104US (17 << 8) //added for RS +#define MAIN_TIMER_TX_98_4US (16 << 8) +#define MAIN_TIMER_TX_123US (20 << 8) //added 21.08 CR + +#define MAIN_CP_CUR_0 0x000000 //MODE4 400uA, 1.6mA +#define MAIN_CP_CUR_1 BIT_21 //MODE4 400uA, 3.2mA +#define MAIN_CP_CUR_2 BIT_22 //MODE4 800uA, 3.2mA +#define MAIN_CP_CUR_3 (BIT_22 | BIT_21)//MODE4 same as 2 + +#define FC_60 (60 << 13) +#define FC_63 (63 << 13) +#define FC_70 (70 << 13) +#define FC_100 (100 << 13) +#define FC_109 (109 << 13) +#define FC_110 (110 << 13) + +//MODE5 +#define SHDW_LOAD BIT_3 //MODE5 +#define AUX_PRG_MOD BIT_4 //MODE5 +#define AUX_PFD BIT_14 //MODE5 + +//MODE6 +#define FREQ_CAL_ON BIT_4 //MODE6 +#define FREQ_CAL_MODE BIT_5 //MODE6 + +//MODE7 +#define FREQ_CAL_DATA (0xd << 19) // 6.15 (00000)-8.88 (01101)-12.66 pF (11111)- modified CR 11.09.01, was (0xb << 19) + + +// RF signals connected to TSPACT [0..7] +//#define RESET_RF BIT_0 // act0 +#define CLA_SER_ON BIT_0 // act0 +#define CLA_SER_OFF 0 +#define TXVCO_ON 0 // act3 inverted +#define TXVCO_OFF BIT_3 +#define TX_ON BIT_5 // act5 +#define TX_OFF 0 + +// RF signals connected to TSPACT for Titanium v2.2 +#if 0 +//B-Sample +#define PA900_ON BIT_2 // signals are inverted therefore PA900_ON act1 +#define PA1800_ON BIT_1 // and PA1800_ON act2 +#define PA900_OFF BIT_1 // +#define PA1800_OFF BIT_2 // +#endif + +#if 0 +//C-Sample +#define PA900_ON BIT_1 // signals are inverted therefore PA900_ON act1 +#define PA1800_ON BIT_2 // and PA1800_ON act2 +#define PA900_OFF BIT_2 // +#define PA1800_OFF BIT_1 // +#endif + +#if 1 +//D-Sample +#define PA900_ON BIT_1 // signals are inverted therefore PA900_ON act1 +#define PA1800_ON BIT_2 // and PA1800_ON act2 +#define RX1900_ON 0 +#define PA900_OFF BIT_2 // +#define PA1800_OFF BIT_1 // +#define RX1900_OFF BIT_4 + +//RX_UP/DOWN and TX_UP/DOWN +#define RU_900 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define RD_900 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define TU_900 (PA900_ON | PA1800_OFF | RX1900_OFF) +#define TD_900 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define TU_REV_900 (PA900_OFF | PA1800_ON | RX1900_OFF) + +#define RU_850 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define RD_850 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define TU_850 (PA900_ON | PA1800_OFF | RX1900_OFF) +#define TD_850 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define TU_REV_850 (PA900_OFF | PA1800_ON | RX1900_OFF) + +#define RU_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define RD_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define TU_1800 (PA900_OFF | PA1800_ON | RX1900_OFF) +#define TD_1800 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define TU_REV_1800 (PA900_ON | PA1800_OFF | RX1900_OFF) + +#define RU_1900 (PA900_OFF | PA1800_OFF | RX1900_ON) +#define RD_1900 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define TU_1900 (PA900_OFF | PA1800_ON | RX1900_OFF) +#define TD_1900 (PA900_OFF | PA1800_OFF | RX1900_OFF) +#define TU_REV_1900 (PA900_ON | PA1800_OFF | RX1900_OFF) + + +#endif + +#define TC1_DEVICE_ABB TC1_DEVICE0 +#define TC1_DEVICE_RF TC1_DEVICE2 + + + #define SL_SU_DELAY1 4 // No. bits to send + load data to shift + send write cmd + 1 + #define SL_SU_DELAY2 3 // load data to shift + send write cmd + 1 + #define SL_SU_DELAY3 5 // SL_SU_DELAY1 + serialization + +#define DLT 20 // (TRF6150) DownLoadTime + +#define DLT_1 1 // 1 tpu instruction = 1 qbit +#define DLT_2 2 +#define DLT_3 3 + +#define DLT_1B 4 // 3*move + 1*byte (download) +#define DLT_2B 6 // 4*move + 2*byte +#define DLT_3B 8 // 5*move + 3*byte + +//#define crch_timing 420//250//420//0 // CR d.07.08.01 - Temperary movement of Rx and Tx timing for Titanium. Will be set to 0 when new LF is ready. +#define rdt 0//359 // rx delta timing +#define tdt 0//293 // tx delta timing + +/*------------------------------------------*/ +/* Download delay values */ +/*------------------------------------------*/ +// 0.9230769 usec ~ 1 qbit i.e. 200 usec is ~ 217 qbit + +#define T TPU_CLOCK_RANGE + +#define TRF_I7 334 //qbit +#define TRF_I8 378 //qbit + +// time below are offset to when BDLENA goes low +#define TRF_R15 ( 0 - DLT_1B) // 0, BDLENA low, needs DLT_1B to execute +#define TRF_R13 ( - 32 - DLT_1B) // 8 right after, power off transceiver + +//burst data comes here +// time below are offset to when BDLENA goes high +#define TRF_R12 (PROVISION_TIME - 0 - DLT_1B) // BDLENA i/q comes 32qbit later +#define TRF_R10 (PROVISION_TIME - 8 - DLT_1B) // Set RX/TX switch (not really necessary as the default setting is RX mode) +#define TRF_R9 (PROVISION_TIME - 16 - DLT_2B) // RX_ON_CLARA +#define TRF_R7 (PROVISION_TIME - 66 - DLT_1B) // 67qbit duration BDLON + BDLCAL +#define TRF_R6 (PROVISION_TIME - 83 - DLT_1B) // BDLON, RX_ON_CLARA +#define TRF_R5 (PROVISION_TIME - 172 - DLT_2B - rdt) // DC offset comp. start LNA ON +//#define TRF_R4 (PROVISION_TIME - 172 - DLT_2B - rdt) // DC offset comp. LNA +#define TRF_R3 (PROVISION_TIME - 177 - DLT_2B - rdt) // DC offset comp. GAIN +//l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst +//#define TRF_R2_1 (PROVISION_TIME - 199 - DLT_2B - rdt) // fc +//#define TRF_R2 (PROVISION_TIME - 199 - DLT_2B - rdt) // select band +#define TRF_R1 (PROVISION_TIME - 209 - DLT_3B - rdt) // Main PLL + set of Main PLL FC & CP current + + +// time below are offset to when BULENA goes low +#define TRF_T17 ( 32 - SL_SU_DELAY2) // right after, BULON low +//#define TRF_T17 ( 32 ) // right after, BULON low +#define TRF_T16 ( 26 - DLT_1B) // Power down Clara +#define TRF_T15 ( 14 - DLT_1) // disable TX_ON +#define TRF_T14 ( 0 - DLT_1B) // BULENA off +#define TRF_T13_3 (- 40 - DLT_1B) // ADC read +//burst data comes here +// time below are offset to when BULENA goes high +#define TRF_T13_2 ( 25 - DLT_1) // TX_ON +#define TRF_T13_1 ( 17 - DLT_1) // set rf switch +#define TRF_T12 (- 0 - DLT_1B) // BULENA Start of TX burst +#define TRF_T10 (- 70 - DLT_3B - tdt) // normal speed +#define TRF_T9 (- 121 - DLT_2B - tdt) // Power up TXVCO +#define TRF_T8 (- 127 - DLT_1B - tdt) // BULON, disable BULCAL +#define TRF_T7 (- 127 - DLT_1B - tdt) // 131 BULON, disable BULCAL +#define TRF_T6 (- 137 - DLT_3B - tdt) // Speed up +#define TRF_T4 (- 249 - DLT_1B - tdt) // prog AUX PLL & detector polarity +#define TRF_T3_1 (- 258 - DLT_2B - tdt) // fc +#define TRF_T3 (- 258 - DLT_2B - tdt) // 20 BULON + BULCAL + select band +#define TRF_T2 (- 267 - DLT_3B - tdt) // set of Main PLL FC & CP current +#define TRF_T1 (- 277 - DLT_3B - tdt) // BULON + Main PLL + + +/*------------------------------------------*/ +/* Is arfcn in the DCS band (512-885) ? */ +/*------------------------------------------*/ +// is working only for GSM and DCS (not PCN) +#define IS_DCS_HIGH(arfcn) (((arfcn >= 576) && (arfcn <= 885))? 1 : 0) //Changed by CR 30.08.01, was (((arfcn >= 822) && (arfcn <= 885))? 1 : 0) + +#ifdef TPUDRV10_C + +#endif + +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/L1/tpudrv/tpudrv12.h Sun Nov 17 05:10:06 2013 +0000 @@ -0,0 +1,459 @@ +/****************** Revision Controle System Header *********************** + * GSM Layer 1 software + * Copyright (c) Texas Instruments 1998 + * + * Filename tpudrv12.h + * Copyright 2003 (C) Texas Instruments + * + ****************** Revision Controle System Header ***********************/ + +//--- Configuration values +#define FEM_TEST 0 // 1 => ENABLE the FEM_TEST mode +#define RF_VERSION 1 // 1 or V1, 5 for V5, etc +#define SAFE_INIT_WA 0 // 1 => ENABLE the "RITA safe init" +// TeST - Enable Main VCO buffer for test +#define MAIN_VCO_ACCESS_WA 0 // 1 => ENABLE the Main VCO buffer + +#include "rf.cfg" + +//--- RITA PG declaration + +#define R_PG_10 0 +#define R_PG_13 1 +#define R_PG_20 2 // For RFPG 2.2, use 2.0 +#define R_PG_23 3 + +//--- PA declaration +#define PA_MGF9009 0 +#define PA_RF3146 1 +#define PA_RF3133 2 +#define PA_PF08123B 3 +#define PA_AWT6108 4 + +#if (RF_PA == PA_MGF9009 || RF_PA == PA_PF08123B) + #define PA_CTRL_INT 0 +#else + #define PA_CTRL_INT 1 +#endif + +//- Select the RF PG (x10), i.e. 10 for 1.0, 11 for 1.1 or 20 for 2.0 +// AlphaRF7 => "PG #1.3" for TPU purposes (not an official PC number) +// This is also used in l1_rf12.h to select the SWAP_IQ +#if (RF_PG >= R_PG_20) + // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX + #define PLL2_WA 0 // 0 => DISABLE the PLL2_WA (Rene's "Work-Around") + #define ALPHA_RF7_WA 0 // 0 => DISABLE the Alpha RF7 work-arounds +#elif (RF_PG == R_PG_13) + // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX + #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around") + #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds +#else + // TeST - PLL2 WA activation => Set PLL2 Speed-up ON in RX + #define PLL2_WA 1 // 1 => ENABLE the PLL2_WA (Rene's "Work-Around") + #define ALPHA_RF7_WA 1 // 1 => ENABLE the Alpha RF7 work-arounds +#endif + +//- Bit definitions for TST register programings, etc +#define BIT_0 0x000001 +#define BIT_1 0x000002 +#define BIT_2 0x000004 +#define BIT_3 0x000008 +#define BIT_4 0x000010 +#define BIT_5 0x000020 +#define BIT_6 0x000040 +#define BIT_7 0x000080 +#define BIT_8 0x000100 +#define BIT_9 0x000200 +#define BIT_10 0x000400 +#define BIT_11 0x000800 +#define BIT_12 0x001000 +#define BIT_13 0x002000 +#define BIT_14 0x004000 +#define BIT_15 0x008000 +#define BIT_16 0x010000 +#define BIT_17 0x020000 +#define BIT_18 0x040000 +#define BIT_19 0x080000 +#define BIT_20 0x100000 +#define BIT_21 0x200000 +#define BIT_22 0x400000 +#define BIT_23 0x800000 + +//--- TRF6151 definitions ------------------------------------------ + +//- BASE REGISTER definitions +#define REG_RX 0x000000 // MODE0 +#define REG_PLL 0x000001 // MODE1 +#define REG_PWR 0x000002 // MODE2 +#define REG_CFG 0x000003 // MODE3 + +//- TeST REGISTER definitions => Used for WA only +// TeST - PLL2 WA => Define PLL2 TEST register +#define TST_PLL2 0x00001E // MODE 14 + +// TeST - Enable Main VCO buffer for test => Define TST_VCO3 register +#define TST_VCO3 0x00000F // MODE 15 (0*16+15*1) +#define TST_VCO4 0x000024 // MODE 36 (2*16+4*1) + +// Alpha RF7 WA TeST registers +#define TST_LDO 0x000027 // MODE 39 (2*16+7*1) +#define TST_PLL1 0x00001D // MODE 29 (1*16+13*1) +#define TST_TX2 0x000037 // MODE 55 (3*16+7*1) + +// More Alpha RF7 WA TeST registers +#define TST_TX3 0x00003C // MODE 61 (3*16+12*1) +#define TST_TX4 0x00003D // MODE 61 (3*16+13*1) + +// PG 2.1 WA TeST registers +#define TST_PLL3 0x00001F // MODE 31 (1*16+15*1) +// #define TST_PLL4 0x00002C // MODE 44 (2*16+12*1) +#define TST_MISC 0x00003E // MODE 62 (3*16+14*1) => Used for setting the VCXO current +#define TST_LO 0x00001C // MODE 28 (1*16+12*1) + +// Registers used to improve the Modulation Spectrum in DCS/PCS for PG2.1 V1 +// UPDATE_SERIAL_REGISTER_COPY is a "dummy addres" that, +// when accessed, triggers the copy of the serial registers. +// This is necessary to switch into "manual operation mode" +#define UPDATE_SERIAL_INTERFACE_COPY 0x000007 +#define TX_LOOP_MANUAL BIT_3 + + +//- REG_RX - MODE0 +#define BLOCK_DETECT_0 BIT_3 +#define BLOCK_DETECT_1 BIT_4 +#define RST_BLOCK_DETECT_0 BIT_5 +#define RST_BLOCK_DETECT_1 BIT_6 +#define READ_EN BIT_7 +#define RX_CAL_MODE BIT_8 +#define RF_GAIN (BIT_10 | BIT_9) + + +//- REG_PLL - MODE1 +//PLL_REGB +//PLL_REGA + +//- REG_PWR - MODE2 +#define BANDGAP_MODE_OFF 0x0 +#define BANDGAP_MODE_ON_ENA BIT_4 +#define BANDGAP_MODE_ON_DIS (BIT_4 | BIT_3) +#define REGUL_MODE_ON BIT_5 +// BIT[8..6] band +#define BAND_SELECT_GSM BIT_6 +#define BAND_SELECT_DCS BIT_7 +#define BAND_SELECT_850_LO BIT_8 +#define BAND_SELECT_850_HI (BIT_8 | BIT_6) +#define BAND_SELECT_PCS (BIT_8 | BIT_7) + +#define SYNTHE_MODE_OFF 0x0 +#define SYNTHE_MODE_RX BIT_9 +#define SYNTHE_MODE_TX BIT_10 +#define RX_MODE_OFF 0x0 +#define RX_MODE_A BIT_11 +#define RX_MODE_B1 BIT_12 +#define RX_MODE_B2 (BIT_12 | BIT_11) +#define TX_MODE_OFF 0x0 +#define TX_MODE_ON BIT_13 +#define PACTRL_APC_OFF 0x0 +#define PACTRL_APC_ON BIT_14 +#define PACTRL_APC_DIS 0x0 +#define PACTRL_APC_ENA BIT_15 + + +//- REG_CFG - MODE3 +// Common PA controller settings: +#define PACTRL_TYPE_PWR 0x0 +#define PACTRL_TYPE_CUR BIT_3 +#define PACTRL_IDIOD_30_UA 0x0 +#define PACTRL_IDIOD_300_UA BIT_4 + +// PA controller Clara-like (Power Sensing) settings: + #define PACTRL_VHOME_610_MV (BIT_7 | BIT_5) +#define PACTRL_VHOME_839_MV (BIT_7 | BIT_5) + #define PACTRL_VHOME_1000_MV (BIT_6 | BIT_9) + #define PACTRL_VHOME_1600_MV (BIT_8 | BIT_5) + #define PACTRL_RES_OPEN 0x0 + #define PACTRL_RES_150_K BIT_10 + #define PACTRL_RES_300_K BIT_11 + #define PACTRL_RES_NU (BIT_10 | BIT_11) + #define PACTRL_CAP_0_PF 0x0 + #define PACTRL_CAP_12_5_PF BIT_12 + #define PACTRL_CAP_25_PF (BIT_13 | BIT_12) + #define PACTRL_CAP_50_PF BIT_13 + + // PACTRL_CFG contains the configuration of the PACTRL that will + // be put into the REG_CFG register at initialization time + // WARNING - Do not forget to set the PACTRL_TYPE (PWR or CUR) + // in this #define!!! +#if (RF_PA == 0) // MGF9009 (LCPA) + #define PACTRL_CFG \ + PACTRL_IDIOD_300_UA | \ + PACTRL_CAP_25_PF | \ + PACTRL_VHOME_1000_MV | \ + PACTRL_RES_300_K +#elif (RF_PA == 1) // 3146 + #define PACTRL_CFG 0 + +#elif (RF_PA == 2) // 3133 + #define PACTRL_CFG 0 + +#elif (RF_PA == 3) // PF08123B + #define PACTRL_CFG \ + PACTRL_TYPE_PWR | \ + PACTRL_CAP_50_PF | \ + PACTRL_RES_300_K | \ + PACTRL_VHOME_610_MV +#elif (RF_PA == 4) // AWT6108 + #define PACTRL_CFG 0 + #else + #error Unknown PA specifiec! + #endif + +// Temperature sensor +#define TEMP_SENSOR_OFF 0x0 +#define TEMP_SENSOR_ON BIT_14 +// Internal Logic Init Disable +#define ILOGIC_INIT_DIS BIT_15 +// ILOGIC_INIT_DIS must be ALWAYS set when programming the REG_CFG register +// It was introduced in PG 1.2 +// For previous PGs this BIT was unused, so it can be safelly programmed +// for all PGs + + +// RF signals connected to TSPACT [0..7] +//#define RESET_RF BIT_0 // act0 +#define RF_SER_ON BIT_0 // act0 +#define RF_SER_OFF 0 + + +#if (FEM_TEST==1) + //for test + #define TEST_TX_ON BIT_2 // act2 + #define TEST_RX_ON BIT_3 // act3 + + //3-band config (D-sample) + #define FEM_1 BIT_1 // act1 + #define FEM_2 0 //BIT_2 // act2 + #define FEM_3 0 //BIT_3 // act3 +#elif (BOARD == 42 || BOARD == 43 || BOARD == 35 || (BOARD == 41 && (RF_PA == 0 || RF_PA == 1 || RF_PA == 2 || RF_PA == 4))) // ESample, P2, Leonardo + #define TEST_TX_ON 0 + #define TEST_RX_ON 0 + // 4-band config (E-sample, P2, Leonardo) + #define FEM_7 BIT_2 // act2 + #define FEM_8 BIT_1 // act1 + #define FEM_9 BIT_4 // act4 + + #if (RF_PA == 0) // LCPA for ES, P2 and Leo + #define PA_HI_BAND BIT_3 // act3 + #define PA_LO_BAND 0 + #define PA_OFF 0 + #elif (RF_PA == 1) // RF3146 for ES and Leonardo + #define PA_HI_BAND BIT_3 // act3 + #define PA_LO_BAND 0 + #define PA_OFF 0 + #elif (RF_PA == 2) // RF3133 for P2 and Leonardo + #define PA_HI_BAND BIT_3 // act3 + #define PA_LO_BAND 0 + #define PA_OFF 0 + #elif (RF_PA == 4) // AWT6108 for Leonardo + #define PA_HI_BAND BIT_3 // act3 + #define PA_LO_BAND 0 + #define PA_OFF 0 + #else + #error "RF_PA not correctly defined" + #endif + +#else // DSample + EVARITA + #if (RF_PA != 3) // Hitachi for EVARITA + #error + #endif + + //#define TEST_RX_ON 0 + //#define TEST_TX_ON BIT_3 // act3 + #define TEST_TX_ON 0 + #define TEST_RX_ON BIT_3 // act3 + + //3-band config (D-sample) + #define FEM_1 BIT_1 // act1 + #define FEM_2 BIT_2 // act2 + #define FEM_3 BIT_3 // act3 +#endif + +#if (BOARD == 42 || BOARD == 43 || BOARD == 35 || (BOARD == 41 && (RF_PA == 0 || RF_PA == 1 || RF_PA == 2 || RF_PA == 4))) // ESample, P2, Leonardo + + #define FEM_PINS (FEM_7 | FEM_8 | FEM_9) + + #define FEM_OFF ( FEM_PINS ^ 0 ) + + #define FEM_SLEEP ( 0 ) + + // This configuration is always inverted. + + // 4-band config + // RX_UP/DOWN and TX_UP/DOWN + #define RU_900 ( PA_OFF | FEM_PINS ^ 0 ) + #define RD_900 ( PA_OFF | FEM_PINS ^ 0 ) + #define TU_900 ( PA_LO_BAND | FEM_PINS ^ FEM_9 ) + #define TD_900 ( PA_OFF | FEM_PINS ^ 0 ) + + #define RU_850 ( PA_LO_BAND | FEM_PINS ^ 0 ) + #define RD_850 ( PA_OFF | FEM_PINS ^ 0 ) + #define TU_850 ( PA_LO_BAND | FEM_PINS ^ FEM_9 ) + #define TD_850 ( PA_OFF | FEM_PINS ^ 0 ) + + #define RU_1800 ( PA_OFF | FEM_PINS ^ 0 ) + #define RD_1800 ( PA_OFF | FEM_PINS ^ 0 ) + #define TU_1800 ( PA_HI_BAND | FEM_PINS ^ FEM_7 ) + #define TD_1800 ( PA_OFF | FEM_PINS ^ 0 ) + + #define RU_1900 ( PA_LO_BAND | FEM_PINS ^ FEM_8 ) + #define RD_1900 ( PA_OFF | FEM_PINS ^ 0 ) + #define TU_1900 ( PA_HI_BAND | FEM_PINS ^ FEM_7 ) + #define TD_1900 ( PA_OFF | FEM_PINS ^ 0 ) + +#else // end BOARD = 43 + // start RF HW interfacing with EVARITA + + #define FEM_OFF (FEM_1 | FEM_2) + #define FEM_SLEEP (0) // To avoid leakage during Deep-Seep + + // 3-band config + // RX_UP/DOWN and TX_UP/DOWN + #define RU_900 ( FEM_1 | FEM_2 ) + #define RD_900 ( FEM_1 | FEM_2 ) + #define TU_900 ( FEM_1 ) + #define TD_900 ( FEM_1 | FEM_2 ) + + #define RU_850 ( FEM_1 | FEM_2 ) + #define RD_850 ( FEM_1 | FEM_2 ) + #define TU_850 ( FEM_1 ) + #define TD_850 ( FEM_1 | FEM_2 ) + + #define RU_1800 ( FEM_1 | FEM_2 ) + #define RD_1800 ( FEM_1 | FEM_2 ) + #define TU_1800 ( FEM_2 ) + #define TD_1800 ( FEM_1 | FEM_2 ) + + #define RU_1900 ( FEM_1 | FEM_2 ) + #define RD_1900 ( FEM_1 | FEM_2 ) + #define TU_1900 ( FEM_2) + #define TD_1900 ( FEM_1 | FEM_2 ) + +#endif // BOARD != 43 + +#define TC1_DEVICE_ABB TC1_DEVICE0 // TSPEN0 +#define TC1_DEVICE_RF TC1_DEVICE2 // TSPEN2 + + +//--- TIMINGS ---------------------------------------------------------- + +/*------------------------------------------*/ +/* Download delay values */ +/*------------------------------------------*/ +// 1 qbit = 12/13 usec (~0.9230769), i.e. 200 usec is ~ 217 qbit (200 * 13 / 12) + +#define T TPU_CLOCK_RANGE + + +// - TPU instruction into TSP timings --- +// 1 tpu instruction = 1 qbit +#define DLT_1 1 // 1 tpu instruction = 1 qbit +#define DLT_2 2 // 2 tpu instruction = 2 qbit +#define DLT_3 3 // 3 tpu instruction = 3 qbit +#define DLT_4 4 // 4 tpu instruction = 4 qbit +#define SL_SU_DELAY2 DLT_3 // Needed to compile with old l1_rf12 + +// - Serialization timings --- +// The following values where calculated with Katrin Matthes... +//#define SL_7 3 // To send 7 bits to the ABB, 14*T (1/6.5MHz) are needed, +// // i.e. 14 / 6 qbit = 2.333 ~ 3 qbit +//#define SL_2B 6 // To send 2 bytes to the RF, 34*T (1/6.5MHz) are needed, +// // i.e. 34 / 6 qbit = 5.7 ~ 6 qbit +// ... while the following values are based on the HYP004.doc document +#define SL_7 2 // To send 7 bits to the ABB, 12*T (1/6.5MHz) are needed, + // i.e. 12 / 6 qbit = 2 qbit +#define SL_2B 4 // To send 2 bytes to the RF, 21*T (1/6.5MHz) are needed, + // i.e. 21 / 6 qbit = 3.5 ~ 4 qbit + +// - TPU command execution + serialization length --- +#define DLT_1B 4 // 3*move + serialization of 7 bits +#define DLT_2B 7 // 4*move + serialization of 2 bytes +//#define DLT_1B DLT_3 + SL_7 // 3*move + serialization of 7 bits +//#define DLT_2B DLT_4 + SL_2B // 4*move + serialization of 2 bytes + + +// - INIT (delta or DLT) timings --- +#define DLT_I1 5 // Time required to set EN high before RF_SER_OFF -> RF_SER_ON +#define DLT_I2 8 // Time required to set RF_SER_OFF +#define DLT_I3 5 // Time required to set RF_SER_ON +#define DLT_I4 110 // Regulator Turn-ON time + + +// - tdt & rdt --- +// MAX GSM (not GPRS) rdt and tdt values are... +//#define rdt 380 // MAX GSM rx delta timing +//#define tdt 400 // MAX GSM tx delta timing +// but current rdt and tdt values are... +#define rdt 0 // rx delta timing +#define tdt 0 // tx delta timing + +// - RX timings --- +// - RX down: +// The times below are offsets to when BDLENA goes down +#define TRF_R10 ( 0 - DLT_1B ) // disable BDLENA & BDLON -> power DOWN ABB (end of RX burst), needs DLT_1B to execute +#define TRF_R9 ( - 30 - DLT_2B ) // disable RF SWITCH, power DOWN Rita (go to Idle2 mode) + +// - RX up: +// The times below are offsets to when BDLENA goes high +// Burst data comes here +#define TRF_R8 ( PROVISION_TIME - 0 - DLT_1B ) // enable BDLENA, disable BDLCAL (I/Q comes 32qbit later) +#define TRF_R7 ( PROVISION_TIME - 7 - DLT_1 ) // enable RF SWITCH +#define TRF_R6 ( PROVISION_TIME - 67 - DLT_1B ) // enable BDLCAL -> ABB DL filter init +#define TRF_R5 ( PROVISION_TIME - 72 - DLT_1B ) // enable BDLON -> power ON ABB DL path +#define TRF_R4 ( PROVISION_TIME - 76 - DLT_2B - rdt ) // power ON RX +#define TRF_R3 (PROVISION_TIME - 143 - DLT_2B - rdt ) // select the AGC & LNA gains + start DC offset calibration (stops automatically) +//l1dmacro_adc_read_rx() called here requires ~ 16 tpuinst +#define TRF_R2 (PROVISION_TIME - 198 - DLT_2B - rdt ) // set BAND + power ON RX Synth +#define TRF_R1 (PROVISION_TIME - 208 - DLT_2B - rdt ) // set RX Synth channel + +// - TX timings --- +// - TX down: +// The times below are offsets to when BULENA goes down + +#if (PA_CTRL_INT == 1) +#define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low +#define TRF_T12_5 ( 32 - DLT_2B ) // Power OFF TX loop => power down RF. +#define TRF_T12_3 ( 23 - DLT_1 ) // Disable TXEN. +#endif + +#if (PA_CTRL_INT == 0) +#define TRF_T13 ( 35 - DLT_1B ) // right after, BULON low +#define TRF_T12_2 ( 32 - DLT_2B ) // power down RF step 2 +#define TRF_T12 ( 18 - DLT_2B ) // power down RF step 1 +#endif + +#define TRF_T11 ( 0 - DLT_1B ) // disable BULENA -> end of TX burst +#define TRF_T10_5 ( - 40 - DLT_1B ) // ADC read + +// - TX up: +// The times below are offsets to when BULENA goes high +//burst data comes here +#define TRF_T10_4 ( 22 - DLT_1 ) // enable RF SWITCH + TXEN +#define TRF_T10 ( 17 - DLT_1 ) // enable RF SWITCH + +#if (PA_CTRL_INT == 0) +#define TRF_T9 ( 8 - DLT_2B ) // enable PACTRL +#endif + +#define TRF_T8 ( - 0 - DLT_1B ) // enable BULENA -> start of TX burst +#define TRF_T7 ( - 50 - DLT_1B - tdt ) // disable BULCAL -> stop ABB UL calibration +#define TRF_T6 ( - 130 - DLT_1B - tdt ) // enable BULCAL -> start ABB UL calibration +#define TRF_T5 ( - 158 - DLT_2B - tdt ) // power ON TX +#define TRF_T4 ( - 190 - DLT_1B - tdt ) // enable BULON -> power ON ABB UL path +// TRF_T3_MAN_1, TRF_T3_MAN_2 & TRF_T3_MAN_3 are only executed in DCS for PG 2.0 and above +#define TRF_T3_MAN_3 ( - 239 - DLT_2B - tdt ) // PG2.1: Set the right TX loop charge pump current for DCS & PCS +#define TRF_T3_MAN_2 ( - 249 - DLT_2B - tdt ) // PG2.1: Go into "TX Manual mode" +#define TRF_T3_MAN_1 ( - 259 - DLT_2B - tdt ) // PG2.1: IN DCS, use manual mode: Copy Serial Interface Registers for "Manual operation" +#define TRF_T3 ( - 259 - DLT_2B - tdt ) // PG2.1: In GSM & PCS go to "Automatic TX mode" +#define TRF_T2 ( - 269 - DLT_2B - tdt ) // PG2.0: set BAND + Power ON Main TX PLL + PACTRL ON +#define TRF_T1 ( - 279 - DLT_2B - tdt ) // set TX Main PLL channel +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/L1/tpudrv/tpudrv2.h Sun Nov 17 05:10:06 2013 +0000 @@ -0,0 +1,274 @@ +/****************** Revision Controle System Header *********************** + * GSM Layer 1 software + * Copyright (c) Texas Instruments 1998 + * + * Filename tpudrv2.h + * Copyright 2003 (C) Texas Instruments + * + ****************** Revision Controle System Header ***********************/ + +/***********************************************************/ +/* */ +/* Used Timing definitions given in "L1_TIME.H" */ +/* -------------------------------------------- */ +/* */ +/* START_RX_FB STOP_RX_FB */ +/* START_RX_SB STOP_RX_SB */ +/* START_RX_SNB STOP_RX_SNB */ +/* START_RX_NNB STOP_RX_NNB */ +/* START_RX_PW_1 STOP_RX_PW_1 */ +/* START_RX_FB26 STOP_RX_FB26 */ +/* START_TX_NB STOP_TX_NB */ +/* START_RX_RA STOP_RX_RA */ +/* */ +/***********************************************************/ + +// BB Timings +#define VG_CAL_RX_DELAY 65 +#define VG_CAL_TX_DELAY 143 +#define VG_BDLON_DELAY 70 +#define VG_BULOFF_DELAY 35 +#define VG_BULON_DELAY 159 + +#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) + #define OM_CAL_RX_DELAY 65 + #define OM_CAL_TX_DELAY 230 + #define OM_BDLON_DELAY 166 + #define OM_BULOFF_DELAY 35 + #define OM_BULON_DELAY 250 + + #define SL_SU_DELAY1 4 + #define SL_SU_DELAY2 3 +#endif + +#define RA_TRANSMIS_DURATION ( RA_BURST_DURATION + 46L ) +#define NB_TRANSMIS_DURATION ( NB_BURST_DURATION_UL + 29L ) +#define START_TX_NB ( 4984L ) // Calibration time is reduced of 4 GSM bit due to a slow APC ramp +#define STOP_TX_NB ( START_TX_NB + NB_TRANSMIS_DURATION ) +#define STOP_TX_RA ( START_TX_RA + RA_TRANSMIS_DURATION ) + + +#ifdef TPUDRV2_C + +#if ((ANLG_FAM == 1) || (ANLG_FAM == 2) || (ANLG_FAM == 3)) + const unsigned short RF_Sleep[] ={ + /*** Immediate ***/ + TPU_MOVE(TSP_SPI_SET1, TSP_ENA_POS_MSB), + TPU_MOVE(TSP_SPI_SET2, TSP_ENA_POS_MSB | TSP_ENA_POS), + 0 + }; + + const unsigned short RF_Wakeup[] ={ + /*** Immediate ***/ + TPU_MOVE(TSP_SPI_SET1, 0x00), + TPU_MOVE(TSP_SPI_SET2, TSP_ENA_POS), + 0 + }; + + +/*--------------------------------------------------------------------------------------------------------------*/ +/* Serial link delay for OMEGA. this delay includes */ +/* TSP register programming and serialization of data to OMEGA */ +/* */ +/* */ +/* 4991 4992 4993 4994 4995 4996 4997 */ +/* ---------------------------------------------------------------------------------------------- */ +/* | | | | | | | */ +/*OMEGA | AT(4991) | Clock conf | Nb of bit | Load data | Send write | Serialization */ +/* | | | to shift | to shift | command | | */ +/* ---------------------------------------------------------------------------------------------- */ +/* | | | | | | | */ +/* VEGA | | | | | | AT(4996) | TSPACT */ +/* | | | | | | | */ +/* ------------------------------------------------------------------------------------------|--- */ +/* <------------------------------------------------------------------> | */ +/* SL_SU_DELAY1 | */ +/* V */ +/* ACTION ON WINDOW */ +/* */ +/* When the TSP port is already configured is not necessary to configure the clock and the number of bits */ +/* */ +/* */ +/* 4998 4999 0 1 2 */ +/* ------------------------------------------------------------------- */ +/* | | | | | | */ +/*OMEGA | AT(4998) | Load data | Send write | Serialization | */ +/* | | to shift | command | | | */ +/* ---------------------------------------------------------------------- */ +/* | | | | | | */ +/* VEGA | | | | AT(4996) | TSPACT */ +/* | | | | | | */ +/* ------------------------------------------------------------|------- */ +/* <---------------------------------------> | */ +/* SL_SU_DELAY2 | */ +/* V */ +/* ACTION ON WINDOW */ +/* */ +/* */ +/* NOTE : WITH THIS IMPLEMENTATION THE OMEGA SCENARIO ANTICIPATES THE ACTION ON WINDOW SIGNAL OF 347 ns. */ +/* ANYWAY ACTION IS TAKEN IN THE SAME QB INTERVAL */ +/* */ +/* */ +/*--------------------------------------------------------------------------------------------------------------*/ + + + +/***********************************************************/ +/* BASEBAND TPU SCENARIOS FOR OMEGA */ +/***********************************************************/ + + #if ((CHIPSET == 4) || (CHIPSET == 7) || (CHIPSET == 8) || (CHIPSET == 10) || (CHIPSET == 11)) + // Samson TPU scenario: add 1 bit to reception window for DMA thres = 2 + const SYS_UWORD16 VG_DlNormalBurst [] = { + + TPU_AT (START_RX_SNB -VG_BDLON_DELAY - SL_SU_DELAY1 ), // AT(4991) +// TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), + TPU_MOVE (TSP_CTRL1,6), + TPU_MOVE (TSP_TX_REG_1,BDLON), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + + TPU_AT (START_RX_SNB - VG_CAL_RX_DELAY - SL_SU_DELAY2), // AT(4998) + TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + TPU_AT (START_RX_SNB - SL_SU_DELAY2), // AT(63) + TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + TPU_AT (STOP_RX_SNB - SL_SU_DELAY2), // AT(699) + TPU_MOVE (TSP_TX_REG_1,0x00), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + 0 + }; + + + // HERCULES TPU scenario + const SYS_UWORD16 VG_DlFrequencyBurstIdle [] = { + + TPU_AT (START_RX_FB - VG_BDLON_DELAY -SL_SU_DELAY1 ), // AT(4991) +// TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), + TPU_MOVE (TSP_CTRL1,6), + TPU_MOVE (TSP_TX_REG_1,BDLON), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + + TPU_AT (START_RX_FB - VG_CAL_RX_DELAY -SL_SU_DELAY2), // AT(4998) + TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + + TPU_AT (START_RX_FB - SL_SU_DELAY2), // AT(63) + TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + + TPU_AT (STOP_RX_FB - SL_SU_DELAY2), // AT(2119) + TPU_MOVE (TSP_TX_REG_1,0X00), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + 0 + }; + + + #else + /* HERCULES TPU scenario */ + + const SYS_UWORD16 VG_DlNormalBurst [] = { + + TPU_AT (START_RX_SNB -VG_BDLON_DELAY - SL_SU_DELAY1 ), // AT(4991) +// TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), + TPU_MOVE (TSP_CTRL1,6), + TPU_MOVE (TSP_TX_REG_1,BDLON), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + + TPU_AT (START_RX_SNB - VG_CAL_RX_DELAY - SL_SU_DELAY2), // AT(4998) + TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + TPU_AT (START_RX_SNB - SL_SU_DELAY2), // AT(63) + TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + TPU_AT (STOP_RX_SNB - SL_SU_DELAY2), // AT(699) + TPU_MOVE (TSP_TX_REG_1,0x00), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + 0 + }; + + + // HERCULES TPU scenario + const SYS_UWORD16 VG_DlFrequencyBurstIdle [] = { + + TPU_AT (START_RX_FB - VG_BDLON_DELAY -SL_SU_DELAY1 ), // AT(4991) +// TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), + TPU_MOVE (TSP_CTRL1,6), + TPU_MOVE (TSP_TX_REG_1,BDLON), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + + TPU_AT (START_RX_FB - VG_CAL_RX_DELAY -SL_SU_DELAY2), // AT(4998) + TPU_MOVE (TSP_TX_REG_1,BDLON | BDLCAL), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + + TPU_AT (START_RX_FB - SL_SU_DELAY2), // AT(63) + TPU_MOVE (TSP_TX_REG_1,BDLON | BDLENA), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + TPU_AT (0), + + TPU_AT (STOP_RX_FB - SL_SU_DELAY2), // AT(2119) + TPU_MOVE (TSP_TX_REG_1,0X00), + TPU_MOVE (TSP_CTRL2, TC2_WR), + + 0 + }; + + + + #endif + + + + // HERCULES TPU scenario for Omega windows reset + const SYS_UWORD16 VG_Omega_win_reset[] = { + + TPU_MOVE (TSP_SPI_SET1, TSP_CLK_RISE), + TPU_MOVE (TSP_CTRL1,6), + TPU_MOVE (TSP_TX_REG_1,0x00), + TPU_MOVE (TSP_CTRL2, TC2_WR), + 0 + }; + + #endif + +#else + extern const SYS_UWORD16 VG_DlNormalBurst[]; + extern const SYS_UWORD16 VG_DlFrequencyBurstIdle[]; +#endif +
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/gsm-fw/L1/tpudrv/tpudrv8.h Sun Nov 17 05:10:06 2013 +0000 @@ -0,0 +1,143 @@ +/****************** Revision Controle System Header *********************** + * GSM Layer 1 software + * Copyright (c) Texas Instruments 1998 + * + * Filename tpudrv8.h + * Copyright 2003 (C) Texas Instruments + * + ****************** Revision Controle System Header ***********************/ + +//SI4133 definitions +#define WordAdd0000 0x000000 //Main Configuration +#define AutoPDB 0x000080 //Auto Power Down - Uses PWDNB pin +#define AuxSel 0x030000 //Auxiliary output pin use = LOCK Detect +#define WordAdd0011 0x000003 //RF1 N Divider +#define WordAdd0100 0x000004 //RF2 N Divider +#define WordAdd0101 0x000005 //IF N Divider +#define RFPWR 0x000020 //RF LO high power +#define XPDM 0x000100 //Reference amplifier ON when PWDNB pin = 0 + +//TRF6053 definitions +#define Mode0 0x000000 +#define Mode1 0x000001 +#define Mode2 0x000003 +#define Mode3 0x000005 +#define Mode4 0x000007 +#define LNAMixPwrOn 0x000080 //Mode0 +#define VCODiv2PwrOn 0x000040 //Mode0 +#define RXBBIFStgPwrOn 0x000020 //Mode0 +#define OFFStrCalOn 0x000010 //Mode0 +#define VCORDivPwrOn 0x000008 //Mode0 +#define MixLOBuffPwrOn 0x000004 //Mode0 +#define TXStagesPwrOn 0x000002 //Mode0 +#define FreqDetDis 0x000400 //Mode4 +#define IFVCOExternal 0x000200 //Mode4 +#define IFPLLBuffDis 0x000100 //Mode4 +#define LBandLNAExt 0x000080 //Mode4 +#define HBandLNAExt 0x000040 //Mode4 +#define Div2ToRXStgs 0x000020 //Mode4 +#define DivRToTXStgs 0x000010 //Mode4 +#define ChgPPLBNeg 0x000010 //Mode2 +#define ChgPPHBNeg 0x000010 //Mode3 +#define PreCCLBDis 0x000008 //Mode2 +#define PreCCHBDis 0x000008 //Mode3 +#define LNAGainLow 0x000010 //Mode2 +#define BandHigh 0x000008 //Mode1 +#define LowBIF610 0x000020 //Mode2 +#define HighBIF412 0x000020 //Mode3 +#define HighBIF25 0x000040 //Mode3 +#define HighBIF410 0x000060 //Mode3 + +/*------------------------------------------*/ +/* Download delay values */ +/*------------------------------------------*/ +#define TRF6053_DOWNLOAD_TIME 15 +#define SYNTH_DOWNLOAD_TIME 20 + +//-------------------------------------------- +// internal tpu timing +//-------------------------------------------- + +#define DLT_1 1 // 1 tpu instruction = 1 qbit +#define DLT_2 2 +#define DLT_3 3 +#define DLT_4 4 + +#define DLT_1B 4 // 3*move + 1*byte (download) +#define DLT_2B 6 // 4*move + 2*byte +#define DLT_3B 8 // 5*move + 3*byte + +#define SL_SU_DELAY1 4 // No. bits to send + load data to shift + send write cmd + 1 +#define SL_SU_DELAY2 3 // load data to shift + send write cmd + 1 +#define SL_SU_DELAY3 5 // SL_SU_DELAY1 + serialization + +/*------------------------------------------*/ +/* Download delay values */ +/*------------------------------------------*/ +// 0.9230769 usec ~ 1 qbit i.e. 200 usec is ~ 217 qbit + +#define T TPU_CLOCK_RANGE // TODO: should be a define from L1. + +// time below are offset to when BDLENA goes low +#define TRF_R11 ( 0 - DLT_1B) // disable BDLON & BDLENA +#define TRF_R10 ( - 5 - DLT_1B) // disable TRF6053 + +// burst data comes here +// time below are offset to when BDLENA goes high +#define TRF_R9 (PROVISION_TIME - 0 - DLT_1B) // enable BDLENA, disable BDLCAL +#define TRF_R8 (PROVISION_TIME - 11 - DLT_1B) // power on RX front end, DC cal. off +#define TRF_R7 (PROVISION_TIME - 65 - DLT_1B) // enable BDLCAL +#define TRF_R6 (PROVISION_TIME - 72 - DLT_1B) // enable BDLON +#define TRF_R5 (PROVISION_TIME - 76 - DLT_1B) // power on receiver, start DC cal. +#define TRF_R4 (PROVISION_TIME - 80 - DLT_2B) // set RX gain & band. + // ADC read, uses min 11 qbit due to 5 wait +#define TRF_R3 (PROVISION_TIME - 196 - DLT_1B) // power up TRF2253 +#define TRF_R1 (PROVISION_TIME - 205 - DLT_3B) // set RF PLL N counter = r1 and IF PLL N counter in TRF2253 = r2 + +// time below are offset to when BULENA goes low +#define TRF_T13 ( 32 - DLT_1B) // disable PA_ON, BULON, TRF6053 +#define TRF_T12 ( 18 - DLT_1 ) // disable TSPACT01 +#define TRF_T11 ( 0 - DLT_1B) // disable BULENA +#define TRF_T10_1 (- 40 - DLT_1B) // ADC read +// burst data comes here +// time below are offset to when BULENA goes high +#define TRF_T10 (+ 15 - DLT_3) // enable PA_ON + 2*rfswitch +#define TRF_T9 (- 0 - DLT_1B) // enable BULENA +#define TRF_T8 (- 109 - DLT_2B) // power on transceiver +#define TRF_T7 (- 115 - DLT_1B) // disable BULCAL +#define TRF_T6 (- 230 - DLT_1B) // power up TRF2253 +#define TRF_T5 (- 233 - DLT_2B) // set TX band in TRF6053 +#define TRF_T3 (- 249 - DLT_3B) // set RF PLL N counter = t3 and IF PLL N counter in TRF2253 = t4 +#define TRF_T2 (- 260 - DLT_1B) // enable BULCAL +#define TRF_T1 (- 278 - DLT_1B) // enable BULON + +#if (BOARD == 7) || (BOARD == 8) || (BOARD == 9) || (BOARD == 40) || (BOARD == 41) || (BOARD == 42) || (BOARD == 43) || (BOARD == 45) + #define PA_ON 0x20 // act5 + #define TSPACT01 0x02 // act1 + + // RF signals connected to TSPACTX + #define RX900 0x04 // act10 + #define RX1800 0x08 // act11 + + #define TC1_DEVICE_ABB TC1_DEVICE0 + #define TC1_DEVICE_RF TC1_DEVICE1 + #define TC1_DEVICE_PLL TC1_DEVICE2 +#endif + +#if (BOARD == 6) + #define PA_ON 0x10 // act4 + + // RF signals connected to TSPACTX + #define RX900 0x08 // act11 => needs to be connected to act12 + #define RX1800 0x04 // act10 + + #define TC1_DEVICE_ABB TC1_DEVICE0 + #define TC1_DEVICE_PLL TC1_DEVICE1 + #define TC1_DEVICE_RF TC1_DEVICE2 +#endif + +#ifdef TPUDRV8_C +// Function prototypes +SYS_UWORD16 Convert_l1_radio_freq(SYS_UWORD16 radio_freq); + +#endif