--- a/gsm-fw/sysglue/Makefile	Mon Sep 01 09:28:09 2014 +0000
+++ b/gsm-fw/sysglue/Makefile	Mon Sep 01 17:04:19 2014 +0000
@@ -5,7 +5,10 @@
 
 OBJS=	appinit.o exceptions.o irqfiq.o sysinit.o
 
-all:	xipcode.o
+all:	xipcode.o flashboot.o
+
+flashboot.o:	flashboot.S vectors.S
+sysinit.o:	sysinit.S vectors.S
 
 xipcode.o:	${OBJS}
 	${LD} -r -o $@ ${OBJS}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gsm-fw/sysglue/flashboot.S	Mon Sep 01 17:04:19 2014 +0000
@@ -0,0 +1,82 @@
+/*
+ * This assembly module contains those bits which are specific to flashable
+ * image builds only. It puts bits of code into several different sections.
+ */
+
+#include "../include/config.h"
+
+	.section	flashboot.text,"ax",%progbits
+	.code	32
+	.org	0
+#if FLASH_BOOT_VIA_BOOTROM
+/* sane targets with Calypso boot ROM enabled by the PCB wiring */
+/* provide the necessary magic words for the boot ROM */
+	.word	0
+	.word	_Flash_boot_entry
+#elif CONFIG_TARGET_C139
+/*
+ * On this target we are going to put a special flash boot stage at 0x2000,
+ * and then the actual gsm-fw image at the flash erase block boundary
+ * at 0x10000.  The following bits will be read by our intermediate
+ * flash boot stage.
+ */
+	.asciz	"FreeCalypso"
+	.word	_Flash_boot_entry
+#elif CONFIG_TARGET_C155
+/*
+ * On this target the hand-off point between the bootloader and the main
+ * fw image coincides with a flash erase block boundary, thus no need
+ * for an intermediate flash boot stage.  The following bits will appear
+ * at 0x20000.
+ */
+	.asciz	"FreeCalypso firmware for C155/156 target"
+	.org	0xE0
+/* C155/156 bootloader jumps here */
+	b	_Flash_boot_entry
+#include "vectors.S"
+#else
+#error "Unsupported flash boot configuration"
+#endif
+
+	.globl	_Flash_boot_entry
+_Flash_boot_entry:
+/* first order of business: configure flash and XRAM access */
+	ldr	r2, =0xFFFFFB00
+#if CONFIG_TARGET_PIRELLI
+	mov	r0, #0x00A4
+	strh	r0, [r2, #0]
+	strh	r0, [r2, #2]
+	strh	r0, [r2, #6]
+#else
+	mov	r0, #0x00A3
+	strh	r0, [r2, #0]
+	strh	r0, [r2, #2]
+#endif
+/*
+ * Switch the CS4/ADD22 pin to the ADD22 function.  We only need this
+ * setting on targets with 8 MiB flash (or XRAM) banks, but it doesn't
+ * hurt to do it on all targets (like TI's original code does),
+ * until and unless we encounter a target that uses the CS4 function.
+ */
+	ldr	r1, =0xFFFEF006
+	mov	r2, #0x0008
+	strh	r2, [r1]
+/* we now have full access to all flash and RAM on the device */
+/* copy iram.text to where it's supposed to be */
+	ldr	r8, =__iramtext_flash_addr
+	ldr	r9, =__iramtext_ram_addr
+	ldr	r10, =__iramtext_size
+1:	ldmia	r8!, {r0-r7}
+	stmia	r9!, {r0-r7}
+	subs	r10, r10, #0x20
+	bhi	1b
+/* likewise copy .data from flash to XRAM */
+	ldr	r8, =__initdata_flash_addr
+	ldr	r9, =__initdata_ram_addr
+	ldr	r10, =__initdata_size
+1:	ldmia	r8!, {r0-r7}
+	stmia	r9!, {r0-r7}
+	subs	r10, r10, #0x20
+	bhi	1b
+/* boot path joins with fc-xram loadable builds */
+	b	_FlashorXram_entry

--- a/gsm-fw/sysglue/sysinit.S	Mon Sep 01 09:28:09 2014 +0000
+++ b/gsm-fw/sysglue/sysinit.S	Mon Sep 01 17:04:19 2014 +0000
@@ -6,16 +6,7 @@
 
 	.section	iram.vectors,"ax",%progbits
 	.code	32
-/* ARM exceptions */
-	b	_arm_undefined
-	b	_arm_swi
-	b	_arm_abort_prefetch
-	b	_arm_abort_data
-	b	_arm_reserved
-/* IRQ */
-	b	_INT_IRQ
-/* FIQ */
-	b	_INT_FIQ
+#include "vectors.S"
 
 	.section	xip.text,"ax",%progbits
 	.code	32

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/gsm-fw/sysglue/vectors.S	Mon Sep 01 17:04:19 2014 +0000
@@ -0,0 +1,14 @@
+/*
+ * These 7 branch instructions, corresponding to ARM exception and interrupt
+ * vectors, will be placed in different sections depending on the flashImage
+ * vs. ramImage configuration and which target we build for; this little
+ * snippet file will be #included where it is needed.
+ */
+
+	b	_arm_undefined
+	b	_arm_swi
+	b	_arm_abort_prefetch
+	b	_arm_abort_data
+	b	_arm_reserved
+	b	_INT_IRQ
+	b	_INT_FIQ