changeset 313:9df7f9c72e17

ARM exception handling: stack setup added
author Michael Spacefalcon <msokolov@ivan.Harhan.ORG>
date Mon, 17 Mar 2014 07:47:18 +0000
parents f05ae34f7ca0
children 48c08499cede
files gsm-fw/nucleus/asm_defs.h gsm-fw/nucleus/init.S
diffstat 2 files changed, 17 insertions(+), 0 deletions(-) [+]
line wrap: on
line diff
--- a/gsm-fw/nucleus/asm_defs.h	Mon Mar 17 07:37:28 2014 +0000
+++ b/gsm-fw/nucleus/asm_defs.h	Mon Mar 17 07:47:18 2014 +0000
@@ -53,6 +53,8 @@
 #define	FIQ_BIT			0x40	/* Interrupt bit of CPSR and SPSR */
 #define	IRQ_BIT_OR_FIQ_BIT	0xC0	/* IRQ or FIQ interrupt bit of CPSR */
 					/* and SPSR */
+#define	ABORT_MODE		0x17
+#define	UNDEF_MODE		0x1B
 
 /*
  ********************************************
--- a/gsm-fw/nucleus/init.S	Mon Mar 17 07:37:28 2014 +0000
+++ b/gsm-fw/nucleus/init.S	Mon Mar 17 07:47:18 2014 +0000
@@ -261,6 +261,21 @@
 
     LDR     sp,FIQ_Stack_SP                 @ Setup FIQ stack pointer
 
+@ set up abort and undef mode stacks - code from TI
+        MRS     a1,CPSR                     @ Pickup current CPSR
+        BIC     a1,a1,#MODE_MASK            @ Clear the mode bits
+        ORR     a1,a1,#ABORT_MODE           @ Set the Abort mode bits
+        MSR     CPSR,a1                     @ Move to the Abort mode
+        LDR     sp,=_Except_Stack_SP	    @ Setup Abort stack pointer
+
+        MRS     a1,CPSR                     @ Pickup current CPSR
+        BIC     a1,a1,#MODE_MASK            @ Clear the mode bits
+        ORR     a1,a1,#UNDEF_MODE           @ Set the Undefined mode bits
+        MSR     CPSR,a1                     @ Move to the Undefined mode
+        LDR     sp,=_Except_Stack_SP        @ Setup Undefined stack pointer
+                                            @   (should never be used)
+
+@ original Nucleus code continues
     MRS     r0,CPSR                         @ Pickup current CPSR
     BIC     r0,r0,#MODE_MASK                @ Clear mode bits
     ORR     r0,r0,#SUP_MODE                 @ Set the supervisor mode bits